SOI substrate comprising intermediate semiconductor layer and preparation method thereof

Abstract

The invention provides an SOI substrate containing an intermediate semiconductor layer and a preparation method thereof, and the method comprises the steps: sequentially forming a first insulating layer and an amorphous semiconductor material layer on one of a semiconductor layer and a second substrate, and forming a second insulating layer on the other one; forming an initial bonding structure in a mode that the first insulating layer, the amorphous semiconductor material layer and the second insulating layer are clamped between the first substrate and the second substrate; transferring the semiconductor layer to the second substrate by removing a portion of the first substrate away from the amorphous semiconductor material layer; and performing reinforcement treatment on the initial bonding structure, and recrystallizing the amorphous semiconductor material layer and converting the amorphous semiconductor material layer into a polycrystalline state to form an intermediate semiconductor layer. In the preparation method, the amorphous semiconductor material layer is introduced between the substrate layer and the top functional layer, compared with a polycrystalline semiconductor layer, the amorphous semiconductor material layer is easy to polish, the surface roughness can be optimized, the polishing difficulty of a bonding interface is further reduced, and the bonding quality and the processing quality of the SOI substrate are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to an SOI substrate comprising an intermediate semiconductor layer and a preparation method thereof. Background Art

[0002] The semiconductor substrate on insulator is usually a multi-layer structure, including a substrate layer, an insulating buried layer and a top semiconductor layer from bottom to top. Existing SOI substrates usually introduce a polycrystalline semiconductor layer under the top semiconductor layer. The polycrystalline semiconductor layer can be used as the back adjustment electrode of the SOI device, which is convenient for expanding the functions of the SOI device, enriching the design scheme of the SOI device, and simplifying the back electrode process. On the other hand, when the polycrystalline semiconductor layer in this SOI structure is in a high-resistance state, it can be used as a shielding layer for the oxide layer charge and the RF bias, reducing the loss of the RF signal in the substrate layer. Figure 1 A typical structural schematic diagram of an SOI substrate including a polycrystalline semiconductor layer is provided.

[0003] like Figure 1 As shown, the SOI substrate includes a substrate layer 2, an insulating buried layer and a top semiconductor layer 11, and a polycrystalline semiconductor layer 3 is inserted between the substrate layer 2 and the top semiconductor layer 11. Such an SOI substrate usually requires multiple thin film depositions, as well as a series of processes such as planarization, bonding, stripping, and thinning to be manufactured.

[0004] The above preparation process requires SOI wafer bonding technology, but SOI wafer bonding has very high requirements on the quality of the bonding surface, requiring extremely small roughness, extremely high flatness, and thickness uniformity, so the bonding surface must be properly polished. For polycrystalline semiconductor materials, when polishing them, because the material contains a variety of small grains with different crystal orientations, the polishing rate of these small grains will also be affected by the crystal orientation, which in turn affects the polishing uniformity, that is, the polishing process is more difficult.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology part of the present application. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide an SOI substrate including an intermediate semiconductor layer and a preparation method thereof, so as to solve the problems in the production process of the existing SOI substrate, such as the difficulty of wafer bonding and the quality failing to meet the processing requirements of advanced semiconductor processes.

[0007] To achieve the above object and other related objects, the present invention provides a method for preparing an SOI substrate including an intermediate semiconductor layer, comprising the following steps:

[0008] Providing a first substrate and a second substrate, wherein the first substrate includes a first substrate and a semiconductor layer located on the first substrate;

[0009] forming a first insulating layer and an amorphous semiconductor material layer on one of the semiconductor layer and the second substrate in sequence, and forming a second insulating layer on the other of the semiconductor layer and the second substrate;

[0010] forming an initial bonding structure in a manner that the first insulating layer, the amorphous semiconductor material layer and the second insulating layer are sandwiched between the first substrate and the second substrate;

[0011] transferring the semiconductor layer onto the second substrate by removing a portion of the first substrate away from the amorphous semiconductor material layer;

[0012] The initial bonding structure is reinforced, and the amorphous semiconductor material layer is recrystallized and the amorphous semiconductor material therein is transformed into a polycrystalline semiconductor material to form an intermediate semiconductor layer.

[0013] Optionally, before the step of forming the amorphous semiconductor layer, the method further includes: forming a functional stack on the first insulating layer, wherein the functional stack includes one or a combination of a single crystal semiconductor layer, a polycrystalline semiconductor layer and an insulating dielectric layer.

[0014] Optionally, the first substrate is selected as a semiconductor substrate, and after the step of forming the first insulating layer, a portion of the first substrate away from the amorphous semiconductor material layer is removed in the following manner: ion implantation is performed from a side of the first substrate on which the first insulating layer is formed, and a preset stripping interface is defined in the first substrate, and the implanted ions include one of hydrogen ions and helium ions; an ion stripping process is used to crack the first substrate along a position defined by the preset stripping interface.

[0015] Optionally, a first insulating layer and an amorphous semiconductor material layer are sequentially formed on the second substrate, and a second insulating layer is formed on the semiconductor layer; wherein the first insulating layer and the second insulating layer respectively include a single layer composed of one selected from the following materials, or a composite layer composed of multiple thereof: oxides, nitrides, oxynitrides containing Group IV elements, metal oxides and wide bandgap semiconductor materials.

[0016] Optionally, the step of forming the amorphous semiconductor material layer includes: controlling the temperature of the first substrate to be below 350° C. and depositing the amorphous semiconductor material on the first insulating layer by a plasma enhanced chemical vapor deposition process; then performing a dehydrogenation process to reduce the hydrogen dangling bond concentration in the amorphous semiconductor material layer to less than 10 19 / cm 3 .

[0017] Optionally, the step of forming the amorphous semiconductor material layer includes:

[0018] By controlling the temperature of the first substrate to be below 200° C., amorphous semiconductor material is deposited on the first insulating layer by using a magnetron sputtering process.

[0019] Optionally, after the step of forming the amorphous semiconductor material layer, the method further comprises: performing pre-bonding using the amorphous semiconductor material layer and the second insulating layer as bonding interfaces to form an initial bonding structure, wherein the thickness of the second insulating layer is not greater than 15 nm.

[0020] Optionally, after the step of forming the amorphous semiconductor material layer on the first insulating layer, the method further comprises:

[0021] forming a third insulating layer on the amorphous semiconductor material layer;

[0022] The third insulating layer and the second insulating layer are used as bonding interfaces for pre-bonding to form an initial bonding structure.

[0023] Optionally, it also includes:

[0024] Before the step of forming the second insulating layer, a planarization process is performed on the exposed surface of the semiconductor layer or the second substrate;

[0025] Before the step of forming the amorphous semiconductor material layer, a planarization process is performed on the first insulating layer; or

[0026] performing a planarization process on at least one of the second insulating layer and the amorphous semiconductor material layer;

[0027] The planarization process includes one or more of a chemical mechanical polishing process and a physical mechanical polishing process.

[0028] Optionally, the step of reinforcing the initial bonding structure is performed after removing a portion of the first substrate, and includes:

[0029] The initial bonding structure is subjected to a heating treatment to cause bonding reinforcement, and at the same time the amorphous semiconductor material layer is recrystallized and the amorphous semiconductor material therein is transformed into a polycrystalline semiconductor material; wherein the reinforcement treatment includes a heating temperature ≥ 1000°C and a duration ≥ 1 hour.

[0030] The present invention also provides an SOI substrate including an intermediate semiconductor layer, comprising a substrate layer, an insulating buried layer and a top functional layer, wherein an intermediate semiconductor layer is inserted between the substrate layer and the top functional layer, the insulating buried layer comprises a first insulating layer and a second insulating layer, the intermediate semiconductor layer is formed based on a polycrystalline semiconductor material that is crystallized from an amorphous semiconductor material layer, and the intermediate semiconductor layer is sandwiched between the first insulating layer and the second insulating layer.

[0031] Optionally, the intermediate semiconductor layer is sandwiched between the first insulating layer and the second insulating layer by bonding the amorphous semiconductor material layer to the second insulating layer, wherein the thickness of the second insulating layer is not greater than 15 nm.

[0032] As described above, the SOI substrate including the intermediate semiconductor layer and the preparation method thereof of the present invention have the following beneficial effects:

[0033] The preparation method of the SOI substrate including the intermediate semiconductor layer provided by the present invention, by introducing an amorphous semiconductor material layer between the substrate layer and the top functional layer, is easier to polish than the polycrystalline semiconductor layer, can optimize the surface roughness and flatness, and thus reduce the difficulty of polishing the bonding interface, which is beneficial to improving the bonding quality and the processing quality of the SOI substrate structure; in addition, the amorphous semiconductor material layer itself has a relatively loose structure, and its interior can absorb the defects caused by hydrophilic bonding, and when it acts as a bonding interface in the bonding process, it can reduce the thickness requirement of the insulating buried layer; using the amorphous semiconductor material to recrystallize into a polycrystalline state instead of directly forming a polycrystalline semiconductor layer can give the SOI device design flexibility and expand the application scenarios of the SOI substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A typical structural diagram of a SOI substrate including a polycrystalline semiconductor layer is shown.

[0035] Figure 2a to Figure 2b Display as Figure 1 The schematic diagram shown is a process for preparing an SOI substrate in which a side of a supporting substrate having a polycrystalline semiconductor layer formed thereon is bonded to a semiconductor substrate serving as a supply substrate.

[0036] Figure 3a to Figure 3b Display as Figure 1The schematic diagram shown is a process for preparing an SOI substrate in which a side of a supporting substrate having a polycrystalline semiconductor layer is bonded to an SOI substrate serving as a supply substrate.

[0037] Figure 4 It shows a process flow chart of a method for preparing an SOI substrate including an intermediate semiconductor layer according to the first embodiment of the present invention.

[0038] Figure 5a to Figure 5h It is a schematic diagram showing the structure obtained at different stages in the preparation process of the SOI substrate including the intermediate semiconductor layer according to the first embodiment of the present invention, using the semiconductor substrate as the supply substrate; wherein, Figure 5d is a schematic structural diagram of pre-bonding in step S300 using the amorphous semiconductor material layer and the second insulating layer as bonding interfaces, Figure 5e It is a structural schematic diagram of pre-bonding in step S300 using the second insulating layer and the third insulating layer as bonding interfaces.

[0039] Figures 6a to 6f It is a schematic diagram showing the structure obtained at different stages in the preparation process of the SOI substrate including the intermediate semiconductor layer according to the first embodiment of the present invention, using SOI as the supply substrate; wherein, Figure 6d is a schematic structural diagram of pre-bonding in step S300 using the amorphous semiconductor material layer and the second insulating layer as bonding interfaces, Figure 6e It is a structural schematic diagram of pre-bonding in step S300 using the second insulating layer and the third insulating layer as bonding interfaces.

[0040] Figures 7a to 7d Schematic diagram of structures obtained at different stages in the preparation process of an SOI substrate including an intermediate semiconductor layer according to the second embodiment of the present invention using a bulk substrate as a supply substrate.

[0041] Figures 8a to 8e Schematic diagram of structures obtained at different stages using SOI as a supply substrate during the preparation of an SOI substrate including an intermediate semiconductor layer according to the second embodiment of the present invention.

[0042] Figures 9 to 13 It is a schematic structural diagram of an SOI substrate including an intermediate semiconductor layer according to a third embodiment of the present invention.

[0043] Component number description

[0044] 1 Supply substrate

[0045] 2. Substrate layer

[0046] 11 Semiconductor thin films

[0047] 21 First insulation layer

[0048] 22 Second insulation layer

[0049] 3 Polycrystalline semiconductor layer

[0050] 10 First Base

[0051] 20 Second Base

[0052] 110 Semiconductor layer

[0053] 120 First insulation layer

[0054] 130 Amorphous semiconductor material layer

[0055] 160 Second insulation layer

[0056] 240b Third insulation layer

[0057] 510 Cavity

[0058] 50 Patterned functional layer

[0059] 210 SOI substrate

[0060] 220 First insulation layer

[0061] 230 Amorphous semiconductor material layer

[0062] 260, 240a Second insulating layer

[0063] 30 Intermediate semiconductor layer

[0064] 310 substrate layer

[0065] 40 Functional laminates

[0066] 101 preset stripping interface DETAILED DESCRIPTION

[0067] The following is a description of the implementation of the present invention by means of specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0068] See also Figures 1 to 13. It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings in this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0069] Figure 1 The SOI substrate shown can be manufactured using the following process flow:

[0070] 1) preparing a substrate for the wafer, wherein the substrate for the wafer includes a semiconductor film to be transferred;

[0071] 2) preparing a polycrystalline semiconductor layer on a supporting substrate, with the surface of the polycrystalline semiconductor layer as a bonding interface; optionally, covering the surface of the polycrystalline semiconductor layer with another insulating layer;

[0072] 3) The side of the supporting substrate on which the polycrystalline semiconductor layer (or the insulating layer on the polycrystalline semiconductor layer) is formed is bonded to the supply substrate.

[0073] 4) By removing a portion of the supply substrate, the semiconductor film is transferred to the supporting substrate to form a new type of SOI substrate.

[0074] In step 1), the supply substrate 1 may be a semiconductor substrate, or an SOI substrate; when the supply substrate 1 is a semiconductor substrate, the supply substrate contains a preset peeling interface.

[0075] In step 2), the supporting substrate includes a substrate layer 2 and a second insulating layer 22 located on the substrate layer 2 .

[0076] Figure 2a to Figure 2b It is a schematic diagram showing a process of preparing an SOI substrate in which a side of a supporting substrate on which a polycrystalline semiconductor layer is formed is bonded to a semiconductor substrate serving as a supply substrate.

[0077] When the substrate 1 is a semiconductor substrate with a preset peeling interface, the mainstream preparation process adopts smart peeling technology (Smart-cut), such as Figure 2a As shown, at step 3), the side of the support substrate formed with the polycrystalline semiconductor layer is bonded to the supply substrate 1; at step 4), as Figure 2aAs shown, the supply substrate is ion stripped along a preset stripping interface 101, so that the semiconductor film 11 is transferred to the supporting substrate to form a novel SOI substrate structure.

[0078] Figure 3a to Figure 3b It is a schematic diagram showing a process of preparing an SOI substrate in which a side of a supporting substrate on which a polycrystalline semiconductor layer is formed is bonded to an SOI substrate serving as a supply substrate.

[0079] When the substrate 1 is an SOI substrate, in step 3), as Figure 3a As shown, the side of the support substrate formed with the polycrystalline semiconductor layer is bonded to the supply substrate 1; at step 4), as Figure 3b As shown, the thick substrate portion below the top semiconductor layer and the buried insulating layer are removed, for example, by a backside thinning process.

[0080] However, the above-mentioned preparation process has the following defects and shortcomings:

[0081] 1) If Figure 2a and Figure 2b As shown, directly preparing a polycrystalline semiconductor layer 3 on the surface of a supply substrate containing a preset stripping interface often requires a higher process temperature. However, high temperature may cause a risk of stripping at the preset stripping interface. Taking hydrogen ion implantation into a polycrystalline silicon layer to form a stripping layer as an example, the process temperature required for depositing polycrystalline silicon needs to reach 600°C. When the ambient temperature exceeds 350°C, it will cause a risk of stripping at the preset stripping interface, resulting in process failure.

[0082] 2) If Figure 2a and Figure 2b As shown, a polycrystalline semiconductor layer 3 can be first prepared on the surface of a supply substrate, and then a preset stripping interface 101 can be defined in the supply substrate 1 by ion implantation. Since the stripping interface is determined by the ion implantation energy (depth), the depth uniformity of the stripping interface obtained by the implantation will be affected by the thickness uniformity of the polycrystalline semiconductor. That is, when the thickness uniformity of the polycrystalline semiconductor layer is poor, the depth uniformity of the stripping interface obtained in the supply substrate cannot be guaranteed, so that the thickness uniformity of the top functional layer stripped from the supply substrate is also poor, which cannot meet the quality requirements of advanced semiconductor processes for SOI substrates.

[0083] 3) If Figure 2a and Figure 3aAs shown, the above preparation process requires SOI wafer bonding technology, so that the side of the supporting substrate formed with a polycrystalline material layer is bonded to the wafer supply substrate 1, but SOI wafer bonding has very high requirements on the quality of the bonding surface, requiring extremely small roughness, such as an average roughness as low as 0.2nm, and extremely high flatness and thickness uniformity, so the bonding surface must be properly polished. For polycrystalline semiconductor materials, when polishing them, because the material contains a variety of small grains with different crystal orientations, the polishing rate of these small grains will also be affected by the crystal orientation, thereby affecting the polishing uniformity, that is, the polishing process is more difficult.

[0084] 4) In order to avoid premature peeling of the preset peeling interface, a low-temperature bonding process with a dielectric layer is often used during the SOI wafer bonding process, including, for example, hydrophilic bonding and surface activated bonding.

[0085] When hydrophilic bonding is used, for example, hydrophilic bonding is performed between polycrystalline silicon and silicon oxide buried layer, the bonding surface contains hydroxyl -OH, and several water molecules. The semiconductor material and hydroxyl will undergo redox reaction during the high-temperature consolidation process to generate hydrogen. These hydrogen are difficult to discharge and easily agglomerate at the bonding interface to form bubble defects. In conventional hydrophilic bonding processes, thicker oxide buried layers such as silicon oxide and germanium oxide are often used as bonding interfaces (one of the two bonding material layers is an oxide semiconductor layer or all are oxide semiconductor layers). The oxide semiconductor layer has a certain adsorption capacity for hydrogen, which can reduce the formation of bubble defects. The polycrystalline semiconductor layer has a weaker adsorption capacity for hydrogen. Therefore, when a polycrystalline semiconductor layer is used as a bonding layer, there must be a thicker oxide semiconductor layer as a buffer layer at its bonding interface. This imposes certain restrictions on the process conditions of the SOI substrate.

[0086] When surface activated bonding is used, although the bonding surface does not contain hydroxyl groups and hydrogen will not be generated during high temperature, it places extremely high demands on the surface roughness, flatness, thickness uniformity, etc. of the bonding material. Generally speaking, bonding materials with high plastic deformation ability, such as silicon oxide, are used. Such materials are easy to deform under high temperature and high pressure environments, can fill bonding voids, reduce bonding defects, and easily obtain better bonding quality. However, the plastic deformation ability of polycrystalline semiconductor materials during the bonding process is limited, which also poses a great challenge to high-quality bonding.

[0087] like Figure 2a and Figure 3a As shown, when a polycrystalline semiconductor layer is prepared on another supporting substrate for bonding, due to the inherent disadvantages of hydrophilic bonding, the insulating buried layer at the bonding interface needs to maintain a large thickness, making it difficult to achieve an ultra-thin insulating buried layer, which limits the process parameter range of the SOI substrate.

[0088] Embodiment 1

[0089] In order to improve the bonding effect, this embodiment provides a method for preparing an SOI substrate including an intermediate semiconductor layer. Figure 4 , is a process flow chart of a method for preparing a SOI substrate including an intermediate semiconductor layer in this embodiment, wherein the method for preparing the SOI substrate comprises the following steps:

[0090] First, step S100 is performed to provide a first substrate and a second substrate, wherein the first substrate includes a first substrate and a semiconductor layer located on the first substrate.

[0091] Specifically, the first substrate 10 serves as a substrate for film supply, and includes a first substrate (not shown) and a semiconductor layer 110 located on the first substrate; the second substrate 20 serves as a supporting substrate. Figure 5a The first substrate 10 is selected as a semiconductor substrate, that is, a substrate of a single material; the material of the first substrate 10 includes silicon, silicon carbide, silicon germanium or other suitable semiconductor materials, such as a single crystal silicon substrate, the first substrate 10 includes a first main surface and a second main surface relative to each other, and a preset stripping interface 101 is formed in the first substrate close to its first main surface, and the portion of the first substrate between its first main surface and the preset stripping interface is a semiconductor layer 110.

[0092] As an example, the step of forming the preset stripping interface 101 includes: performing ion implantation from the first main surface of the first substrate, the implanted ions include, for example, one of hydrogen ions and helium ions, and the position of the preset stripping interface in the first substrate can be appropriately adjusted according to the required SOI top layer structure.

[0093] Next, step S200 is performed to sequentially form a first insulating layer and an amorphous semiconductor material layer on the first substrate, and form a second insulating layer on the second substrate.

[0094] Specifically, after the step of defining the preset peeling interface 101, a first insulating layer 120 and an amorphous semiconductor material layer 130 are sequentially formed on the semiconductor layer 110, wherein the amorphous semiconductor material layer 130 can be made of semiconductor materials commonly used in the relevant technical field, including but not limited to: single substances, alloys or compounds of the IV main group, such as silicon, germanium, Si x Ge 1-x alloy, SiC; or, a semiconductor compound of the III-V main group, such as a binary compound of the III-V main group, a ternary compound of the III-V main group, or a quaternary compound of the III-V main group.

[0095] For some examples, see Figure 5b to Figure 5c, the step of forming the first insulating layer 120 can be performed by thermal oxidation or a thin film deposition process with high film thickness uniformity / in-plane film thickness uniformity; wherein the first insulating layer 120 may include a single layer composed of one selected from the following items or a composite layer composed of the above combination: oxides, nitrides or oxynitrides used to constitute the semiconductor substrate body material, especially oxides, nitrides, and oxynitrides containing IV main group elements; for example, oxides, nitrides, and oxynitrides of silicon, silicon germanium or silicon carbide; or metal oxides, wide bandgap semiconductor materials. In this embodiment, the first insulating layer 120 and the second insulating layer 260 can be made of the same or different materials.

[0096] Further, see Figure 5d , an amorphous semiconductor material layer 130 is formed on the first insulating layer 120, and a second insulating layer 260 is formed on the second substrate 20. The amorphous semiconductor material layer 130 and the second insulating layer 260 can serve as bonding interfaces in subsequent processes. Since the amorphous semiconductor material is easy to prepare and maintains a high in-plane film thickness uniformity, and the amorphous semiconductor material layer 130 contains fewer hydrogen bonds inside. When serving as a bonding interface in subsequent processes, it can better absorb the hydrogen generated by hydrophilic bonding and avoid bubble defects, so that the second insulating layer used in combination therewith can have a reduced film thickness; in particular, the second insulating layer can be formed as an ultra-thin film layer; more particularly, the thickness of the second insulating layer 260 is not more than 15nm.

[0097] Optionally, before the step of forming the amorphous semiconductor material layer 130, the step further includes: forming a functional stack on the first insulating layer 120 (see FIG. 8 ), the functional stack including one of a single crystal semiconductor layer, a polycrystalline semiconductor layer and an insulating dielectric layer or a combination thereof. Regardless of whether there is a functional stack between the amorphous semiconductor material layer and the first insulating layer, a defect-rich layer (not shown) is also formed between the second substrate 20 and the second insulating layer 260, and the defect-rich layer of the second substrate 20 includes one of a polycrystalline semiconductor material, a porous semiconductor material, a nanocrystalline material, a porous insulating dielectric material or a combination thereof.

[0098] Some examples include Figure 5c to Figure 5d As shown, the step of defining the preset stripping interface 101 can be performed after the step of forming the first insulating layer and before the step of forming the amorphous semiconductor material layer; wherein the step of forming the amorphous semiconductor material layer 130 is performed at a temperature lower than 350°C to avoid premature stripping of the preset stripping interface. The ion stripping position is preset in the supply substrate by an ion implantation process, and then the amorphous semiconductor material is deposited to avoid the depth uniformity of the ion stripping being affected by the amorphous semiconductor material layer.

[0099] Preferably, the amorphous semiconductor material is deposited on the first insulating layer 120 by one or more of a magnetron sputtering process and a plasma enhanced chemical vapor deposition (PECVD) process to form an amorphous semiconductor material layer 130. In a specific example, by controlling the temperature of the first substrate 10 below 200° C. and depositing the amorphous semiconductor material layer 130 by a magnetron sputtering process, the obtained film layer has high thickness uniformity and strong adhesion, and the deposited material layer contains less impurities and a lower concentration of hydrogen dangling bonds, which can avoid the precipitation of hydrogen in the high-temperature process after bonding.

[0100] In other examples, a plasma enhanced chemical vapor deposition process is used to deposit an amorphous semiconductor material on the first insulating layer 120 to form an amorphous semiconductor material layer 130. Due to the hydrogen in the deposition precursor used in the PECVD process, such as SiH4, a precursor for depositing amorphous silicon, a dehydrogenation process can be performed after the deposition step of the amorphous semiconductor material in the following manner: the obtained amorphous semiconductor material layer 130 is annealed, for example, the temperature of the first substrate is controlled below 350° C., or sulfur vapor is used for cleaning in a low-pressure and low-temperature environment to reduce the hydrogen dangling bonds in the amorphous semiconductor material layer, for example, the concentration of hydrogen dangling bonds in the amorphous semiconductor material layer is reduced to 10 19 / cm 3 the following.

[0101] Alternatively, if Figure 5g As shown, after the step of forming the amorphous semiconductor material layer 130 , a third insulating layer 240 b is formed on the amorphous semiconductor material layer 130 . The third insulating layer can serve as a bonding interface in subsequent processes.

[0102] Next, step S300 is performed to form an initial bonding structure in a manner that the first insulating layer, the amorphous semiconductor material layer, and the second insulating layer are sandwiched between the first substrate and the second substrate.

[0103] Specifically, the amorphous semiconductor material layer 130 and the second insulating layer 260 are used as bonding interfaces for pre-bonding to form an initial bonding structure; Figure 5f As shown, the first insulating layer 120, the amorphous semiconductor material layer 130 and the second insulating layer 260 are sandwiched between the first substrate and the second substrate. The amorphous semiconductor material has a relatively loose structure, which can absorb more hydrogen inside, reducing hydrogen bubble defects at the bonding interface, thereby reducing the thickness requirement of the semiconductor oxide material at the bonding interface.

[0104] As an example, before performing the pre-bonding step of the amorphous semiconductor material layer 130 and the second insulating layer 260, a planarization process is performed on at least one of the second insulating layer 260 and the amorphous semiconductor material layer 130; wherein the planarization process includes one or more of chemical mechanical polishing and physical mechanical polishing. Figure 5e As shown, after the amorphous semiconductor material layer 130 is subjected to chemical mechanical polishing and / or physical mechanical polishing processes, a polished surface 130p is obtained. Since the amorphous semiconductor material is easy to polish, a surface with extremely low roughness can be obtained, for example, a roughness as low as 0.1 nm, thereby improving the bonding quality.

[0105] In other examples, the surface processed by the planarization process is not limited to the bonding interface, but is also applicable to the film-forming surface where the bonding material is to be formed. For example, before the step of forming the second insulating layer 120 as the bonding interface, the exposed surface of the second substrate is planarized; or before the step of forming the amorphous semiconductor material layer 130 as the bonding interface, the exposed surface of the first insulating layer is planarized. After the above-mentioned film-forming surface is planarized, a bonding material layer is formed on the above-mentioned film-forming surface using a thin film deposition process with high uniformity. Since the surface quality is not significantly deteriorated and can still meet the bonding requirements, direct bonding can be performed on the bonding material layer.

[0106] like Figure 5g As shown, when the third insulating layer 240 b is formed on the amorphous semiconductor material layer 130 , a low-temperature bonding, such as a hydrophilic bonding, is formed at the interface between the third insulating layer 240 b and the second insulating layer 240 a .

[0107] Next, step S400 is performed to transfer the semiconductor layer onto the second substrate by removing a portion of the first substrate away from the amorphous semiconductor material layer.

[0108] Specifically, an ion stripping process is used to crack the first substrate along the position defined by the preset stripping interface, and a portion of the first substrate away from the amorphous semiconductor material layer is removed, and the semiconductor layer retained on the first insulating layer is formed as a top functional layer; the top functional layer can be made of the same or different material as the semiconductor substrate, and its material includes but is not limited to one or more combinations of semiconductor materials, piezoelectric materials, and conductive materials.

[0109] As an example, Figure 5hAs shown, the initial bonding structure obtained in step S300 is annealed, and ion stripping is performed along the preset stripping interface according to actual selection to initially form an SOI structure. The processing temperature for performing ion stripping can be determined according to the material of the bonding interface. Typically, the annealing process can be performed at a temperature of 350°C to 800°C. Of course, other commonly used stripping methods can also be used, and the SOI top layer structure can also be obtained by back polishing and thinning.

[0110] Optionally, after the step of removing a portion of the first substrate away from the amorphous semiconductor material layer, the exposed surface of the semiconductor layer is polished and thinned as necessary, and the semiconductor layer remaining on the second substrate 20 is formed as a top functional layer.

[0111] Next, step S500 is performed to reinforce the initial bonding structure, and to recrystallize the amorphous semiconductor material layer and transform the amorphous semiconductor material therein into a polycrystalline semiconductor material to form an intermediate semiconductor layer.

[0112] Specifically, the initial bonding structure is reinforced to cause the amorphous semiconductor material layer to recrystallize and transform the amorphous semiconductor material therein into a polycrystalline semiconductor material, while causing bonding reinforcement. Compared with the method of directly forming a polycrystalline material layer, the low internal stress of the amorphous semiconductor material is utilized to cause the amorphous semiconductor material to recrystallize and transform into a polycrystalline semiconductor material, which significantly improves the substrate warping caused by stress and can also improve the flatness of the substrate; moreover, the transfer of the semiconductor layer is achieved based on a preset stripping interface, and since the position of ion stripping is avoided from being affected by subsequent thin film deposition, an SOI substrate with good top functional layer thickness uniformity can be prepared. Taking a fully depleted silicon-on-insulator substrate, i.e., an FDSOI substrate, as an example, a substrate with a thickness uniformity of 1000 nm can be prepared through the above technical solution. of the top silicon layer.

[0113] As an example, the step of reinforcing the initial bonding structure includes heating the initial bonding structure, for example, causing a dehydration polymerization reaction at the interface to enhance the bonding strength, and at the same time causing the amorphous semiconductor material layer to recrystallize and convert the amorphous semiconductor material therein into a polycrystalline semiconductor material, so as to obtain Fig. 9 The SOI shown in the figure; wherein the temperature of the heat treatment is ≥1000°C and the duration is ≥1 hour. By controlling the heating rate of the heat treatment, the stress effect generated during the recrystallization of the amorphous semiconductor material can be avoided, and even defects can be introduced; preferably, the heat treatment step is performed at a heating rate of ≤3°C / min.

[0114] In another implementation, an SOI substrate 210 is used to replace the first substrate to manufacture the SOI substrate including the intermediate semiconductor layer; wherein the SOI substrate 210 includes a semiconductor layer 110, an insulating buried layer 102 and a back substrate 103, and there is no need to form the preset stripping interface. Figures 6a to 6f The schematic diagram shows the structure obtained at different stages in the preparation process of the SOI substrate including the intermediate semiconductor layer using SOI as the substrate for the wafer. Figures 6a to 6c As shown, a first insulating layer 120 and an amorphous semiconductor material layer 130 are sequentially formed on the semiconductor layer 110; Figure 6d As shown, the surface of the amorphous semiconductor material layer is polished, and the surface of the amorphous semiconductor material layer can meet the bonding requirements after the polishing process; Figure 6e After the bonding process shown, there is no need to perform an ion stripping process, and the steps of removing the buried insulating layer and the substrate layer are performed. Further, when removing the buried insulating layer, in one example, a back thinning process is used to remove the back substrate in the SOI substrate by grinding or etching, and the back substrate is stopped at the buried insulating layer 102; then, a selective etching process is used to remove the buried insulating layer 102, leaving the semiconductor layer 110, and a high-quality SOI structure is obtained. The specific process can be referred to the description in the above example.

[0115] Alternatively, if Figure 6e As shown, after the step of polishing the surface of the amorphous semiconductor material layer, a third insulating layer 240b is formed on the resulting surface, and the third insulating layer 240b serves as a bonding interface in subsequent processes to pre-bond the second insulating layer 240a and the third insulating layer 240b.

[0116] Embodiment 2

[0117] This embodiment provides a method for preparing an SOI substrate including an intermediate semiconductor layer, comprising the following steps:

[0118] S100': providing a first substrate and a second substrate, wherein the first substrate comprises a first substrate and a semiconductor layer located on the first substrate;

[0119] S200': forming a first insulating layer and an amorphous semiconductor material layer in sequence on the second substrate, and forming a second insulating layer on the semiconductor layer;

[0120] S300': forming an initial bonding structure in a manner that the first insulating layer, the amorphous semiconductor material layer and the second insulating layer are sandwiched between the first substrate and the second substrate;

[0121] S400': transferring the semiconductor layer to the second substrate by removing a portion of the first substrate away from the amorphous semiconductor material layer;

[0122] S500 ′: reinforcing the initial bonding structure, and causing the amorphous semiconductor material layer to recrystallize and transform the amorphous semiconductor material therein into a polycrystalline semiconductor material to form an intermediate semiconductor layer.

[0123] It should be noted that the above sequence does not strictly represent the execution sequence of the method for preparing the SOI substrate structure protected by the present invention, and those skilled in the art may change the sequence of steps according to the actual process.

[0124] In this embodiment, step S200' can be performed in a similar manner to step S200, except that the first insulating layer 220 is formed on the second substrate 20, and the second insulating layer 160 is formed on the semiconductor layer 110. Figures 7a to 7d , which is a schematic diagram of the structures obtained at different stages of the method for preparing a SOI substrate including an intermediate semiconductor layer according to this embodiment.

[0125] Specifically, in step S200', the first substrate includes a first main surface and a second main surface relative to each other. After the step of forming the second insulating layer 160 on the first main surface of the first substrate, ion implantation is performed from the side of the first substrate on which the second insulating layer is formed, and a preset stripping interface 101 is defined in the first substrate. The section of the first substrate between its first main surface and the preset stripping interface is formed as a semiconductor layer.

[0126] Accordingly, the step of forming the amorphous semiconductor material layer may adopt, in addition to the method described in the previous embodiment, other deposition processes with higher film uniformity may also be used.

[0127] In some examples, step S200' further includes: performing a planarization process, which may be performed before the step of forming the second insulating layer 160 and the amorphous semiconductor material layer 230; or, after the above-mentioned forming step; preferably, Figure 7b As shown, after the step of forming the amorphous semiconductor material layer 230 , a planarization process is performed on the amorphous semiconductor material layer 230 , and the planarization process includes one or more of a chemical mechanical polishing (CMP) process and a physical mechanical polishing process.

[0128] In step S300', the first substrate and the second substrate 20 are bonded by using the amorphous semiconductor material layer 230 and the second insulating layer 160 as bonding interfaces. Figure 7cAs shown, the first substrate and the second substrate sandwich the first insulating layer, the amorphous semiconductor material layer and the second insulating layer therebetween.

[0129] Steps S400' to S500' in this embodiment can be performed in a manner substantially similar to steps S400 to S500. Figure 7d As shown, the first substrate is peeled off along the preset peeling interface 101 , so that a portion of the first substrate away from the first insulating layer is removed.

[0130] In another implementation, an SOI substrate 210 is used to replace the first substrate to manufacture the SOI substrate including the intermediate semiconductor layer; wherein the SOI substrate 210 includes a semiconductor layer 110, an insulating buried layer 102 and a back substrate 103, and there is no need to form the preset stripping interface. Figures 8a to 8e The schematic diagram shows the structure obtained at different stages in the preparation process of the SOI substrate including the intermediate semiconductor layer using SOI as the substrate for the wafer. Figure 8a to Figure 8b As shown, a second insulating layer 160 is formed on the semiconductor layer 110; Figure 8c As shown, a first insulating layer 220 and an amorphous semiconductor material layer 230 are sequentially formed on the second substrate 20. Further, the surface of the amorphous semiconductor material layer is polished, and the polished surface 230p of the amorphous semiconductor material layer can meet the bonding requirements. Figure 8e After the bonding process shown, there is no need to perform an ion stripping process, and the insulating buried layer and the substrate layer removal steps are performed. Further, when removing the insulating buried layer, in one example, a back thinning process is used to remove the back substrate in the SOI substrate by grinding or etching, and the back substrate is stopped at the insulating buried layer 102; then, a selective etching process is used to remove the insulating buried layer 102, leaving the semiconductor layer 110, and a high-quality SOI structure is obtained. The specific process can be referred to the description in the above example.

[0131] Optionally, after the step of polishing the surface of the amorphous semiconductor material layer, a third insulating layer is formed on the obtained surface, and the third insulating layer serves as a bonding interface in a subsequent process to bond the first substrate and the second substrate.

[0132] Embodiment 3

[0133] This embodiment provides an SOI substrate including an intermediate semiconductor layer. The SOI substrate is preferably prepared by the method for preparing the SOI substrate including an intermediate semiconductor layer described above, and of course, other methods may also be used for preparation.

[0134] The SOI substrate includes a substrate layer 310, an insulating buried layer and a top functional layer, and an intermediate semiconductor layer 30 is inserted between the substrate layer and the top functional layer. The intermediate semiconductor layer 30 is formed based on a polycrystalline semiconductor material that is crystallized from an amorphous semiconductor material layer. The insulating buried layer includes a first insulating layer and a second insulating layer, and the intermediate semiconductor layer is sandwiched between the first insulating layer and the second insulating layer.

[0135] The intermediate semiconductor layer 30 includes a first main surface and a second main surface opposite to each other. Figures 9 to 13 Schematic diagrams of the structures of several examples of SOI substrates including an intermediate semiconductor layer. Fig. 9 As shown, the first insulating layer 120 is located on the first main surface of the intermediate semiconductor layer, and the second insulating layer 260 is located on the second main surface of the intermediate semiconductor layer; vice versa, as shown in Fig.10 Specifically, the first insulating layer 120 and the second insulating layer 260 respectively include a single layer composed of one of the following materials, or a composite layer composed of the above combination: oxides, nitrides, oxynitrides containing IV main group elements, metal oxides and wide bandgap semiconductor materials; the material of the top functional layer is selected from one or more combinations of semiconductor materials, piezoelectric materials, and conductive materials.

[0136] Preferably, the intermediate semiconductor layer is sandwiched between the first insulating layer and the second insulating layer by bonding the second insulating layer and the amorphous semiconductor material layer, wherein the second insulating layer may have a thickness of no more than 15 nm.

[0137] The SOI substrate further includes an additional functional stack, which may be disposed between the intermediate semiconductor layer 30 and the substrate layer 310 or the top functional layer. In some examples, for example Fig. 9 As shown, the functional stack 40 is disposed between the substrate layer 310 and the intermediate semiconductor layer 30; wherein the functional stack 40 is selected from one of a polycrystalline semiconductor layer, a single crystal semiconductor layer and an insulating material layer or a combination thereof. In a specific example, the functional stack 40 includes a defect-rich layer 410, and the defect-rich layer 410 is disposed between the substrate layer 310 and the insulating buried layer, for example, Fig.10 As shown, between the substrate layer 310 and the second insulating layer 220, the insulating buried layer is kept away from the substrate layer, thereby reducing the influence of the charges in the insulating buried layer (eg, silicon oxide) on the substrate layer, thereby satisfying the radio frequency shielding function.

[0138] Furthermore, a part or the whole of the functional stack can be configured as a patterned functional layer 50, and a graphical structure is provided in the patterned functional layer 50. Figures 11 to 13As shown, in some examples, the patterned structure may be composed of an arrangement of cavities and functional material regions, or may be composed of an arrangement of heterogeneous functional material regions.

[0139] When a cavity 510 is provided in the stacked structure, the cavity 510 may be located in one of the insulating buried layer, the intermediate semiconductor layer, the second insulating layer 220 and the top functional layer 230 or at the interface, and the cavity 510 may be configured as a vacuum cavity or a cavity filled with air.

[0140] The SOI substrate is used for FDSOI devices, dual-gate devices, gate-all-around (GAA) devices, vertical channel devices or similar devices. The application of the above-mentioned SOI substrate can give SOI devices design flexibility and expand the application scenarios of SOI substrates.

[0141] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing an SOI substrate comprising an intermediate semiconductor layer, characterized in that: The following steps are involved: Providing a first substrate and a second substrate, wherein the first substrate includes a first substrate and a semiconductor layer located on the first substrate; forming a first insulating layer and an amorphous semiconductor material layer on one of the semiconductor layer and the second substrate in sequence, and forming a second insulating layer on the other of the semiconductor layer and the second substrate; forming an initial bonding structure in a manner that the first insulating layer, the amorphous semiconductor material layer and the second insulating layer are sandwiched between the first substrate and the second substrate; transferring the semiconductor layer onto the second substrate by removing a portion of the first substrate away from the amorphous semiconductor material layer; The initial bonding structure is reinforced, and the amorphous semiconductor material layer is recrystallized and the amorphous semiconductor material therein is transformed into a polycrystalline semiconductor material to form an intermediate semiconductor layer.

2. The method for preparing an SOI substrate according to claim 1, characterized in that: Before the step of forming the amorphous semiconductor material layer, the method further includes: forming a functional stack on the first insulating layer, wherein the functional stack includes one or a combination of a single crystal semiconductor layer, a polycrystalline semiconductor layer and an insulating dielectric layer.

3. The method for preparing an SOI substrate according to claim 1, characterized in that: The first substrate is selected as a semiconductor substrate. After the step of forming the first insulating layer, a portion of the first substrate away from the amorphous semiconductor material layer is removed in the following manner: ion implantation is performed from the side of the first substrate where the first insulating layer is formed, and a preset stripping interface is defined in the first substrate, and the implanted ions include one of hydrogen ions and helium ions; an ion stripping process is used to crack the first substrate along a position defined by the preset stripping interface.

4. The method for preparing an SOI substrate according to claim 1, characterized in that: A first insulating layer and an amorphous semiconductor material layer are sequentially formed on the second substrate, and a second insulating layer is formed on the semiconductor layer; wherein the first insulating layer and the second insulating layer respectively include a single layer composed of one selected from the following materials, or a composite layer composed of multiple thereof: oxides, nitrides, oxynitrides containing elements of the IV main group, metal oxides and wide bandgap semiconductor materials.

5. The method for preparing an SOI substrate according to claim 1, characterized in that: The step of forming the amorphous semiconductor material layer comprises: controlling the temperature of the first substrate to be below 350° C. and depositing the amorphous semiconductor material on the first insulating layer by a plasma enhanced chemical vapor deposition process; then performing a dehydrogenation process to reduce the hydrogen dangling bond concentration in the amorphous semiconductor material layer to less than 10 19 / cm 3 .

6. The method for preparing an SOI substrate according to claim 1, characterized in that: The step of forming the amorphous semiconductor material layer comprises: By controlling the temperature of the first substrate to be below 200° C., amorphous semiconductor material is deposited on the first insulating layer by using a magnetron sputtering process.

7. The method for preparing an SOI substrate according to claim 5 or 6, characterized in that: After the step of forming the amorphous semiconductor material layer, the method includes: performing pre-bonding using the amorphous semiconductor material layer and the second insulating layer as bonding interfaces to form an initial bonding structure, wherein the thickness of the second insulating layer is not greater than 15 nm.

8. The method for preparing an SOI substrate according to claim 1, characterized in that: After the step of forming the amorphous semiconductor material layer on the first insulating layer, the method further comprises: forming a third insulating layer on the amorphous semiconductor material layer; The third insulating layer and the second insulating layer are used as bonding interfaces for pre-bonding to form an initial bonding structure.

9. The method for preparing an SOI substrate according to claim 1, characterized in that: Also includes: Before the step of forming the second insulating layer, a planarization process is performed on the exposed surface of the semiconductor layer or the second substrate; Before the step of forming the amorphous semiconductor material layer, performing a planarization process on the first insulating layer; or, performing a planarization process on at least one of the second insulating layer and the amorphous semiconductor material layer; The planarization process includes one or more of a chemical mechanical polishing process and a physical mechanical polishing process.

10. The method for preparing an SOI substrate according to claim 1, characterized in that: The step of reinforcing the initial bonding structure is performed after removing a portion of the first substrate, and includes: The initial bonding structure is subjected to a heating treatment to cause bonding reinforcement, and at the same time the amorphous semiconductor material layer is recrystallized and the amorphous semiconductor material therein is transformed into a polycrystalline semiconductor material; wherein the reinforcement treatment includes a heating temperature ≥ 1000°C and a duration ≥ 1 hour.

11. An SOI substrate comprising an intermediate semiconductor layer, characterized in that: The invention comprises a substrate layer, an insulating buried layer and a top functional layer, wherein an intermediate semiconductor layer is inserted between the substrate layer and the top functional layer, the insulating buried layer comprises a first insulating layer and a second insulating layer, the intermediate semiconductor layer is formed based on a polycrystalline semiconductor material which is a result of crystallization transformation of an amorphous semiconductor material layer, and the intermediate semiconductor layer is sandwiched between the first insulating layer and the second insulating layer.

12. The SOI substrate according to claim 11, characterized in that: The intermediate semiconductor layer is sandwiched between the first insulating layer and the second insulating layer by bonding the amorphous semiconductor material layer to the second insulating layer, wherein the thickness of the second insulating layer is not greater than 15 nm.

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