Multi-chip 3D stacked packaging structure

Abstract

The invention relates to a multi-chip 3D stacked packaging structure, which comprises a stacked chip set, a plastic package layer and a substrate, and is characterized in that the stacked chip set comprises n layers of stacked chips, the back surfaces of the first chip to the (n-1) th chip are sequentially stacked on the substrate, and part of the front surface of the nth chip is stacked on the (n-1) th chip; the front surfaces of the first chip to the (n-1) th chip are bonded on the substrate through leads; the nth chip is bonded to the substrate through flip-chip bonding. And the part, which is not stacked on the (n-2) th chip, of the back surface of the (n-1) th chip is welded with the heat dissipation cushion block through the heat dissipation welding layer. Heat of the stacked chips is conducted to the heat dissipation cushion block through the heat dissipation welding layer, the heat of the stacked chips is conducted to the radiator through the heat dissipation cushion block, and heat of the stacked chip set, especially the upper layer chips, is reduced. Meanwhile, as the plastic packaging layer does not cover the back surface of the nth chip, heat generated by the nth chip can be directly dissipated through the back surface. And the failure risk caused by overhigh junction temperature of the stacked upper-layer chips is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging technology, and in particular to a multi-chip 3D stacking packaging structure. Background Art

[0002] With the continuous development of electronic information technology, chip packaging technology is moving towards miniaturization and high integration. The emergence of three-dimensional packaging technology has greatly increased the storage capacity and the utilization ratio of packaging area, and is therefore widely used.

[0003] 3D stacking packaging, that is, encapsulating two or more chips in the same package in the vertical direction, and using TSV (Through Silicon Via) silicon through-hole technology or wire bonding (Wire Bonding) to achieve electrical interconnection between chips and chips, chips and substrates. The use of 3D stacking packaging can greatly increase the ratio of storage capacity and packaging area. At present, most 3D packaging solutions are mainly based on epoxy molding compound packaging. Epoxy molding compound is a composite material composed of epoxy resin as a matrix, silicon powder, curing agent, etc., and the material properties show dynamic changes during the curing process. Due to the characteristics of the plastic material itself, there are still some reliability deficiencies in use, which are not as good as metal and ceramic packaging. For example, due to the difference in material properties and thermal expansion coefficients between the materials of each component, there will be warping; in actual production, the bonding wires will be offset due to melt flow during the plastic sealing process; in actual use, the stacked upper chip will have the risk of failure due to excessive junction temperature.

[0004] Therefore, it is necessary to continuously optimize the design of three-dimensional packaging structures to improve the reliability of chip packaging structure devices. Summary of the invention

[0005] The object of the present invention is to provide a novel multi-chip 3D stacking packaging structure to solve the above problems.

[0006] To achieve the purpose of the present invention, the technical solution is as follows: A multi-chip 3D stacked packaging structure includes a stacked chipset, a plastic sealing layer, and a substrate, wherein: the stacked chipset includes n layers of stacked chips, a first chip, a second chip to an n-1th chip, and an nth chip; the back of the first chip is located on the substrate, the backs of the second chip to the n-1th chip are partially stacked on the first chip in sequence, and the front of the nth chip is partially stacked on the n-1th chip; the fronts of the first chip, the second chip to the n-1th chip are bonded to the substrate through wire bonding; the nth chip is flip-chip bonded to the substrate; the multi-chip 3D stacked packaging structure also includes a heat dissipation welding layer and a heat dissipation pad, the unstacked back of the n-1th chip is welded to the heat dissipation welding layer, and the heat dissipation welding layer is welded to the heat dissipation pad; n is an integer greater than or equal to 3.

[0007] Furthermore, a first through hole is formed on the substrate, and a first opening and a second opening are formed on the upper and lower surfaces of the substrate; the heat dissipation pad is embedded in the first through hole and is clamped at the interface between the first opening and the second opening of the through hole.

[0008] Furthermore, the multi-chip 3D stacked packaging structure also includes a PCB board for board-level packaging, a thermal interface material layer and a heat sink; the PCB board for board-level packaging is provided with a second through hole, the second through hole is opposite to the heat dissipation pad, the heat dissipation pad is adhered to the heat sink through the thermal interface material layer, and the heat sink is embedded in the second through hole.

[0009] Furthermore, the heat sink is a "convex" structure, including a base and a convex top block; the convex top block of the heat sink is embedded in the second through hole and adhered to the heat dissipation pad through the thermal interface material layer.

[0010] Furthermore, the unstacked portions of the back sides of the second chip to the (n-1)th chip are all welded to the heat dissipation welding layer.

[0011] Furthermore, the multi-chip 3D stacked packaging structure also includes a first solder ball array layer, a TSV adapter board and a second solder ball array layer; the unstacked portion of the front side of the nth chip is electrically connected to the first solder ball array layer, the first solder ball array layer is electrically connected to the TSV adapter board, the TSV adapter board is electrically connected to the second solder ball array layer, and the second solder ball array layer is electrically connected to the substrate.

[0012] Furthermore, the side walls of the heat dissipation pad are attached to the side walls of the first chip to the (n-2)th chip.

[0013] Furthermore, the plastic encapsulation layer is located on the substrate, wrapping around the first chip, the second chip, the leads, the stacked chipset, the heat dissipation welding layer, the heat dissipation pad, the first solder ball array layer, the TSV adapter board and the external gap of the second solder ball array layer, and the height of the plastic encapsulation layer is flush with the back side of the nth chip.

[0014] Furthermore, n is selected from 3 or 4.

[0015] The present invention also provides a method for manufacturing the above-mentioned multi-chip 3D stacked packaging structure, comprising the following steps: S1, completing the wiring structure on the substrate and opening the first through hole; S2, welding the first chip to the substrate and wire bonding; S3, embedding the heat dissipation pad into the first through hole of the substrate; S4, coating the first chip with thermal conductive adhesive to bond the second chip, and completing welding of the second chip to the heat dissipation pad through the heat dissipation welding layer; S5, repeat step S4 until the n-1th chip is welded; S6, completing wire bonding from the second chip to the n-1th chip; S7, completing welding with the TSV adapter board through the second solder ball array layer on the substrate; S8, soldering the nth chip to the TSV adapter board through the first solder ball array layer, and pasting it to the n-1th chip; S9, injecting plastic sealing layer; S10, a second through hole is opened in the PCB board for preparing board-level packaging, and the heat sink is assembled with the PCB board for preparing board-level packaging; S11, bonding the plastic-sealed substrate to the PCB board for preparing board-level packaging.

[0016] Compared with the prior art, the present invention has the following significant advantages: The heat of the stacked chips is conducted to the heat dissipation pad through the heat dissipation welding layer, and the heat dissipation pad conducts it to the radiator to reduce the heat of the stacked chipset, especially the upper chip. The nth chip conducts heat to the substrate by flipping the chip, using the first solder ball array layer, TSV adapter plate and the second solder ball array layer. At the same time, since the plastic encapsulation layer does not cover the back of the nth chip, the heat generated by the nth chip can be directly dissipated through the back. This reduces the risk of failure of the stacked upper chips due to excessive junction temperature. At the same time, since the top nth chip is electrically connected to the substrate by flipping the chip, the use of leads is reduced, the height of the plastic encapsulation layer is effectively reduced, and the offset of the bonding leads and the junction temperature of the upper chip are reduced. Through the connection between the n-1th chip and the heat dissipation welding layer and the heat dissipation pad, the incidence of warping can be reduced to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the structure of embodiment 1 of the present invention.

[0018] Figure 2 It is a structural diagram of embodiment 2 of the present invention.

[0019] In the figure, 1 is a substrate, 11 is a first through hole, 21 is a first chip, 22 is a second chip, 23 is an n-1th chip, 24 is an nth chip, 3 is a heat dissipation welding layer, 4 is a heat dissipation pad, 5 is a thermal interface material layer, 6 is a heat sink, 7 is a plastic sealing layer, 8 is a PCB board for preparing board-level packaging, 81 is a second through hole, 91 is a first solder ball array layer, 92 is a TSV adapter board, and 93 is a second solder ball array layer. DETAILED DESCRIPTION

[0020] The following is a further detailed description of the multi-chip 3D stacked packaging structure and packaging method provided by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description and claims, the advantages and features of the present invention will become clearer. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, unless otherwise stated, the features in different embodiments of the present invention may be combined with each other. For example, a feature in the second embodiment may be used to replace a corresponding or functionally identical or similar feature in the first embodiment, and the resulting embodiment also falls within the scope of disclosure or the scope of record of this application.

[0021] Example 1 like Figure 1 As shown, a multi-chip 3D stacked packaging structure: the stacked chipset includes n (n is 3) layers of stacked chips, the first chip 21, the n-1th (n-1 is 2)th chip 23 and the nth (n is 3)th chip 24; wherein the back of the first chip 21 is located on the substrate 1, the back of the second chip 22 is partially stacked on the first chip 21, and the front of the third chip 23 is partially stacked on the second chip 22. The front of the first chip 21 and the second chip 22 are bonded to the substrate 1 by wire bonding. The front of the first chip 21 and the second chip 22 are active surfaces, and the back of the third chip 23 is an active surface.

[0022] The back side of the second chip 22 that is not stacked on the first chip 21 is welded to the heat dissipation welding layer 3, so that the heat dissipation welding layer 3 and the second chip 22 are heat-conducted. The heat dissipation welding layer 3 is welded to the heat dissipation pad 4, and the heat dissipation pad 4 and the heat dissipation welding layer 3 are heat-conducted. The heat dissipation pad 4 is a rectangular parallelepiped. And the side wall of the heat dissipation pad 4 is in contact with the side wall of the first chip 21.

[0023] The multi-chip 3D stacked packaging structure has a first through hole 11 on the substrate 1, and a first opening and a second opening on the upper and lower surfaces of the substrate 1. The heat dissipation pad 4 is embedded in the first through hole 11 and is clamped at the interface between the first opening and the second opening of the through hole.

[0024] In this embodiment, if Figure 1 As shown, in the packaging structure of the multi-chip 3D stack, a PCB board 8 for preparing board-level packaging is also included, wherein: the PCB board 8 for preparing board-level packaging is provided with a second through hole 81. The heat dissipation pad 4 is adhered to the heat sink 6 through the thermal interface material layer. The heat sink 6 is a "convex" structure, including a base and a convex top block. The second through hole 81 is opposite to the heat dissipation pad 4, and the convex top block of the heat sink 6 is embedded in the second through hole 81 and adhered to the heat dissipation pad 4 through the thermal interface material layer.

[0025] The front portion of the third chip 24 that is not stacked on the second chip 22 is electrically connected to the substrate 1 through the first solder ball array layer 91, the TSV adapter plate 92 and the second solder ball array layer 93. Figure 1 As shown, the unstacked portion of the front side of the nth chip 24 is electrically connected to the first solder ball array layer 91, the first solder ball array layer 91 is electrically connected to the TSV adapter plate 92, the TSV adapter plate 92 is electrically connected to the second solder ball array layer 93, and the second solder ball array layer 93 is electrically connected to the substrate 1. The first solder ball array layer 91 and the second solder ball array layer 93 are composed of a number of bumps (bumps) arranged horizontally and vertically, and the material can be gold, copper or solder. The bump diameter of the first solder ball array is smaller than the bump diameter of the second solder ball array. The TSV adapter plate 92 is responsible for merging and leading out the power supply and ground inside the third chip to reduce the number of ports.

[0026] Furthermore, the multi-chip 3D stacked packaging structure also includes a plastic encapsulation layer 7, which is located on the substrate 1 and wraps around the first chip 21, the second chip 22, the leads, the stacked chipset, the heat dissipation welding layer 3, the heat dissipation pad 4, the first solder ball array layer 91, the TSV adapter board 92 and the external gap of the second solder ball array layer 93, and the height of the plastic encapsulation layer is flush with the back side of the third chip 24.

[0027] The heat of the second chip 22 and the third chip 24 is conducted to the heat dissipation pad 4 through the heat dissipation welding layer 3, and the heat dissipation pad 4 conducts it to the radiator 6. To reduce the heat of the stacked chipset and the upper chip. The third chip 24 conducts heat to the substrate 1 by flip-chip method using the first solder ball array layer 91, the TSV adapter plate 92 and the second solder ball array layer 93. At the same time, since the plastic encapsulation layer does not cover the back of the third chip 24, the heat generated by the third chip 24 can be directly dissipated through the back. This reduces the risk of failure of the stacked upper chips due to excessively high junction temperature. At the same time, since the third chip on the top layer is electrically connected to the substrate 1 by flip-chip method, the use of leads is reduced, the height of the plastic encapsulation layer 7 is effectively reduced, and the offset of the bonding leads and the junction temperature of the upper chip are reduced. Through the connection between the second chip 22 in the middle layer and the heat dissipation welding layer 3 and the heat dissipation pad 4, the incidence of warping can be reduced to a certain extent.

[0028] Accordingly, the packaging method of the multi-chip 3D stacked packaging structure of this embodiment includes the following steps: S1, completing the wiring structure on the substrate 1 and opening the first through hole 11; S2, welding the first chip 21 to the substrate 1, wire bonding; S3, embedding the heat dissipation pad into the first through hole 11 of the substrate 1; S4, coating the first chip 21 with a thermally conductive adhesive to attach the second chip 22 and completing welding of the second chip 22 to the heat dissipation pad 4 through the heat dissipation welding layer 3; S5, completing the wire bonding of the second chip 22; S6, completing welding with the TSV adapter board 92 on the substrate 1 through the second solder ball array layer 93; S7, the third chip 24 is welded to the TSV adapter plate 92 through the first solder ball array layer 91, and is pasted to the second chip 22; S8, injecting plastic sealing layer 7; S9, a second through hole 81 is opened in the PCB board 8 for preparing board-level packaging, and the heat sink 6 is assembled with the PCB board 8 for preparing board-level packaging; S10, bonding the plastic-sealed substrate 1 to the PCB board 8 for preparing board-level packaging.

[0029] Example 2 like Figure 2 As shown, the difference from Example 1 is that: a multi-chip 3D stacked packaging structure includes: a stacked chipset includes n (n is 4) layers of stacked chips, a first chip 21, a second chip 22 to an n-1th (n-1 is three) chip 23 and an nth (n is four) chip 24; wherein, the back of the first chip 21 is located on the substrate 1, the back of the second chip 22 to the n-1th (n-1 is three) chip 23 is partially stacked on the first chip 21, and the front of the nth (n is four) chip 24 is partially stacked on the n-1th (n-1 is three) chip 23. The front of the first chip 21, the n-2th (n-2 is two) chip 22 and the n-1th (n-1 is three) 23 chip is bonded to the substrate 1 by wire bonding. The front of the first chip 21, the second chip 22 and the n-1th (n-1 is three) chip 23 is an active surface, and the back of the nth (n is four) chip 24 is an active surface.

[0030] The back side of the n-1th (n-1 is three) chip 23 that is not stacked on the chip is welded to the heat dissipation welding layer 3, so that the heat dissipation welding layer 3 and the n-1th (n-1 is three) chip 23 are heat-conducted. The heat dissipation welding layer 3 is welded to the heat dissipation pad 4, and the heat dissipation pad 4 and the heat dissipation welding layer 3 are heat-conducted.

[0031] Further, the backside portions of the second chip 22 to the n-1th (n-1 is three) chip 23 that are not stacked on the chip are all welded to the heat dissipation welding layer 3, and the heat dissipation welding layer 3 is welded to the heat dissipation pad 4. Heat conduction is performed through the heat dissipation pad 4 and the heat dissipation welding layer 3. The heat dissipation pad 4 is an irregular rectangular parallelepiped. The side walls of the heat dissipation pad 4 are bonded to the side walls of the first chip 21 to the n-2th (n-2 is two) chip 22.

[0032] Accordingly, the packaging method of the multi-chip 3D stacked packaging structure of this embodiment includes the following steps: S1, completing the wiring structure on the substrate 1 and opening the first through hole 11; S2, welding the first chip 21 to the substrate 1, wire bonding; S3, embedding the heat dissipation pad 4 into the first through hole 11 of the substrate 1; S4, coating the first chip 21 with heat-conducting adhesive to bond the second chip 22, and completing welding of the second chip 22 to the heat-dissipating pad 4 through the heat-dissipating welding layer 3; S5, coating the second chip 22 with a thermally conductive adhesive to adhere the third chip 23 and completing welding the third chip 23 to the heat dissipation pad 4 through the heat dissipation welding layer 3; S6, completing the wire bonding of the second chip 22 and then completing the wire bonding of the third chip 23; S7, completing welding with the TSV adapter board 92 on the substrate 1 through the second solder ball array layer 93; S8, soldering the fourth chip 24 to the TSV adapter board 92 through the first solder ball array layer 91, and pasting it to the third chip 23; S9, injecting plastic sealing layer 7; S10, a second through hole 81 is opened in the PCB board 8 for preparing board-level packaging, and the heat sink 6 is assembled with the PCB board 8 for preparing board-level packaging; S11, bonding the plastic-sealed substrate 1 to the PCB board 8 for preparing board-level packaging.

Claims

1. A multi-chip 3D stacked packaging structure, comprising a stacked chipset, a plastic encapsulation layer (7), and a substrate (1), characterized in that: The stacked chipset comprises n layers of stacked chips, namely, a first chip (21), a second chip (22) to an n-1th chip (23), and an nth chip (24); wherein the back surface of the first chip (21) is located on a substrate (1), and portions of the back surfaces of the second chips (22) to the n-1th chip (23) are sequentially stacked on the first chip (21), and portions of the front surface of the nth chip (24) are stacked on the n-1th chip (23); the first chip (21), the second chip (22) to the n-1th chip (23) The front side of the n-1 chip (24) is bonded to the substrate (1) via wire bonding; the portion of the n-1 chip (24) not stacked on the n-1 chip (23) is bonded to the substrate (1) via flip-chip bonding; the multi-chip 3D stacked packaging structure further comprises a heat dissipation welding layer (3) and a heat dissipation pad (4); a portion of the heat dissipation pad (4) is buried in the substrate (1), and a portion of the back side of the n-1 chip (23) not stacked on the n-2 chip is welded to the heat dissipation pad (4) via the heat dissipation welding layer (3); and n is an integer greater than or equal to 3.

2. The multi-chip 3D stacked packaging structure according to claim 1, characterized in that: The base plate (1) is provided with a first through hole (11), and an upper opening and a lower opening are formed on the base plate (1); a portion of the heat dissipation pad (4) is embedded in the first through hole (11) and is clamped at the upper opening and the lower opening.

3. The multi-chip 3D stacked packaging structure according to claim 2, characterized in that: The multi-chip 3D stacked packaging structure further comprises a PCB board (8), a thermal interface material layer (5) and a heat sink (6); the PCB board (8) is provided with a second through hole (81), the second through hole (81) is opposite to the heat sink pad (4), the heat sink pad (4) is adhered to the heat sink (6) through the thermal interface material layer (5), and the heat sink (6) is embedded in the second through hole (81).

4. The multi-chip 3D stacked packaging structure according to claim 3, characterized in that: The heat sink (6) is a "convex" structure, comprising a base and a convex top block; the convex top block of the heat sink (6) is embedded in the second through hole (81) and adhered to the heat dissipation pad (4) through the thermal interface material layer (5).

5. The multi-chip 3D stacked packaging structure according to claim 2, characterized in that: The unstacked portions of the back surfaces of the second chip (22) to the n-1th chip (23) are all welded to the heat dissipation welding layer (3).

6. The multi-chip 3D stacked packaging structure according to claim 2, characterized in that: The multi-chip 3D stacked packaging structure further comprises a first solder ball array layer (91), a TSV adapter plate (92) and a second solder ball array layer (93); the unstacked portion of the front side of the nth chip (24) is electrically connected to the first solder ball array layer (91), the first solder ball array layer (91) is electrically connected to the TSV adapter plate (92), the TSV adapter plate (92) is electrically connected to the second solder ball array layer (93), and the second solder ball array layer (93) is electrically connected to the substrate (1).

7. The multi-chip 3D stacked packaging structure according to claim 5, characterized in that: The side wall of the heat dissipation pad (4) is bonded to the side walls of the first chip (21) to the n-2th chip.

8. The multi-chip 3D stacked packaging structure according to claim 6, characterized in that: The plastic encapsulation layer (7) is located on the substrate (1), and wraps around the first chip (21), the second chip (22), the leads, the stacked chip set, the heat dissipation welding layer (3), the heat dissipation pad (4), the first solder ball array layer (91), the TSV adapter plate (92) and the external gap of the second solder ball array layer (93), and the height of the plastic encapsulation layer (7) is flush with the back surface of the nth chip (24).

9. The multi-chip 3D stacked packaging structure according to claim 1, characterized in that: n is selected from 3 or 4.

10. A method for manufacturing a multi-chip 3D stacked packaging structure as claimed in claim 8, characterized in that: The method comprises the following steps: S1, preparing a substrate (1), wherein the substrate (1) has a completed wiring structure, is provided with a first through hole (11), and a heat dissipation pad (4) is embedded in the first through hole (11) of the substrate (1); S2, welding the first chip (21) to the substrate (1), and wire bonding; S3, coating the first chip (21) with heat-conductive adhesive to bond the second chip (22), and completing welding of the second chip (22) to the heat-dissipating pad (4) via the heat-dissipating welding layer (3); S4, repeating step S4 until the n-1th chip (23) is bonded and welded; S5, completing wire bonding from the second chip (22) to the n-1th chip (23); S6, completing welding with the TSV adapter plate (92) on the substrate (1) through the second solder ball array layer (93); S7, welding the nth chip (24) to the TSV adapter plate (92) through the first solder ball array layer (91), and pasting the n-1th chip (23); S8, injecting the plastic sealing layer (7); S9, a second through hole (81) is formed in the PCB board (8), and the heat sink (6) is assembled with the PCB board (8); S10, bonding the plastic-sealed substrate (1) to the PCB (8).

Images