Square flat leadless package and manufacturing method thereof

Abstract

The invention provides a quad flat no-lead package and a manufacturing method thereof. The quad flat no-lead package comprises a lead frame, a plurality of conductive columns, a chip and a molding compound. The lead frame comprises a chip seat and a plurality of leads. The plurality of conductive columns are arranged on the plurality of leads and electrically connected with the plurality of leads, each of the plurality of conductive columns comprises a base part and a column body part connected with the base part, and the maximum outer diameter of the base part is larger than the maximum outer diameter of the column body part. The chip is arranged on the chip seat and is electrically connected with the plurality of leads. The molding compound covers the chip, the lead frame and the plurality of conductive pillars, wherein the molding compound exposes the lower surfaces of the plurality of leads and the top surfaces of the plurality of conductive pillars.

Description

Technical Field

[0001] The present disclosure relates to a quad flat no-lead package and a method for manufacturing the same. Background Art

[0002] As electronic products become smaller, the market for handheld products continues to expand. Driven primarily by the mobile phone and digital assistant markets, manufacturers of these devices are facing the challenge of product size reduction and the need for more personal computer-like functions. The additional functions can only be achieved through high-performance logic integrated circuits combined with increased memory capacity. In response to this challenge, smaller printed circuit boards will put pressure on surface mount component manufacturers to design products.

[0003] In today's handheld product market, many widely used components are beginning to transition from leaded to leadless form. This makes electronic components increasingly designed to save printed circuit board space. Therefore, the extra space saved can be used to configure components required for additional device functions.

[0004] The currently widely used leadless packaging structures such as quad flat no leads (QFN) or dual flat no-lead (DFN) mostly have electrical connection pads on one side as terminals for external connection. Therefore, only planar (2D) package mounting operations can be performed, and three-dimensional (3D) stacking settings cannot be performed, resulting in difficulty in further expanding the functions and performance of this packaging structure. Summary of the invention

[0005] The present disclosure is directed to a semiconductor package and a manufacturing method thereof, which can enable the original lead frame type semiconductor package to achieve the purpose of three-dimensional stacking and can also improve the function and performance of the semiconductor package.

[0006] According to an embodiment of the present disclosure, a quad flat leadless package includes a lead frame, a plurality of conductive pillars, a chip, and a molding compound. The lead frame includes a chip seat and a plurality of leads. The plurality of conductive pillars are arranged on the plurality of leads and electrically connected to the plurality of leads, wherein each of the plurality of conductive pillars includes a base portion and a column portion connected to the base portion, and the maximum outer diameter of the base portion is greater than the maximum outer diameter of the column portion. The chip is arranged on the chip seat and electrically connected to the plurality of leads. The molding compound covers the chip, the lead frame, and the plurality of conductive pillars, wherein the molding compound exposes the lower surfaces of the plurality of leads and the top surfaces of the plurality of conductive pillars.

[0007] According to an embodiment of the present disclosure, a method for manufacturing a quad flat leadless package includes the following steps: providing a lead frame, wherein the lead frame includes a chip holder and a plurality of leads; forming a conductive column on one of the plurality of leads using a wire bonding device, wherein the conductive column includes a base portion and a column portion connected to the base portion, and the maximum outer diameter of the base portion is greater than the maximum outer diameter of the column portion; arranging a chip on the chip holder and electrically connecting the chip to the plurality of leads; and forming a molding compound to cover the chip, the lead frame, and the conductive column.

[0008] Based on the above, the quad flat leadless package disclosed in the present invention forms conductive pillars on corresponding leads with wire bonding devices, so that the configuration of the conductive pillars can have the characteristics of selectivity and adjustability according to the requirements of electrical connection, and is formed on the leads of the lead frame as required, and the chip is set on the chip seat of the lead frame, and the molding material exposes the lower surface of the lead and the top surface of the conductive pillar. In this configuration, the lower surface of the lead and the top surface of the conductive pillar exposed by the molding material can be electrically connected to other components respectively, so that the quad flat leadless package can be stacked with other substrates or packaging components on the upper and lower sides of the molding material respectively, so as to achieve the purpose of three-dimensional stacking, and can also improve the function and performance of the semiconductor package. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure.

[0010] Figures 1 to 6 is a schematic cross-sectional view of a process of manufacturing a quad flat no-lead package according to an embodiment of the present disclosure;

[0011] Figure 7 is a cross-sectional schematic diagram of a quad flat no-lead package according to an embodiment of the present disclosure;

[0012] Fig. 8A is a cross-sectional schematic diagram of a quad flat no-lead package according to an embodiment of the present disclosure;

[0013] Figure 8B yes Fig. 8A A partial top view schematic diagram of a quad flat no-lead package;

[0014] Figure 8C is a cross-sectional schematic diagram of a quad flat no-lead package according to an embodiment of the present disclosure;

[0015] Fig.8D yes Figure 8C A partial top view schematic diagram of a quad flat no-lead package;

[0016] Fig. 9is a cross-sectional schematic diagram of a quad flat no-lead package according to an embodiment of the present disclosure;

[0017] Figures 10 to 12 is a cross-sectional schematic diagram of a semiconductor package structure having a quad flat no-lead package according to different embodiments of the present disclosure;

[0018] Fig.13 is a top view schematic diagram of some components of a quad flat no-lead package according to an embodiment of the present disclosure;

[0019] Fig.14 and Fig.15 2 is a cross-sectional schematic diagram of a quad flat no-lead package according to different embodiments of the present disclosure.

[0020] Description of Figure Numbers

[0021] 10, 10a, 10b: Semiconductor packaging

[0022] 50: Thinning tools

[0023] 100, 100a, 100b, 100c, 100d, 100e: Quad Flat No-Lead Package

[0024] 100', 300: Encapsulation

[0025] 105: Wire bonding devices

[0026] 110, 110a: Lead frame

[0027] 112, 112a: Chip holder

[0028] 112a: Extension

[0029] 114, 114a: Lead

[0030] 1141: First Lead

[0031] 1142: Second lead

[0032] 120, 120a, 120b, 120c: conductive pillars

[0033] 1201, 1202: Sub-conductive column, conductive column

[0034] 122: base portion, first base portion

[0035] 124: Column

[0036] 1241: First column part, column part

[0037] 1243: Second column, column

[0038] 1242: Bending part

[0039] 125: Second base

[0040] 126: Top

[0041] 140, 140a, 140b: Chip

[0042] 142: Contact

[0043] 150: Wire

[0044] 160: Molding compound

[0045] 162: Upper surface

[0046] 164: Bottom surface

[0047] 180: Bump

[0048] 200: Substrate

[0049] 230: Electrical conduction path

[0050] 232, 236, 170: Electrical contacts

[0051] 234: Electrically conductive vias

[0052] 310: Upper substrate

[0053] 320: Chip loading

[0054] 330: Upper bump

[0055] 340: Upper mold plastic

[0056] S1: Active surface

[0057] S2: Back surface

[0058] D1, D2, D3: outer diameter DETAILED DESCRIPTION

[0059] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0060] The other technical contents, features and effects mentioned above in the present disclosure will be clearly presented in the detailed description of the embodiments described below with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as "up", "down", "front", "back", "left", "right", etc., are only the directions of the referenced accompanying drawings. Therefore, the directional terms used are for illustration and not for limiting the present disclosure. In addition, in the following embodiments, the same or similar components will be labeled with the same or similar numbers.

[0061] Figures 1 to 6 FIG. 1 is a schematic cross-sectional view of a process of manufacturing a quad flat leadless package according to an embodiment of the present disclosure. In some embodiments, the method of manufacturing a semiconductor package may include the following steps. First, refer to Figure 1 , providing a lead frame 110, wherein the lead frame 110 includes a chip base 112 and a plurality of leads 114. In this embodiment, the leads 114 may surround the chip base 112 and be disposed at the periphery of the chip base 112. In one embodiment, the lead frame 110 may be formed into a patterned lead frame by etching a metal layer.

[0062] Next, please refer to Figure 2 , the chip 140 is disposed on the chip base 112, and the chip 140 is electrically connected to the corresponding lead 114. In one embodiment, the chip 140 may include a plurality of contacts 142, which may be formed on the active surface S1 of the chip 140. In this embodiment, the chip 140 may include a display driver circuit integrated circuit (IC), an image sensor integrated circuit, a memory integrated circuit, a logic integrated circuit, an analog integrated circuit, an ultra-high frequency (UHF) integrated circuit, or a radio frequency (RF) integrated circuit, but the present disclosure is not limited thereto.

[0063] Next, please refer to Figure 3 In this embodiment, the chip 140 can be disposed on the lead frame 110 and electrically connected to the corresponding lead 114 by wire bonding, for example. Specifically, the semiconductor package may further include a plurality of wires 150, wherein the chip 140 includes an active surface S1 having a plurality of contacts 142 and a back surface S2 relative to the active surface S1, and the chip 140 is disposed on the chip holder 112 with the back surface S2, and then the wires 150 are connected between the contacts 142 of the chip 140 and the leads 114 of the lead frame 110 to electrically connect the chip 140 and the lead frame 110. In this embodiment, the chip 140 can be attached to the chip holder 112 via a die attach film (DAF). Of course, the present disclosure does not limit the method of disposing the chip 140 on the chip holder 112 and electrically connecting it to the corresponding lead 114.

[0064] Next, please refer to Figure 4In this embodiment, a conductive column 120 is formed on at least one of the plurality of leads by a wire bonding device 105, and the conductive column 120 is electrically connected to the corresponding lead 114. In this embodiment, the conductive column 120 includes a base portion 122 and a column portion 124 connected to the base portion 122, and the maximum outer diameter D1 of the base portion 122 is substantially greater than the maximum outer diameter D2 of the column portion 124. The conductive column 120 may include a suitable conductive material such as copper, gold, silver, titanium, tungsten, aluminum and / or the like. In this embodiment, the conductive column 120 is a copper wire or an aluminum wire formed by the wire bonding device 105. For example, in this embodiment, the method of forming the conductive pillar 120 may include first forming a base portion 122 on the lead 114 using a wire bonding device 105, and moving the wire bonding device 105 away from the lead 114 by a predetermined distance to form a column portion 124 connected to the base portion 122 and extending by the predetermined distance. In other words, the base portion 122 of the conductive pillar 120 may be an initial solder joint in the wire bonding process, and the column portion 124 may be a solder wire formed in the wire bonding process. Therefore, the outer diameter D1 of the base portion 122 is greater than the outer diameter D2 of the column portion 124. For example, the maximum outer diameter D2 of the column portion 124 is generally greater than or equal to 10 mils, but the present disclosure is not limited thereto.

[0065] In one embodiment, the conductive pillar 120 may further include a top portion 126 connected to the pillar portion 124, and the maximum outer diameter D3 of the top portion 126 is substantially greater than the maximum outer diameter D2 of the pillar portion 124. For example, in this embodiment, after the pillar portion 124 is formed by the wire bonding device 105, the top portion 126 may be formed on the pillar portion 124 by the wire bonding device 105, that is, the base portion 122 of the conductive pillar 120 may be an initial solder joint in the wire bonding process, the pillar portion 124 may be a solder wire formed in the wire bonding process, and the top portion 126 may be a terminal solder joint in the wire bonding process. Therefore, the outer diameter D2 of the top portion 126 is greater than the outer diameter D2 of the pillar portion 124, and the pillar portion 124 is connected between the base portion 122 and the top portion 126.

[0066] It is worth noting that in the aforementioned embodiment, the chip 140 is first set on the chip seat 112, and then the wire bonding device 105 is used to perform wire bonding to electrically connect the chip 140 to the lead 114, and then the wire bonding device 105 is used to form the conductive column 120 on the corresponding lead 114, but the present disclosure is not limited to this. In other feasible embodiments, the process of chip 140, conductive column 120 and wire bonding can adjust the process sequence as needed. For example, the present disclosure can first place the chip 140 on the chip seat 112, and then form the conductive column 120 on the corresponding lead 114 with the wire bonding device 105, and then perform wire bonding with the wire bonding device 105 to electrically connect the chip 140 to the lead 114. This also falls within the scope of application of the present disclosure.

[0067] Next, please refer to Figure 5 , forming a molding compound 160 to cover the chip 140, the lead frame 110 and the conductive pillar 120. The molding compound 160 may be formed, for example, by a molding process. In the present embodiment, the wire 150 is also covered in the molding compound 160. For example, the molding compound 160 may include an epoxy resin. In the present embodiment, the molding compound 160 may fully cover the chip 140, the wire 150 and the conductive pillar 120 (including the top end 126) at this stage, and the bottom surface 164 of the molding compound 160 exposes the lower surface of the chip base 112 and the lead 114.

[0068] Next, please refer to Figure 6 , the molding material 160 is subjected to a thinning process so that the molding material 160 exposes the top surface of the conductive column 120. In the present embodiment, the molding material 160 can be subjected to a thinning process such as chemical mechanical polishing, laser thinning and / or grinding by a thinning tool 50 until the molding material 160 exposes the top surface of the top end portion 126. It is worth noting that, for the convenience of explanation, the grinding thinning method is used as an example in the drawings of the present embodiment. In other words, the molding material 160 above the top surface of the conductive column 120 can be removed by a thinning process such as chemical mechanical polishing and laser thinning in the present embodiment so that the top surface of the conductive column 120 is substantially coplanar with the upper surface 162 of the molding material 160. In this way, the molding material 160 can expose at least the lower surface of the lead 114 and the top surface of the conductive column 120.

[0069] In this embodiment, the thinning process such as grinding can be performed until a portion of the top portion 126 is removed. The outer diameter D3 of the grinded top portion 126 is substantially larger than the outer diameter D2 of the column portion 124, thereby increasing the area of ​​the conductive column 120 exposed to the outside, thereby increasing the bonding area when electrically connected to an external electronic component. At this point, the manufacturing method of the quad flat no-lead package 100 can be substantially completed.

[0070] It must be noted here that the quad flat no-lead package of each subsequent embodiment is similar to the quad flat no-lead package of the previous embodiment, so the component numbers and part of the content of the previous embodiment are used in each subsequent embodiment, wherein the same number is used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted part, please refer to the previous embodiment, and the embodiments will not be repeated.

[0071] Figure 7is a cross-sectional schematic diagram of a quad flat no-lead package according to an embodiment of the present disclosure. In this embodiment, the method of forming a conductive column 120a may include forming a plurality of (sub) conductive columns 1201, 1202 stacked on each other on a corresponding lead 114 using a wire bonding device, wherein each of the plurality of conductive columns 1201, 1202 includes a base portion 122 and a column portion 124 connected to the base portion 122, and the maximum outer diameter D1 of the base portion 122 is substantially greater than the maximum outer diameter D2 of the column portion 124. For example, in this embodiment, the method of forming the conductive column 120a may include, for example, first forming the base portion 122 of the conductive column 1201 on the lead 114 using a wire bonding device, and moving the wire bonding device in a direction away from the lead 114 by a predetermined distance to form the column portion 124 of the conductive column 1201 connected to the base portion 122 and extending the predetermined distance. Next, a wire bonding device is used to form a base portion 122 of a conductive column 1202 on the column portion 124 of the conductive column 1201, and the wire bonding device is moved a predetermined distance away from the base portion 122 to form a column portion 124 of the conductive column 1202 connected to the base portion 122 and extending the predetermined distance. This embodiment only shows two stacked sub-conductive columns 1201 and 1202, however, in other embodiments, the conductive column 120a can be formed by stacking more than two sub-conductive columns. The number of sub-conductive columns can depend on the height of the quad flat no-lead package 100a, and the present disclosure is not limited thereto.

[0072] Fig. 8A It is a cross-sectional schematic diagram of a quad flat no-lead package according to an embodiment of the present disclosure. Figure 8B yes Fig. 8A It must be noted that the number of conductive pillars disclosed in the following figures is for the convenience of explanation, and is only drawn as a group on the schematic diagram, and is not intended to limit the number of conductive pillars disclosed in the present invention. Fig. 8A and Figure 8B In this embodiment, the following is formed: Fig. 8AThe method of forming the conductive column 120b shown includes forming a base portion 122 on a corresponding lead by a wire bonding device, and moving a predetermined distance in a direction away from the corresponding lead 114 to form a first column portion 1241, and then moving back to the corresponding lead 114 to form a bent portion 1242 and a second column portion 1243. In this way, the column portion extends upward from the base portion 122 by a predetermined distance and extends downward to the corresponding lead 114 through bending. In detail, from a structural point of view, the base portion 122 is disposed on the corresponding lead 114, and the column portion extends upward from the base portion 122 to the upper surface of the molding material 160, and then extends downward from the upper surface of the molding material 160 through bending to the corresponding lead 114. In this embodiment, the outer diameter D1 of the base portion 122 is generally larger than the outer diameter D2 of the column portions 1241 and 1243. Furthermore, after the encapsulation glue 160 is formed, a thinning process may be performed on the molding material 160 so that the molding material 160 exposes the top surface of the bent portion 1242 of the conductive pillar 120 b .

[0073] Figure 8C It is a cross-sectional schematic diagram of a quad flat no-lead package according to an embodiment of the present disclosure. Fig.8D yes Figure 8C A partial top view of a quad flat no-lead package.

[0074] Please also refer to Figure 8C and Fig.8D In this embodiment, it is possible to further Fig. 8A The molding material 160 and the conductive pillars of the package structure shown in the figure are subjected to a thinning process until the molded material 160 and the conductive pillars are removed. Fig. 8A The bent portion 1242 shown in the figure exposes the top surfaces of the column portions 1241 and 1243. From a structural perspective, the base portion of the conductive column 120c includes a first base portion 122 and a second base portion 125, and the column portion includes a first column portion 1241 connected to the first base portion 122 and a second column portion 1243 connected to the second base portion 125, and the molding material 160 exposes the top surfaces of the first column portion 1241 and the second column portion 1243. In addition, the maximum outer diameters of the first base portion 122 and the second base portion 125 are substantially greater than the maximum outer diameters of the first column portion 1241 and the second column portion 1243. It is worth noting that the top surfaces of the first column portion 1241 and the second column portion 1243 are exposed on the surface of the molding material 160, and can be used as conductive terminals for product 3D stacking or further manufacturing of redistribution wiring (RDL) process. The actual application can be determined according to product requirements and is not limited thereto.

[0075] Fig. 9 FIG. 1 is a cross-sectional view of a quad flat no-lead package according to an embodiment of the present disclosure. Figure 6The molding compound 160 and the conductive pillar of the package structure shown are subjected to a thinning process until the entire top portion 126 of the conductive pillar is removed to expose the top surface of the pillar portion 124. From a structural perspective, the base portion 122 is disposed on the corresponding lead 114, and the pillar portion 124 extends upward from the base portion 122 to be exposed to the upper surface of the molding compound 160. In this embodiment, the outer diameter D1 of the base portion 122 is substantially greater than the outer diameter D2 of the pillar portion 124.

[0076] Fig.10 FIG. 4 is a cross-sectional schematic diagram of a semiconductor package structure having a quad flat no-lead package according to an embodiment of the present disclosure. Fig.10 The subsequent conductive columns are Figure 6 However, a person skilled in the art should understand that the conductive pillar types of all the aforementioned embodiments can be applied to all quad flat no-lead packages taught subsequently.

[0077] Please refer to Figure 6 and Fig.10 In some embodiments, the molding compound 160 of the quad flat no-lead package 100 formed by the above process exposes at least the lower surface of the lead 114 and the top surface of the conductive pillar 120, so that the quad flat no-lead package 100 can be electrically connected to other components at its upper and lower sides. Fig.10 In an embodiment of the present invention, the substrate 200 may be further disposed on the bottom surface of the molding material 160 of the quad flat no-lead package 100 and electrically connected to the lead 114. In an embodiment, the substrate 200 includes a plurality of electrical contacts 232, which are respectively connected to the lower surface of the lead 114 exposed by the molding material 160 to form a Fig.10 A semiconductor package 10 is shown.

[0078] In the present embodiment, the substrate 200 may further include a plurality of electrical vias 234 and a plurality of electrical contacts 236, wherein the electrical contacts 232 and the electrical contacts 236 may be respectively disposed on two opposite surfaces of the substrate 200, and the electrical vias 234 may extend through the substrate 200 to electrically connect the electrical contacts 232 and the electrical contacts 236. Thus, the electrical contacts 232, the electrical vias 234, the electrical contacts 236 and other conductive components may together form an electrical conduction path 230 to electrically connect the two opposite surfaces of the substrate 200. In the present embodiment, the substrate 200 may include electronic components such as a circuit board, an interposer, and a chip that may be electrically connected to the package.

[0079] Fig.111 is a cross-sectional schematic diagram of a semiconductor package structure having a quad flat no-lead package according to an embodiment of the present disclosure. In the present embodiment, the semiconductor package structure 10a may further include a package 100', which is disposed on the top surface of the molding material 160, and the package 100' includes a plurality of electrical contacts 170, which are respectively connected to the top surfaces of the conductive pillars 120 exposed by the molding material 160. In the present embodiment, the package 100' may be substantially similar to the structure of the quad flat no-lead package 100 (also including components such as a lead frame, a chip, a wire, and a molding material). However, in other embodiments, the package 100' may also be a package that is completely different in structure from the quad flat no-lead package 100, as long as its electrical contacts 170 can be electrically connected to the conductive pillars 120 of the quad flat no-lead package 100.

[0080] Fig.12 1 is a cross-sectional schematic diagram of a semiconductor package structure having a quad flat no-lead package according to an embodiment of the present disclosure. In this embodiment, the package 300 of the semiconductor package 10b may be a package having a structure completely different from that of the quad flat no-lead package 100. The package 300 may include components such as an upper substrate 310, an upper chip 320, an upper bump 330, and an upper mold material 340. Specifically, the upper chip 320 is disposed on the upper substrate 310 and may be electrically connected to the upper substrate 310 through the upper bump 330, for example, by flip chip bonding. The upper mold material 340 is disposed on the upper substrate 310 and encapsulates the upper chip 320 and the upper bump 330 therein.

[0081] In one embodiment, the package 300 stacked on the quad flat no-lead package 100 may include a semiconductor device such as a memory device, which may be used to provide stored data to the chip 140 in the quad flat no-lead package 100. In this embodiment, the chip 140 may include a memory control module, which may provide a control function for the memory device of the package 300. However, this embodiment is only used for illustration, and the present disclosure does not limit the type and function of the package stacked on the quad flat no-lead package 100.

[0082] Fig.13 FIG. 1 is a top view of a partial component of a quad flat leadless package according to an embodiment of the present disclosure. Fig.13In this embodiment, the lead 114 includes a plurality of first leads 1141 and at least one second lead 1142, wherein a plurality of conductive pillars 120 are respectively formed on the plurality of first leads 1141. In one embodiment, the conductive pillar 120 is not formed on the second lead 1142. That is, the conductive pillar 120 is not disposed on all the leads 114, but is selectively disposed on part of the leads 114 according to actual electrical requirements, and has adjustable flexibility in circuit design. In addition, in this embodiment, the contacts 142 of the chip 140 can be disposed along opposite sides of the chip 140, and the leads 114 and the corresponding conductive pillars 120 are also correspondingly located on opposite sides of the chip 140, so that they can be connected to the corresponding contacts 142 via the wires 150. However, in other embodiments, the contacts 142 of the chip 140 can also be disposed around all edges of the chip 140, for example, along the four sides of the chip 140. Thus, the leads 114 and the corresponding conductive pillars 120 are also correspondingly disposed around the periphery of the chip 140, so that they can be connected to the corresponding contacts 142 respectively through the conductive wires 150. The present disclosure is not limited thereto.

[0083] Fig.14 is a cross-sectional view of a quad flat no-lead package according to an embodiment of the present disclosure. Fig.14 In the present embodiment, the chip 140 is disposed on the chip base 112a by means of flip chip bonding. Specifically, the chip base 112a is composed of a plurality of extension portions 112a extending from a plurality of leads 114a to the central region of the lead frame 110a, and a plurality of contacts of the chip 140 are respectively connected to the plurality of extension portions 112a. In other words, the lead frame 110a includes a plurality of leads 114a disposed around the center point of the lead frame 110a, and each lead 114a includes an extension portion 112a extending in the direction of the center point. These extension portions 112a surrounding the center point together constitute the chip base 112a for the chip 140 to be disposed. In this way, the chip 140 can be disposed on the chip base 112 by means of flip chip bonding via a plurality of bumps 180.

[0084] Fig.15 is a cross-sectional view of a quad flat no-lead package according to an embodiment of the present disclosure. Fig.15In this embodiment, the chip disposed on the lead frame 110a may include a plurality of chips 140a and 140b stacked on each other. Moreover, the chips 140a and 140b are stacked on each other and disposed on the chip holder 112a of the lead frame 110a, for example, by flip chip bonding. In this embodiment, the chip 140a is bonded to the chip holder 112a (a plurality of extensions of a plurality of leads 114a) via a plurality of bumps 180, and the chip 140b is bonded to the chip 140a via a plurality of bumps 180. Of course, the present disclosure does not limit the method of disposing the chips 140a and 140b on the chip holder 112a.

[0085] In summary, the quad flat leadless package disclosed in the present invention forms conductive pillars on corresponding leads with wire bonding devices, so that the configuration of the conductive pillars can have the characteristics of selectivity and adjustability according to the needs of electrical connection, and is formed on the leads of the lead frame according to needs, and the chip is set on the chip seat of the lead frame, and the molding material exposes the lower surface of the lead and the top surface of the conductive pillar. In this configuration, the lower surface of the lead and the top surface of the conductive pillar exposed by the molding material can be electrically connected to other components respectively, so that the quad flat leadless package can be stacked with other substrates or packaging components on the upper and lower sides of the molding material respectively, so as to achieve the purpose of three-dimensional stacking, and can also improve the function and performance of the semiconductor package.

[0086] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A quad flat no-lead package, characterized in that: include: A lead frame, including a chip holder and a plurality of leads; A plurality of conductive pillars, disposed on the plurality of leads and electrically connected to the plurality of leads, wherein each of the plurality of conductive pillars comprises a base portion and a column portion connected to the base portion, and a maximum outer diameter of the base portion is greater than a maximum outer diameter of the column portion; A chip, disposed on the chip seat and electrically connected to the plurality of leads; as well as A molding compound covers the chip, the lead frame and the plurality of conductive pillars, wherein the molding compound exposes lower surfaces of the plurality of leads and top surfaces of the plurality of conductive pillars.

2. The quad flat no-lead package according to claim 1, characterized in that: The base portion is disposed on the corresponding lead, and the column portion extends upward from the base portion to be exposed on the upper surface of the molding material.

3. The quad flat no-lead package according to claim 1, characterized in that: Each of the plurality of conductive pillars further includes a top end portion, the pillar body portion is connected between the top end portion and the base portion, and the molding material exposes the top surface of the top end portion, wherein a maximum outer diameter of the top end portion is greater than a maximum outer diameter of the pillar body portion.

4. The quad flat no-lead package according to claim 1, characterized in that: Each of the plurality of conductive pillars includes a plurality of sub-conductive pillars stacked on each other.

5. The quad flat no-lead package according to claim 1, wherein: The base portion is disposed on the corresponding lead, and the column portion extends upward from the base portion to the upper surface of the molding material, and then is bent and extends downward from the upper surface of the molding material to the corresponding lead.

6. The quad flat no-lead package according to claim 1, characterized in that: The base portion includes a first base portion and a second base portion, the column portion includes a first column portion connected to the first base portion and a second column portion connected to the second base portion, and the molding material exposes top surfaces of the first column portion and the second column portion.

7. The quad flat no-lead package according to claim 1, characterized in that: It also includes a plurality of wires, wherein the chip includes an active surface with a plurality of contacts and a back surface relative to the active surface, and the chip is arranged on the chip seat with the back surface, and the plurality of wires are respectively connected between the plurality of contacts of the chip and the plurality of leads.

8. The quad flat no-lead package according to claim 1, wherein: The chip seat is composed of a plurality of extension parts extending from the plurality of leads toward the central area of ​​the lead frame, and a plurality of contacts of the chip are respectively connected to the plurality of extension parts.

9. The quad flat no-lead package according to claim 1, characterized in that: The chip includes a plurality of chips stacked on each other.

10. The quad flat no-lead package according to claim 1, wherein: Also includes: A substrate is disposed on the bottom surface of the molding material, and the substrate includes a plurality of first electrical contacts respectively connected to the lower surfaces of the plurality of leads exposed by the molding material; as well as The package is disposed on the top surface of the molding material, and the package includes a plurality of second electrical contacts respectively connected to the top surfaces of the plurality of conductive pillars exposed by the molding material.

11. The quad flat no-lead package according to claim 1, wherein: The plurality of leads include a plurality of first leads and at least one second lead, wherein the plurality of conductive pillars are respectively disposed on the plurality of first leads.

12. The quad flat no-lead package according to claim 1, wherein: The plurality of conductive pillars are copper wires or aluminum wires.

13. The quad flat no-lead package according to claim 1, wherein: The maximum outer diameter of the column portion is greater than or equal to 10 mils.

14. A method for manufacturing a quad flat no-lead package, characterized in that: include: Providing a lead frame, wherein the lead frame comprises a chip holder and a plurality of leads; Forming a conductive column on one of the plurality of leads by a wire bonding device, wherein the conductive column comprises a base portion and a column portion connected to the base portion, and a maximum outer diameter of the base portion is greater than a maximum outer diameter of the column portion; Disposing a chip on the chip holder and electrically connecting the chip to the plurality of leads; and A molding compound is formed to cover the chip, the lead frame and the conductive pillar.

15. The method for manufacturing a quad flat no-lead package according to claim 14, characterized in that: Forming the conductive column on one of the plurality of leads using the wire bonding device further comprises: The base portion is formed on one of the plurality of leads by the wire bonding device, and is moved a predetermined distance away from the one of the plurality of leads to form a column portion connected to the base portion and extending the predetermined distance, wherein the maximum outer diameter of the base portion is greater than the maximum outer diameter of the column portion.

16. The method for manufacturing a quad flat no-lead package according to claim 15, characterized in that: Forming the conductive column on one of the plurality of leads using the wire bonding device further comprises: The wire bonding device is used to form a top end portion on the column portion, wherein the maximum outer diameter of the top end portion is greater than the maximum outer diameter of the column portion.

17. The method for manufacturing a quad flat no-lead package according to claim 14, wherein: Forming the conductive column on one of the plurality of leads using the wire bonding device includes: A plurality of conductive pillars stacked on one of the plurality of leads are formed by a wire bonding device, wherein each of the plurality of conductive pillars comprises a base portion and a column portion connected to the base portion, and the maximum outer diameter of the base portion is greater than the maximum outer diameter of the column portion.

18. The method for manufacturing a quad flat no-lead package according to claim 14, wherein: Forming the conductive column on one of the plurality of leads using the wire bonding device includes: The base portion is formed on one of the multiple leads by the wire bonding device, and is moved a predetermined distance away from the one of the multiple leads and then moved back to the one of the multiple leads to form a column portion, wherein the column portion extends upward from the base portion the predetermined distance and is bent and extends downward to the corresponding lead.

19. The method for manufacturing a quad flat no-lead package according to claim 14, wherein: Also includes: The molding material is subjected to a thinning process so that the molding material exposes the conductive pillar.

20. The method for manufacturing a quad flat no-lead package according to claim 19, wherein: The thinning process for the molding compound includes laser thinning and grinding process. 21 . The method for manufacturing a quad flat no-lead package according to claim 14 , wherein the plurality of leads include at least one first lead and at least one second lead, and wherein the conductive column is formed on the at least one first lead.

22. The method for manufacturing a quad flat no-lead package according to claim 14, wherein: Also includes: A substrate is disposed on the bottom surface of the molding material, and the substrate includes a plurality of first electrical contacts respectively connected to the lower surfaces of the plurality of leads exposed by the molding material, and A package is disposed on the top surface of the molding material, and the package includes a plurality of second electrical contacts respectively connected to the top surfaces of the plurality of conductive pillars exposed by the molding material.

23. The method for manufacturing a quad flat no-lead package according to claim 14, wherein: The chip is bonded to the chip base by wire bonding or flip chip bonding.

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