Method for measuring ion implantation depth, semiconductor structure and method for manufacturing the same

Abstract

The application relates to a method for measuring ion implantation depth, a semiconductor structure and a preparation method thereof. The method comprises the following steps: providing a wafer; the wafer comprises a substrate and a groove in the substrate, the size of the groove in a first direction increases first and then decreases in a direction towards the substrate; the first direction is parallel to the top surface of the substrate; after forming a barrier layer on the inner surface of the groove, the groove is filled with a semiconductor layer; part of the substrate and part of the semiconductor layer are removed along the first direction, so that the semiconductor layer has a longitudinal section in the shape of a right-angled triangle with a target acute angle; an ion implantation process is performed on the semiconductor layer and the substrate, so as to form an amorphous layer extending in the direction towards the substrate; and the size of the first side wall of the barrier layer in the first direction is related to the thickness of the amorphous layer. The method can directly measure the depth of the amorphous layer caused by part of the ion implantation, and the depth of the amorphous layer can be used to deduce the energy of the ion implantation for calibration; the method is simple and low in cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a method for measuring ion implantation depth, a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] Ion implantation is one of the methods for ion doping of semiconductor materials in modern integrated circuit preparation processes, and is widely used in the modification of the surface and near-surface of semiconductor, metal and insulator materials, and plays a very important role. With the increase of integrated circuit element density and the further reduction of chip process size, ion implantation technology has more advantages than diffusion technology in some doping aspects due to its special doping method.

[0003] Ion implantation technology accelerates ions in an ion source through a high-voltage electric field and forms an ion beam with a specified energy, so that the ions bombard the material surface. After the incident ions enter the crystal lattice, they continuously collide with electrons and atomic nuclei in the crystal lattice, and finally stop at a certain depth after losing a certain amount of energy. This process often causes the crystal structure of the material to become amorphous. In some applications, the depth of amorphization often needs to be simulated, or the relationship between the depth and the energy of ion implantation needs to be calibrated. By controlling the amorphization rate of the phase change material, different resistivities can be achieved, and then used in the field of phase change storage. The importance of ion implantation depth is self-evident.

[0004] However, the current traditional ion implantation detection methods, sheet resistance and thermal wave detection methods, can only measure whether the ion implantation dose of the wafer reaches the specified parameters, and use the energy of ion implantation to calculate the depth of ion implantation. It cannot accurately detect the depth of ion implantation and reflect the amorphization depth.

[0005] Therefore, it is necessary to provide a method for detecting the depth of ion implantation to solve the problems existing in the prior art. SUMMARY

[0006] Therefore, it is necessary to provide a method for detecting the depth of ion implantation to solve the problems existing in the prior art.

[0007] In a first aspect, the present application provides a preparation method of a semiconductor structure, comprising:

[0008] A wafer is provided, which includes a substrate and a trench in the substrate, the trench having a dimension in a first direction that increases first and then decreases in a direction toward the substrate, wherein the first direction is parallel to a top surface of the substrate; a barrier layer is formed on an inner surface of the trench, and a semiconductor layer is filled into the trench; a portion of the substrate and a portion of the semiconductor layer are removed along the first direction, so as to obtain a semiconductor layer having a longitudinal cross section in the shape of a "right triangle" with a target acute angle; and an ion implantation process is performed on the semiconductor layer and the substrate, so as to form an amorphous layer extending in the direction toward the substrate; and a first sidewall of the barrier layer has a dimension in the first direction that is related to a thickness of the amorphous layer.

[0009] In the provided preparation method, a semiconductor structure for measuring the depth of ion implantation is manufactured by using standard semiconductor material preparation processes. By using precise semiconductor growth techniques, a semiconductor layer covering an upper surface of the barrier layer and having a longitudinal cross section in the shape of a "right triangle" with a target acute angle is formed, and then, by using the principle of transition to amorphization caused by material lattice disordering due to continuous bombardment of implantation ions during ion implantation, an amorphous layer with a certain thickness is formed in the substrate and the semiconductor layer.

[0010] In some embodiments, forming the trench includes: forming a patterned photoresist layer on the top surface of the substrate; patterning the substrate based on the patterned photoresist layer to form an initial trench; and selectively etching and removing a portion of the substrate in the initial trench by using a target etching solution to obtain the trench.

[0011] In some embodiments, the target etching solution includes tetramethylammonium hydroxide.

[0012] In some embodiments, filling the semiconductor layer into the trench includes: forming a semiconductor material layer with a top surface not lower than the bottom surface in the trench; and wherein the semiconductor material layer is consistent with the material of the substrate.

[0013] In some embodiments, the material of the barrier layer includes titanium nitride, silicon nitride, zirconium oxide, tungsten, molybdenum, or a combination thereof.

[0014] In some embodiments, the light transmittance of the barrier layer is less than the light transmittance of the amorphous layer.

[0015] In some embodiments, the dimension of the barrier layer in the direction toward the substrate is greater than the dimension of the amorphous layer in the direction toward the substrate.

[0016] In a second aspect, the present application also provides a semiconductor structure prepared by using the preparation method in any of the above embodiments.

[0017] In the semiconductor structure prepared by the method, the thickness of the amorphous layer has a certain geometric relationship with the first side wall of the barrier layer. At the same time, as part of the semiconductor layer material changes from a crystalline state to an amorphous state, the amorphization affects its original electrical and optical properties, such as light transmittance, providing a quantifiable index for subsequent tracking of ion implantation depth.

[0018] In a third aspect, the application also provides a measuring method, including the semiconductor structure prepared by any one of the above preparation methods, and the measuring method further includes: obtaining the size of the first side wall of the semiconductor layer in the first direction in the amorphous layer based on the light transmittance difference; the size is related to the thickness of the amorphous layer, and the depth of ion implantation is equal to the thickness of the amorphous layer.

[0019] In some embodiments, the size is related to the thickness of the amorphous layer, and the thickness of the amorphous layer is equal to the product of the size and the tangent value of the target acute angle.

[0020] Based on the change of light transmittance in the substrate and in combination with the above geometric relationship, the exact thickness of the amorphous layer can be calculated and determined, and the purpose of accurately measuring the depth of ion implantation is achieved without contact. In addition, the energy of ion implantation can be deduced from the depth of amorphization for calibration.

[0021] In the above embodiments, the unexpected technical effects of the application are:

[0022] The application provides a method for measuring the depth of ion implantation, a semiconductor structure and a preparation method thereof, which takes a simple and practical process as a premise, aims to prepare a semiconductor structure with lower cost and simpler process, wherein the semiconductor layer with a vertical cross-section in the shape of a "right-angled triangle" only needs basic growth technology, which can avoid redundant steps, simplify the preparation process, reduce its complexity, and is conducive to standardization and efficient execution in mass production, thereby significantly saving time and raw material cost. The influence of the amorphization process is directly converted into the calculation of the depth of ion implantation by accurately monitoring the change of light transmittance and the pre-set geometric relationship, realizing the double optimization of performance and economy. Overall, its high efficiency and economic practicality have important value in the semiconductor technology industry. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can also be obtained by those skilled in the art without creating laborious work.

[0024] Figure 1 A flowchart of the semiconductor structure preparation method provided in an embodiment;

[0025] Figure 2 A cross-sectional view of the structure after forming the patterned photoresist layer in step S1022 of the semiconductor structure preparation method provided in an embodiment;

[0026] Figure 3 A cross-sectional view of the structure after forming the initial trench in step S1024 of the semiconductor structure preparation method provided in an embodiment;

[0027] Figure 4 A cross-sectional view of the structure after removing the photoresist layer in step S1026 of the semiconductor structure preparation method provided in an embodiment; Figure 3

[0028] Figure 5 A cross-sectional view of the structure after forming the trench in step S1026 of the semiconductor structure preparation method provided in an embodiment;

[0029] Figure 6 A cross-sectional view of the structure after forming the barrier layer in step S1042 of the semiconductor structure preparation method provided in an embodiment;

[0030] Figure 7 A cross-sectional view of the structure after forming the semiconductor layer in step S1044 of the semiconductor structure preparation method provided in an embodiment;

[0031] Figure 8 A cross-sectional view of the structure after planarizing the substrate and the semiconductor layer in step S1046 of the semiconductor structure preparation method provided in an embodiment; Figure 7

[0032] Figure 9 A cross-sectional view of the structure after forming the amorphous layer in step S108 of the semiconductor structure preparation method provided in an embodiment;

[0033] Figure 10 A schematic view of the measurement method provided in an embodiment.

[0034] Legend of reference numerals:

[0035] 10, substrate; 11, photoresist layer; 201, initial trench; 20, trench; 202, cavity; 12, barrier layer; 13, semiconductor layer; 12a, first sidewall; 12b, second sidewall; 14, amorphous layer. DETAILED DESCRIPTION

[0036] In order to facilitate the understanding of the present application, a more complete and thorough description of the present application will be presented below with reference to the relevant drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be realized in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.​​

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application.

[0038] It will be understood that when an element or layer is referred to as being "on" or "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

[0039] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The devices can also be oriented in the other directions (such as rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0040] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It should also be understood that the term "comprising" and / or "comprises", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0041] Embodiments of the application will be described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the application.

[0042] Referring now to the drawings, wherein like reference numerals designate identical structures throughout the several views, Figure 1 The present application provides a method for preparing a semiconductor structure, comprising: step S102-step S108.

[0043] Step S102: providing a wafer; the wafer comprises a substrate, and a trench in the substrate, the size of the trench in a first direction increases first and then decreases in a direction towards the substrate; wherein the first direction is parallel to the top surface of the substrate.

[0044] For example, the substrate can be a silicon (Si) substrate, or a III / V semiconductor substrate or a II / VI semiconductor substrate. Alternatively, for example, the substrate can be a layered substrate, such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon germanium on insulator. Therefore, the type of substrate should not limit the scope of protection of the present disclosure. It should be noted that all the substrates mentioned herein are silicon substrates.

[0045] For example, in addition to the trench described above, the substrate can also include, but is not limited to, other peripheral components, such as components for implementing logic functions.

[0046] Step S104: after forming a barrier layer on the inner surface of the trench, filling a semiconductor layer into the trench.

[0047] For example, the material of the barrier layer includes, but is not limited to, titanium nitride, silicon nitride, zirconium oxide, tungsten, molybdenum, or a combination thereof. For the material constituting the barrier layer, it is necessary to ensure that the barrier layer remains unchanged during the amorphization process of ion implantation, maintaining its original crystal characteristics, i.e., having low light transmittance. Specific personalized material selection and combination can be made according to the process conditions and actual application scenarios, and the barrier layer material is not specifically limited in the present embodiment.

[0048] For example, the material of the filled semiconductor layer is the same as that of the substrate, and therefore the semiconductor layer material in the present application is silicon.

[0049] Step S106: removing part of the substrate and part of the semiconductor layer along the first direction to obtain a semiconductor layer with a longitudinal cross-section in the shape of a "right-angled triangle" with a target acute angle.

[0050] Step S108: performing ion implantation process on the semiconductor layer and the substrate to form an amorphous layer extending along the direction towards the substrate; the size of the barrier layer first sidewall in the amorphous layer along the first direction is related to the amorphous layer.

[0051] For example, the amorphization process of a preset depth under the substrate surface can be realized based on ion impact or implantation process, i.e., to form an amorphous layer extending along the direction towards the substrate in the substrate, wherein any one or a combination of several of xenon, germanium, arsenic and the like can be used as a suitable implantation source to provide the desired amorphization. Ions with high enough energy will penetrate the crystal structure of silicon atoms, causing the bonds between silicon atoms to break, so that the arrangement of silicon atoms is disordered, showing an amorphous state.

[0052] The semiconductor structure obtained after steps S102-S108 can be referred to Figure 9 For the purpose of facilitating the understanding of the present application, Figures 2 to 9 is a schematic diagram of each step of an exemplary semiconductor structure preparation method provided by the embodiments of the present application, wherein Figure 9 An example of the semiconductor structure prepared by the preparation method of the present application can be provided, and other suitable examples of the semiconductor structure prepared by the present application can also be provided, which are not limited herein. The following will be described in detail Figures 2 to 9 The preparation method of the semiconductor structure provided by the embodiments of the present application will be described in detail.

[0053] In the embodiments of the present application, the substrate can include a first surface located on the front surface, and a back surface opposite to the front surface, i.e., a second surface. In the case of ignoring the flatness of the first surface and the second surface, a first direction parallel to the first surface is defined, and the direction towards the substrate includes a second direction perpendicular to the first surface of the substrate. The first direction and a third direction are defined to be perpendicular to each other on the top surface and the bottom surface direction of the substrate (i.e., the plane on which the substrate is located). For example, the direction parallel to the top surface of the substrate is the first direction, and the direction towards the substrate is the second direction. The first direction, the second direction and the third direction can be perpendicular to each other. In the embodiments of the present application, the first direction is defined as the Y-axis direction, and the second direction is defined as the X-axis direction.

[0054] Please refer to Figures 2-5 In some embodiments, step S102 includes:

[0055] Step S1022: forming a patterned photoresist layer 11 on the top surface of the substrate 10.

[0056] Please refer to Figure 2Specifically, a photoresist layer 11 is formed on the top surface of the substrate 10, and a series of steps such as exposure and development are performed to form a patterned photoresist layer 11 by using a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process to define the position of the initial trench 201, so that the subsequent process can be performed by using the directly patternable photoresist layer 11 as a mask, thereby simplifying the process and improving the preparation efficiency.

[0057] Step S1024: The substrate is patterned based on the patterned photoresist layer 11 to form an initial trench 201.

[0058] Referring to Figure 3 For example, the etching process can be mainly divided into two types, dry etching and wet etching. The dry etching can be generally divided into plasma etching (PE), sputtering etching, and reaction ion etching (RIE). The two processes have advantages and disadvantages, and the specific selection should be made according to different processing objects, requirements, and actual conditions.

[0059] The cross-sectional shape of the initial trench 201 along the OY direction can include, but is not limited to, an inverted trapezoid, a rectangle, or a combination of these shapes. Of course, the embodiments of the present application are not limited to these shapes. Figure 3 The shape of the initial trench 201 described above only represents one method, and in fact, as long as the initial trench 201 can be formed at one time.

[0060] Referring to Figure 4 After the initial trench 201 is formed, the photoresist layer 11 is removed along the OY direction to expose the top surface of the substrate 10 and the opening of the initial trench 201.

[0061] Step S1026: A target etching liquid is used to selectively etch and remove part of the substrate 10 in the initial trench 201 to obtain a trench 20.

[0062] Referring to Figure 5 The target etching liquid includes tetramethylammonium hydroxide (TMAH). Specifically, the target etching liquid is used to perform a wet etching process on the initial trench 201 to form a trench 20 along the OY direction, the size of which first increases and then decreases along the OX direction. The trench 20 is also called a sigma groove, and the cross section of the sigma groove is in a sigma shape, which is also called a Σ shape or a diamond shape.

[0063] It should be noted that in the wet etching, the crystal direction has a significant impact on the etching rate, and the TMAH wet etching process mainly utilizes the principle that the

[111] crystal direction of the silicon substrate is not etched to obtain the sigma shape, wherein the

[111] crystal direction corresponds to the (111) crystal surface, and since the (111) crystal surface has a tight atomic arrangement and a high bonding energy, it is difficult to penetrate the etching solution, so that the crystal surface with the

[111] side direction is difficult to etch, and in contrast, the etching rate of other crystal surfaces is relatively fast. Therefore, in the etching, the crystal surface along the

[111] crystal direction is etched, that is, the side wall of the trench 20 is along the crystal surface with the

[111] side direction of the substrate silicon.

[0064] At other devices in the substrate 10, the sigma groove is usually used as a filling area of the embedded epitaxial layer on both sides of the gate structure of the PMOS, and the smaller the distance between the top point and the top surface of the semiconductor substrate, the higher the carrier mobility of the conductive channel at the bottom of the gate structure of the PMOS, and the better the electrical performance of the PMOS.

[0065] Referring to Figures 6-7 In some embodiments, step S104 further includes:

[0066] Step S1042: forming a barrier layer 12 covering the inner surface of the trench 20 and the top surface of the substrate 10.

[0067] Referring to Figure 6 Specifically, one or more of the following processes are used to form the above structure: high-density plasma (HDP), atomic layer deposition (ALD), or chemical vapor deposition (CVD) process, so as to ensure that the barrier layer can uniformly cover the inner surface of the trench 20, and there is still a cavity 202 in the middle of the trench 20, and the opening is not closed.

[0068] Step S1044: forming a semiconductor layer 13 in the trench 20, the top surface of which is not lower than the top surface of the barrier layer.

[0069] Referring to Figure 7 For example, the deposition process is also used to fill the cavity 202 with the semiconductor layer 13, and the top surface of the semiconductor layer 13 formed covers the top surface of the barrier layer 12. Specifically, the material of the semiconductor layer should be consistent with the material of the substrate, so as to ensure that the amorphization depth of the semiconductor layer material and the substrate material is highly synchronized during the ion implantation process.

[0070] Referring to Figure 8, step S106: removing part of the substrate 10 and part of the semiconductor layer 13 along the OY direction, to obtain a semiconductor layer 13 with a longitudinal section in the shape of a "right-angled triangle" with a target acute angle, further comprising:

[0071] For example, the substrate 10 and the semiconductor layer 13 are subjected to a planarization process, which can be but is not limited to a chemical mechanical polishing process, to further remove part of the substrate 10 and part of the semiconductor layer 13 along the OY direction, until a semiconductor layer 13 with a longitudinal section in the shape of a "right-angled triangle" with a target acute angle is obtained. Specifically, referring to Figure 7 The barrier layer 12 after the planarization process includes a first side wall 12a and a second side wall 12b. The first side wall 12a and the second side wall 12b form a right angle; the first side wall 12a and the top surface form a target acute angle.

[0072] Please refer to Figure 9 , step S108: performing an ion implantation process on the semiconductor layer 13 and the substrate 10 to form an amorphous layer 14 extending along the direction towards the substrate; the size of the first side wall of the barrier layer 12 along the OY direction in the amorphous layer 14 is related to the amorphous layer.

[0073] For example, the amorphous layer 14 is formed in the semiconductor layer 13 and the substrate 10 away from the second surface by ion implantation on the first surface of the semiconductor layer 13 and the substrate 10. Specifically, methods such as plasma immersion ion implantation (PIII) or traditional scanning beam implantation can be used, as previously described, to significantly introduce lattice defects and promote local amorphization, thereby achieving the preparation of the amorphous layer 14. It should be noted that the size of the amorphous layer 14 along the OX direction is smaller than the size of the barrier layer 12 along the OX direction, that is, during the ion implantation process, part of the region of the semiconductor layer undergoes an amorphization process, while the barrier layer 12 remains in its original state due to its material properties. By constructing the difference in light transmittance between the amorphous layer and the barrier layer, the propagation of light in different regions is controlled, providing a quantifiable index for subsequent tracking of the depth of ion implantation.

[0074] In the above preparation method, only basic growth techniques are required, which can avoid redundant steps, simplify the preparation process, and reduce its complexity, which is conducive to standardization and efficient execution in large-scale production, thereby significantly saving time and raw material costs.

[0075] Please continue to refer to Figure 9 The application also provides a semiconductor structure prepared by the preparation method of any of the above embodiments.

[0076] The semiconductor structure for detecting the depth of ion implantation in combination with the change of the transmittance of the material caused by amorphization can directly measure the depth of ion implantation, and has low cost and simple process.

[0077] Please refer to Figure 10 The application also provides a measuring method, which comprises the semiconductor structure prepared by the preparation method in any one of the above embodiments. The measuring method further comprises: obtaining the size of the first side wall 12a of the blocking layer 12 in the OY direction in the amorphous layer 14 based on the transmittance difference; the size is related to the thickness of the amorphous layer 14, and the depth of ion implantation is equal to the thickness of the amorphous layer 14.

[0078] Specifically, the size can be measured by a CD measuring machine, but is not limited thereto. Please refer to Figure 9 Wherein, D is used to represent the size of the first side wall 12a of the blocking layer 12 in the OY direction in the amorphous layer 14; and H is used to represent the thickness of the amorphous layer, i.e. the depth of ion implantation.

[0079] It should be noted that during the detection process, it is necessary to ensure that the penetration depth of the measuring light covers the ion implantation depth range, which includes the amorphous layer 14, the semiconductor layer 13 and the blocking layer 12. Due to the transmittance difference, when the measuring light is transmitted from the front end of the sample to the rear end through the amorphous layer 14, the transmittance will gradually decrease.

[0080] Within the range of D, the measuring light penetrates the amorphous layer 14 to reach the blocking layer 12, and part of the light is reflected back. The intensity of this part of the reflected light reflects the amount of light that has passed through the amorphous layer 14; when the measuring light is incident beyond the range of D, after penetrating the amorphous layer 14, the measuring light will continue to propagate in the semiconductor layer 13. Since the semiconductor layer is an electronic conductive medium, the absorption and scattering of light may cause the signal intensity to weaken, and the light signal further weakens, and the signal returns after reaching the blocking layer 12. Therefore, by measuring the difference in signal intensity of different reflected measuring light, the size D of the first side wall 12a can be obtained.

[0081] Please continue to refer to Figure 10 In some embodiments, the size D is related to the thickness H of the amorphous layer 14, and further comprises: the thickness H of the amorphous layer 14 is equal to the product of the size D and the tangent value of the target acute angle.

[0082] Specifically, the thickness of the amorphous layer 14 is calculated according to the following formula:

[0083] H = D • tan A;

[0084] Wherein A is the angle value of the target acute angle.

[0085] For example, in the embodiment, the target acute angle is 45°, and the ion implantation depth H is equal to D. Of course, the target acute angle can have a certain error. Based on the variation of the light transmittance in the substrate and in combination with the above geometric relationship, the exact thickness of the amorphous layer can be calculated and determined, and in the case of non-contact, the purpose of accurately measuring the ion implantation depth is achieved. In addition, the ion implantation energy can be deduced from the amorphization depth for calibration.

[0086] In some embodiments, the method for measuring the ion implantation depth, the semiconductor structure and the preparation method thereof are also compatible with the CMOS process, and are used in the process for preparing an NMOS transistor. In the CMOS process, the amorphization implantation region is formed in the semiconductor substrate on both sides of the gate structure, which is often used as a mask. The purpose of the amorphization implantation is to reduce the punch through effect caused by the reduction of the device size and the junction leakage caused thereby, and to improve the transient enhanced diffusion (TED) effect of the device. By the above method, the formation position of the amorphization implantation region can be accurately evaluated. Precise control of the formation of the amorphization implantation region can also provide key parameters for subsequent device optimization, ensure that the performance indicators of the transistor accurately match the design specifications, and provide reliable guarantee for large-scale manufacturing in the industrial production process, and further promote the development of CMOS technology.

[0087] The technical features of the above-described embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described, but it should be considered that any combination of the technical features is within the scope of the present disclosure as long as the combination does not cause contradiction.

[0088] The above-described embodiments only express several implementation methods of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent application. It should be noted that for ordinary skilled persons in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of the present application. Therefore, the scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method of producing a semiconductor structure for measuring the depth of ion implantation, characterized by, The application provides a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate and a trench in the substrate, wherein the trench has a first sidewall and a second sidewall, and the first sidewall has a first sidewall length and a second sidewall length, and the first sidewall length is greater than the second sidewall length. The trench is formed by the following steps: forming a patterned photoresist layer on the substrate; patterning the substrate based on the patterned photoresist layer to form an initial trench; and selectively etching and removing part of the substrate in the initial trench by using a target etching solution to form the trench. The target etching solution comprises tetramethylammonium hydroxide. The semiconductor structure further comprises a semiconductor layer in the trench. The semiconductor layer is formed by the following steps: forming a semiconductor material layer in the trench, wherein the top surface of the semiconductor material layer is not lower than the top surface of the substrate, and the material of the semiconductor material layer is consistent with the material of the substrate.

2. The production method according to claim 1, characterized by, The material of the barrier layer comprises titanium nitride, silicon nitride, zirconium oxide, tungsten, molybdenum or a combination thereof. The light transmittance of the barrier layer is less than the light transmittance of the amorphous layer after ion implantation. The size of the barrier layer along the direction towards the substrate is greater than the size of the amorphous layer along the direction towards the substrate. The semiconductor structure is prepared by the preparation method of any one of claims 1-7.

3. The preparation method according to claim 2, characterized in that, The semiconductor structure is prepared by the preparation method of any one of claims 1-7.

4. The method of claim 1, wherein, The measurement method further comprises the following steps: obtaining the size of the first sidewall of the barrier layer in the amorphous layer along the first direction based on the difference in light transmittance, wherein the size is related to the thickness of the amorphous layer, and the depth of ion implantation is equal to the thickness of the amorphous layer. The size related to the thickness of the amorphous layer further comprises the following steps: the thickness of the amorphous layer is equal to the product of the size and the tangent value of the target acute angle.

5. The method of any one of claims 1-4, wherein, ​ 6. The method of any one of claims 1-4, wherein, ​ 7. The method of any one of claims 1-4, wherein the method further comprises, ​ 8. A semiconductor structure, characterized by ​ 9. A method of measuring, characterized by, ​ ​ ​ 10. The measurement method according to claim 9, characterized in that, ​ ​

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