Surge current suppression circuit and method

Abstract

The present invention provides a surge current suppression circuit and method, which relates to the field of power electronics technology. The circuit includes: a control system, a power module, a first sampling unit, an inductor and a suppression circuit, wherein: the control system is connected to the power module, the first sampling unit and the suppression circuit; the first sampling unit is also connected to the power load, the power module, the inductor and the suppression circuit; the inductor is also connected to the power load and the suppression circuit; the suppression circuit is also connected to the power module and the power load; the first sampling unit is used to collect two sets of sampling potentials based on a sampling control signal; the control system is used to determine the estimated capacitance value of the power load based on the two sets of sampling potentials; based on the estimated capacitance value and the inductance value of the inductor, the PWM working state of the suppression circuit is controlled. The present invention can solve the problem of surge current triggering overcurrent protection of the power module due to the uncertainty of the input capacitance of the power load.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and in particular to a surge current suppression circuit and method. Background Art

[0002] In centralized power distribution equipment such as distribution boxes, there is usually a situation where DC power is supplied to the external power supply. When the power supply equipment supplies power to the DC power receiving equipment through the control switch, due to the presence of capacitors in the power input of the DC power receiving equipment, there is a large surge current at the moment the control switch is turned on. Especially when multiple DC power receiving equipment are supplied with power at the same time, it is very easy to cause the power supply in the power supply equipment to trigger the overcurrent protection.

[0003] In the prior art, inrush current is generally suppressed by connecting an NTC (Negative Temperature Coefficient) thermistor or a slow-start circuit in series between the control switch and the DC power receiving device. However, the NTC thermistor or the slow-start circuit has poor adaptability to unknown capacitance in the DC power receiving device, resulting in uncontrollable suppression of inrush current. Summary of the invention

[0004] The present invention provides a surge current suppression circuit and method, which are used to solve the defect that the NTC thermistor or the slow start circuit in the prior art has poor adaptability to the unknown capacitor in the DC power receiving device, resulting in uncontrollable surge current suppression effect.

[0005] The present invention provides a surge current suppression circuit, comprising: a control system, a power module, a first sampling unit, an inductor and a suppression circuit, wherein:

[0006] The control system is connected to the power module, the first sampling unit and the suppression circuit; the first sampling unit is also connected to the power load, the power module, the inductor and the suppression circuit; the inductor is also connected to the power load and the suppression circuit; the suppression circuit is also connected to the power module and the power load;

[0007] The control system is used to generate a sampling control signal for controlling the working state of the first sampling unit; the first sampling unit is used to collect two groups of sampling potentials based on the sampling control signal; the control system is also used to determine the estimated capacitance value of the electrical load based on the two groups of sampling potentials; based on the estimated capacitance value and the inductance value of the inductor, the PWM working state of the suppression circuit is controlled, and the PWM working state is used to control the power supply process of the power module to the electrical load.

[0008] According to the surge current suppression circuit provided by the present invention, the first sampling unit includes a first switch tube, a current limiting resistor and a second sampling unit, wherein:

[0009] The first end of the first switch tube is connected to the first end of the control system, and the first end of the first switch tube is used to receive a sampling control signal sent by the control system, and the sampling control signal is used to control the on-off state of the first switch tube to control the working state of the first sampling unit; the second end of the first switch tube is respectively connected to the positive electrode of the power module and the second end of the suppression circuit, and the third end of the first switch tube is connected to the first end of the current limiting resistor and the first end of the second sampling unit;

[0010] The second end of the current limiting resistor is connected to the fourth end of the second sampling unit, the second end of the inductor and the first end of the power load;

[0011] The second end of the second sampling unit is connected to the second end of the control system, the fifth end of the second sampling unit is connected to the fourth end of the control system, and the third end, the sixth end of the second sampling unit and the second end of the power load are all connected to the negative electrode of the power module;

[0012] When the sampling control signal controls the first switch tube to be turned on, the second sampling unit is used to collect the sampling potentials at both ends of the two groups of current limiting resistors, and send the two groups of sampling potentials to the control system.

[0013] According to the surge current suppression circuit provided by the present invention, the second sampling unit includes a first sampling circuit and a second sampling circuit, wherein:

[0014] The first end of the first sampling circuit serves as the first end of the second sampling unit, the second end of the first sampling circuit serves as the second end of the second sampling unit, and the third end of the first sampling circuit serves as the third end of the second sampling unit;

[0015] The first end of the second sampling circuit serves as the fourth end of the second sampling unit, the second end of the second sampling circuit serves as the fifth end of the second sampling unit, and the third end of the second sampling circuit serves as the sixth end of the second sampling unit;

[0016] Each group of sampling potentials includes the first potential and the second potential corresponding to the current limiting resistor which are collected synchronously;

[0017] The first sampling circuit is used to collect the first potential of the first end of the current limiting resistor twice, and send the two first potentials to the second end of the control system, and the second sampling circuit is used to synchronously collect the second potential of the second end of the current limiting resistor twice, and send the two second potentials to the fourth end of the control system.

[0018] According to the surge current suppression circuit provided by the present invention, the suppression circuit includes a second switch tube and a diode, wherein:

[0019] The first end of the second switch tube is connected to the third end of the control system, the second end of the second switch tube serves as the second end of the suppression circuit, the third end of the second switch tube is connected to the first end of the inductor and the cathode of the diode, and the anode of the diode is connected to the cathode of the power module.

[0020] According to the surge current suppression circuit provided by the present invention, the control system includes a control module, a first drive circuit and a second drive circuit, wherein:

[0021] The first end of the control module is connected to the input end of the first driving circuit, and the first end of the control module is used to send an initial sampling control signal to the first driving circuit; the second end of the control module serves as the second end of the control system, and the second end of the control module is used to receive two first potentials sent by the first sampling circuit;

[0022] The third terminal of the control module is connected to the input terminal of the second driving circuit, and the control module is used to determine the cut-off frequency based on the estimated capacitance value and the inductance value of the inductor; determine the PWM frequency after the suppression circuit is turned on based on the inductance value of the inductor; generate an initial suppression control signal based on the comparison result of the cut-off frequency and the PWM frequency, and the initial suppression control signal is used to control the PWM working state of the second switch tube; the third terminal of the control module is used to send the initial suppression control signal to the second driving circuit;

[0023] The fourth end of the control module serves as the fourth end of the control system, and the fourth end of the control module is used to receive two second potentials sent by the second sampling circuit;

[0024] The output end of the first driving circuit serves as the first end of the control system, and the first driving circuit is used to generate a sampling control signal matching the first switch tube voltage based on the initial sampling control signal;

[0025] The output end of the second driving circuit serves as the third end of the control system, and the second driving circuit is used to generate a suppression control signal matching the second switch tube voltage based on the initial suppression control signal.

[0026] The present invention further provides a surge current suppression method, which is applied to the surge current suppression circuit as described in any one of the above items, and the method comprises:

[0027] generating a sampling control signal for controlling the working state of the first sampling unit;

[0028] Determining an estimated capacitance value of the electrical load based on the two sets of sampling potentials sent by the first sampling unit;

[0029] Based on the estimated capacitance value and the inductance value of the inductor, the PWM working state of the suppression circuit is controlled, and the PWM working state is used to control the power supply process of the power module to the power load.

[0030] According to the inrush current suppression method provided by the present invention, the step of controlling the PWM working state of the suppression circuit based on the estimated capacitance value and the inductance value of the inductor includes:

[0031] Determining a cutoff frequency based on the estimated capacitance value and the inductance value of the inductor;

[0032] Determining a PWM frequency after the suppression circuit is turned on based on the inductance value of the inductor;

[0033] Determining a conduction frequency of the suppression circuit based on a comparison result of the cut-off frequency and the PWM frequency;

[0034] The suppression circuit is controlled to be turned on at the conduction frequency, and the PWM working state of the suppression circuit is controlled to increase step by step at equal intervals of the duty cycle, until the real-time sampling potential of the second end of the current limiting resistor is greater than or equal to a preset voltage, and the suppression circuit is controlled to complete conduction; the preset voltage is determined based on the power supply voltage of the power supply module.

[0035] According to the inrush current suppression method provided by the present invention, the determination of the conduction frequency of the suppression circuit based on the comparison result of the cut-off frequency and the PWM frequency includes:

[0036] When the comparison result is that the PWM frequency is greater than the cut-off frequency, determining the PWM frequency as the on-frequency of the suppression circuit;

[0037] When the comparison result is that the PWM frequency is less than or equal to the cut-off frequency, the cut-off frequency is determined as the conduction frequency of the suppression circuit.

[0038] According to the inrush current suppression method provided by the present invention, determining the estimated capacitance value of the electrical load based on the two sets of sampling potentials sent by the first sampling unit includes:

[0039] Determine the sampling voltages sampled twice across the current limiting resistor based on the two sets of sampling potentials sent by the first sampling unit;

[0040] Determine the two-sampled sampling current flowing through the current limiting resistor based on the two-sampled sampling voltages and the resistance value of the current limiting resistor;

[0041] Based on the sampled currents of the two samples, determining an average sampled current corresponding to the current limiting resistor;

[0042] Determine a sampling voltage difference corresponding to the sampling voltages of the two samples;

[0043] An estimated capacitance value of the electrical load is determined based on a sampling interval between two samples, the average sampled current, and the sampled voltage difference.

[0044] According to the surge current suppression method provided by the present invention, the determining of the cut-off frequency based on the estimated capacitance value and the inductance value of the inductor includes:

[0045] determining a resonant frequency based on the estimated capacitance value and the inductance value of the inductor;

[0046] Based on the resonant frequency, the cutoff frequency is determined.

[0047] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, any of the above-mentioned surge current suppression methods is implemented.

[0048] The present invention also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the surge current suppression method described in any one of the above methods is implemented.

[0049] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the inrush current suppression method described above is implemented.

[0050] The inrush current suppression circuit and method provided by the present invention generates a sampling control signal for controlling the working state of the first sampling unit through a control system. The first sampling unit collects two sets of sampling potentials according to the sampling control signal and uploads them to the control system. The control system determines the estimated capacitance value of the power load according to the two sets of sampling potentials, and controls the PWM working state of the suppression circuit according to the estimated capacitance value and the inductance value of the inductor. In the present invention, by determining the estimated capacitance value of the power load, the power supply process of the power module to the power load is automatically adjusted, and the inductor generates a current limiting impedance during the startup process of the power load, effectively suppressing the inrush current generated when the power load is started, solving the problem of the inrush current triggering the overcurrent protection of the power module due to the uncertainty of the input capacitance of the power load, and improving the startup stability of the power supply module to the outside. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0052] Figure 1 It is a connection diagram of an NTC thermistor provided by the prior art.

[0053] Figure 2 It is a connection diagram of a slow start circuit provided by the prior art.

[0054] Figure 3 It is a connection diagram of the surge current suppression circuit provided by an embodiment of the present invention.

[0055] Figure 4 It is a structural schematic diagram of a first sampling unit provided in an embodiment of the present invention.

[0056] Figure 5 Schematic diagram of the structure of the suppression circuit provided by the embodiment of the present invention.

[0057] Figure 6 It is a schematic diagram of the structure of a control system provided by an embodiment of the present invention.

[0058] Figure 7 This is one of the flow charts of the surge current suppression method provided by the embodiment of the present invention.

[0059] Figure 8 This is the second flow chart of the surge current suppression method provided by the embodiment of the present invention.

[0060] Fig. 9 It is a schematic diagram of the structure of a surge current suppression device provided by an embodiment of the present invention.

[0061] Fig.10 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention.

[0062] Reference numerals:

[0063] 110: control system; 111: control module; 112: first drive circuit; 113: second drive circuit; 120: first sampling unit; 121: second sampling unit; 1211: first sampling circuit; 1212: second sampling circuit; 130: suppression circuit; 140: inductor; 150: power module; 200: power load. DETAILED DESCRIPTION

[0064] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0065] In the prior art, inrush current is generally suppressed by connecting an NTC (Negative Temperature Coefficient) thermistor or a slow-start circuit in series between a control switch and a DC power receiving device.

[0066] (1) Figure 1 This is a connection diagram of an NTC thermistor provided by the prior art, such as Figure 1 As shown, NTC thermistors are not suitable for power supply equipment with single power supply and multi-channel control. There are uncertainties in the powered equipment. When multiple powered equipment are powered on at the same time, the action process of the NTC thermistor is uncontrollable. If the NTC thermistor is too large, it is easy to cause the power supply equipment to trigger overcurrent protection, causing multiple powered equipment to restart continuously; if the NTC thermistor is smaller than the power supply overcurrent value, it will cause each power supply to not meet the requirements of the powered equipment. In addition, after the NTC thermistor is connected in series Figure 1 The line shown has high losses.

[0067] (2) Figure 2 It is a connection diagram of the slow start circuit provided by the prior art, such as Figure 2 As shown in FIG. 1 , the slow-start circuit generally utilizes the Miller platform constant current characteristic of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) to suppress the surge current. However, the slow-start circuit utilizing the Miller platform constant current characteristic needs to be designed accordingly according to the input capacitance of the powered device. Due to the uncertainty of the input capacitance in the powered device, the slow-start circuit cannot control the surge current suppression effect.

[0068] Therefore, in view of the problem that the NTC or slow start circuit in the above-mentioned prior art has poor adaptability to the unknown capacitor in the DC power receiving device, resulting in uncontrollable surge current suppression effect, an embodiment of the present invention provides a surge current suppression circuit. Figure 3 is a connection diagram of a surge current suppression circuit provided by an embodiment of the present invention, such as Figure 3 As shown, the circuit includes: a control system 110 , a power module 150 , a first sampling unit 120 , an inductor 140 and a suppression circuit 130 .

[0069] The control system 110 is connected to the power module 150, the first sampling unit 120 and the suppression circuit 130; the first sampling unit 120 is also connected to the power load 200, the power module 150, the inductor 140 and the suppression circuit 130; the inductor 140 is also connected to the power load 200 and the suppression circuit 130; the suppression circuit 130 is also connected to the power module 150 and the power load 200.

[0070] The control system 110 is used to generate a sampling control signal for controlling the working state of the first sampling unit 120; the first sampling unit 120 is used to collect two sets of sampling potentials based on the sampling control signal; the control system 110 is also used to determine the estimated capacitance value of the electrical load 200 based on the two sets of sampling potentials; based on the estimated capacitance value and the inductance value of the inductor 140, control the PWM (Pulse width modulation) working state of the suppression circuit 130, and the PWM working state is used to control the power supply process of the power module 150 to the electrical load 200.

[0071] Specifically, the control system 110 may generate a sampling control signal corresponding to the first sampling unit 120. The level state of the sampling control signal may control the working state of the first sampling unit 120. For example, when the sampling control signal is a high level signal, the first sampling unit 120 may be controlled to be in a non-sampling state, that is, the first sampling unit 120 does not work at this time. When the sampling control signal is a low level signal, the first sampling unit 120 may be controlled to be in a sampling state. The first sampling unit 120 may sample two sampling points twice, collect two sets of sampling potentials, and upload the two sets of sampling potentials to the control system 110. After receiving the two sets of sampling potentials, the control system 110 can estimate the estimated capacitance value of the input capacitor in the connected power load 200 based on the two sets of sampling potentials, and automatically adjust the PWM working state of the suppression circuit 130 in combination with the estimated capacitance value and the characteristics of the inductor 140, that is, adjust the duty cycle change trend of the suppression circuit 130, so that the inductor 140 generates a current limiting impedance, effectively suppressing the surge current, and avoiding the surge current triggering the overcurrent protection of the power module 150, which causes the power load 200 to restart frequently.

[0072] It should be noted that both sampling points are in the first sampling unit 120, and each set of sampling potentials includes potential values ​​corresponding to the two sampling points. There may be a sampling interval between two samplings of the first sampling unit 120, and the sampling interval may be set according to historical experience, for example, the sampling interval may be 1ms, 1.5ms or 2ms, etc., which is not limited in the embodiment of the present invention.

[0073] Further, Figure 4 is a schematic diagram of the structure of a first sampling unit provided in an embodiment of the present invention, such as Figure 4 As shown, the first sampling unit 120 includes a first switch tube Q1, a current limiting resistor R1 and a second sampling unit 121, wherein:

[0074] The first end of the first switch tube Q1 is connected to the first end of the control system 110, and the first end of the first switch tube Q1 is used to receive a sampling control signal sent by the control system 110, and the sampling control signal is used to control the working state of the first sampling unit 120 by controlling the on-off state of the first switch tube Q1; the second end of the first switch tube Q1 is respectively connected to the positive electrode of the power module 150 and the second end of the suppression circuit 130, and the third end of the first switch tube Q1 is connected to the first end of the current limiting resistor R1 and the first end of the second sampling unit 121;

[0075] The second end of the current limiting resistor R1 is connected to the fourth end of the second sampling unit 121, the second end of the inductor 140 and the first end of the power load 200;

[0076] The second end of the second sampling unit 121 is connected to the second end of the control system 110, the fifth end of the second sampling unit 121 is connected to the fourth end of the control system 110, and the third end, the sixth end of the second sampling unit 121 and the second end of the power load 200 are all connected to the negative electrode of the power module 150;

[0077] When the sampling control signal controls the first switch tube Q1 to be turned on, the second sampling unit 121 is used to collect two groups of sampling potentials at both ends of the current limiting resistor R1 and send the two groups of sampling potentials to the control system 110 .

[0078] Specifically, after the control system 110 generates a sampling control signal, the sampling control signal is sent to the first end of the first switch tube Q1, and the conduction state of the first switch tube Q1 is controlled by the level state of the sampling control signal, thereby controlling the working state of the first sampling unit 120. For example, if the sampling control signal is a high-level signal, the first switch tube Q1 is controlled to be in an off state, thereby controlling the first sampling unit 120 to be in a non-sampling state, that is, controlling the first sampling unit 120 not to work. If the sampling control signal is a low-level signal, the first switch tube Q1 is controlled to be in an on state, thereby controlling the output current of the power module 150 to flow through the current limiting resistor R1, and at the same time controlling the second sampling unit 121 to be in a sampling state, that is, controlling the second sampling unit 121 to synchronously collect the sampling potentials of the sampling points at both ends of the current limiting resistor R1, and collecting a group of sampling potentials before and after the sampling interval. After collecting two sets of sampling potentials, the second sampling unit 121 may upload the two sets of sampling potentials to the control system 110 via the second terminal and the fifth terminal, so that the control system 110 can determine the estimated capacitance value of the connected electrical load 200 .

[0079] Optionally, the first switch tube Q1 can be a PNP transistor or a PMOS, which is not limited in the embodiment of the present invention. When the first switch tube Q1 is a PNP transistor, the base of the PNP transistor serves as the first end of the first switch tube Q1, the emitter of the PNP transistor serves as the second end of the first switch tube Q1, and the collector of the PNP transistor serves as the third end of the first switch tube Q1. Therefore, when the sampling control signal is a high-level signal, the voltage drop between the base and the emitter of the PNP transistor is less than the conduction voltage, so that the PNP transistor is in an off state. When the sampling control signal is a low-level signal, the voltage drop between the base and the emitter of the PNP transistor is greater than the conduction voltage, so that the PNP transistor is in an on state, and the output current of the power module 150 can flow from the emitter of the PNP transistor to the collector, thereby flowing to the current limiting resistor R1. When the first switch tube Q1 is a PMOS, the gate of the PMOS serves as the first end of the first switch tube Q1, the source of the PMOS serves as the second end of the first switch tube Q1, and the drain of the PMOS serves as the third end of the first switch tube Q1. Therefore, when the sampling control signal is a high-level signal, the PMOS is in a cut-off state, and when the sampling control signal is a low-level signal, the PMOS is in a conducting state, so that the output current of the power module 150 can flow from the source of the PMOS to the drain, and then flow to the current limiting resistor R1.

[0080] Furthermore, if Figure 4 As shown, the second sampling unit 121 includes a first sampling circuit 1211 and a second sampling circuit 1212, wherein:

[0081] The first end of the first sampling circuit 1211 serves as the first end of the second sampling unit 121, the second end of the first sampling circuit 1211 serves as the second end of the second sampling unit 121, and the third end of the first sampling circuit 1211 serves as the third end of the second sampling unit 121;

[0082] The first end of the second sampling circuit 1212 serves as the fourth end of the second sampling unit 121, the second end of the second sampling circuit 1212 serves as the fifth end of the second sampling unit 121, and the third end of the second sampling circuit 1212 serves as the sixth end of the second sampling unit 121;

[0083] Each group of sampling potentials includes the first potential and the second potential corresponding to the current limiting resistor R1 which are collected synchronously;

[0084] The first sampling circuit 1211 is used to collect the first potential of the first end of the current limiting resistor R1 twice, and send the two first potentials to the second end of the control system 110, and the second sampling circuit 1212 is used to synchronously collect the second potential of the second end of the current limiting resistor R1 twice, and send the two second potentials to the fourth end of the control system 110.

[0085] Specifically, after the first switch tube Q1 is turned on, the first sampling circuit 1211 can collect the first potential of the first end of the current limiting resistor R1, and the second sampling circuit 1212 synchronously collects the second potential of the second end of the current limiting resistor R1. After the sampling interval, the first sampling circuit 1211 collects the first potential of the first end of the current limiting resistor R1 for the second time, and the second sampling circuit 1212 synchronously collects the second potential of the second end of the current limiting resistor R1 for the second time. Afterwards, the first sampling circuit 1211 can send the first potential collected twice to the second end of the control system 110 through the second end, and the second sampling circuit 1212 can send the second potential collected twice to the fourth end of the control system 110 through the second end.

[0086] Optionally, the embodiment of the present invention does not limit the order in which the first sampling circuit 1211 sends the first potential sampled twice, that is, the first sampling circuit 1211 can send the first potential to the second end of the control system 110 after collecting the first potential for the first time, and send the first potential to the second end of the control system 110 after collecting the first potential for the second time. The first sampling circuit 1211 can also send the first potential collected twice to the second end of the control system 110 after the two collections are completed. Similarly, the order in which the second sampling circuit 1212 sends the second potential collected twice can refer to the order in which the first sampling circuit 1211 sends the first potential collected twice, and the embodiment of the present invention will not be repeated here.

[0087] It should be noted that after the second sampling unit 121 collects two sets of sampling potentials and sends them to the control system 110 , the control system 110 can control the first switch tube Q1 to be turned off, thereby controlling the first sampling unit 120 to not work.

[0088] Further, Figure 5 is a schematic diagram of the structure of the suppression circuit provided by an embodiment of the present invention, such as Figure 5 As shown, the suppression circuit 130 includes a second switch tube Q2 and a diode D1, wherein:

[0089] The first end of the second switch tube Q2 is connected to the third end of the control system 110, the second end of the second switch tube Q2 serves as the second end of the suppression circuit 130, the third end of the second switch tube Q2 is connected to the first end of the inductor 140 and the cathode of the diode D1, and the anode of the diode D1 is connected to the cathode of the power module 150.

[0090] Optionally, the second switch tube Q2 may be a PNP transistor or a PMOS, which is not limited in the embodiment of the present invention. When the second switch tube Q2 is a PNP transistor, the base of the PNP transistor serves as the first end of the second switch tube Q2, the emitter of the PNP transistor serves as the second end of the second switch tube Q2, and the collector of the PNP transistor serves as the third end of the second switch tube Q2. When the second switch tube Q2 is a PMOS, the gate of the PMOS serves as the first end of the second switch tube Q2, the source of the PMOS serves as the second end of the second switch tube Q2, and the drain of the PMOS serves as the third end of the second switch tube Q2.

[0091] Further, Figure 6 is a schematic diagram of the structure of a control system provided by an embodiment of the present invention, such as Figure 6 As shown, the control system 110 includes a control module 111, a first drive circuit 112 and a second drive circuit 113, wherein:

[0092] The first end of the control module 111 is connected to the input end of the first driving circuit 112, and the first end of the control module 111 is used to send an initial sampling control signal to the first driving circuit 112; the second end of the control module 111 serves as the second end of the control system 110, and the second end of the control module 111 is used to receive two first potentials sent by the first sampling circuit 1211;

[0093] The third terminal of the control module 111 is connected to the input terminal of the second driving circuit 113. The control module 111 is used to determine the cut-off frequency based on the estimated capacitance value and the inductance value of the inductor 140; determine the PWM frequency after the suppression circuit 130 is turned on based on the inductance value of the inductor 140; generate an initial suppression control signal based on the comparison result of the cut-off frequency and the PWM frequency, and the initial suppression control signal is used to control the PWM working state of the second switch tube Q2; the third terminal of the control module 111 is used to send the initial suppression control signal to the second driving circuit 113;

[0094] The fourth end of the control module 111 serves as the fourth end of the control system 110 , and the fourth end of the control module 111 is used to receive the two second potentials sent by the second sampling circuit 1212 ;

[0095] The output end of the first driving circuit 112 serves as the first end of the control system 110, and the first driving circuit 112 is used to generate a sampling control signal matching the voltage of the first switch tube Q1 based on the initial sampling control signal;

[0096] The output terminal of the second driving circuit 113 serves as the third terminal of the control system 110 . The second driving circuit 113 is used to generate a suppression control signal that matches the voltage of the second switch tube Q2 based on the initial suppression control signal.

[0097] Specifically, the control module 111 controls the on / off state of the first switch tube Q1 and the second switch tube Q2. However, when the first switch tube Q1 and the second switch tube Q2 are PNP transistors or PMOS, the output voltage of the control module 111 may not be able to directly meet the driving voltage required by the base of the PNP transistor or the gate of the PMOS. Therefore, the first end of the control module 111 is connected to the first drive circuit 112, and the third end is connected to the second drive circuit 113. After the control module 111 generates an initial sampling control signal, the voltage conversion can be achieved through the first drive circuit 112 to generate a voltage-matched sampling control signal, and then the first drive circuit 112 sends the sampling control signal to the first end of the first switch tube Q1 to ensure that the first switch tube Q1 can be reliably turned on or off. Secondly, after receiving the sampling potentials of the two samples through the second end and the fourth end, the control module 111 determines the estimated capacitance value of the electrical load 200 according to the two sets of sampling potentials. By utilizing the characteristic that the impedance of the inductor 140 is proportional to the frequency of the AC signal, the control module 111 can calculate the cutoff frequency according to the estimated capacitance value and the inductance value of the inductor 140, and calculate the PWM frequency according to the inductance value of the inductor 140. According to the comparison result of the cutoff frequency and the PWM frequency, an initial suppression control signal that meets the estimated capacitance value is generated, and voltage conversion is achieved through the second drive circuit 113 to generate a voltage-matched suppression control signal. The second drive circuit 113 then sends the suppression control signal to the first end of the second switch tube Q2 to ensure reliable control of the PWM working state of the second switch tube Q2.

[0098] Optionally, the control module 111 may be a processor such as an MCU (Micro Controller Unit) or a CPU (Central Processing Unit), which is not limited in the embodiment of the present invention.

[0099] The inrush current suppression circuit provided by the embodiment of the present invention generates a sampling control signal for controlling the working state of the first sampling unit through a control system. The first sampling unit collects two sets of sampling potentials according to the sampling control signal and uploads them to the control system. The control system determines the estimated capacitance value of the power load according to the two sets of sampling potentials, and controls the PWM working state of the suppression circuit according to the estimated capacitance value and the inductance value of the inductor. In the present invention, by determining the estimated capacitance value of the power load, the power supply process of the power module to the power load is automatically adjusted, and the inductor generates a current limiting impedance during the startup process of the power load, which effectively suppresses the inrush current generated when the power load is started, solves the problem of the inrush current triggering the overcurrent protection of the power module due to the uncertainty of the input capacitance of the power load, and improves the startup stability of the power supply module to the outside.

[0100] The embodiment of the present invention further provides a surge current suppression method, which is applied to the surge current suppression circuit as described in any one of the above items. Figure 7 FIG. 1 is a flow chart of a surge current suppression method provided by an embodiment of the present invention. Figure 7 As shown, the method includes the following steps 710 to 730.

[0101] Step 710: Generate a sampling control signal for controlling the working state of the first sampling unit.

[0102] Specifically, in the surge current suppression circuit, the control system can generate a sampling control signal corresponding to the first sampling unit. Through the level state of the sampling control, the first switch tube in the first sampling unit can be controlled to be turned on, so that the power supply module can micro-charge the input capacitor in the power load through the current limiting resistor, and control the second sampling unit in the first sampling unit to collect the sampling potentials at both ends of the two groups of internal current limiting resistors, and send the two groups of sampling potentials to the control system.

[0103] Step 720: Determine an estimated capacitance value of the electrical load based on the two sets of sampling potentials sent by the first sampling unit.

[0104] Specifically, after receiving the two sets of sampled potentials, the control system can determine the voltage change rate across the current-limiting resistor within the sampling interval T, thereby estimating the estimated capacitance value of the input capacitance of the electrical load.

[0105] Further, Figure 8 FIG. 2 is a flow chart of the surge current suppression method provided by an embodiment of the present invention. Figure 8 As shown, the step of determining the estimated capacitance value of the electrical load based on the two sets of sampling potentials sent by the first sampling unit includes:

[0106] Determine the sampling voltages sampled twice across the current limiting resistor based on the two sets of sampling potentials sent by the first sampling unit;

[0107] Determine the two-sampled sampling current flowing through the current limiting resistor based on the two-sampled sampling voltages and the resistance value of the current limiting resistor;

[0108] Based on the sampled currents of the two samples, determining an average sampled current corresponding to the current limiting resistor;

[0109] Determine a sampling voltage difference corresponding to the sampling voltages of the two samples;

[0110] Based on the sampling interval T between two samplings, the average sampled current and the sampled voltage difference, the estimated capacitance value of the electrical load is determined.

[0111] Specifically, the two groups of sampling potentials sent by the first sampling unit include the first potential and the second potential collected for the first time, and the first potential and the second potential collected for the second time, and the first difference between the first potential and the second potential collected for the first time is calculated. The first difference is the first sampling voltage across the current limiting resistor collected for the first time. The first sampling voltage can be expressed as: U1=Ua1-Ub1, where U1 represents the first sampling voltage, Ua1 represents the first potential collected for the first time, and Ub1 represents the second potential collected for the first time. The first sampling voltage is the sampling voltage across the current limiting resistor, so the first sampling current flowing through the current limiting resistor during the first collection can be expressed as: I1=U1 / R1, where I1 represents the first sampling current flowing through the current limiting resistor during the first collection, and R1 represents the resistance value of the current limiting resistor. Afterwards, the second difference between the first potential and the second potential collected for the second time is calculated, and the second difference is the second sampling voltage across the current limiting resistor collected for the second time, and the second sampling voltage can be expressed as: U2=Ua2-Ub2, where U2 represents the second sampling voltage, Ua2 represents the first potential collected for the second time, and Ub2 represents the second potential collected for the second time. The second sampling voltage is also the sampling voltage across the current limiting resistor, so the second sampling current flowing through the current limiting resistor during the second collection can be expressed as: I2=U2 / R1, where I2 represents the second sampling current flowing through the current limiting resistor during the second collection.

[0112] After the first sampling current and the second sampling current are calculated, the arithmetic average of the first sampling current and the second sampling current is determined as the average sampling current corresponding to the current limiting resistor within the sampling interval T. The average sampling current can be expressed as: i=(I1+I2) / 2, where i represents the average sampling current.

[0113] After calculating the first sampling voltage and the second sampling voltage, the third difference between the first sampling voltage and the second sampling voltage can be calculated. The third difference is the sampling voltage difference, which can be expressed as: du=U1-U2, where du represents the sampling voltage difference, which can be understood as the voltage change value across the current limiting resistor within the sampling interval T.

[0114] After determining the difference between the average sampling current and the sampling voltage, the estimated capacitance value of the input capacitance of the power load can be estimated using formula (1), which is:

[0115] ,

[0116] Wherein, C represents the estimated capacitance value, dt represents the sampling time, and the sampling time is the sampling interval T. It represents the voltage change rate within the sampling interval T. The estimated capacitance value of the input capacitance of the electrical load can be obtained by calculating the product of the inverse of the voltage change rate and the average sampling current.

[0117] It should be noted that, ignoring the internal resistance of the first switch tube, the first potential of the first end of the current limiting resistor is a fixed value, and is equal to the output voltage of the power module, so the first potentials obtained by two samplings are equal, that is, Ua1=Ua2. The second potential of the second end of the current limiting resistor changes dynamically, and the second potential obtained by the first sampling is less than the second potential obtained by the second sampling, so that the first sampling voltage is greater than the second sampling voltage, that is, U1>U2.

[0118] It should be noted that the current limiting resistor can be a low-power resistor, which is used as a detection resistor for estimating the capacitance value of the input capacitance of the power load. Compared with suppressing the surge current through an NTC thermistor or a pre-charge resistor, the line loss can be greatly reduced.

[0119] Step 730: Based on the estimated capacitance value and the inductance value of the inductor, control the PWM working state of the suppression circuit, wherein the PWM working state is used to control the power supply process of the power module to the power load.

[0120] Specifically, the inductor has an inductor impedance characteristic, which is expressed as follows: when a high-frequency signal acts on the inductor, the inductor will generate a large impedance, and the inductor impedance is proportional to the frequency of the AC signal. That is, the inductor has a current limiting effect on the AC. After determining the estimated capacitance, the inductor impedance characteristic and the estimated capacitance value can be used to control the PWM working state of the suppression circuit, that is, the suppression circuit is controlled to be turned on at high frequency, and a large inductor impedance is generated after acting on the inductor, effectively suppressing the surge current.

[0121] Furthermore, if Figure 8 As shown, the controlling the PWM working state of the suppression circuit based on the estimated capacitance value and the inductance value of the inductor includes:

[0122] Determining a cutoff frequency based on the estimated capacitance value and the inductance value of the inductor;

[0123] Determining a PWM frequency after the suppression circuit is turned on based on the inductance value of the inductor;

[0124] Determining a conduction frequency of the suppression circuit based on a comparison result of the cut-off frequency and the PWM frequency;

[0125] The suppression circuit is controlled to be turned on at the conduction frequency, and the PWM working state of the suppression circuit is controlled to increase step by step at equal intervals of the duty cycle, until the real-time sampling potential of the second end of the current limiting resistor is greater than or equal to a preset voltage, and the suppression circuit is controlled to complete conduction; the preset voltage is determined based on the power supply voltage of the power supply module.

[0126] Further, the determining the cut-off frequency based on the estimated capacitance value and the inductance value of the inductor includes:

[0127] determining a resonant frequency based on the estimated capacitance value and the inductance value of the inductor;

[0128] Based on the resonant frequency, the cutoff frequency is determined.

[0129] Specifically, after the estimated capacitance value is determined, the resonant frequency can be calculated according to the estimated capacitance value and the inductance value using formula (2). Formula (2) is:

[0130] ,

[0131] Wherein, fr represents the resonant frequency, L represents the inductance value of the inductor, and sqrt() represents the square root function.

[0132] At this resonant frequency point, the gain of the second-order low-pass filter composed of the inductor and the input power supply of the power load is infinite, so that a small change in the input signal of the second-order low-pass filter will cause a large fluctuation in the output signal, that is, after the surge current is input into the second-order low-pass filter, a larger surge current may be output. Therefore, after determining the resonant frequency, use formula (3) to calculate the cutoff frequency. Formula (3) is:

[0133] ,

[0134] Among them, fc represents the cut-off frequency, which is greater than the resonant frequency. At this cut-off frequency, the gain of the second-order low-pass filter is small, and the second-order low-pass filter is insensitive to surge current. At the same time, the high-frequency cut-off frequency can make the inductor produce a larger inductive impedance, thereby effectively suppressing the surge current.

[0135] After calculating the cut-off frequency, the second sampling circuit is controlled to collect the real-time sampling potential of the second end of the current limiting resistor in real time, and the fourth difference between the first potential and the real-time sampling potential is calculated, and the fourth difference is determined as the real-time sampling voltage corresponding to the current limiting resistor. The real-time sampling voltage can be expressed as: UL=Ua1-Ubn, where UL represents the real-time sampling voltage and Ubn represents the real-time sampling potential. After determining the real-time sampling voltage, the PWM frequency after the second switch tube is turned on is calculated using formula (4) according to the real-time sampling voltage, the inductance value and the maximum surge current allowable value. Formula (4) is:

[0136] ,

[0137] Wherein, f represents the PWM frequency after the second switch tube is turned on, and Imax represents the maximum allowable surge current value.

[0138] After determining the cut-off frequency and the PWM frequency, the cut-off frequency and the PWM frequency are compared, and the conduction frequency of the second switch tube is determined according to the comparison result. The second switch tube is controlled to be turned on at high frequency by the conduction frequency, so that a higher inductance impedance is generated on the inductor to suppress the surge current. At the same time, the duty cycle of the second switch tube is controlled to increase at equal intervals from the initial value, and the step amplitude is equal each time, until the real-time sampling potential is greater than or equal to the preset potential, and the second switch tube is controlled to complete the conduction. By adjusting the duty cycle of the second switch tube, the surge current can be controlled to increase slowly, and combined with the suppression effect of the inductance impedance, the suppression effect of the surge current can be improved.

[0139] Optionally, the initial value, interval duration and step amplitude of the duty cycle of the second switch tube can be set according to historical experience. For example, the initial value can be 10%, 15%, 20%, etc., the interval duration can be 1ms, 10ms or 20ms, etc., and the step amplitude can be 1%, 1.5%, 2%, etc. The embodiment of the present invention does not limit this.

[0140] For example, taking the initial value as 10%, the step amplitude as 1% and the interval duration as 10s, after determining the conduction frequency according to the comparison result of the cut-off frequency and the PWM frequency, the second switch tube can be controlled to be turned on at high frequency according to the conduction frequency, and the duty cycle of the second switch tube is controlled to start from the initial value of 10%, and the duty cycle of the second switch tube is increased by 1% every 10s.

[0141] It should be noted that the preset voltage can be a preset proportion of the power supply voltage of the power supply module, and the preset proportion can be set based on experience. For example, the preset proportion can be 85%, 90%, or 95%. When the preset proportion is 90%, the preset voltage can be 90% of the power supply voltage.

[0142] Furthermore, if Figure 8 As shown, the determination of the conduction frequency of the suppression circuit based on the comparison result of the cut-off frequency and the PWM frequency includes:

[0143] When the comparison result is that the PWM frequency is greater than the cut-off frequency, determining the PWM frequency as the on-frequency of the suppression circuit;

[0144] When the comparison result is that the PWM frequency is less than or equal to the cut-off frequency, the cut-off frequency is determined as the conduction frequency of the suppression circuit.

[0145] Specifically, after comparing the cutoff frequency and the PWM frequency, the larger value of the two can be determined as the conduction frequency of the second switch tube, that is, if the PWM frequency is greater than the cutoff frequency, the PWM frequency can be determined as the conduction frequency of the second switch tube; if the PWM frequency is less than or equal to the cutoff frequency, the cutoff frequency can be determined as the conduction frequency of the second switch tube, ensuring that the high-frequency signal acts on the inductor, so that the inductor can generate a larger inductive impedance to suppress surge current.

[0146] The inrush current suppression method provided by the embodiment of the present invention generates a sampling control signal for controlling the working state of the first sampling unit through a control system. The first sampling unit collects two sets of sampling potentials according to the sampling control signal and uploads them to the control system. The control system determines the estimated capacitance value of the power load according to the two sets of sampling potentials, and controls the PWM working state of the suppression circuit according to the estimated capacitance value and the inductance value of the inductor. In the present invention, by determining the estimated capacitance value of the power load, the power supply process of the power module to the power load is automatically adjusted, and the inductor generates a current limiting impedance during the startup process of the power load, which effectively suppresses the inrush current generated when the power load is started, solves the problem of the inrush current triggering the overcurrent protection of the power module due to the uncertainty of the input capacitance of the power load, and improves the startup stability of the power supply module to the outside.

[0147] The surge current suppression device provided by the present invention is described below. The surge current suppression device described below and the surge current suppression method described above can be referred to each other.

[0148] The embodiment of the present invention further provides a surge current suppression device, Fig. 9 is a schematic diagram of the structure of a surge current suppression device provided by an embodiment of the present invention, such as Fig. 9 As shown, the surge current suppression device 900 includes: a generating unit 910 , a determining unit 920 and a control unit 930 .

[0149] A generating unit 910, configured to generate a sampling control signal for controlling a working state of the first sampling unit;

[0150] A determination unit 920, configured to determine an estimated capacitance value of the electrical load based on the two sets of sampled potentials sent by the first sampling unit;

[0151] The control unit 930 is used to control the PWM working state of the suppression circuit based on the estimated capacitance value and the inductance value of the inductor, and the PWM working state is used to control the power supply process of the power module to the power load.

[0152] Optionally, the determining unit 920 is specifically configured to:

[0153] Determine the sampling voltages sampled twice across the current limiting resistor based on the two sets of sampling potentials sent by the first sampling unit;

[0154] Determine the two-sampled sampling current flowing through the current limiting resistor based on the two-sampled sampling voltages and the resistance value of the current limiting resistor;

[0155] Based on the sampled currents of the two samples, determining an average sampled current corresponding to the current limiting resistor;

[0156] Determine a sampling voltage difference corresponding to the sampling voltages of the two samples;

[0157] An estimated capacitance value of the electrical load is determined based on a sampling interval between two samples, the average sampled current, and the sampled voltage difference.

[0158] Optionally, the control unit 930 is specifically configured to:

[0159] Determining a cutoff frequency based on the estimated capacitance value and the inductance value of the inductor;

[0160] Determining a PWM frequency after the suppression circuit is turned on based on the inductance value of the inductor;

[0161] Determining a conduction frequency of the suppression circuit based on a comparison result of the cut-off frequency and the PWM frequency;

[0162] The suppression circuit is controlled to be turned on at the conduction frequency, and the PWM working state of the suppression circuit is controlled to increase step by step at equal intervals of the duty cycle, until the real-time sampling potential of the second end of the current limiting resistor is greater than or equal to a preset voltage, and the suppression circuit is controlled to complete conduction; the preset voltage is determined based on the power supply voltage of the power supply module.

[0163] Optionally, the control unit 930 is specifically configured to:

[0164] When the comparison result is that the PWM frequency is greater than the cut-off frequency, determining the PWM frequency as the on-frequency of the suppression circuit;

[0165] When the comparison result is that the PWM frequency is less than or equal to the cut-off frequency, the cut-off frequency is determined as the conduction frequency of the suppression circuit.

[0166] Optionally, the control unit 930 is specifically configured to:

[0167] determining a resonant frequency based on the estimated capacitance value and the inductance value of the inductor;

[0168] Based on the resonant frequency, the cutoff frequency is determined.

[0169] Fig.10 is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention, such as Fig.10 As shown, the electronic device may include: a processor 1010, a communication interface 1020, a memory 1030 and a communication bus 1040, wherein the processor 1010, the communication interface 1020, and the memory 1030 communicate with each other through the communication bus 1040. The processor 1010 may call the logic instructions in the memory 1030 to execute the surge current suppression method, which includes:

[0170] generating a sampling control signal for controlling the working state of the first sampling unit;

[0171] Determining an estimated capacitance value of the electrical load based on the two sets of sampling potentials sent by the first sampling unit;

[0172] Based on the estimated capacitance value and the inductance value of the inductor, the PWM working state of the suppression circuit is controlled, and the PWM working state is used to control the power supply process of the power module to the power load.

[0173] In addition, the logic instructions in the above-mentioned memory 1030 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0174] On the other hand, the present invention further provides a computer program product, the computer program product includes a computer program, the computer program can be stored in a computer-readable storage medium, when the computer program is executed by a processor, the computer can execute the surge current suppression method provided by the above methods, the method includes:

[0175] generating a sampling control signal for controlling the working state of the first sampling unit;

[0176] Determining an estimated capacitance value of the electrical load based on the two sets of sampling potentials sent by the first sampling unit;

[0177] Based on the estimated capacitance value and the inductance value of the inductor, the PWM working state of the suppression circuit is controlled, and the PWM working state is used to control the power supply process of the power module to the power load.

[0178] In another aspect, the present invention further provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the surge current suppression method provided by the above methods is implemented, and the method includes:

[0179] generating a sampling control signal for controlling the working state of the first sampling unit;

[0180] Determining an estimated capacitance value of the electrical load based on the two sets of sampling potentials sent by the first sampling unit;

[0181] Based on the estimated capacitance value and the inductance value of the inductor, the PWM working state of the suppression circuit is controlled, and the PWM working state is used to control the power supply process of the power module to the power load.

[0182] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0183] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0184] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A surge current suppression circuit, characterized in that: include: A control system, a power module, a first sampling unit, an inductor and a suppression circuit, wherein: The control system is connected to the power module, the first sampling unit and the suppression circuit; the first sampling unit is also connected to the power load, the power module, the inductor and the suppression circuit; the inductor is also connected to the power load and the suppression circuit; the suppression circuit is also connected to the power module and the power load; The control system is used to generate a sampling control signal for controlling the working state of the first sampling unit; the first sampling unit includes a current limiting resistor, and the first sampling unit is used to collect two groups of sampling potentials at both ends of the current limiting resistor based on the sampling control signal, and each group of sampling potentials includes a first potential and a second potential corresponding to the current limiting resistor collected synchronously; the control system is also used to determine the estimated capacitance value of the electrical load based on the two groups of sampling potentials; based on the estimated capacitance value and the inductance value of the inductor, control the PWM working state of the suppression circuit, and the PWM working state is used to control the power supply process of the power module to the electrical load; The controlling the PWM working state of the suppression circuit based on the estimated capacitance value and the inductance value of the inductor includes: Determining a cutoff frequency based on the estimated capacitance value and the inductance value of the inductor; Determining a PWM frequency after the suppression circuit is turned on based on the inductance value of the inductor; Determining a conduction frequency of the suppression circuit based on a comparison result of the cut-off frequency and the PWM frequency; Controlling the suppression circuit to conduct at the conduction frequency, and controlling the PWM working state of the suppression circuit to step-increase the duty cycle at equal intervals, until the real-time sampling potential of the second end of the current limiting resistor is greater than or equal to a preset voltage, and controlling the suppression circuit to complete conduction; the preset voltage is determined based on the power supply voltage of the power supply module; The step of determining the conduction frequency of the suppression circuit based on the comparison result between the cut-off frequency and the PWM frequency comprises: When the comparison result is that the PWM frequency is greater than the cut-off frequency, determining the PWM frequency as the on-frequency of the suppression circuit; When the comparison result is that the PWM frequency is less than or equal to the cut-off frequency, the cut-off frequency is determined as the conduction frequency of the suppression circuit.

2. The surge current suppression circuit according to claim 1, characterized in that: The first sampling unit further includes a first switch tube and a second sampling unit, wherein: The first end of the first switch tube is connected to the first end of the control system, and the first end of the first switch tube is used to receive a sampling control signal sent by the control system, and the sampling control signal is used to control the on-off state of the first switch tube to control the working state of the first sampling unit; the second end of the first switch tube is respectively connected to the positive electrode of the power module and the second end of the suppression circuit, and the third end of the first switch tube is connected to the first end of the current limiting resistor and the first end of the second sampling unit; The second end of the current limiting resistor is connected to the fourth end of the second sampling unit, the second end of the inductor and the first end of the power load; The second end of the second sampling unit is connected to the second end of the control system, the fifth end of the second sampling unit is connected to the fourth end of the control system, and the third end, the sixth end of the second sampling unit and the second end of the power load are all connected to the negative electrode of the power module; When the sampling control signal controls the first switch tube to be turned on, the second sampling unit is used to collect the sampling potentials at both ends of the two groups of current limiting resistors, and send the two groups of sampling potentials to the control system.

3. The surge current suppression circuit according to claim 2, characterized in that: The second sampling unit includes a first sampling circuit and a second sampling circuit, wherein: The first end of the first sampling circuit serves as the first end of the second sampling unit, the second end of the first sampling circuit serves as the second end of the second sampling unit, and the third end of the first sampling circuit serves as the third end of the second sampling unit; The first end of the second sampling circuit serves as the fourth end of the second sampling unit, the second end of the second sampling circuit serves as the fifth end of the second sampling unit, and the third end of the second sampling circuit serves as the sixth end of the second sampling unit; The first sampling circuit is used to collect the first potential of the first end of the current limiting resistor twice, and send the two first potentials to the second end of the control system, and the second sampling circuit is used to synchronously collect the second potential of the second end of the current limiting resistor twice, and send the two second potentials to the fourth end of the control system.

4. The surge current suppression circuit according to claim 3, characterized in that: The suppression circuit includes a second switch tube and a diode, wherein: The first end of the second switch tube is connected to the third end of the control system, the second end of the second switch tube serves as the second end of the suppression circuit, the third end of the second switch tube is connected to the first end of the inductor and the cathode of the diode, and the anode of the diode is connected to the cathode of the power module.

5. The surge current suppression circuit according to claim 4, characterized in that: The control system comprises a control module, a first drive circuit and a second drive circuit, wherein: The first end of the control module is connected to the input end of the first driving circuit, and the first end of the control module is used to send an initial sampling control signal to the first driving circuit; the second end of the control module serves as the second end of the control system, and the second end of the control module is used to receive two first potentials sent by the first sampling circuit; The third terminal of the control module is connected to the input terminal of the second driving circuit, and the control module is used to determine the cut-off frequency based on the estimated capacitance value and the inductance value of the inductor; determine the PWM frequency after the suppression circuit is turned on based on the inductance value of the inductor; generate an initial suppression control signal based on the comparison result of the cut-off frequency and the PWM frequency, and the initial suppression control signal is used to control the PWM working state of the second switch tube; the third terminal of the control module is used to send the initial suppression control signal to the second driving circuit; The fourth end of the control module serves as the fourth end of the control system, and the fourth end of the control module is used to receive two second potentials sent by the second sampling circuit; The output end of the first driving circuit serves as the first end of the control system, and the first driving circuit is used to generate a sampling control signal matching the first switch tube voltage based on the initial sampling control signal; The output end of the second driving circuit serves as the third end of the control system, and the second driving circuit is used to generate a suppression control signal matching the second switch tube voltage based on the initial suppression control signal.

6. A surge current suppression method, characterized in that: Applied to the surge current suppression circuit according to any one of claims 1 to 5, the method comprising: generating a sampling control signal for controlling the working state of the first sampling unit; Determining an estimated capacitance value of the electrical load based on the two sets of sampling potentials sent by the first sampling unit; Based on the estimated capacitance value and the inductance value of the inductor, the PWM working state of the suppression circuit is controlled, and the PWM working state is used to control the power supply process of the power module to the power load.

7. The surge current suppression method according to claim 6, characterized in that: The step of determining the estimated capacitance value of the electrical load based on the two sets of sampling potentials sent by the first sampling unit includes: Determine the sampling voltages sampled twice across the current limiting resistor based on the two sets of sampling potentials sent by the first sampling unit; Determine the two-sampled sampling current flowing through the current limiting resistor based on the two-sampled sampling voltages and the resistance value of the current limiting resistor; Based on the sampled currents of the two samples, determining an average sampled current corresponding to the current limiting resistor; Determine a sampling voltage difference corresponding to the sampling voltages of the two samples; An estimated capacitance value of the electrical load is determined based on a sampling interval between two samples, the average sampled current, and the sampled voltage difference.

8. The surge current suppression method according to claim 6, characterized in that: The step of determining a cutoff frequency based on the estimated capacitance value and the inductance value of the inductor comprises: determining a resonant frequency based on the estimated capacitance value and the inductance value of the inductor; Based on the resonant frequency, the cutoff frequency is determined.

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