Semiconductor device, semiconductor system, and switching power supply device

Abstract

The invention relates to a semiconductor device, a semiconductor system and a switching power supply device. The mode can be set without a special terminal. The present invention is provided with: a synchronous input terminal; a synchronous output terminal; the functional circuit comprises a circuit for generating a reference clock signal; a signal output circuit; and a mode setting circuit that sets the operation mode of the functional circuit and the signal output circuit to a first mode or a second mode by means of a mode determination process. The functional circuit performs a predetermined functional operation in synchronization with a reference clock signal in a first mode, and performs a functional operation in synchronization with an input clock signal supplied from another semiconductor device to the synchronous input terminal in a second mode. The signal output circuit outputs a clock signal based on a reference clock signal from the synchronous output terminal in a first mode. The mode setting circuit determines whether or not a specific voltage satisfying a predetermined condition is supplied to the synchronous output terminal from the outside of the semiconductor device in the mode determination process.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, a semiconductor system and a switching power supply device. Background Art

[0002] Sometimes, a configuration is adopted in which a plurality of semiconductor devices are synchronized. For example, a method of synchronizing a plurality of channels of DC (Direct Current) / DC converters to form a multi-phase DC / DC converter is known (see, for example, Patent Document 1 below).

[0003] [Prior Technical Literature]

[0004] [Patent Document]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2022-6829 Summary of the invention

[0006] [summary]

[0007] When a system including multiple semiconductor devices is constructed, the multiple semiconductor devices are often operated in different operation modes. The operation mode can be set by providing a dedicated terminal for setting the operation mode for each semiconductor device, but the provision of a dedicated terminal hinders the miniaturization and cost reduction of the semiconductor device.

[0008] A semiconductor device of one aspect of the present disclosure comprises: a synchronous input terminal; a synchronous output terminal; a functional circuit having a reference clock signal generating circuit configured to generate a reference clock signal; a signal output circuit connected to the synchronous output terminal; and a mode setting circuit configured to set the operation mode of the functional circuit and the signal output circuit to a first mode or a second mode based on a result of the mode determination processing after performing a mode determination processing; the functional circuit performs a prescribed functional operation in synchronization with the reference clock signal in the first mode, and performs the functional operation in synchronization with an input clock signal supplied from other semiconductor devices to the synchronous input terminal in the second mode; the signal output circuit outputs a clock signal based on the reference clock signal from the synchronous output terminal in the first mode, and the mode setting circuit determines in the mode determination processing whether a specific voltage satisfying a prescribed condition is supplied to the synchronous output terminal from outside the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a diagram showing the overall configuration of a switching power supply device according to an embodiment of the present disclosure.

[0010] Figure 2 It is a perspective view of the appearance of a power supply control device according to an embodiment of the present disclosure.

[0011] Figure 3 It is a diagram showing the overall configuration of a switching power supply device according to an embodiment of the present disclosure.

[0012] Figure 4 It is a diagram showing the internal structure of a power supply control device according to an embodiment of the present disclosure.

[0013] Figure 5 This is an operation flow chart of the power supply control device according to the embodiment of the present disclosure.

[0014] Figure 6 It is a diagram showing the internal structure of the first power supply control device according to the embodiment of the present disclosure.

[0015] Figure 7 It is a diagram showing the internal structure of a second power supply control device according to an embodiment of the present disclosure.

[0016] Figure 8 It is a waveform diagram of several signals in the first power supply control device according to the embodiment of the present disclosure.

[0017] Fig. 9 It is a waveform diagram of several signals in the second power supply control device according to the embodiment of the present disclosure.

[0018] Fig.10 is a diagram showing the relationship between two clock signals in an embodiment of the present disclosure.

[0019] Fig.11 It is a circuit diagram of a synchronization management circuit according to a first embodiment of the implementation mode of the present disclosure.

[0020] Fig.12 This is a diagram showing one DFF (D-type Flip Flop) according to the first example of the implementation of the present disclosure.

[0021] Fig.13 This is a timing chart when the first power supply control device of the first example of the implementation mode of the present disclosure is started.

[0022] Fig.14 It is an explanatory diagram of a signal state when the first power supply control device according to the first example of the embodiment of the present disclosure is started.

[0023] Fig.15 It is an explanatory diagram of a signal state when the first power supply control device according to the first example of the embodiment of the present disclosure is started.

[0024] Fig.16 It is an explanatory diagram of a signal state when the first power supply control device according to the first example of the embodiment of the present disclosure is started.

[0025] Fig.17 It is an explanatory diagram of a signal state when the first power supply control device according to the first example of the embodiment of the present disclosure is started.

[0026] Fig.18 It is an explanatory diagram of a signal state when the first power supply control device according to the first example of the embodiment of the present disclosure is started.

[0027] Fig.19 This is an explanatory diagram of a signal state when the second power supply control device according to the first example of the embodiment of the present disclosure is started.

[0028] Fig. 20 This is an explanatory diagram of a signal state when the second power supply control device according to the first example of the embodiment of the present disclosure is started.

[0029] Fig.21 It is a circuit diagram of a synchronization management circuit according to a second example of an implementation mode of the present disclosure.

[0030] Fig. 22 This is a diagram showing a modified configuration of a switching power supply device according to the fourth embodiment of the implementation scheme of the present disclosure. DETAILED DESCRIPTION

[0031] [Detailed description]

[0032] Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the accompanying drawings. In each of the drawings for reference, the same parts are marked with the same symbols, and in principle, repeated descriptions related to the same parts are omitted. In addition, in this specification, in order to simplify the description, sometimes the names of the information, signals, physical quantities, functional parts, circuits, components or parts corresponding to the marks or symbols are omitted or abbreviated by marking the marks or symbols to represent information, signals, physical quantities, functional parts, circuits, components or parts.

[0033] First, several terms used in recording the embodiments of the present disclosure are explained. The earth refers to a reference conductive portion having a 0V (zero volt) potential as a reference, or refers to the 0V potential itself. The reference conductive portion can be formed using a conductor such as a metal. The 0V potential is sometimes referred to as a ground potential. In the embodiments of the present disclosure, a voltage expressed without specifically setting a reference represents a potential relative to the earth.

[0034] Level refers to the level of potential. For any signal or voltage in question, a high level has a higher potential than a low level. For any signal in question, when the signal has a high level, the inverted signal of the signal has a low level, and when the signal has a low level, the inverted signal of the signal has a high level.

[0035] In any signal or voltage, the transition from a low level to a high level is called a rising edge, and the transition from a high level to a low level is called a falling edge.

[0036] For any transistor configured as a FET (field effect transistor) such as a MOSFET, the on-state refers to a state in which the drain and source of the transistor are conducting, and the off-state refers to a state in which the drain and source of the transistor are not conducting (blocking state). The same applies to transistors that are not classified as FETs. Regarding MOSFET, unless otherwise specified, it is considered to be an enhancement-type MOSFET. MOSFET is the abbreviation of "metal-oxide-semiconductor field-effect transistor". In addition, in any MOSFET, unless otherwise specified, the back gate and the source can be considered to be short-circuited.

[0037] In the following, regarding any transistor, the on state and the off state may be simply expressed as on and off. Regarding any transistor, switching from the off state to the on state is expressed as on, and switching from the on state to the off state is expressed as off. In addition, regarding any transistor, the period when the transistor is in the on state is called the on period, and the period when the transistor is in the off state is called the off period.

[0038] For any signal having a high signal level or a low signal level, the period during which the signal level is high is referred to as a high level period, and the period during which the signal level is low is referred to as a low level period. The same is true for any voltage having a high voltage level or a low voltage level.

[0039] Unless otherwise specified, the connection between a plurality of parts forming a circuit, such as arbitrary circuit elements, wirings, and nodes, can be regarded as an electrical connection.

[0040] Figure 1 The overall structure of the switching power supply device 1 of the embodiment of the present disclosure is shown in the figure. The switching power supply device 1 receives a supply of a positive input voltage Vin from a voltage source not shown in the figure, and generates a positive output voltage Vout by stepping down the input voltage Vin. Therefore, the output voltage Vout is lower than the input voltage Vin. The switching power supply device 1 stabilizes the output voltage Vout to a specified target voltage. That is, in a stable state, the output voltage Vout is substantially consistent with the target voltage. Hereinafter, the symbol "Vtg" is used to represent the target voltage. The switching power supply device 1 has two power supply control devices 10. The wiring provided outside the two power supply control devices 10 can be particularly referred to as external wiring.

[0041] The switching power supply device 1 can be mounted on a vehicle such as a car. In this case, the input voltage Vin can be the output voltage of a battery mounted on the vehicle. In addition, the switching power supply device 1 can be provided in any device (such as a smart phone, a portable information terminal, a computer device, a game console, a television, an air conditioner).

[0042] Figure 2 This is a perspective view of the appearance of a power control device 10. The power control device 10 is an electronic component (semiconductor device) having the following components: a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate; a housing (package) accommodating the semiconductor chip; and a plurality of external terminals exposed from the housing to the outside of the power control device 10. The power control device 10 is formed by enclosing the semiconductor chip in a housing (package) made of resin. In addition, Figure 2 The number of external terminals of the power control device 10 shown and the type of the housing of the power control device 10 are merely examples, and they can be designed arbitrarily. The multiple external terminals provided in the power control device 10 include an input terminal IN, a switch terminal SW, a ground terminal GND, a feedback terminal FB, an error common terminal CMPOUT, a synchronous input terminal S_IN, a synchronous output terminal S_OUT, and an internal power output terminal REG. External terminals other than the above terminals can also be provided in the power control device 10. In addition, the synchronous input terminal can be replaced with a synchronous clock input terminal, and the synchronous output terminal can be replaced with a synchronous clock output terminal.

[0043] The switching power supply device 1 is provided with a coil L for each power supply control device 10. The coil L is provided outside the power supply control device 10. The first end of the coil L paired with the power supply control device 10 is connected to the switch terminal SW of a certain power supply control device 10. The second ends of all coils L are commonly connected to the output terminal OUT. In each coil L, the current flowing to the coil L is called the coil current IL. In principle, the coil current IL flows from the switch terminal SW to the output terminal OUT (only the principle case is considered below).

[0044] The switching power supply device 1 is also provided with an output capacitor Cout, and feedback resistors R1 and R2. The output capacitor Cout is inserted between the output terminal OUT and the ground. That is, the first end of the output capacitor Cout is connected to the output terminal OUT, and the second end of the output capacitor Cout is grounded. The voltage at the output terminal OUT is the output voltage Vout. That is, the output terminal OUT is the application end of the output voltage Vout. The load LD is connected to the output terminal OUT. The load LD is an arbitrary load driven based on the output voltage Vout.

[0045] The first end of the feedback resistor R1 is connected to the output terminal OUT, the second end of the feedback resistor R1 is connected to the first end of the feedback resistor R2, and the second end of the feedback resistor R2 is grounded. A feedback voltage Vfb corresponding to the output voltage Vout is generated at the connection node between the feedback resistors R1 and R2. The feedback voltage Vfb is a divided voltage of the output voltage Vout, and is therefore proportional to the output voltage Vout. The feedback voltage generating circuit for generating the feedback voltage Vfb is formed by the feedback resistors R1 and R2. The feedback terminal FB of each power supply control device 10 is connected to the connection node between the feedback resistors R1 and R2 to receive the feedback voltage Vfb. In addition, the output voltage Vout itself can also be the feedback voltage Vfb. In any case, the feedback voltage Vfb is a voltage corresponding to the output voltage Vout.

[0046] The two power supply control devices 10 may be referred to as the first and second power supply control devices 10. Of the first and second power supply control devices 10, the first power supply control device 10 operates in the first mode (reading mode), and the second power supply control device 10 operates in the second mode (tracking mode), and the details thereof will be described below. The feedback voltage Vfb may also be applied only to the feedback terminal FB of the first power supply control device 10 operating in the first mode.

[0047] An input voltage Vin is supplied to an input terminal IN of each power control device 10. A ground terminal GND of each power control device 10 is grounded. Two error common terminals CMPOUT in two power control devices 10 are connected to each other via an external wiring Wc. A synchronization output terminal S_OUT of the first power control device 10 and a synchronization input terminal S_IN of the second power control device 10 are connected to each other via an external wiring Ws.

[0048] Each power supply control device 10 includes an internal power supply circuit (internal power supply circuit 80 described below; see Figure 4 ), and the generated internal power supply voltage Vreg is output from the internal power supply output terminal REG. Outside the power supply control device 10, a capacitor Creg is provided for each power supply control device 10. The capacitor Creg of each power supply control device 10 is inserted between the internal power supply output terminal REG and the ground.

[0049] A group consisting of one power supply control device 10, one coil L, and an output capacitor Cout cooperate to form a DC / DC converter of one channel that performs current mode control. Therefore, a DC / DC converter of two channels is formed in the switching power supply device 1. The output capacitor Cout is shared by the DC / DC converters of the two channels. However, the output capacitor Cout can also be set for each channel. In the switching power supply device 1, a signal corresponding to the feedback voltage Vfb (the error signal described below) can be shared by the power supply control devices 10 of all channels, and multi-phase control can be performed by staggering the phase of the switch between multiple channels.

[0050] In the following, based on the need to clearly distinguish between the first and second power supply control devices 10, as shown in FIG. Figure 3 As shown, sometimes the symbol "10[1]" is used to represent the first power supply control device 10, and sometimes the symbol "10[2]" is used to represent the second power supply control device 10. In addition, the coils L paired with the power supply control devices 10[1] and 10[2] are respectively referred to as coils L[1] and L[2]. That is, the switch terminal SW of the power supply control device 10[i] is connected to the first end of the coil L[i], and the second end of the coil L[i] is connected to the output terminal OUT. The coil current IL flowing through the coil L[i] can be specifically referred to as the coil current IL[i]. i represents an arbitrary integer.

[0051] In addition, the synchronous input terminal S_IN and the synchronous output terminal S_OUT in the power supply control device 10[i] can be specifically referred to as the synchronous input terminal S_IN[i] and the synchronous output terminal S_OUT[i]. In the switching power supply device 1, the synchronous input terminal S_IN[1] is open. The synchronous input terminal S_IN[1] can also be grounded. In the switching power supply device 1, the synchronous output terminal S_OUT[1] is connected to the synchronous input terminal S_IN[2] via the external wiring Ws. In the switching power supply device 1, the synchronous output terminal S_OUT[2] is connected to the internal power output terminal REG of the power supply control device 10[2] via the external wiring Wr, thereby receiving the supply of the internal power supply voltage Vreg.

[0052] Figure 4The internal structure of a power supply control device 10 is shown in the figure. The internal structures of the power supply control devices 10[1] and 10[2] are the same. Therefore, the internal structure of the power supply control device 10 is described with a focus on one power supply control device 10. However, there are parts that operate differently between the power supply control devices 10[1] and 10[2], and these parts will be described in additional detail as appropriate. The power supply control device 10 includes an output stage MM, and a switch control circuit 20 for switching the output stage MM, and includes a synchronization management circuit 30 and an internal power supply circuit 80. The synchronization management circuit 30 includes a signal output circuit 40 connected to a synchronization output terminal S_OUT, and a mode setting circuit 60. In the following, in order to simplify the description, the power supply control devices 10, 10[i] are often abbreviated as devices 10, 10[i].

[0053] The output stage MM is provided between the application end (input terminal IN) of the input voltage Vin and the application end (output terminal OUT) of the output voltage Vout, and generates the output voltage Vout by switching the input voltage Vin, in cooperation with the coil L and the output capacitor Cout. The output stage MM includes transistors MH and ML configured as N-channel MOSFETs. Transistors MH and ML are a pair of switching elements connected in series between the input terminal IN and the ground terminal GND (in other words, the earth). By switching them (switch driving), the input voltage Vin is switched and a rectangular wave-shaped switching voltage appears at the switch terminal SW. Transistor MH is provided at a position closer to the high potential side than transistor ML. Specifically, the drain of transistor MH is connected to the application end of the input voltage Vin, that is, the input terminal IN, and receives the supply of the input voltage Vin. The source of transistor MH and the drain of transistor ML are commonly connected to the switch terminal SW. The source of transistor ML is connected to the ground terminal GND (i.e., grounded). However, a resistor for detecting current is sometimes inserted between the source of transistor ML and the ground terminal GND.

[0054] The transistor MH functions as an output element (output transistor), and the transistor ML functions as a rectifying element (synchronous rectifying transistor). In the switching control of the output stage MM, the output element (MH) and the rectifying element (ML) are alternately turned on and off. The coil L connected to the switch terminal SW and the output capacitor Cout constitute a rectifying and smoothing circuit that rectifies and smoothes the rectangular wave switching voltage appearing at the switch terminal SW (see also Figure 1 ).

[0055] Gate signals GH and GL are supplied as driving signals to the gates of transistors MH and ML, respectively, and transistors MH and ML are turned on and off according to the gate signals GH and GL. When the gate signal GH is at a high level, transistor MH is turned on, and when the gate signal GH is at a low level, transistor MH is turned off. Similarly, when the gate signal GL is at a high level, transistor ML is turned on, and when the gate signal GL is at a low level, transistor ML is turned off. Basically, transistors MH and ML are turned on and off alternately, but sometimes both transistors MH and ML are maintained in an off state. Transistors MH and ML will not be turned on at the same time. In addition, at least one of the output element (MH) and the rectifying element (ML) can be set outside the device 10. Sometimes the output stage MM is entirely set outside the device 10.

[0056] During the on-period of transistor MH, coil current IL flows through the channel (between the drain and the source) of transistor MH. During the off-period of transistor MH, coil current IL flows through the channel of transistor ML or the parasitic diode of transistor ML.

[0057] By performing switch control on the output stage MM, the input voltage Vin is electrically converted to the output voltage Vout. The switch control circuit 20 is responsible for the switch control of the output stage MM, and converts the input voltage Vin into the output voltage Vout by performing switch control on the output stage MM. During the switch control, the switch control circuit 20 controls the on / off state of each of the transistors MH and ML by controlling the level of the gate signals GH and GL, thereby causing the output terminal OUT to generate the desired output voltage Vout. When the two switch control circuits 20 in the two devices 10 perform switch control at the same time, the input voltage Vin is converted into the output voltage Vout by the cooperation of the two devices 10.

[0058] In addition, the gate signal GL is a signal based on the ground potential, while the gate signal GH is a signal based on the potential of the switch terminal SW. The low-level gate signal GH has the potential of the switch terminal SW, and the high-level gate signal GH is higher than the potential of the switch terminal SW by a specified voltage. The specified voltage mentioned here is greater than the gate threshold voltage of the transistor MH. A boost power supply for generating the gate signal GH can be formed by a well-known bootstrap circuit (not shown). The transistor MH can also be formed by a P-channel MOSFET, in which case a boost power supply is not required.

[0059] In addition, as a variation, a diode rectification method may also be adopted in the device 10. In this case, as a rectifying element, a synchronous rectifying diode having an anode connected to the ground terminal GND and a cathode connected to the switch terminal SW may be used instead of the transistor ML. In this case, in the switch control of the output stage MM, only the output element (MH) is turned on and off. In any case, the output voltage Vout is generated based on the current (IL) flowing to the coil L by switching the output element (MH) between on and off in the switch control of the output stage MM.

[0060] Before describing the detailed operation of the switch control circuit 20, Figure 5 The mode setting circuit 60 provided in the device 10 will be described. Figure 5 This is an operation flow chart of the device 10. In step STP1, the input voltage Vin starts to be supplied to the device 10, and then in step STP2, the device 10 performs an initial setting process. The period during which the initial setting process is performed is referred to as the initial setting period. In the initial setting process, initialization of various signals in the device 10 is performed. The initial setting process includes a mode determination process. Therefore, the mode determination process is performed during the initial setting period. After the initial setting process is completed, in step STP3, the device 10 performs a normal operation. The period during which the normal operation is performed is referred to as the normal operation period. After the normal operation starts, the normal operation will basically continue until the supply of the input voltage Vin is interrupted.

[0061] In the device 10[i], the mode setting circuit 60 performs a mode determination process and sets the operation mode of the device 10[i] to the first mode or the second mode based on the result of the mode determination process. In the switching power supply device 1, the operation mode of the device 10[1] is set to the first mode, and the operation mode of the device 10[2] is set to the second mode. The method of setting the operation mode will be described below.

[0062] The mode setting circuit 60 supplies a mode setting signal MODE indicating the result of setting the operation mode to each circuit in the device 10. Specifically, when the mode setting circuit 60 of the device 10[i] sets the operation mode of the device 10[i] to the first mode, it supplies the first mode setting signal MODE indicating this to each circuit in the device 10[i]. When the mode setting circuit 60 of the device 10[i] sets the operation mode of the device 10[i] to the second mode, it supplies the second mode setting signal MODE indicating this to each circuit in the device 10[i]. In the switching power supply device 1, after the mode determination process, the first mode setting signal MODE is supplied to each circuit in the device 10[1], and the second mode setting signal MODE is supplied to each circuit in the device 10[2]. Hereinafter, the device 10 in the first mode refers to the device 10 in which the first mode has been set as the operation mode, and the device 10 in the second mode refers to the device 10 in which the second mode has been set as the operation mode.

[0063] The operation of the device 10, especially the operation of the switch control circuit 20 and the signal output circuit 40, is largely related to the setting content of the operation mode. Therefore, the operation mode of the device 10 (hereinafter referred to as the operation mode) can be understood as the operation mode of the switch control circuit 20 and the signal output circuit 40 in the components of the device 10. Figure 4 As shown, the mode setting signal MODE is supplied to the switch control circuit 20 and the signal output circuit 40 .

[0064] The internal structure of the switch control circuit 20 and the operation of each part of the switch control circuit 20 during the normal operation period are described. The operation of each part of the switch control circuit 20 shown below is included in the normal operation (refer to Figure 5 The switch control circuit 20 includes an error amplifier 21, a sensing circuit 22, a reset circuit 23, a switch circuit 24, a setting circuit 25 and a controller 26.

[0065] The error amplifier 21 is a current output type transconductance amplifier. The error amplifier 21 has an inverting input terminal, a non-inverting input terminal, and an output terminal. The inverting input terminal of the error amplifier 21 is connected to the feedback terminal FB. A predetermined reference voltage Vref is supplied to the non-inverting input terminal of the error amplifier 21. The reference voltage Vref is a DC voltage having a positive predetermined voltage value, and is generated by a reference voltage generation circuit (not shown) in the device 10. The output terminal of the error amplifier 21 is connected to the wiring WR1.

[0066] The error amplifier 21 is activated only in the device 10 in the first mode, and the error amplifier 21 in the device 10 in the second mode is not activated (does not operate). In the device 10[i], the first or second mode setting signal MODE from the mode setting circuit 60 is supplied to the switch control circuit 20. The switch control circuit 20 activates the error amplifier 21 when the first mode setting signal MODE is supplied to the switch control circuit 20, and does not activate the error amplifier 21 (stops the error amplifier 21) when the second mode setting signal MODE is supplied to the switch control circuit 20. Therefore, of the error amplifiers 21 of the devices 10[1] and 10[2], only the error amplifier 21 of the device 10[1] is activated. In addition, when the device 10[1] is started, it is sufficient to perform soft start control to gradually increase the value of the reference voltage Vref from 0V to a positive predetermined voltage value, but the existence of the soft start control is ignored below.

[0067] In the device 10[1], the feedback voltage Vfb is input to the inverting input terminal of the error amplifier 21, and the error amplifier 21 outputs a current signal corresponding to the difference between the feedback voltage Vfb and the reference voltage Vref from its own output terminal, thereby causing the wiring WR1 to generate an error signal CMP corresponding to the difference between the feedback voltage Vfb and the reference voltage Vref. The error signal CMP, as well as the following signals Isns, SET, and RST are all voltage signals. In any voltage signal, the rise and fall of the voltage signal represent the rise and fall of the potential of the voltage signal. The same is true for other similar expressions.

[0068] In the device 10[1], the error amplifier 21 outputs a current from its output terminal to the wiring WR1 when "Vfb<Vref" is satisfied so that the potential of the error signal CMP increases, and feeds a current from the wiring WR1 to its output terminal when "Vfb>Vref" is satisfied so that the potential of the error signal CMP decreases. In addition, a phase compensation circuit including a capacitor may be connected between the wiring WR1 and the ground, but this is not particularly shown.

[0069] The sensing circuit 22 detects the coil current IL and generates a sensing signal Isns indicating the detection result of the coil current IL. As the coil current IL increases, the potential of the sensing signal Isns increases, and as the coil current IL decreases, the potential of the sensing signal Isns decreases. The coil current IL detected by the sensing circuit 22 of the device 10[i] is the coil current IL[i].

[0070] The sensing circuit 22 can generate the sensing signal Isns by detecting the current flowing to the transistor MH during the conduction period of the transistor MH (i.e., the coil current IL), or by detecting the current flowing to the transistor ML during the conduction period of the transistor ML (i.e., the coil current IL). Alternatively, a shunt resistor (not shown) can be inserted between the connection node between the transistors MH and ML and the coil L. In this case, the sensing circuit 22 can generate the sensing signal Isns based on the voltage drop of the shunt resistor. In addition, the sensing signal Isns can be generated by detecting the voltage of any part that generates a voltage corresponding to the coil current IL.

[0071] The reset circuit 23 has input terminals in1 and in2. The sensing signal Isns is supplied to the input terminal in2 of the reset circuit 23. A switch circuit 24 is provided between the input terminal in1 of the reset circuit 23, the wiring WR1, and the error common terminal CMPOUT. The switch circuit 24 has either a first switch state or a second switch state. When the first mode setting signal MODE is supplied to the switch control circuit 20, the switch control circuit 20 sets the switch circuit 24 to the first switch state, and when the second mode setting signal MODE is supplied to the switch control circuit 20, the switch circuit 24 is set to the second switch state. Therefore, the switch circuit 24 of the device 10[1] is set to the first switch state, and the switch circuit 24 of the device 10[2] is set to the second switch state.

[0072] Figure 6 FIG. 2 shows a case where the switch circuit 24 of the device 10 [1] is set to the first switch state. Figure 7 FIG. 2 shows a case where the switch circuit 24 of the device 10[2] is set to the second switch state. In the device 10[1], as Figure 6 As shown, the switch circuit 24 in the first switch state connects the wiring WR1 to the input terminal in1 of the reset circuit 23 and the error common terminal CMPOUT. Therefore, the error signal CMP generated by the error amplifier 21 in the device 10[1] is input to the input terminal in1 of the reset circuit 23 in the device 10[1]. In the device 10[2], as shown in FIG. Figure 7 As shown, the switch circuit 24 in the second switch state disconnects the wiring WR1 from the input terminal in1 of the reset circuit 23, and connects the error common terminal CMPOUT to the input terminal in1 of the reset circuit 23. As described above, the error common terminal CMPOUT in the devices 10[1] and 10[2] is connected to each other via the external wiring Wc (see Figure 3 ), and therefore the error signal CMP generated by the error amplifier 21 in the device 10[1] is also input to the input terminal in1 of the reset circuit 23 in the device 10[2].

[0073] also, Figure 6 FIG. 2 shows a situation in which the device 10 [ 1 ] outputs the clock signal CLKb from the synchronous output terminal S_OUT [ 1 ] during the normal operation period. Figure 7 2 shows the input of the clock signal CLKb to the synchronous input terminal S_IN[2] of the device 10[2] during the normal operation period. The content of the clock signal CLKb will be described below.

[0074] The reset circuit 23 generates and outputs a signal RST by pulse width modulation based on the error signal CMP and the sensing signal Isns supplied to the input terminals in1 and in2 .

[0075] The setting circuit 25 has an oscillation circuit 25a, which generates and outputs a signal SET. The signals SET and RST are binary signals having a high level or a low level. The oscillation circuit 25a is an example of a reference clock signal generating circuit that generates and outputs a reference clock signal CLKa. The reference clock signal CLKa is a clock signal having a predetermined frequency fpwm. Any clock signal alternately has a high level and a low level. Sometimes, a clock signal CLKb different from the reference clock signal CLKa is input to the synchronization input terminal S_IN from the outside of the device 10. The setting circuit 25 generates and outputs a binary signal based on the reference clock signal CLKa, or a binary signal based on the clock signal CLKb as the signal SET.

[0076] Figure 8 , several signal waveforms in the device 10[1] are shown. In the device 10[1] operating in the first mode, the setting circuit 25 generates and outputs the signal SET based on the reference clock signal CLKa. In principle, the setting circuit 25 in the device 10[1] sets the level of the signal SET to a low level, but sets the level of the signal SET to a high level for a short time when the rising edge of the reference clock signal CLKa is used as an opportunity. Therefore, in the device 10[1], at the time point of the rising edge of the reference clock signal CLKa, the signal SET generates a rising edge. In the device 10[1], the reference clock signal CLKa itself can also be used as the signal SET.

[0077] In the switching power supply device 1, during the normal operation period, the clock signal CLKb output from the synchronous output terminal S_OUT[1] is input to the synchronous input terminal S_IN[2] (see also Figure 6 and Figure 7 ). The clock signal CLKb is an output clock signal for the device 10[1] and an input clock signal for the device 10[2].

[0078] Fig. 9, several signal waveforms in the device 10[2] are shown. In the device 10[2] operating in the second mode, the setting circuit 25 generates and outputs the signal SET based on the input clock signal CLKb. In principle, the setting circuit 25 in the device 10[2] sets the level of the signal SET to a low level, but sets the level of the signal SET to a high level for a short time when the rising edge of the input clock signal CLKb is used as an opportunity. Therefore, in the device 10[2], at the time point of the rising edge of the input clock signal CLKb, the signal SET generates a rising edge. In the device 10[2], the input clock signal CLKb itself can also be used as the signal SET.

[0079] To the controller 26 (refer to Figure 4 ) The controller 26 inputs a signal SET from the setting circuit 25 and a signal RST from the reset circuit 23. The controller 26 turns on the transistor MH by causing the gate signal GH to generate a rising edge, and turns off the transistor ML by causing the gate signal GL to generate a falling edge, when the rising edge of the signal SET is used as an opportunity. Thereafter, the controller 26 turns off the transistor MH by causing the gate signal GH to generate a falling edge, and turns on the transistor ML by causing the gate signal GL to generate a rising edge, when the rising edge of the signal RST is used as an opportunity.

[0080] The signal SET in the device 10[1] is synchronized with the reference clock signal CLKa generated in the device 10[1]. Therefore, the controller 26 in the device 10[1] performs switching control of the output stage MM in synchronization with the reference clock signal CLKa generated in the device 10[1]. In contrast, the signal SET in the device 10[2] is synchronized with the input clock signal CLKb supplied to the synchronization input terminal S_IN[2]. Therefore, the controller 26 in the device 10[2] performs switching control of the output stage MM in synchronization with the input clock signal CLKb supplied to the synchronization input terminal S_IN[2].

[0081] When "Vout=Vtg", "Vfb=Vref". When "Vfb<Vref" becomes as the supply current to the load LD increases, the error signal CMP rises. The reset circuit 23 generates a signal RST in a manner that the duty cycle of the output stage MM increases when "CMP>Isns" becomes as the error signal CMP rises. The increase in the duty cycle of the output stage MM will lead to an increase in the coil current IL, and the increase in the coil current IL will cause the output voltage Vout and the sense signal Isns to increase. Conversely, when "Vfb>Vref" becomes as the supply current to the load LD decreases, the error signal CMP decreases. The reset circuit 23 generates a signal RST in a manner that the duty cycle of the output stage MM decreases when "CMP<Isns" becomes as the error signal CMP decreases. The reduction in the duty cycle of the output stage MM will lead to a reduction in the coil current IL, and the reduction in the coil current IL will cause the output voltage Vout and the sense signal Isns to decrease. In this way, in the switching power supply device 1 (in the device 10 that performs switching control), control is performed to reduce the difference between the output voltage Vout and the target voltage Vtg.

[0082] The duty cycle of the output stage MM represents the ratio of the on period of the transistor MH to the sum of the on period and the off period of the transistor MH. There are various configurations for switching control of the output stage MM based on the information (Vfb) of the output voltage Vout and the information (Isns) of the coil current IL, and any configuration that realizes the switching control can be adopted in the switching control circuit 20.

[0083] In the switching power supply device 1, during normal operation, current is supplied from the application end of the input voltage Vin to the application end of the output voltage Vout through each output stage MM of the devices 10[1] and 10[2]. At this time, current mode control is performed using a common error signal CMP between the devices 10[1] and 10[2], so that the coil currents IL[1] and IL[2] are substantially the same in magnitude.

[0084] The operation of the mode setting circuit 60 is described. In the mode determination process, the mode setting circuit 60 in the device 10[i] determines whether a specific voltage is supplied to the synchronous output terminal S_OUT[i] from the outside of the device 10[i]. The state in which the specific voltage is supplied to the synchronous output terminal S_OUT[i] is referred to as the specific voltage supply state, and the state in which the specific voltage is not supplied to the synchronous output terminal S_OUT[i] is referred to as the specific voltage non-supply state.

[0085] A specific voltage is a voltage that satisfies specified conditions. A specific voltage that satisfies specified conditions is a voltage having a specified upper threshold voltage Vth_H or above. In the synchronization management circuit 30, a level above the upper threshold voltage Vth_H belongs to a high level. That is, in each signal within the synchronization management circuit 30, a high level refers to a potential above a specified upper threshold voltage Vth_H. In each signal within the synchronization management circuit 30, a low level refers to a potential below a specified lower threshold voltage Vth_L. Here, "0<Vth_L<Vth_H<Vreg" holds. Therefore, the internal power supply voltage Vreg belongs to a specific voltage that satisfies specified conditions. For example, "Vth_L=Vreg×0.3" and "Vth_H=Vreg×0.7".

[0086] In the switching power supply device 1, the internal power supply voltage Vreg (see Figure 3 ), so the synchronous output terminal S_OUT[2] is in a supply state of a specific voltage.

[0087] When the mode setting circuit 60 in the device 10[i] determines that the specific voltage is being supplied to the synchronous output terminal S_OUT[i] (i.e., the specific voltage is being supplied to the synchronous output terminal S_OUT[i]), the operation mode of the device 10[i] (i.e., the operation mode of the switch control circuit 20 and the signal output circuit 40 in the device 10[i]) is set to the second mode. Therefore, the mode setting circuit 60 in the device 10[2] sets the operation mode of the device 10[2] (i.e., the operation mode of the switch control circuit 20 and the signal output circuit 40 in the device 10[2]) to the second mode by outputting the second mode setting signal MODE in accordance with the result of the determination.

[0088] On the other hand, in the switching power supply device 1, no specific voltage is supplied from the outside to the synchronization output terminal S_OUT[1] of the device 10[1]. Although the synchronization output terminal S_OUT[1] is connected to the synchronization input terminal S_IN[2], since the device 10[2] does not have a function of outputting a signal from the synchronization input terminal S_IN[2], the synchronization input terminal S_IN[1] is substantially in an open state.

[0089] When the mode setting circuit 60 in the device 10[i] determines that the specific voltage is not supplied to the synchronous output terminal S_OUT[i] (i.e., the specific voltage is not supplied to the synchronous output terminal S_OUT[i]), the operation mode of the device 10[i] (i.e., the operation mode of the switch control circuit 20 and the signal output circuit 40 in the device 10[i]) is set to the first mode. Therefore, the mode setting circuit 60 in the device 10[1] sets the operation mode of the device 10[1] (i.e., the operation mode of the switch control circuit 20 and the signal output circuit 40 in the device 10[1]) to the first mode by outputting the first mode setting signal MODE in accordance with the result of the determination.

[0090] When the signal output circuit 40 is supplied with the first mode setting signal MODE, it outputs the clock signal CLKb based on the reference clock signal CLKa from the synchronous output terminal S_OUT during the normal operation period. Therefore, the signal output circuit 40 of the device 10[1] outputs the clock signal CLKb based on the reference clock signal CLKa from the synchronous output terminal S_OUT[1] during the normal operation period. Fig.10 , the waveforms of the clock signals CLKa and CLKb are shown in FIG. The frequencies of the clock signals CLKa and CLKb are the same. The phases of the reference clock signal CLKa generated in the device 10[1] and the clock signal CLKb output by the signal output circuit 40 of the device 10[1] (in other words, the clock signal CLKb supplied to the device 10[2]) are shifted by 180°. However, the amount of phase shift may differ from 180° by a certain amount.

[0091] When the signal output circuit 40 is supplied with the second mode setting signal MODE, the clock signal CLKb is not output from the synchronous output terminal S_OUT during the normal operation period, and the input impedance of the synchronous output terminal S_OUT is maintained at a sufficiently high state (at least compared to when the first mode setting signal MODE is supplied to the signal output circuit 40, the input impedance of the synchronous output terminal S_OUT is maintained at a sufficiently high state). Therefore, the signal output circuit 40 of the device 10[2] does not output the clock signal CLKb from the synchronous output terminal S_OUT[2] during the normal operation period, and the input impedance of the synchronous output terminal S_OUT[2] is maintained at a sufficiently high state.

[0092] The internal power supply circuit 80 generates one or more internal power supply voltages including the internal power supply voltage Vreg based on the input voltage Vin. The switch control circuit 20 and the synchronization management circuit 30 operate based on the internal power supply voltage generated by the internal power supply circuit 80 or based on the input voltage Vin.

[0093] Below, in multiple embodiments, several specific configuration examples, operation examples, application technologies, and variation technologies related to the switching power supply device 1 or the power supply control device 10 are described. Unless otherwise specified and not contradictory, the matters described in this embodiment are also applicable to the following embodiments. In each embodiment, when there are matters that contradict the matters described above, the records in each embodiment may be given priority. In addition, as long as they do not contradict each other, the matters recorded in any of the multiple embodiments shown below may also be applied to any other embodiment (that is, any two or more of the multiple embodiments may also be combined).

[0094] <<First embodiment>>

[0095] The first embodiment will be described. Fig.11 1 shows a circuit diagram of the synchronization management circuit 130 of the first embodiment. The synchronization management circuit 130 includes a signal output circuit 140 and a mode setting circuit 160. In the first embodiment, the synchronization management circuit 130, the signal output circuit 140, and the mode setting circuit 160 are used as the synchronization management circuit 30, the signal output circuit 40, and the mode setting circuit 60 in each device 10, respectively (see Figure 4 ).

[0096] The signal output circuit 140 includes inverter circuits 141 to 144, AND circuits 145 and 146, OR circuits 147 and 148, transistors 149 to 151, and a resistor 152. The mode setting circuit 160 includes a synchronization circuit 161, an inverter circuit 162, and AND circuits 163 to 165. The synchronization management circuit 130 is further provided with a DFF 171 and an inverter circuit 172. The synchronization circuit 161 includes a plurality of DFFs and a plurality of inverter circuits. The transistor 149 is a P-channel MOSFET, and the transistors 150 and 151 are N-channel MOSFETs.

[0097] Any inverting circuit has an input terminal and an output terminal, and an inverted signal of an input signal to the input terminal is outputted from the output terminal. With respect to any inverting circuit, the input signal to the inverting circuit is a signal inputted to the input terminal of the inverting circuit, and the output signal of the inverting circuit is a signal outputted from the output terminal of the inverting circuit.

[0098] AND circuits 145, 146, and 163 to 165 are all two-input AND circuits (AND gate circuits). The two-input AND circuit has a first input terminal, a second input terminal, and an output terminal, and outputs a logical product signal of an input signal to the first input terminal and an input signal to the second input terminal from the output terminal. With respect to any AND circuit, the output signal of the AND circuit refers to a signal output from the output terminal of the AND circuit.

[0099] Both OR circuits 147 and 148 are two-input OR circuits (OR gate circuits). The two-input OR circuit has a first input terminal, a second input terminal, and an output terminal, and outputs a logical sum signal of an input signal to the first input terminal and an input signal to the second input terminal from the output terminal. With respect to any OR circuit, the output signal of the OR circuit refers to a signal output from the output terminal of the OR circuit.

[0100] DFF171 and each DFF in the synchronization circuit 161 are Fig.12 The same component as DFF170. DFF170 is a positive edge triggered and D-type flip-flop, having a data input terminal (D), a data output terminal (Q), a clock input terminal (CP) and a negative logic reset input terminal. DFF170 stores a value of "0" or "1". When DFF170 stores the value "0", it outputs a low-level signal from the data output terminal (Q), and when it stores the value "1", it outputs a high-level signal from the data output terminal (Q). When the input signal toward the reset input terminal has a low level, DFF170 is in a reset state, and DFF170 in the reset state always stores the value "0". When the input signal toward the clock input terminal (CP) generates a rising edge during the period when the input signal toward the reset input terminal has a high level, DFF170 imports the value of the input signal toward the data input terminal (D) at the time point of the rising edge and stores it. The value of the input signal to the data input terminal (D) is "1" when the input signal to the data input terminal (D) has a high level, and is "0" when the input signal to the data input terminal (D) has a low level. As long as the input signal to the clock input terminal (CP) does not generate a rising edge during the period when the input signal to the reset input terminal has a high level, the DFF170 retains the current storage value as it is. With respect to any DFF, the output signal of the DFF refers to the signal output from the data output terminal (Q) of the DFF.

[0101] The connection relationship of each element in the synchronization management circuit 130 and the input and output relationship of the signal are described. The reference clock signal CLKa is input to the input terminal of the inverter circuit 141. The output signal of the inverter circuit 141 is input to the input terminal of the inverter circuit 142. The signal POR is input to the data input terminal (D) and the reset input terminal of the DFF 171, and the signal JUDGE is input to the clock input terminal (CP) of the DFF 171. The data output terminal (Q) of the DFF 171 is connected to the input terminal of the inverter circuit 172. The signal POR is input to the first input terminal of the AND circuit 145, and the output signal of the inverter circuit 172 is input to the second input terminal of the AND circuit 145. The mode setting signal MODE is input to the input terminal of the inverter circuit 144. The output signal of the AND circuit 145 and the output signal of the inverter circuit 144 are input to the first input terminal and the second input terminal of the OR circuit 148, respectively.

[0102] The output signal of the OR circuit 148 is input to the first input terminal of the OR circuit 147 and the input terminal of the inverter circuit 143. The output signal of the inverter circuit 142 is input to the second input terminal of the OR circuit 147. The output signal of the inverter circuit 142 is also input to the first input terminal of the AND circuit 146. The output signal of the inverter circuit 143 is input to the second input terminal of the AND circuit 146.

[0103] The source of transistor 149 is connected to the application end of internal power supply voltage Vreg, and receives the supply of internal power supply voltage Vreg. The drains of transistor 149 and transistor 150 are connected to the synchronous output terminal S_OUT. The synchronous output terminal S_OUT is connected to the first end of resistor 152, and the second end of resistor 152 is connected to the drain of transistor 151. The sources of transistors 150 and 151 are grounded. The signal in the synchronous output terminal S_OUT is called signal CLKOUT. The output end of OR circuit 147, the output end of AND circuit 146, and the output end of OR circuit 148 are connected to the gates of transistors 149, 150, and 151, respectively. When the output signal of OR circuit 147 has a low level, transistor 149 is turned on, and when the output signal of OR circuit 147 has a high level, transistor 149 is turned off. When the output signal of AND circuit 146 has a high level, transistor 150 is turned on, and when the output signal of AND circuit 146 has a low level, transistor 150 is turned off. When the output signal of the OR circuit 148 has a high level, the transistor 151 is turned on, and when the output signal of the OR circuit 148 has a low level, the transistor 151 is turned off.

[0104] The input end of the inverter circuit 162 is connected to the synchronous output terminal S_OUT, thereby receiving the signal CLKOUT. The output signal of the inverter circuit 162 is input to the first input end of the AND circuit 163, and the signal POR is input to the second input end of the AND circuit 163. The output signal of the inverter circuit 141 and the output signal of the AND circuit 163 are respectively input to the first input end and the second input end of the AND circuit 164. The output signal of the AND circuit 164 is particularly referred to as a signal S11. The output signal of the DFF 171 is particularly referred to as S12.

[0105] The signals S11, S12 and POR are input to the synchronization circuit 161. The inverted signal of the reference clock signal CLKa is input to the synchronization circuit 161 as the signal S11 only during the period when the output signal of the AND circuit 163 has a high level. When the signal S11 is the inverted signal of the reference clock signal CLKa, the signal S11 is specifically referred to as the clock signal S11. When the output signal of the AND circuit 163 has a low level, the clock signal S11 is not generated, and the signal S11 is maintained at a low level. The synchronization circuit 161 outputs a signal S13 based on the signals S11, S12 and POR. The signals S13 and POR are input to the first input terminal and the second input terminal of the AND circuit 165, respectively. The output signal of the AND circuit 165 is the mode setting signal MODE.

[0106] The synchronization circuit 161 is a circuit driven synchronously with the clock signal S11. In principle, the synchronization circuit 161 sets the signal S13 to a low level. If the clock signal S11 generates a rising edge a predetermined number of times (here 5 times) during the period when the signal S12 and the POR are both at a high level, the synchronization circuit 161 generates a rising edge in the signal S13, and thereafter keeps the signal S13 at a high level. When the input of the clock signal S11 to the synchronization circuit 161 is blocked (i.e., when the signal S11 is maintained at a low level), the signal S13 is maintained at the initial level, i.e., a low level.

[0107] Specifically, the synchronization circuit 161 includes DFF161a to 161e, and inverter circuits 161f and 161g. Among them, DFF161a to 161d, and inverter circuits 161f and 161g form a counter driven synchronously with the clock signal S11. It can also be understood that DFF161e is also included in the components of the counter. Signal S11 is supplied to each clock input terminal (CP) of DFF161a and 161d. Signal S12 is supplied to each reset input terminal of DFF161a to 161d.

[0108] The inverting circuit 161f inputs the inverted signal of the output signal of DFF161a to the data input terminal (D) of DFF161a, and to the clock input terminal (CP) of DFF161b. The inverting circuit 161g inputs the inverted signal of the output signal of DFF161b to the data input terminal (D) of DFF161b, and to the clock input terminal (CP) of DFF161c. The signal S12 is input to the data input terminal (D) of DFF161c. The output signal of DFF161c is input to the data input terminal (D) of DFF161d. The output signal of DFF161d is input to the clock input terminal (CP) of DFF161e. The signal POR is input to the data input terminal (D) and the reset input terminal of DFF161e. The output signal of DFF161e is the signal S13.

[0109] Reference Fig.13 The mode determination process will be described. Fig.13 It is a timing chart when the device 10 is started. Fig.13 1 shows the waveforms of the internal power supply voltage Vreg, the signal POR, OSC_EN, JUDGE, and MODE. The signal POR is a power reset signal. The signal OSC_EN is an enable signal of the oscillation circuit 25a. The signal JUDGE is a determination instruction signal for instructing the execution of the mode determination process.

[0110] When the input voltage Vin starts to be supplied to the device 10, the internal power supply circuit 80 starts, and the internal power supply voltage Vreg rises from 0V to the specified voltage Vreg_tg. If the internal power supply voltage Vreg reaches the specified threshold voltage Vreg_th (<Vreg_tg) at time T1 during the internal power supply voltage Vreg rising process, the power reset circuit (not shown) provided in the device 10 causes the signal POR to generate a rising edge. At time T1, the signals OSC_EN, JUDGE and MODE all have an initial level, that is, a low level. The initial setting process starts from time T1 (refer to Figure 5 ).

[0111] The start-up circuit (not shown) provided in the device 10 causes the signal OSC_EN to generate a rising edge at time T2 after a predetermined time Δt1 has passed from time T1, and further causes the signal JUDGE to generate a rising edge at time T3 after a predetermined time Δt2 has passed from time T2. The oscillation circuit 25a performs an oscillation operation only during the high level period of the signal OSC_EN, and generates and outputs the reference clock signal CLKa. During the low level period of the signal OSC_EN, the input signal to the inverter circuit 141 is fixed at a low level.

[0112] After time T3, time T4 comes. Before time T4, the mode setting signal MODE has an initial level, that is, a low level. The high-level mode setting signal MODE is the first mode setting signal MODE having a first value. The low-level mode setting signal MODE is the second mode setting signal MODE having a second value. Between time T3 and T4, the mode determination process is performed (refer to Figure 5 ). In device 10[1], after the mode determination process, at time T4, the level of the mode setting signal MODE is switched from a low level to a high level. In device 10[2], after the mode determination process, even after time T4, the mode setting signal MODE remains at a low level, and the mode setting signal MODE does not become a high level.

[0113] Reference Figures 14 to 18 , the operation of the synchronization management circuit 130 in the device 10[1] is described. Figures 14 to 18 In the example, "(L)" indicates that the corresponding signal has a low level, and "(H)" indicates that the corresponding signal has a high level (hereinafter referred to as Fig.19 and Fig. 20 The synchronization management circuit 130 of the device 10[1] is specifically referred to as the synchronization management circuit 130[1].

[0114] Fig.14 Indicates the state of the synchronization management circuit 130[1] before time T1. In the synchronization management circuit 130[1], during the low level period of the signal POR, the mode setting signal MODE has a low level, so the output signal of the OR circuit 148 is a high level, so that the transistors 149 and 150 are disconnected and the transistor 151 is turned on. In the device 10[1], the synchronization output terminal S_OUT[1] is substantially in an open state. Therefore, when in the device 10[1], the transistors 149 and 150 are disconnected and the transistor 151 is turned on, the synchronization output terminal S_OUT[1] is pulled down to ground (i.e., pulled down to a low level) by the transistor 151 via the resistor 152, so the signal CLKOUT has a low level. In addition, before time T1, the signals S11 to S13 are maintained at a low level.

[0115] Fig.15Indicates the state of the synchronization management circuit 130[1] from time T1 to time T2. Since the signal POR generates a rising edge at time T1, several signals other than the signal POR in the synchronization management circuit 130[1] also change in level. However, before time T2, since the signals S11 and S12 have been fixed at a low level, the signal S13 has a low level, and therefore the mode setting signal MODE has a low level. If the mode setting signal MODE is a low level, then based on the high level output signal from the OR circuit 148, the transistors 149 and 150 are turned off, and the transistor 151 is turned on, and the signal CLKOUT has a low level.

[0116] Fig.16 Indicates the state of the synchronization management circuit 130[1] from time T2 to time T3. During the period from time T2 to time T3, the input signals and output signals of the inverter circuits 141 and 142, and the signal S11 alternately change between the high level and the low level. In terms of the occurrence of the above changes, the period from time T2 to time T3 is different from the period from time T1 to time T2. However, since DFF161a~161d is in the reset state before time T3, the counter in the synchronization circuit 161 is not driven, so that the signal S13 has a low level. If the signal S13 is low, the mode setting signal MODE is also low. As described above, if the mode setting signal MODE is low, based on the high-level output signal from the OR circuit 148, the transistors 149 and 150 are turned off, and the transistor 151 is turned on, and the signal CLKOUT has a low level.

[0117] Fig.17 The state of the synchronization management circuit 130[1] from time T3 to time T4 is shown. In the synchronization management circuit 130[1], if the signal JUDGE is switched to a high level at time T3, the output signal of the DFF 171 generates a rising edge, and thus the output signals of the inverter circuit 172 and the AND circuit 145 generate falling edges. However, until time T4, the mode setting signal MODE is at a low level.

[0118] On the other hand, since the rising edge of the output signal of DFF171 is equivalent to the rising edge of signal S12, the reset state of DFF161a to 161d is released at time T3. In this way, in the synchronization management circuit 130[1], after time T3, the inverted signal of the reference clock signal CLKa is input to the synchronization circuit 161 as the clock signal S11. Therefore, in the synchronization management circuit 130[1], through the operation of the counter, at time T4, the input signal to the clock input terminal of DFF161e generates a rising edge, and as a result, the signal S13 generates a rising edge, and further, the mode setting signal MODE generates a rising edge.

[0119] Fig.18 Indicates the state of the synchronization management circuit 130[1] after time T4. In the synchronization management circuit 130[1], after time T4, based on the high-level signal S13 and POR, the mode setting signal MODE is maintained at a high level. In addition, with the rising edge of the signal JUDGE generated at time T3 as an opportunity, after time T4, the output signal of the AND circuit 145 has a low level. Therefore, in the synchronization management circuit 130[1], after time T4, the output signal of the OR circuit 148 has a low level. When the output signal of the OR circuit 148 is low, the transistor 151 is turned off, and a clock signal equivalent to the reference clock signal CLKa is supplied to the gates of the transistors 149 and 150 through the OR circuit 147 and the AND circuit 146. Therefore, the transistors 149 and 150 are alternately turned on and off in synchronization with the reference clock signal CLKa. In this way, in the synchronization management circuit 130[1], after time T4, the inverted signal of the reference clock signal CLKa appears as the signal CLKOUT. A signal CLKOUT corresponding to an inverted signal of the reference clock signal CLKa is output from the synchronous output terminal S_OUT[1] and supplied to the synchronous input terminal S_IN[2].

[0120] Reference Fig.19 and Fig. 20 , the operation of the synchronization management circuit 130 in the device 10[2] is described. The synchronization management circuit 130 of the device 10[2] is specifically referred to as the synchronization management circuit 130[2].

[0121] Fig.19 The state of the synchronization management circuit 130[2] from time T1 to time T3 is shown. Until time T3, as described for the synchronization management circuit 130[1], in the synchronization management circuit 130[2], the mode setting signal MODE also has a low level. Therefore, in the synchronization management circuit 130[2], until time T3, based on the low-level mode setting signal MODE, transistors 149 and 150 are turned off, and transistor 151 is turned on. However, the synchronization output terminal S_OUT[2] of the device 10[2] is always supplied with the internal power supply voltage Vreg. Therefore, in the synchronization management circuit 130[2], even if the transistor 151 is turned on, the signal CLKOUT has a high level. When the signal CLKOUT has a high level, the signal S11 is maintained at a low level through the functions of the circuits 162 to 164.

[0122] In the synchronization management circuit 130[2], at time T3, the signal JUDGE generates a rising edge, but after time T3, the signal CLKOUT is still fixed at a high level, so the signal S11 to the synchronization circuit 161 is fixed at a low level, and the counter is not driven. Therefore, in the synchronization management circuit 130[2], after time T1, the signal S13 is always at a low level, and as a result, the mode setting signal MODE is also always at a low level. Fig. 20 It shows the state of the synchronization management circuit 130[2] after time T4.

[0123] The period after time T4 is the normal operation period ( Figure 5 ), after time T4, normal operation is performed in devices 10[1] and 10[2] respectively. Normal operation includes switch control of output stage MM by switch control circuit 20. At least before time T4, in each device 10, transistors MH and ML are maintained to be turned off.

[0124] In the device 10[1], during the normal operation period, the switch control circuit 20 generates a signal SET from the reference clock signal CLKa based on the high-level mode setting signal MODE (first mode setting signal MODE), and performs switch control of the output stage MM synchronously with the generated signal SET (i.e., synchronously with the reference clock signal CLKa). In addition, during the normal operation period, the signal output circuit 140 in the device 10[1] receives the high-level mode setting signal MODE, and outputs the signal CLKOUT as the clock signal CLKb from the synchronous output terminal S_OUT[1]. The clock signal CLKb is input to the synchronous input terminal S_IN[2].

[0125] In the device 10[2], during normal operation, the switch control circuit 20 generates a signal SET from the input clock signal CLKb based on the low-level mode setting signal MODE (the second mode setting signal MODE), and performs switch control of the output stage MM synchronously with the generated signal SET (i.e., synchronously with the input clock signal CLKb).

[0126] Thus, the signal output circuit 140 pulls down the synchronous output terminal S_OUT to a low level via the resistor 152 during the execution period of the mode determination process (between time T3 and time T4). By this pull-down, in a state where a specific voltage (here, the internal power supply voltage Vreg) is not supplied to the synchronous output terminal S_OUT, the signal CLKOUT of the synchronous output terminal S_OUT has a low level during the execution period of the mode determination process. In a state where a specific voltage is supplied to the positive synchronous output terminal S_OUT, the signal CLKOUT of the synchronous output terminal S_OUT has a high level. In the device 10[i], if the level of the signal CLKOUT is a low level during the execution period of the mode determination process, the mode setting circuit 160 generates a rising edge of the mode setting signal MODE, and sets the operation mode of the device 10[i] to the first mode. If the level of the signal CLKOUT is a high level during the execution period of the mode determination process, the mode setting circuit 160 maintains the mode setting signal MODE at a low level, thereby setting the operation mode of the device 10[i] to the second mode.

[0127] In addition, as described above, the high-level mode setting signal MODE has a first value, and the mode setting signal MODE has a second value. When the signal of the synchronization output terminal S_OUT has a low level during the execution of the mode determination process, the mode setting circuit 160 drives the synchronization circuit 161 using the reference clock signal CLKa, thereby setting the first value for the mode setting signal MODE. When the signal of the synchronization output terminal S_OUT has a high level during the execution of the mode determination process, the mode setting circuit 160 also maintains the value of the mode setting signal MODE at the initial value, that is, the second value. In addition, the relationship between the first value and the second value and the high level and the low level may be opposite to that described above.

[0128] As a reference structure, the switching power supply device described below was discussed. In the switching power supply device involved in the reference structure, an external terminal dedicated to mode setting is provided for each power control device, and the operation mode of each power control device is set based on the input voltage toward the external terminal dedicated to mode setting. In the switching power supply device involved in the reference structure, since a dedicated external terminal is required, the power control device will be correspondingly large-scale. The enlargement of the power control device will also lead to an increase in cost. According to the switching power supply device 1 of this embodiment, the operation mode of each device 10 can be set without a dedicated external terminal, so the device 10 can be miniaturized and cost-effective.

[0129] <<Second embodiment>>

[0130] The second embodiment is described. The second embodiment and the following third to sixth embodiments are embodiments based on the first embodiment. For matters not specifically stated in the second to sixth embodiments, as long as there is no contradiction, the description of the first embodiment is also applicable to the second to sixth embodiments. However, when interpreting the description of the second embodiment, regarding matters that contradict each other between the first and second embodiments, the description of the second embodiment takes precedence (the same applies to the following third to sixth embodiments). Any multiple embodiments of the first to sixth embodiments may be combined as long as there is no contradiction.

[0131] The signal output circuit 40 in the device 10[i] may be configured in any manner as long as the synchronous output terminal S_OUT[i] is pulled down to a low level (e.g., grounded) via a resistor during the execution of the mode determination process. The mode setting circuit 60 in the device 10[i] may be configured in any manner as long as the operation mode of the device 10[i] is set to the first mode or the second mode based on the level of the signal at the synchronous output terminal S_OUT[i] during the execution of the mode determination process.

[0132] Fig.21 Another configuration example of the mode setting circuit 60 is shown in FIG. Fig.21 1 is a circuit diagram of a synchronization management circuit 230 of the second embodiment. The synchronization management circuit 230 includes a signal output circuit 140 and a mode setting circuit 260, and includes a DFF 171 and an inverting circuit 172. In the second embodiment, the synchronization management circuit 230, the signal output circuit 140, and the mode setting circuit 260 are used as the synchronization management circuit 30, the signal output circuit 40, and the mode setting circuit 60 in each device 10, respectively (see Figure 4 ).

[0133] by Fig.11 The synchronization management circuit 130 is used as a reference, and the mode setting circuit 160 is replaced by the mode setting circuit 260, thereby obtaining Fig.21 In addition to the above replacement and the following matters, Fig.21 The structure and operation of the synchronization management circuit 230 are similar to Fig.11 The structure and operation of the synchronization management circuit 130 are the same.

[0134] The mode setting circuit 260 includes a comparator 261, an inverter circuit 262, and a DFF 263. Fig.12 The same composition as DFF170.

[0135] The comparator 261 has a non-inverting input terminal, an inverting input terminal, and an output terminal. The signal CLKOUT and the voltage Vjudge are input to the non-inverting input terminal and the inverting input terminal of the comparator 261, respectively. The voltage Vjudge is a reference voltage for determination having a predetermined positive DC voltage value. As described above, the signal CLKOUT is a signal in the synchronous output terminal S_OUT. When the voltage of the signal CLKOUT is higher than the voltage Vjudge, the comparator 261 outputs a high-level signal from its output terminal, and when the voltage of the signal CLKOUT is lower than the voltage Vjudge, the comparator 261 outputs a low-level signal from its output terminal. The value of the voltage Vjudge is set in such a way that when the signal CLKOUT has a high level, a high-level signal is output from the comparator 261, and when the signal CLKOUT has a low level, a low-level signal is output from the comparator 261. "Vth_L<Vjudge<Vth_H" can be established. In addition, a hysteresis characteristic can also be given to the comparator 261.

[0136] The inverting circuit 262 outputs an inverted signal of the output signal of the comparator 261. The output signal of the inverting circuit 262 is input to the data input terminal (D) of the DFF 263. The signals JUDGE and POR are input to the clock input terminal (CP) and the reset input terminal of the DFF 263, respectively. The mode setting signal MODE is output from the data output terminal (Q) of the DFF 263.

[0137] In the second embodiment, the timing diagram of the device 10 when starting is similar to Fig.13 The timing diagram shown is the same. However, the time difference between time T3 and T4 in the second embodiment is shorter than that in the first embodiment. This time difference is equivalent to the transmission delay time from the rising edge of the signal JUDGE to the signal at the data input terminal (D) of DFF263 being reflected on the signal at the data output terminal (Q) of DFF263.

[0138] As described in the first embodiment, before time T4, the mode setting signal MODE has an initial level, ie, a low level.

[0139] In the device 10[1], after the mode determination process, at time T4, the level of the mode setting signal MODE is switched from a low level to a high level. This is because: in the device 10[1], before the signal JUDGE generates a rising edge and at the time when the signal JUDGE generates a rising edge, the signal CLKOUT has a low level, so the input signal to the data input terminal (D) of the DFF263 has a high level.

[0140] In contrast, in device 10[2], after the mode determination process, the mode setting signal MODE remains at a low level even after time T4, and the mode setting signal MODE does not become a high level. This is because: in device 10[1], before the signal JUDGE generates a rising edge and at the time when the signal JUDGE generates a rising edge, the signal CLKOUT has a high level, so the input signal to the data input terminal (D) of DFF263 has a low level.

[0141] <<Third embodiment>>

[0142] The third embodiment is described. The specific voltage supply source is arbitrary as long as it can supply the specific voltage to the synchronous output terminal S_OUT[2] from the outside of the device 10[2]. Therefore, for example, the specific voltage can be supplied to the synchronous output terminal S_OUT[2] from a DC voltage source (not shown) provided outside the device 10[2].

[0143] <<Fourth embodiment>>

[0144] A fourth embodiment will be described. A switching power supply device may be formed using one device 10. Fig. 22 The switching power supply device 1a shown. Figure 1 The switching power supply device 1 is provided with two groups of devices 10 and coils L, and a switching power supply device 1a can be obtained by omitting one of the groups from the switching power supply device 1. Figure 3 The switching power supply device 1a can be obtained by omitting the device 10[2] and the coil L[2]. In the switching power supply device 1a, only one synchronous output terminal S_OUT of the device 10 is opened or grounded. As a result, the operation mode of the device 10 in the switching power supply device 1a is set to the first mode.

[0145] Furthermore, the above description is an example in which the switching power supply devices 1 and 1 a are configured as step-down DC / DC converters, but the switching power supply devices 1 and 1 a may be configured as step-up or step-up / step-down DC / DC converters.

[0146] <<Fifth embodiment>>

[0147] The fifth embodiment is described. Figure 1 The switching power supply device 1 is an example of a semiconductor system having a first semiconductor device and a second semiconductor device. Devices 10[1] and 10[2] are examples of a first semiconductor device and a second semiconductor device. Each semiconductor device includes a functional circuit having a predetermined function. The functional circuit in the device 10 has a switching control circuit 20 and an output stage MM, and performs an operation for converting an input voltage Vin into an output voltage Vout.

[0148] In the present disclosure, the semiconductor device is not limited to a power supply control device assembled in a switching power supply device. The technology disclosed in the present disclosure can be widely applied to any semiconductor system that needs to synchronize the first and second semiconductor devices. For example, each semiconductor device can be a driver device that drives a specified load (light-emitting element, display device, motor, etc.), and in this case, the functional circuit of each semiconductor device performs control to drive the specified load as desired.

[0149] <<Sixth embodiment>>

[0150] The sixth embodiment is described.

[0151] Regarding arbitrary signals or voltages, the relationship between their high level and low level may be opposite to that described above within the scope not detrimental to the subject matter described above.

[0152] The types of channels of FETs (field effect transistors) described in the above embodiments are merely examples, and the types of channels of any FETs may be changed between P-channel type and N-channel type without prejudice to the above-described gist.

[0153] As long as it does not cause any problem, the arbitrary transistor can be any type of transistor. For example, as long as it does not cause any problem, the arbitrary transistor stated above as MOSFET can be replaced by a junction FET, an IGBT (Insulated Gate Bipolar Transistor) or a bipolar transistor. Any transistor has a first electrode, a second electrode and a control electrode. In a FET, one of the first and second electrodes is a drain, the other is a source, and the control electrode is a gate. In an IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is a gate. In a bipolar transistor that is not an IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is a base.

[0154] The embodiments of the present disclosure may be appropriately modified within the scope of the technical concept shown in the claims. The embodiments described above are ultimately examples of the embodiments of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to the meanings described in the embodiments described above. The specific numerical values ​​described in the description are merely examples, and they can of course be changed to various numerical values.

[0155] <<Note>>

[0156] With respect to the present disclosure, in which specific configuration examples are shown through the above-described embodiments, supplementary notes are given.

[0157] A semiconductor device (10) of one form disclosed herein is configured as follows (first configuration), namely, comprising: a synchronous input terminal (S_IN); a synchronous output terminal (S_OUT); a functional circuit (20) having a reference clock signal generating circuit (25a) configured to generate a reference clock signal (CLKa); a signal output circuit (40) connected to the synchronous output terminal; and a mode setting circuit (60) configured to set the operation mode of the functional circuit and the signal output circuit to a first mode or a second mode based on a result of a mode determination process after performing a mode determination process; the functional circuit performs a prescribed functional operation in synchronization with the reference clock signal in the first mode, and performs the prescribed functional operation in synchronization with an input clock signal (CLKb) supplied from another semiconductor device to the synchronous input terminal in the second mode; the signal output circuit outputs a clock signal based on the reference clock signal from the synchronous output terminal in the first mode, and the mode setting circuit determines in the mode determination process whether a specific voltage (e.g., Vreg) satisfying a prescribed condition is supplied to the synchronous output terminal from outside the semiconductor device.

[0158] According to the semiconductor device, the mode can be set by using the synchronization input terminal and the synchronization output terminal originally provided for transmitting the clock signal. That is, the dedicated terminal for setting the mode can be omitted, which contributes to the miniaturization and cost reduction of the semiconductor device.

[0159] It may also be the following configuration (second configuration), that is, in the semiconductor device of the first configuration, when the mode setting circuit determines in the mode determination process that the specific voltage is in a supply state with respect to the synchronous output terminal, the action mode is set to the second mode, and when it is determined that the specific voltage is in a non-supply state with respect to the synchronous output terminal, the action mode is set to the first mode.

[0160] The following configuration (third configuration) may be adopted: in the semiconductor device of the second configuration (see Fig.11 or Fig.21 ), the signal output circuit pulls down the synchronization output terminal to the first level (low level) via the resistor (152) during the execution of the mode determination processing. By the pull-down, in the non-supply state of the specific voltage, during the execution of the mode determination processing, the signal of the synchronization output terminal has the first level, and in the supply state of the specific voltage, the signal of the synchronization output terminal has a second level (high level) higher than the first level. The mode setting circuit sets the action mode to the first mode or the second mode based on the level of the signal of the synchronization output terminal during the execution of the mode determination processing.

[0161] The following configuration (fourth configuration) may be adopted: in the semiconductor device of the third configuration (see Fig.11 ), the mode setting circuit (160) generates a mode setting signal (MODE) corresponding to the result of the mode determination processing, the mode setting signal has a first value or a second value, after the mode determination processing, when the mode setting signal has the first value, the action mode is the first mode, and when the mode setting signal has the second value, the action mode is the second mode, the mode setting circuit has a synchronization circuit (161), when the signal of the synchronization output terminal has the first level during the execution of the mode determination processing, the synchronization circuit is driven by the reference clock signal, thereby setting the first value for the mode setting signal, and when the signal of the synchronization output terminal has the second level during the execution of the mode determination processing, the mode setting signal is maintained at an initial value, that is, the second value.

[0162] The following configuration (fifth configuration) may be adopted: Fig.21 ), the mode setting circuit (260) generates a mode setting signal (MODE) corresponding to the result of the mode determination processing, the mode setting signal has a first value or a second value, after the mode determination processing, the action mode when the mode setting signal has the first value is the first mode, and the action mode when the mode setting signal has the second value is the second mode, in the mode determination processing, the mode setting circuit uses a comparator (261) to compare the voltage of the signal of the synchronization output terminal with a specified judgment reference voltage (Vjudge), when the voltage of the signal of the synchronization output terminal is lower than the judgment reference voltage, the mode setting signal is set to the first value, when the voltage of the signal of the synchronization output terminal is higher than the judgment reference voltage, the mode setting signal is set to the second value.

[0163] It may also be the following configuration (the sixth configuration), that is, in the semiconductor device of any one of the first to fifth configurations, the semiconductor device is a power supply control device (10), which is arranged in a switching power supply device configured in a manner of generating an output voltage (Vout) from an input voltage (Vin); the functional circuit comprises: an output stage (MM), which is arranged between an application end of the input voltage and an application end of the output voltage; and a switching control circuit (20), which is configured in a manner of converting the input voltage power into the output voltage by performing switching control of the output stage; and the switching control is performed in synchronization with the reference clock signal in the first mode, and in synchronization with the input clock signal in the second mode.

[0164] A semiconductor system according to one form of the present disclosure is configured as follows (the seventh configuration), namely, a semiconductor system comprising a first and a second semiconductor device (10[1], 10[2]), each semiconductor device being a semiconductor device of any one of the first to fifth configurations, the synchronization output terminal (S_OUT[1]) of the first semiconductor device being connected to the synchronization input terminal (S_IN[2]) of the second semiconductor device, and the specific voltage (Vreg) being supplied to the synchronization output terminal of the second semiconductor device via a wiring (Wr) provided outside the second semiconductor device, and in the first semiconductor device, the mode setting circuit sets the operation mode to the first mode, and in the second semiconductor device, the mode setting circuit sets the operation mode to the second mode.

[0165] A switching power supply device according to one aspect of the present disclosure is configured as follows (eighth configuration), namely, a switching power supply device (1) configured in such a way that an output voltage (Vout) is generated from an input voltage (Vin), comprising first and second power supply control devices (10[1], 10[2]), each of which is a semiconductor device of the sixth configuration, the synchronization output terminal (S_OUT[1]) of the first power supply control device being connected to the synchronization input terminal (S_IN[2]) of the second power supply control device, and the synchronization output terminal (S_OUT[1]) of the first power supply control device being connected to the synchronization input terminal (S_IN[2]) of the second power supply control device, and the synchronization output terminal (S_OUT[1]) of the first power supply control device being connected to the synchronization input terminal (S_IN[2]) of the second power supply control device being connected to the synchronization input terminal (S_IN[2]) of the second power supply control device. The specific voltage (Vreg) is supplied to the synchronous output terminal of the second power supply control device through an external wiring (Wr) arranged therein, in the first power supply control device, the mode setting circuit sets the operation mode to the first mode, and in the second power supply control device, the mode setting circuit sets the operation mode to the second mode, and a current is supplied from the application end (IN) of the input voltage to the application end (OUT) of the output voltage through the output stage of the first power supply control device and the output stage of the second power supply control device.

[0166] [Explanation of Symbols]

[0167] 1,1a:Switching power supply device

[0168] Vin: Input voltage

[0169] Vout: output voltage

[0170] Vfb: Feedback voltage

[0171] Vreg: internal power supply voltage

[0172] L,L[i]: coil

[0173] Cout: output capacitor

[0174] R1, R2: Feedback resistors

[0175] IN: Input terminal

[0176] SW: switch terminal

[0177] GND: Ground terminal

[0178] FB: Feedback terminal

[0179] CMPOUT: Error common terminal

[0180] S_IN, S_IN[i]: Synchronous input terminal

[0181] S_OUT, S_OUT[i]: Synchronous output terminal

[0182] REG: Internal power output terminal

[0183] Creg:Capacitor

[0184] Wc, Ws, Wr: External wiring

[0185] 10,10[i]: Power supply control device

[0186] 20: Switch control circuit

[0187] 21: Error amplifier

[0188] 22: Sensing circuit

[0189] 23: Reset circuit

[0190] 24: Switching circuit

[0191] 25: Setting up the circuit

[0192] 25a: Oscillator Circuit

[0193] 26: Controller

[0194] 30: Synchronous management circuit

[0195] 40:Signal output circuit

[0196] 60: Mode setting circuit

[0197] 80: Internal power circuit

[0198] MM: Output stage

[0199] MH,ML:Transistor

[0200] GH, GL: Gate signal

[0201] MODE: Mode setting signal

[0202] CLKa: reference clock signal

[0203] CLKb: Input clock signal

[0204] 130,130[i],230: Synchronous management circuit

[0205] 140:Signal output circuit

[0206] 141~144,161f,161g,162,172,262: Inverting circuit

[0207] 145,146,163~165:AND circuit

[0208] 147,148:OR circuit

[0209] 149~151: Transistor

[0210] 152: Resistance

[0211] 160,260: Mode setting circuit

[0212] 161: Synchronous circuit

[0213] 161a~161e,171,263:DFF

[0214] 261: Comparator.

Claims

1. A semiconductor device comprising: Synchronous input terminal; Synchronous output terminal; The functional circuit has a reference clock signal generating circuit configured to generate a reference clock signal; A signal output circuit connected to the synchronous output terminal; as well as a mode setting circuit configured to set the operation mode of the functional circuit and the signal output circuit to the first mode or the second mode based on the result of the mode determination processing after performing the mode determination processing; The functional circuit performs a predetermined functional operation in synchronization with the reference clock signal in the first mode, and performs the functional operation in synchronization with an input clock signal supplied from another semiconductor device to the synchronization input terminal in the second mode; The signal output circuit outputs a clock signal based on the reference clock signal from the synchronization output terminal in the first mode, The mode setting circuit determines in the mode determination process whether a specific voltage satisfying a predetermined condition is supplied to the synchronous output terminal from outside the semiconductor device.

2. A semiconductor device according to claim 1, wherein the mode setting circuit sets the action mode to the second mode when it is determined in the mode determination process that the specific voltage is in a supply state to the synchronous output terminal, and sets the action mode to the first mode when it is determined that the specific voltage is in a non-supply state to the synchronous output terminal.

3. The semiconductor device according to claim 2, wherein the signal output circuit pulls down the synchronization output terminal to the first level via a resistor during the execution period of the mode determination process, By the pull-down, in the non-supply state of the specific voltage, during the execution period of the mode determination process, the signal of the synchronization output terminal has the first level, In the supply state of the specific voltage, the signal of the synchronization output terminal has a second level higher than the first level, The mode setting circuit sets the operation mode to the first mode or the second mode based on the level of the signal at the synchronization output terminal during the execution period of the mode determination process.

4. The semiconductor device according to claim 3, wherein the mode setting circuit generates a mode setting signal corresponding to a result of the mode determination process, The mode setting signal has a first value or a second value, After the mode determination process, when the mode setting signal has the first value, the operation mode is the first mode, and when the mode setting signal has the second value, the operation mode is the second mode. The mode setting circuit has a synchronization circuit. When the signal at the synchronization output terminal has the first level during the execution of the mode determination processing, the synchronization circuit is driven by the reference clock signal to set the first value for the mode setting signal. When the signal at the synchronization output terminal has the second level during the execution of the mode determination processing, the mode setting signal is maintained at an initial value, i.e., the second value.

5. The semiconductor device according to claim 3, wherein the mode setting circuit generates a mode setting signal corresponding to a result of the mode determination process, The mode setting signal has a first value or a second value, After the mode determination process, when the mode setting signal has the first value, the operation mode is the first mode, and when the mode setting signal has the second value, the operation mode is the second mode. In the mode determination process, the mode setting circuit uses a comparator to compare the voltage of the signal of the synchronization output terminal with a specified reference voltage for determination. When the voltage of the signal of the synchronization output terminal is lower than the reference voltage for determination, the mode setting signal is set to the first value; when the voltage of the signal of the synchronization output terminal is higher than the reference voltage for determination, the mode setting signal is set to the second value.

6. The semiconductor device according to any one of claims 1 to 5, wherein the semiconductor device is a power supply control device provided in a switching power supply device configured to generate an output voltage from an input voltage; The functional circuit comprises: an output stage, which is arranged between the application end of the input voltage and the application end of the output voltage; and a switching control circuit, which is configured to convert the input voltage power into the output voltage by performing switching control of the output stage; and the switching control is performed synchronously with the reference clock signal in the first mode, and the switching control is performed synchronously with the input clock signal in the second mode.

7. A semiconductor system comprising first and second semiconductor devices, Each semiconductor device is a semiconductor device according to any one of claims 1 to 5, The synchronization output terminal of the first semiconductor device is connected to the synchronization input terminal of the second semiconductor device, and the specific voltage is supplied to the synchronization output terminal of the second semiconductor device through a wiring provided outside the second semiconductor device. In the first semiconductor device, the mode setting circuit sets the operation mode to the first mode, and in the second semiconductor device, the mode setting circuit sets the operation mode to the second mode.

8. A switching power supply device, configured to generate an output voltage from an input voltage, comprising first and second power supply control devices, each of which is a semiconductor device according to claim 6, The synchronization output terminal of the first power supply control device is connected to the synchronization input terminal of the second power supply control device, and the specific voltage is supplied to the synchronization output terminal of the second power supply control device through wiring provided outside the second power supply control device. In the first power supply control device, the mode setting circuit sets the operation mode to the first mode, and in the second power supply control device, the mode setting circuit sets the operation mode to the second mode, A current is supplied from the input voltage application end to the output voltage application end through the output stage of the first power supply control device and the output stage of the second power supply control device.

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