Radio frequency millimeter wave frequency multiplier circuit

Abstract

The invention discloses a radio frequency millimeter wave frequency multiplier circuit, which comprises a first duty ratio adjusting circuit, a second duty ratio adjusting circuit, a third duty ratio adjusting circuit and a fourth duty ratio adjusting circuit, and is characterized in that the first duty ratio adjusting circuit comprises a duty ratio calibration circuit, a duty ratio detection circuit, a charge pump and a loop filter, and the duty ratio calibration circuit is used for adjusting the duty ratio of a first differential signal received by the current stage according to a feedback signal output by the previous stage; outputting a second differential signal with the same duty ratio at the current stage; the duty ratio detection circuit is used for outputting a common-mode voltage signal; the charge pump is used for converting the common-mode voltage signal into a current signal; the loop filter is used for adjusting and converting the current signal into a feedback signal and outputting a feedback signal required by a next stage to the duty ratio calibration circuit; the first time delay circuit is used for delaying the second differential signal; and the first frequency multiplier circuit is used for multiply increasing the frequency of the second differential signal according to the delayed second differential signal. The frequency multiplier provided by the invention has the advantages of wide bandwidth, full simulation, quick calibration, low power consumption and small occupied area.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog-digital hybrid integrated circuits, and in particular relates to a radio frequency millimeter wave frequency multiplier circuit. Background Art

[0002] At present, there are two main forms of high-frequency phase-locked loops. One is to directly use a high-frequency phase-locked loop, which directly puts forward high requirements on the output frequency of the voltage-controlled oscillator (VCO) in the high-frequency phase-locked loop (PLL). The other is to first use a phase-locked loop (PLL) to generate an output signal, and then increase the frequency of the signal by 2, 4 or 8 times through a frequency multiplier. Among them, the direct use of high-frequency phase-locked loop output method generates a high-frequency signal by using VCO, which has high spectral purity and excellent harmonic performance. However, the phase noise of PLL will deteriorate with the increase of the division ratio. The industry generally uses a reference clock frequency of about 100MHz, which means that when the PLL works at a high frequency of tens of GHz, it needs to deal with an extremely high division ratio, which inevitably damages the phase noise performance. Therefore, the frequency multiplication output method has received widespread attention.

[0003] In the frequency multiplication output mode, the PLL has better phase noise performance, and the high-performance frequency multiplier has a very small impact on the phase noise. However, in the frequency multiplication output mode, the main challenge is that the frequency multiplier requires a large amount of inductance in broadband applications, resulting in it occupying too large an area in the overall design. Therefore, the development of a frequency multiplier with a small area, wide bandwidth and high efficiency has become an urgent need in the industry. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a radio frequency millimeter wave frequency multiplier circuit. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0005] In a first aspect, the present invention provides a radio frequency millimeter wave frequency multiplier circuit, comprising:

[0006] A first duty cycle adjustment circuit comprises a duty cycle calibration circuit, a duty cycle detection circuit, a charge pump and a loop filter, wherein an input end of the duty cycle calibration circuit receives a first differential signal, and the duty cycle calibration circuit is used to adjust the duty cycle of the first differential signal received at this stage according to a feedback signal outputted by a previous stage, and output a second differential signal having the same duty cycle as that of this stage; an output end of the duty cycle calibration circuit is electrically connected to an input end of the duty cycle detection circuit, and the duty cycle detection circuit is used to output a common-mode voltage signal; an output end of the duty cycle detection circuit is electrically connected to an input end of the charge pump, and the charge pump is used to convert the common-mode voltage signal into a current signal; an output end of the charge pump is electrically connected to an input end of the loop filter, and the loop filter is used to adjust and convert the current signal into a feedback signal; an output end of the loop filter is electrically connected to an input end of the duty cycle calibration circuit, and is used to output a feedback signal required for a next stage to the duty cycle calibration circuit;

[0007] A first delay circuit, comprising a delay path consisting of two sets of inverter chains, an input end of the first delay circuit being electrically connected to an output end of the duty cycle calibration circuit, and the first delay circuit being used to delay the second differential signal;

[0008] The first frequency multiplier circuit has an input terminal electrically connected to the output terminal of the first delay circuit and the output terminal of the duty cycle calibration circuit respectively, and is used for multiplying the frequency of the second differential signal according to the delayed second differential signal.

[0009] Beneficial effects of the present invention:

[0010] A radio frequency millimeter wave frequency multiplier circuit provided by the present invention comprises a first duty cycle adjustment circuit, a first delay circuit and a first frequency multiplier circuit, wherein the first duty cycle adjustment circuit comprises a duty cycle calibration circuit, a duty cycle detection circuit, a charge pump and a loop filter, a first differential signal enters the duty cycle calibration circuit, and after AC coupling, the common mode voltage of the second signal in the first differential signal is changed by the negative feedback signal fed back by the loop filter, so that the common mode voltage thereof is equal to the common mode voltage of the first signal in the first differential signal, and the duty cycle of the first differential signal is adjusted and input into the duty cycle detection circuit and the first frequency multiplier circuit, and the duty cycle detection circuit detects the The duty cycle difference voltage is converted into a current signal by a charge pump, and then adjusted by a loop filter to output a feedback signal, which is used in the next stage of processing. The current stage processes the first differential signal using the feedback signal output by the previous stage; before the first frequency multiplier circuit increases the frequency of the second differential signal, it is also necessary to use a first delay circuit to delay the second differential signal, and then increase the frequency of the second differential signal; in this way, the present embodiment introduces the first duty cycle adjustment circuit, which can not only adjust the duty cycle of the output signal of the first frequency multiplier circuit, but also play a role in amplitude amplification, and can provide a frequency multiplier with wide bandwidth, full analog fast calibration, low power consumption and small footprint.

[0011] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a schematic diagram of a radio frequency millimeter wave frequency multiplier circuit provided by an embodiment of the present invention;

[0013] Figure 2 is a schematic diagram of a duty cycle calibration circuit provided by an embodiment of the present invention;

[0014] Figure 3 is a schematic diagram of a duty cycle detection circuit provided by an embodiment of the present invention;

[0015] Figure 4 is a schematic diagram of a charge pump and a loop filter provided by an embodiment of the present invention;

[0016] Figure 5 is a schematic diagram of a first delay circuit provided by an embodiment of the present invention;

[0017] Figure 6 is a schematic diagram of a first frequency multiplier circuit provided by an embodiment of the present invention;

[0018] Figure 7 is a schematic diagram of calibration speed comparison provided by an embodiment of the present invention;

[0019] Figure 8 is a schematic diagram of a loop convergence process provided by an embodiment of the present invention;

[0020] Fig. 9 It is a schematic diagram of a transient waveform diagram of a 48 GHz output frequency multiplier provided in an embodiment of the present invention;

[0021] Fig.10 It is a schematic diagram of the frequency spectrum of the output signal of the frequency multiplier before and after the duty cycle calibration provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0023] A frequency multiplier is essentially a circuit system that multiplies the frequency of an input signal. The input signal passes through a nonlinear system, and harmonics of the input signal are generated at the output. The fundamental wave and harmful harmonics are filtered out through a filtering network, thereby obtaining relatively pure useful harmonic components.

[0024] There are many types of frequency multipliers according to different working principles and classification methods. They can be divided into passive frequency multipliers and active frequency multipliers according to whether power is required during operation. Among them, passive frequency multipliers use nonlinear circuit elements (such as diodes, varactor diodes, etc.) and do not require external power to drive the frequency multiplier. They can multiply the frequency of the input signal. In passive frequency multipliers, nonlinear elements play a core role and achieve the frequency multiplication effect through their unique nonlinear characteristics; active frequency multipliers mainly use active components such as bipolar transistors or field effect transistors as core components, and achieve frequency multiplication through the nonlinear characteristics of these components. If the active components are to generate high-order harmonics, the key is to bias them in the nonlinear working area.

[0025] In the present invention, the fast response characteristics of the CMOS process are utilized to create a wide bandwidth, fully analog fast calibration, low power consumption and small occupied area frequency multiplier composed of three parts: a MOS passive mixer, a duty cycle adjustment circuit and a delay circuit. The focus of the present invention is the introduction of a duty cycle adjustment circuit, which not only adjusts the duty cycle of the mixer output signal, but also plays a role in amplitude amplification. The signal quality of the final output is significantly improved after the duty cycle adjustment and two-stage amplification. The difficulty of the present invention lies in how to make a certain phase difference between the input signals when the MOS passive mixer is used as a frequency multiplier. If there is no phase difference between the input signals, the frequency multiplier will not function normally. In view of this, in order to ensure the normal operation of the frequency multiplier, the present invention introduces a delay circuit, which is composed of two groups of inverters, and uses different inverters to adjust the delay to improve the errors that may be introduced in the manufacturing process.

[0026] See also Figure 1 , Figure 1 : is a schematic diagram of a radio frequency millimeter wave frequency multiplier circuit provided by an embodiment of the present invention. The radio frequency millimeter wave frequency multiplier circuit provided by the present invention includes:

[0027] A first duty cycle adjustment circuit comprises a duty cycle calibration circuit, a duty cycle detection circuit, a charge pump and a loop filter, wherein an input end of the duty cycle calibration circuit receives a first differential signal, and the duty cycle calibration circuit is used to adjust the duty cycle of the first differential signal received at this stage according to a feedback signal outputted by a previous stage, and output a second differential signal having the same duty cycle as that of this stage; an output end of the duty cycle calibration circuit is electrically connected to an input end of the duty cycle detection circuit, and the duty cycle detection circuit is used to output a common-mode voltage signal; an output end of the duty cycle detection circuit is electrically connected to an input end of the charge pump, and the charge pump is used to convert the common-mode voltage signal into a current signal; an output end of the charge pump is electrically connected to an input end of the loop filter, and the loop filter is used to adjust and convert the current signal into a feedback signal; an output end of the loop filter is electrically connected to an input end of the duty cycle calibration circuit, and is used to output a feedback signal required for a next stage to the duty cycle calibration circuit;

[0028] A first delay circuit, comprising a delay path consisting of two sets of inverter chains, an input end of the first delay circuit being electrically connected to an output end of the duty cycle calibration circuit, and the first delay circuit being used to delay the second differential signal;

[0029] The first frequency multiplier circuit has an input terminal electrically connected to the output terminal of the first delay circuit and the output terminal of the duty cycle calibration circuit respectively, and is used for multiplying the frequency of the second differential signal according to the delayed second differential signal.

[0030] For more details, please see Figure 1 The present embodiment provides a radio frequency millimeter wave frequency multiplier circuit, comprising a first duty cycle adjustment circuit, a first delay circuit and a first frequency multiplier circuit, wherein the first duty cycle adjustment circuit comprises a duty cycle calibration circuit, a duty cycle detection circuit, a charge pump and a loop filter, the first differential signal enters the duty cycle calibration circuit, after AC coupling, the common mode voltage of the signal 2 in the first differential signal is changed by the negative feedback signal fed back by the loop filter, so that the common mode voltage thereof is equal to the common mode voltage of the signal 1 in the first differential signal, and the duty cycle of the first differential signal is adjusted and input into the duty cycle detection circuit and the first frequency multiplier circuit, the duty cycle detection circuit detects A duty cycle difference voltage is output, and converted into a current signal through a charge pump, and then adjusted by a loop filter to output a feedback signal, which is used in the next stage of processing. This stage processes the first differential signal using the feedback signal output by the previous stage; before the first frequency multiplier circuit increases the frequency of the second differential signal, it is also necessary to use a first delay circuit to delay the second differential signal, and then increase the frequency of the second differential signal; in this way, the present embodiment introduces the first duty cycle adjustment circuit, which can not only adjust the duty cycle of the output signal of the first frequency multiplier circuit, but also play a role in amplitude amplification, and can provide a frequency multiplier with wide bandwidth, full analog fast calibration, low power consumption and small footprint.

[0031] It should be noted that Figure 1 The illustrated embodiment only schematically shows the schematic diagram of each structure in the RF millimeter wave frequency multiplier circuit, and does not represent its actual schematic diagram. Figure 1 The first delay circuit structure is not shown in the figure.

[0032] In an optional embodiment of the present invention, please continue to refer to Figure 1 , further comprising a second duty cycle adjustment circuit, a second delay circuit and a second frequency multiplier circuit, wherein the input end of the second duty cycle adjustment circuit is electrically connected to the output end of the first frequency multiplier circuit, the output end of the second duty cycle adjustment circuit is electrically connected to the input end of the second delay circuit, the output end of the second duty cycle adjustment circuit is also electrically connected to the input end of the second frequency multiplier circuit, and the output end of the second delay circuit is electrically connected to the input end of the second frequency multiplier circuit;

[0033] Among them, the structure of the second duty cycle adjustment circuit is the same as that of the first duty cycle adjustment circuit, the structure of the second delay circuit is the same as that of the first delay circuit, and the structure of the second frequency multiplier circuit is the same as that of the first frequency multiplier circuit.

[0034] Specifically, in this embodiment, after the frequency of the first differential signal is doubled by the first frequency multiplier, the frequency of the first differential signal whose frequency is doubled is doubled again by the second frequency multiplier, and the frequency of the output differential signal is four times the frequency of the first differential signal.

[0035] In an optional embodiment of the present invention, see Figure 2 , Figure 2 : is a schematic diagram of a duty cycle calibration circuit provided by an embodiment of the present invention, the duty cycle calibration circuit includes a first input terminal, a first capacitor, a first transimpedance amplifier, a first two-stage inverter and a first output terminal, the first input terminal is electrically connected to the first terminal of the first capacitor, the second terminal of the first capacitor is electrically connected to the input terminal of the first transimpedance amplifier, the output terminal of the first transimpedance amplifier is electrically connected to the input terminal of the first two-stage inverter, and the output terminal of the first two-stage inverter is electrically connected to the first output terminal; wherein the first capacitor is used to filter out the DC part after AC coupling of a signal one in the first differential signal, the first transimpedance amplifier is used to convert a signal one in the processed first differential signal into a first square wave signal, the first two-stage inverter is used to add drive to the first square wave signal, and the first output terminal outputs a signal one of the second differential signal;

[0036] The duty cycle calibration circuit includes a second input terminal, a feedback signal input terminal, a second capacitor, a second transimpedance amplifier, a second two-stage inverter and a second output terminal, wherein the second input terminal is electrically connected to the first end of the second capacitor, the second end of the second capacitor is electrically connected to the input end of the second transimpedance amplifier, the feedback signal input terminal is electrically connected to the input end of the second transimpedance amplifier, the output end of the second transimpedance amplifier is electrically connected to the input end of the second two-stage inverter, and the output end of the second two-stage inverter is electrically connected to the second output terminal; wherein the second capacitor is used to filter out the DC part after AC coupling of signal 2 in the first differential signal, add the processed signal 2 in the first differential signal to the feedback signal outputted by the previous stage, the second transimpedance amplifier is used to convert the added signal into a second square wave signal, the second two-stage inverter is used to add drive to the second square wave signal, and output signal 2 in the second differential signal from the second output terminal.

[0037] For more details, please refer to Figure 2In this embodiment, the first differential signals VIN_P and VIN_N enter the duty cycle calibration circuit, and the signal VIN_N in the first differential signal is AC-coupled by the first capacitor C1 to filter out the DC part, and then passes through the first transimpedance amplifier composed of the resistor R2, the transistor M3, the transistor M4, the transistor M5 and the transistor M6 to form a first square wave signal with a common mode of 0.5V and a swing of 1V; the signal VIN_P in the first differential signal is AC-coupled by the second capacitor C2 to filter out the DC part, and intersects with the feedback signal VDT fed back from the loop filter, and passes through the resistor R3, the transistor M7, the transistor M8 and the transistor M9. 8. After the second transimpedance amplifier composed of transistor M9 and transistor M10, a second square wave signal with a common mode of VDT and a swing of 1V is formed; the first square wave signal is driven by a first two-stage inverter composed of transistor M13, transistor M14, transistor M17 and transistor M18 to output signal one in the second differential signal; the second square wave signal is driven by a second two-stage inverter composed of transistor M15, transistor M16, transistor M19 and transistor M20 to output signal two in the second differential signal, and signal one in the second differential signal and signal two in the second differential signal are differential signals with the same duty cycle.

[0038] In an optional embodiment of the present invention, please continue to refer to Figure 2 The duty cycle calibration circuit also includes a positive feedback circuit, the input end of the positive feedback circuit is electrically connected to the output end of the first two-stage inverter and the output end of the second two-stage inverter respectively, and the positive feedback circuit is used to adjust the duty cycle error caused by the delay of the first two-stage inverter and the second two-stage inverter.

[0039] For more details, please see Figure 2 In this embodiment, the duty cycle calibration circuit also includes a positive feedback loop composed of a transistor M21, a transistor M22, a transistor M23 and a transistor M24, which is used to adjust the duty cycle error caused by the delay of the first two-stage inverter and the second two-stage inverter, so that the duty cycle of the signal one in the second differential signal and the signal two in the second differential signal is the same.

[0040] In an optional embodiment of the present invention, see Figure 3 , Figure 3 is a schematic diagram of a duty cycle detection circuit provided by an embodiment of the present invention, the duty cycle detection circuit includes a first inverter, a second inverter, a third capacitor and a fourth capacitor, and the structure of the first inverter is the same as that of the second inverter;

[0041] Among them, the first inverter is used to process signal one in the second differential signal, and the processed signal one in the second differential signal is charged to the third capacitor. The second inverter is used to process signal two in the second differential signal, and the processed signal two in the second differential signal is charged to the fourth capacitor to output a common mode voltage signal.

[0042] For more details, please see Figure 3 In this embodiment, signal one in the second differential signal enters VIN, signal two in the second differential signal enters VIP, signal one in the second differential signal is processed by a first inverter composed of a transistor M25 and a transistor M26, and then charged by a third capacitor C3, and then outputs signal one in the common-mode voltage signal, signal two in the second differential signal is processed by a second inverter composed of a transistor M27 and a transistor M28, and then charged by a fourth capacitor C4, and then outputs signal two in the common-mode voltage signal; wherein, the third capacitor C3 and the fourth capacitor C4 are large capacitors.

[0043] In an optional embodiment of the present invention, see Figure 4 , Figure 4 It is a schematic diagram of a charge pump and a loop filter provided in an embodiment of the present invention. The charge pump includes an operational amplifier, which is used to amplify a common-mode voltage signal and then convert the amplified common-mode voltage signal into a current signal.

[0044] For more details, please see Figure 4 In this embodiment, the charge pump uses a folding operational amplifier as a voltage / current conversion circuit, inputs signal 1 in the common-mode voltage signal to the gate of transistor M29, and inputs signal 2 in the common-mode voltage signal to the gate of transistor M30. The charge pump amplifies the common-mode voltage signal and then converts it into a current signal through a V / I conversion circuit. The current signal passes through transistors M33 and M35 to charge and discharge resistor R4 and capacitor C4 to obtain a feedback voltage signal VDT. The feedback voltage signal VDT is fed back to the duty cycle calibration circuit for the next stage of processing.

[0045] In an optional embodiment of the present invention, see Figure 5 , Figure 5 It is a schematic diagram of a first delay circuit provided in an embodiment of the present invention, wherein the first delay circuit includes a first delay path composed of a first inverter chain and a second delay path composed of a second inverter chain; wherein the delay time of the first delay path is different from the delay time of the second delay path.

[0046] For more details, please see Figure 5In this embodiment, considering that the signal that needs to be input to the first frequency multiplier circuit has a certain phase difference, a first delay circuit is set in this embodiment. The inverter chain composed of transistor M37, transistor M38, transistor M39, transistor M40, transistor M45, transistor M46, transistor M47, transistor M49, transistor M50, transistor M51, transistor M52, transistor M53 and transistor M54 has a delay of 40ps, and the inverter chain composed of transistor M41, transistor M42, transistor M43, transistor M44, transistor M48, transistor M55, transistor M56, transistor M57 and transistor M58 has a delay of 20ps. The delay path is selected according to the frequency of the input second differential signal to control the delay of the input signal.

[0047] In an optional embodiment of the present invention, the delay time of the first delay path is 40 ps, ​​and the delay time of the second delay path is 20 ps.

[0048] In an optional embodiment of the present invention, see Figure 6 , Figure 6 It is a schematic diagram of a first frequency multiplier circuit provided by an embodiment of the present invention. The first frequency multiplier circuit includes a passive mixer, and the passive mixer is used to increase the frequency of the second differential signal by two times according to the delayed second differential signal.

[0049] For more details, please see Figure 6In this embodiment, the first frequency multiplier circuit includes a passive mixer, the output OUT_N of the first delay circuit is input to VCO_ND1, the output OUT_P of the first delay circuit is input to VCO_PD1, the signal 1 in the second differential signal is input to VCO_N1, the signal 2 in the second differential signal is input to VCO_P1, VCO_N1 is input to the gates of transistors M1' and M4', VCO_P1 is input to the gates of transistors M2' and M', VCO_ND1 is input to the sources of transistors M1' and M3', and VCO_P1 is input to the sources of transistors M2' and M4', that is, the second differential signal is mixed with the delayed signal to form a double frequency, QUA_N1 and QUA_P1 are twice the frequency of the second differential signal VCO_N1 and VCO_P1 respectively; the QUA_N1 signal is filtered by capacitor C1' to remove the DC signal to obtain an AC signal, and the AC The signal is then added to the feedback signal VDT, and then processed by a transimpedance amplifier composed of a resistor R2', a transistor M9', and a transistor M12' to form a square wave signal 1. The square wave signal 1 is processed by an inverter composed of a transistor M18', a transistor M19', a transistor M27', and a transistor M28' to output a differential signal 1 with an increased frequency. The QUA_P1 signal is filtered out of the DC signal by a capacitor C2' to obtain an AC signal. The AC signal is then added to the feedback signal VDT, and after being processed by a cross-group amplifier composed of a resistor R4', a transistor M13', and a transistor M16', a square wave signal 2 is formed. The square wave signal 2 is processed by an inverter composed of a transistor M15', a transistor M16', a transistor M19', and a transistor M20' to output a differential signal 2 with an increased frequency. Finally, the differential signal with an increased frequency is input into the next frequency multiplication circuit, and finally the differential signal with a frequency quadrupled is output.

[0050] It should be noted that the mixing process of the passive mixer is essentially the product process of the input signal and the local oscillator signal; the linearity of this mixing structure is mainly determined by the nonlinearity introduced by the switch pair, so high linearity can be achieved at lower power consumption. In order to make the performance of the switching MOS tube as close as possible to that of an ideal switch, the input local oscillator signal VCO_N1 / VCO_P1 needs to have sufficient amplitude.

[0051] In summary, the radio frequency millimeter wave frequency multiplier circuit provided by the present invention has the following beneficial effects:

[0052] First, the frequency multiplier proposed in the present invention consists of three parts: a duty cycle adjustment circuit, a first delay circuit and a first frequency multiplier circuit; wherein, the first frequency multiplier circuit includes a passive mixer, and the passive mixer has strict requirements on the duty cycle of the input signal. Unmatched duty cycles will cause significant frequency deviations in the output signal in adjacent periods, and further cause a large amount of spurious signals to be generated in the output of the frequency multiplier; therefore, the present invention introduces a duty cycle adjustment circuit, which not only adjusts the duty cycle of the output signal of the passive mixer, but also plays a role in amplitude amplification. The key point is that the duty cycle adjustment circuit of the present invention includes a duty cycle calibration circuit, a duty cycle detection circuit, a charge pump and a loop filter. The charge pump charges and discharges the loop filter to adjust the duty cycle of the signal. The calibration speed is fast and the calibration time is less than 50ns. The existing full-digital frequency multiplier or frequency multiplier with digital calibration often adopts a clock controller, a clock calibration circuit and a clock frequency multiplier structure, which not only requires the introduction of an additional digital clock, but also requires the introduction of a DAC for compensation and calibration in the digital calibration module, and has extremely high requirements on the accuracy of the DAC. However, a high-precision DAC will bring speed and area problems. In comparison, the advantages of the full-analog frequency multiplication provided by the present invention are particularly obvious. The calibration time for the same duty cycle difference is as short as 100ns. Figure 7 As shown, Figure 7 It is a schematic diagram of the calibration speed comparison provided by an embodiment of the present invention. The calibration time of the present invention is much shorter than that of the digital calibration solution. In addition, the core area of ​​the present invention is extremely compact, only 24mm*0.082mm, which can reduce the manufacturing cost of the chip. Therefore, the full analog multiplier proposed in this solution has obvious advantages in fast calibration, low power consumption, and small area.

[0053] Second, in the prior art, due to process limitations, a digital-analog hybrid frequency multiplier of a CMOS process usually uses a frequency multiplication circuit composed of a delay circuit and an XOR gate, and its calibration scheme is relatively complex. The traditional digital-analog hybrid frequency multiplier scheme is composed of a duty cycle detection circuit, a DAC and a two-stage low-voltage regulator. The duty cycle detection circuit records the duration of high and low levels and outputs an amplitude signal proportional to the duty cycle to detect the input duty cycle. This detection method has a great limitation on the operating frequency of its input signal, and generally can only work within the range of 160MHz; the present invention proposes a new duty cycle adjustment circuit, which detects the duty cycle of the signal by directly reading the common-mode voltage of the signal, thereby improving the detection range of the detection circuit. In addition, a delay circuit is designed according to the input frequency band range to ensure that the frequency multiplier can operate stably and effectively within its entire operating frequency band; through this design, the frequency multiplier can not only overcome the challenges brought by process variations, but also ensure stability and efficiency within the target frequency band. The introduction of the delay circuit provides additional flexibility for the MOS passive mixer, making it a reliable and efficient frequency multiplication solution, especially suitable for CMOS process phase-locked loops; the digital calibration of the DAC is replaced by a charge pump, which also plays a significant role in improving the working bandwidth. Overall, the design proposed by the present invention greatly improves the working frequency band of the frequency multiplier, and the maximum output multiplication frequency reaches 48GHz.

[0054] In an optional embodiment of the present invention, a simulation experiment is performed to verify the beneficial effects of a radio frequency millimeter wave frequency multiplier circuit provided in the above embodiment. Figure 8 As shown, Figure 8 : is a schematic diagram of the loop convergence process provided by an embodiment of the present invention, (a) represents the duty cycle calibration control voltage waveform, (b) duty cycle change, wherein VCTRL_IN is the input signal duty cycle calibration voltage, VCTRL_DOU is the doubler output duty cycle calibration voltage, the loop can reach a steady state within 100ns, after calibration, the signal duty cycle error can be controlled within 0.3%, the quadruple frequency multiplier time domain waveform at 12GHz input frequency is as follows Fig. 9 As shown, Fig. 9 This is a schematic diagram of a transient waveform diagram of a 48GHz output frequency multiplier provided by an embodiment of the present invention, (a) represents a 12GHz signal input, (b) a calibrated 12GHz signal, (c) a doubler output of 24GHz, (d) a 48GHz quadruple output, the input signal duty cycle is calibrated from an asymmetric state to 50%, and then used by the frequency multiplier, and after being processed by the duty cycle calibration circuit, it provides input to the subsequent frequency multiplier, and finally achieves an output frequency of 48GHz. However, due to the influence of parasitic capacitance, although the amplitude of the final output signal is not high, its phase noise is not affected.

[0055] In this embodiment, see Fig.10 , Fig.10 It is a schematic diagram of the spectrum of the output signal of the frequency multiplier before and after the duty cycle calibration provided by the embodiment of the present invention. When the doubler operates at 12GHz input, the output signal power of 24GHz before the duty cycle calibration is only 10dB higher than the interference signal of 12GHz, and the spurious suppression is improved to 21.5dB after calibration. At this time, the output 48GHz of the quadruple frequency multiplier has been "swamped" by the spurious signal before calibration and cannot work normally. After calibration, the output spurious suppression of the quadruple frequency multiplier is improved to 19.6dB, which fully proves the necessity of the duty cycle calibration circuit.

[0056] The first step of duty cycle calibration is duty cycle detection. This process is closely related to the power of the signal. The present invention adopts a structure similar to an inverter. Transistors M25-M28 are used as inverted ratio tubes and control the output current to be below 20μA. The circuit converts the output current into a voltage signal through a large output capacitor. It is not necessary to accurately measure the duty cycle, but to measure the duty cycle difference between the differential signal VIN and VIP. The duty cycle detection circuit has the highest sensitivity in the duty cycle range of 40%-60%, which meets the needs of practical applications.

[0057] When a MOS passive mixer is used as a frequency multiplier, the key requirement is that there is a certain phase difference between the input signals. Therefore, in order to ensure the normal operation of the frequency multiplier, a delay circuit composed of inverters is introduced into the design, and different inverters are used to adjust the delay to compensate for the errors that may be introduced during the manufacturing process. Since the first-stage output of the frequency multiplier is designed to operate in the 12GHz to 24GHz frequency band, the corresponding input operating frequency range is 6GHz to 12GHz, and the input signal period is between 1 / 12ns and 1 / 6ns. Accordingly, the delay circuit is set to a delay of 20ps and 40ps to ensure that the frequency multiplier can operate stably and effectively throughout its entire operating frequency band.

[0058] The simulation experiments show that the design proposed by the present invention greatly improves the working frequency band of the frequency multiplier, and the maximum output multiplied frequency reaches 48 GHz.

[0059] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant is intended to cover non-exclusive inclusion, so that the article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the article or device including the elements. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The orientation or position relationship indicated by "up", "down", "left", "right", etc. is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention.

[0060] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0061] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A radio frequency millimeter wave frequency multiplier circuit, characterized in that: include: A first duty cycle adjustment circuit, comprising a duty cycle calibration circuit, a duty cycle detection circuit, a charge pump and a loop filter, wherein an input end of the duty cycle calibration circuit receives a first differential signal, and the duty cycle calibration circuit is used to adjust the duty cycle of the first differential signal received at this stage according to a feedback signal output by a previous stage, and output a second differential signal with the same duty cycle at this stage; The output end of the duty cycle calibration circuit is electrically connected to the input end of the duty cycle detection circuit, and the duty cycle detection circuit is used to output a common mode voltage signal; The output end of the duty cycle detection circuit is electrically connected to the input end of the charge pump, and the charge pump is used to convert the common mode voltage signal into a current signal; the output end of the charge pump is electrically connected to the input end of the loop filter, and the loop filter is used to adjust and convert the current signal into a feedback signal; the output end of the loop filter is electrically connected to the input end of the duty cycle calibration circuit, and is used to output the feedback signal required for the next stage to the duty cycle calibration circuit; a first delay circuit, comprising a delay path consisting of two groups of inverter chains, wherein an input end of the first delay circuit is electrically connected to an output end of the duty cycle calibration circuit, and the first delay circuit is used to delay the second differential signal; A first frequency multiplier circuit, wherein the input end of the first frequency multiplier circuit is electrically connected to the output end of the first delay circuit and the output end of the duty cycle calibration circuit respectively, and the first frequency multiplier circuit is used to multiply the frequency of the second differential signal according to the delayed second differential signal.

2. The radio frequency millimeter wave frequency multiplier circuit according to claim 1, characterized in that: Also includes a second duty cycle adjustment circuit, a second delay circuit and a second frequency multiplier circuit, wherein the input end of the second duty cycle adjustment circuit is electrically connected to the output end of the first frequency multiplier circuit, the output end of the second duty cycle adjustment circuit is electrically connected to the input end of the second delay circuit, the output end of the second duty cycle adjustment circuit is also electrically connected to the input end of the second frequency multiplier circuit, and the output end of the second delay circuit is electrically connected to the input end of the second frequency multiplier circuit; Among them, the structure of the second duty cycle adjustment circuit is the same as that of the first duty cycle adjustment circuit, the structure of the second delay circuit is the same as that of the first delay circuit, and the structure of the second frequency multiplier circuit is the same as that of the first frequency multiplier circuit.

3. The radio frequency millimeter wave frequency multiplier circuit according to claim 1, characterized in that: The duty cycle calibration circuit includes a first input terminal, a first capacitor, a first transimpedance amplifier, a first two-stage inverter and a first output terminal, wherein the first input terminal is electrically connected to the first terminal of the first capacitor, the second terminal of the first capacitor is electrically connected to the input terminal of the first transimpedance amplifier, the output terminal of the first transimpedance amplifier is electrically connected to the input terminal of the first two-stage inverter, and the output terminal of the first two-stage inverter is electrically connected to the first output terminal; wherein the first capacitor is used to filter out the DC part after AC coupling of signal 1 in the first differential signal, the first transimpedance amplifier is used to convert signal 1 in the processed first differential signal into a first square wave signal, the first two-stage inverter is used to add drive to the first square wave signal, and the first output terminal outputs signal 1 of the second differential signal; The duty cycle calibration circuit includes a second input terminal, a feedback signal input terminal, a second capacitor, a second transimpedance amplifier, a second two-stage inverter and a second output terminal, wherein the second input terminal is electrically connected to the first terminal of the second capacitor, the second terminal of the second capacitor is electrically connected to the input terminal of the second transimpedance amplifier, the feedback signal input terminal is electrically connected to the input terminal of the second transimpedance amplifier, the output terminal of the second transimpedance amplifier is electrically connected to the input terminal of the second two-stage inverter, and the output terminal of the second two-stage inverter is electrically connected to the second output terminal; wherein the second capacitor is used to filter out the DC part after AC coupling of signal 2 in the first differential signal, add signal 2 in the processed first differential signal to the feedback signal outputted from the previous stage, the second transimpedance amplifier is used to convert the added signal into a second square wave signal, the second two-stage inverter is used to add drive to the second square wave signal, and the second output terminal outputs signal 2 in the second differential signal.

4. The radio frequency millimeter wave frequency multiplier circuit according to claim 3, characterized in that: The duty cycle calibration circuit also includes a positive feedback circuit, the input end of the positive feedback circuit is electrically connected to the output end of the first two-stage inverter and the output end of the second two-stage inverter, respectively, and the positive feedback circuit is used to adjust the duty cycle error caused by the delay of the first two-stage inverter and the second two-stage inverter.

5. The radio frequency millimeter wave frequency multiplier circuit according to claim 1, characterized in that: The duty cycle detection circuit includes a first inverter, a second inverter, a third capacitor and a fourth capacitor, and the structure of the first inverter is the same as that of the second inverter; Among them, the first inverter is used to process signal one in the second differential signal, and the processed signal one in the second differential signal is charged to the third capacitor, and the second inverter is used to process signal two in the second differential signal, and the processed signal two in the second differential signal is charged to the fourth capacitor to output a common mode voltage signal.

6. The radio frequency millimeter wave frequency multiplier circuit according to claim 1, characterized in that: The charge pump includes an operational amplifier, which is used to amplify the common-mode voltage signal and then convert the amplified common-mode voltage signal into a current signal.

7. The radio frequency millimeter wave frequency multiplier circuit according to claim 1, characterized in that: The first delay circuit includes a first delay path composed of a first inverter chain and a second delay path composed of a second inverter chain; wherein a delay time of the first delay path is different from a delay time of the second delay path.

8. The radio frequency millimeter wave frequency multiplier circuit according to claim 7, characterized in that: The first delay path includes a third transimpedance amplifier device, a third two-stage inverter and a fourth transimpedance amplifier, the input end of the third transimpedance amplifier receives the second differential signal, the output end of the third transimpedance amplifier is electrically connected to the input end of the third two-stage inverter, and the output end of the third two-stage inverter is electrically connected to the input end of the fourth transimpedance amplifier.

9. The radio frequency millimeter wave frequency multiplier circuit according to claim 7, characterized in that: The second delay path includes a fifth transimpedance amplifier and a sixth transimpedance amplifier, the input end of the fifth transimpedance amplifier receives the second differential signal, and the output end of the fifth transimpedance amplifier is electrically connected to the input end of the sixth transimpedance amplifier.

10. The radio frequency millimeter wave frequency multiplier circuit according to claim 1, characterized in that: The first frequency multiplier circuit includes a passive mixer configured to increase the frequency of the second differential signal by two times according to the delayed second differential signal.

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