A radio frequency millimeter wave frequency multiplier circuit

Abstract

The present invention discloses a radio frequency millimeter wave frequency multiplier circuit, comprising: a first duty cycle adjustment circuit, including a duty cycle calibration circuit, a duty cycle detection circuit, a charge pump, and a loop filter. The duty cycle calibration circuit is used to adjust the duty cycle of a first differential signal received at a current stage according to a feedback signal output by a previous stage, and output a second differential signal with the same duty cycle at the current stage; a duty cycle detection circuit is used to output a common-mode voltage signal; a charge pump is used to convert the common-mode voltage signal into a current signal; a loop filter is used to adjust the current signal and convert it into a feedback signal, and output the feedback signal required by the next stage to the duty cycle calibration circuit; a first delay circuit is used to delay the second differential signal; and a first frequency multiplier circuit is used to multiply the frequency of the second differential signal according to the delayed second differential signal. The present invention can provide a frequency multiplier with wide bandwidth, full analog fast calibration, low power consumption, and a small footprint.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog-digital hybrid integrated circuits, and in particular relates to a radio frequency millimeter wave frequency multiplier circuit. Background Art

[0002] Currently, there are two main forms of high-frequency phase-locked loops. One is to directly use a high-frequency phase-locked loop, which directly places high requirements on the output frequency of the voltage-controlled oscillator (VCO) in the high-frequency phase-locked loop (PLL). The other is to first use a phase-locked loop (PLL) to generate an output signal, and then use a frequency multiplier to increase the frequency of the signal by 2, 4 or 8 times. Among them, the direct use of high-frequency phase-locked loop output method generates a high-frequency signal by using a VCO, which has high spectral purity and excellent harmonic performance. However, the phase noise of the PLL will deteriorate with the increase of the division ratio. The industry generally uses a reference clock frequency of about 100MHz, which means that when the PLL operates at a high frequency of tens of GHz, it needs to deal with an extremely high division ratio, which inevitably damages the phase noise performance. Therefore, the frequency multiplication output method has received widespread attention.

[0003] The PLL with a frequency multiplication output offers improved phase noise performance, while a high-performance frequency multiplier has minimal impact on phase noise. However, a major challenge with this approach is that in broadband applications, the frequency multiplier requires a large amount of inductor, which occupies a significant area within the overall design. Therefore, the development of a frequency multiplier with a compact footprint, wide bandwidth, and high efficiency has become an urgent industry need. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a radio frequency millimeter wave frequency multiplier circuit. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] In a first aspect, the present invention provides a radio frequency millimeter wave frequency multiplier circuit, comprising:

[0006] A first duty cycle adjustment circuit includes a duty cycle calibration circuit, a duty cycle detection circuit, a charge pump, and a loop filter, wherein an input end of the duty cycle calibration circuit receives a first differential signal, and the duty cycle calibration circuit is configured to adjust the duty cycle of the first differential signal received at the current stage according to a feedback signal output by the previous stage, and output a second differential signal having the same duty cycle as the current stage; an output end of the duty cycle calibration circuit is electrically connected to an input end of the duty cycle detection circuit, and the duty cycle detection circuit is configured to output a common-mode voltage signal; an output end of the duty cycle detection circuit is electrically connected to an input end of the charge pump, and the charge pump is configured to convert the common-mode voltage signal into a current signal; an output end of the charge pump is electrically connected to an input end of the loop filter, and the loop filter is configured to adjust the current signal and convert it into a feedback signal; and an output end of the loop filter is electrically connected to an input end of the duty cycle calibration circuit, and is configured to output a feedback signal required by the next stage to the duty cycle calibration circuit;

[0007] a first delay circuit, comprising a delay path consisting of two groups of inverter chains, wherein an input end of the first delay circuit is electrically connected to an output end of the duty cycle calibration circuit, and the first delay circuit is used to delay the second differential signal;

[0008] A first frequency multiplier circuit, wherein the input end of the first frequency multiplier circuit is electrically connected to the output end of the first delay circuit and the output end of the duty cycle calibration circuit respectively, and the first frequency multiplier circuit is used to multiply the frequency of the second differential signal according to the delayed second differential signal.

[0009] Beneficial effects of the present invention:

[0010] The present invention provides a radio frequency millimeter wave frequency multiplier circuit, comprising a first duty cycle adjustment circuit, a first delay circuit, and a first frequency multiplier circuit, wherein the first duty cycle adjustment circuit comprises a duty cycle calibration circuit, a duty cycle detection circuit, a charge pump, and a loop filter. A first differential signal enters the duty cycle calibration circuit, and after AC coupling, the common mode voltage of signal 2 in the first differential signal is changed by a negative feedback signal fed back by the loop filter, so that the common mode voltage thereof is equal to the common mode voltage of signal 1 in the first differential signal, and the duty cycle of the first differential signal is adjusted and input into the duty cycle detection circuit and the first frequency multiplier circuit. The duty cycle detection circuit detects the duty cycle. The duty cycle difference voltage is converted into a current signal by a charge pump, and then adjusted by a loop filter to output a feedback signal. The feedback signal is used in the next stage of processing. The current stage processes the first differential signal using the feedback signal output by the previous stage. Before the first frequency multiplier circuit increases the frequency of the second differential signal, the first delay circuit is also required to delay the second differential signal, and then increase the frequency of the second differential signal. In this way, the present embodiment introduces the first duty cycle adjustment circuit, which can not only adjust the duty cycle of the output signal of the first frequency multiplier circuit, but also play an amplitude amplification role, and can provide a frequency multiplier with wide bandwidth, full analog fast calibration, low power consumption and small area.

[0011] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a schematic diagram of a radio frequency millimeter wave frequency multiplier circuit provided by an embodiment of the present invention;

[0013] Figure 2 is a schematic diagram of a duty cycle calibration circuit provided by an embodiment of the present invention;

[0014] Figure 3 is a schematic diagram of a duty cycle detection circuit provided by an embodiment of the present invention;

[0015] Figure 4 is a schematic diagram of a charge pump and a loop filter provided by an embodiment of the present invention;

[0016] Figure 5 is a schematic diagram of a first delay circuit provided by an embodiment of the present invention;

[0017] Figure 6 is a schematic diagram of a first frequency multiplier circuit provided by an embodiment of the present invention;

[0018] Figure 7 This is a schematic diagram of a calibration speed comparison provided by an embodiment of the present invention;

[0019] Figure 8 This is a schematic diagram of a loop convergence process provided by an embodiment of the present invention;

[0020] Figure 9 This is a schematic diagram of a transient waveform diagram of a 48 GHz output frequency multiplier provided by an embodiment of the present invention;

[0021] Figure 10 3 is a schematic diagram of the frequency spectrum of the output signal of the frequency multiplier before and after duty cycle calibration provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0023] A frequency multiplier is essentially a circuit system that multiplies the frequency of the input signal. The input signal passes through a nonlinear system, and the harmonics of the input signal are generated at the output. The fundamental wave and harmful harmonics are filtered out through a filtering network, thereby obtaining a relatively pure useful harmonic component.

[0024] Frequency multipliers exist in various types, depending on their operating principles and classification methods. They can be divided into passive and active frequency multipliers, depending on whether they require power during operation. Passive frequency multipliers utilize nonlinear circuit elements (such as diodes and varactors) and do not require an external power source to multiply the frequency of the input signal. In passive frequency multipliers, nonlinear elements play a central role, achieving frequency multiplication through their unique nonlinear characteristics. Active frequency multipliers primarily utilize active components such as bipolar transistors or field-effect transistors as core components, leveraging their nonlinear characteristics to achieve frequency multiplication. Preventing the active components from generating high-order harmonics requires biasing them within their nonlinear operating region.

[0025] In the present invention, the fast response characteristics of the CMOS process are utilized to create a wide bandwidth, fully analog fast calibration, low power consumption and small footprint frequency multiplier composed of three parts: a MOS passive mixer, a duty cycle adjustment circuit and a delay circuit. The focus of the present invention is the introduction of a duty cycle adjustment circuit, which not only adjusts the duty cycle of the mixer output signal, but also plays a role in amplitude amplification. Through the duty cycle adjustment and the signal after two-stage amplification, the final output signal quality is significantly improved. The difficulty of the present invention lies in how to ensure a certain phase difference between the input signals when the MOS passive mixer is used as a frequency multiplier. If there is no phase difference between the input signals, the frequency multiplier will not function normally. In view of this, in order to ensure the normal operation of the frequency multiplier, the present invention introduces a delay circuit, which is composed of two groups of inverters. Different inverters are used to adjust the delay to improve the errors that may be introduced during the manufacturing process.

[0026] See Figure 1 , Figure 1 1 is a schematic diagram of a radio frequency millimeter wave frequency multiplier circuit provided by an embodiment of the present invention. The radio frequency millimeter wave frequency multiplier circuit provided by the present invention includes:

[0027] A first duty cycle adjustment circuit includes a duty cycle calibration circuit, a duty cycle detection circuit, a charge pump, and a loop filter, wherein an input end of the duty cycle calibration circuit receives a first differential signal, and the duty cycle calibration circuit is configured to adjust the duty cycle of the first differential signal received at the current stage according to a feedback signal output by the previous stage, and output a second differential signal having the same duty cycle as the current stage; an output end of the duty cycle calibration circuit is electrically connected to an input end of the duty cycle detection circuit, and the duty cycle detection circuit is configured to output a common-mode voltage signal; an output end of the duty cycle detection circuit is electrically connected to an input end of the charge pump, and the charge pump is configured to convert the common-mode voltage signal into a current signal; an output end of the charge pump is electrically connected to an input end of the loop filter, and the loop filter is configured to adjust the current signal and convert it into a feedback signal; and an output end of the loop filter is electrically connected to an input end of the duty cycle calibration circuit, and is configured to output a feedback signal required by the next stage to the duty cycle calibration circuit;

[0028] a first delay circuit, comprising a delay path consisting of two groups of inverter chains, wherein an input end of the first delay circuit is electrically connected to an output end of the duty cycle calibration circuit, and the first delay circuit is used to delay the second differential signal;

[0029] A first frequency multiplier circuit, wherein the input end of the first frequency multiplier circuit is electrically connected to the output end of the first delay circuit and the output end of the duty cycle calibration circuit respectively, and the first frequency multiplier circuit is used to multiply the frequency of the second differential signal according to the delayed second differential signal.

[0030] For more details, please see Figure 1 The present embodiment provides a radio frequency millimeter wave frequency multiplier circuit, comprising a first duty cycle adjustment circuit, a first delay circuit, and a first frequency multiplier circuit, wherein the first duty cycle adjustment circuit comprises a duty cycle calibration circuit, a duty cycle detection circuit, a charge pump, and a loop filter. The first differential signal enters the duty cycle calibration circuit, and after AC coupling, the common mode voltage of the second signal in the first differential signal is changed by the negative feedback signal fed back by the loop filter, so that the common mode voltage thereof is equal to the common mode voltage of the first signal in the first differential signal, and the duty cycle of the first differential signal is adjusted and input into the duty cycle detection circuit and the first frequency multiplier circuit. The duty cycle detection circuit detects A duty cycle difference voltage is output, which is converted into a current signal through a charge pump, and then adjusted by a loop filter to output a feedback signal. The feedback signal is used in the next stage of processing, and the current stage processes the first differential signal using the feedback signal output by the previous stage; before the first frequency multiplier circuit increases the frequency of the second differential signal, it is also necessary to use a first delay circuit to delay the second differential signal, and then increase the frequency of the second differential signal; in this way, this embodiment introduces the first duty cycle adjustment circuit, which can not only adjust the duty cycle of the output signal of the first frequency multiplier circuit, but also play an amplitude amplification role, and can provide a frequency multiplier with wide bandwidth, full analog fast calibration, low power consumption and small area.

[0031] It should be noted that Figure 1 The illustrated embodiment only schematically illustrates the various structures in the RF millimeter wave frequency multiplier circuit and does not represent its actual schematic diagram. Figure 1 The first delay circuit structure is not shown.

[0032] In an optional embodiment of the present invention, please continue to refer to Figure 1 , further comprising a second duty cycle adjustment circuit, a second delay circuit, and a second frequency multiplier circuit, wherein the input end of the second duty cycle adjustment circuit is electrically connected to the output end of the first frequency multiplier circuit, the output end of the second duty cycle adjustment circuit is electrically connected to the input end of the second delay circuit, the output end of the second duty cycle adjustment circuit is also electrically connected to the input end of the second frequency multiplier circuit, and the output end of the second delay circuit is electrically connected to the input end of the second frequency multiplier circuit;

[0033] Among them, the structure of the second duty cycle adjustment circuit is the same as that of the first duty cycle adjustment circuit, the structure of the second delay circuit is the same as that of the first delay circuit, and the structure of the second frequency multiplier circuit is the same as that of the first frequency multiplier circuit.

[0034] Specifically, in this embodiment, the frequency of the first differential signal is doubled by the first frequency multiplier, and then the frequency of the doubled first differential signal is doubled again by the second frequency multiplier, and the frequency of the output differential signal is four times the frequency of the first differential signal.

[0035] In an optional embodiment of the present invention, see Figure 2 , Figure 2 : This is a schematic diagram of a duty cycle calibration circuit provided by an embodiment of the present invention. The duty cycle calibration circuit includes a first input terminal, a first capacitor, a first transimpedance amplifier, a first two-stage inverter, and a first output terminal. The first input terminal is electrically connected to the first terminal of the first capacitor, the second terminal of the first capacitor is electrically connected to the input terminal of the first transimpedance amplifier, the output terminal of the first transimpedance amplifier is electrically connected to the input terminal of the first two-stage inverter, and the output terminal of the first two-stage inverter is electrically connected to the first output terminal. The first capacitor is used to AC-couple a signal 1 in the first differential signal and then filter out the DC portion. The first transimpedance amplifier is used to convert a signal 1 in the processed first differential signal into a first square wave signal. The first two-stage inverter is used to add drive to the first square wave signal. The first output terminal outputs a signal 1 of the second differential signal.

[0036] The duty cycle calibration circuit includes a second input terminal, a feedback signal input terminal, a second capacitor, a second transimpedance amplifier, a second two-stage inverter and a second output terminal, the second input terminal is electrically connected to the first terminal of the second capacitor, the second terminal of the second capacitor is electrically connected to the input terminal of the second transimpedance amplifier, the feedback signal input terminal is electrically connected to the input terminal of the second transimpedance amplifier, the output terminal of the second transimpedance amplifier is electrically connected to the input terminal of the second two-stage inverter, and the output terminal of the second two-stage inverter is electrically connected to the second output terminal; wherein, the second capacitor is used to AC-couple signal two in the first differential signal and filter out the DC part, and the processed signal two in the first differential signal is added to the feedback signal outputted by the previous stage, the second transimpedance amplifier is used to convert the added signal into a second square wave signal, the second two-stage inverter is used to add drive to the second square wave signal, and the signal two in the second differential signal is outputted from the second output terminal.

[0037] For details, please refer to Figure 2In this embodiment, the first differential signals VIN_P and VIN_N enter the duty cycle calibration circuit. The first signal VIN_N in the first differential signal is AC-coupled by the first capacitor C1 to filter out the DC component, and then passes through the first transimpedance amplifier composed of the resistor R2, the transistor M3, the transistor M4, the transistor M5, and the transistor M6 to form a first square wave signal with a common mode of 0.5V and a swing of 1V; the second signal VIN_P in the first differential signal is AC-coupled by the second capacitor C2 to filter out the DC component, and then intersects with the feedback signal VDT fed back from the loop filter, and passes through the resistor R3, the transistor M7, the transistor M8, and the transistor M9. 8. After the second transimpedance amplifier composed of transistor M9 and transistor M10, a second square wave signal with a common mode of VDT and a swing of 1V is formed; the first square wave signal is further driven by a first two-stage inverter composed of transistor M13, transistor M14, transistor M17, and transistor M18 to output signal 1 in the second differential signal; the second square wave signal is further driven by a second two-stage inverter composed of transistor M15, transistor M16, transistor M19, and transistor M20 to output signal 2 in the second differential signal. Signal 1 in the second differential signal and signal 2 in the second differential signal are differential signals with the same duty cycle.

[0038] In an optional embodiment of the present invention, please continue to refer to Figure 2 The duty cycle calibration circuit also includes a positive feedback circuit, the input end of the positive feedback circuit is electrically connected to the output end of the first two-stage inverter and the output end of the second two-stage inverter respectively, and the positive feedback circuit is used to adjust the duty cycle error caused by the delay of the first two-stage inverter and the second two-stage inverter.

[0039] For more details, please see Figure 2 In this embodiment, the duty cycle calibration circuit further includes a positive feedback loop consisting of a transistor M21, a transistor M22, a transistor M23, and a transistor M24, for adjusting the duty cycle error caused by the delay of the first two-stage inverter and the second two-stage inverter, so that the duty cycles of signal one in the second differential signal and signal two in the second differential signal are the same.

[0040] In an optional embodiment of the present invention, see Figure 3 , Figure 3 1 is a schematic diagram of a duty cycle detection circuit provided by an embodiment of the present invention. The duty cycle detection circuit includes a first inverter, a second inverter, a third capacitor, and a fourth capacitor. The structure of the first inverter is the same as that of the second inverter.

[0041] Among them, the first inverter is used to process signal 1 in the second differential signal, and the processed signal 1 in the second differential signal is charged to the third capacitor. The second inverter is used to process signal 2 in the second differential signal, and the processed signal 2 in the second differential signal is charged to the fourth capacitor to output a common-mode voltage signal.

[0042] For more details, please see Figure 3 In this embodiment, signal 1 in the second differential signal enters VIN, and signal 2 in the second differential signal enters VIP. Signal 1 in the second differential signal is processed by a first inverter composed of transistors M25 and M26, and then charged by the third capacitor C3, and then outputs signal 1 in the common-mode voltage signal. Signal 2 in the second differential signal is processed by a second inverter composed of transistors M27 and M28, and then charged by the fourth capacitor C4, and then outputs signal 2 in the common-mode voltage signal; wherein the third capacitor C3 and the fourth capacitor C4 are large capacitors.

[0043] In an optional embodiment of the present invention, see Figure 4 , Figure 4 This is a schematic diagram of a charge pump and a loop filter provided by an embodiment of the present invention. The charge pump includes an operational amplifier, which is used to amplify a common-mode voltage signal and then convert the amplified common-mode voltage signal into a current signal.

[0044] For more details, please see Figure 4 In this embodiment, the charge pump uses a folding operational amplifier as a voltage / current conversion circuit, inputs signal 1 of the common-mode voltage signal to the gate of transistor M29, and inputs signal 2 of the common-mode voltage signal to the gate of transistor M30. The charge pump amplifies the common-mode voltage signal and then converts it into a current signal through a V / I conversion circuit. The current signal passes through transistors M33 and M35 to charge and discharge resistor R4 and capacitor C4 to obtain a feedback voltage signal VDT. The feedback voltage signal VDT is fed back to the duty cycle calibration circuit for use in the next stage of processing.

[0045] In an optional embodiment of the present invention, see Figure 5 , Figure 5 This is a schematic diagram of a first delay circuit provided in an embodiment of the present invention. The first delay circuit includes a first delay path composed of a first inverter chain and a second delay path composed of a second inverter chain; wherein the delay time of the first delay path is different from the delay time of the second delay path.

[0046] For more details, please see Figure 5In this embodiment, considering that the signal to be input to the first frequency multiplier circuit has a certain phase difference, a first delay circuit is provided in this embodiment. An inverter chain consisting of transistor M37, transistor M38, transistor M39, transistor M40, transistor M45, transistor M46, transistor M47, transistor M49, transistor M50, transistor M51, transistor M52, transistor M53, and transistor M54 has a delay of 40 ps. An inverter chain consisting of transistor M41, transistor M42, transistor M43, transistor M44, transistor M48, transistor M55, transistor M56, transistor M57, and transistor M58 has a delay of 20 ps. A delay path is selected according to the frequency of the input second differential signal to control the delay of the input signal.

[0047] In an optional embodiment of the present invention, the delay time of the first delay path is 40 ps, ​​and the delay time of the second delay path is 20 ps.

[0048] In an optional embodiment of the present invention, see Figure 6 , Figure 6 This is a schematic diagram of a first frequency multiplier circuit provided by an embodiment of the present invention. The first frequency multiplier circuit includes a passive mixer, which is used to double the frequency of the second differential signal according to the delayed second differential signal.

[0049] For more details, please see Figure 6In this embodiment, the first frequency multiplier circuit includes a passive mixer, which inputs the output OUT_N of the first delay circuit to VCO_ND1, inputs the output OUT_P of the first delay circuit to VCO_PD1, inputs the signal 1 in the second differential signal to VCO_N1, inputs the signal 2 in the second differential signal to VCO_P1, VCO_N1 is input to the gates of transistors M1' and M4', VCO_P1 is input to the gates of transistors M2' and M', VCO_ND1 is input to the sources of transistors M1' and M3', and VCO_P1 is input to the sources of transistors M2' and M4'. That is, the second differential signal is mixed with the delayed signal to form a doubled frequency, QUA_N1 and QUA_P1 are twice the frequency of the second differential signals VCO_N1 and VCO_P1 respectively; the QUA_N1 signal is filtered by capacitor C1' to remove the DC signal to obtain an AC signal, and the AC The signal is then added to the feedback signal VDT and processed by a transimpedance amplifier consisting of a resistor R2', a transistor M9', and a transistor M12' to form a square wave signal 1. The square wave signal 1 is further processed by an inverter consisting of a transistor M18', a transistor M19', a transistor M27', and a transistor M28' to output a differential signal 1 with an increased frequency. The QUA_P1 signal is filtered by a capacitor C2' to remove the DC signal to obtain an AC signal. The AC signal is then added to the feedback signal VDT and processed by a trans-group amplifier consisting of a resistor R4', a transistor M13', and a transistor M16' to form a square wave signal 2. The square wave signal 2 is further processed by an inverter consisting of a transistor M15', a transistor M16', a transistor M19', and a transistor M20' to output a differential signal 2 with an increased frequency. Finally, the differential signal with an increased frequency is input to the next frequency multiplication circuit, and ultimately outputs a differential signal with four times the frequency of the initial signal.

[0050] It should be noted that the mixing process of a passive mixer is essentially the product of the input signal and the local oscillator signal. The linearity of this mixing structure is mainly determined by the nonlinearity introduced by the switch pair, so high linearity can be achieved at low power consumption. In order to make the switching MOS tube as close as possible to the performance of an ideal switch, the input local oscillator signal VCO_N1 / VCO_P1 needs to have sufficient amplitude.

[0051] In summary, the RF millimeter wave frequency multiplier circuit provided by the present invention has the following beneficial effects:

[0052] First, the frequency multiplier proposed in the present invention consists of three parts: a duty cycle adjustment circuit, a first delay circuit, and a first frequency multiplier circuit. Among them, the first frequency multiplier circuit includes a passive mixer. The passive mixer has strict requirements on the duty cycle of the input signal. An unmatched duty cycle will cause the output signal to have a significant frequency deviation in adjacent cycles, which will further cause a large amount of spurious signals to be generated in the frequency multiplier output. Therefore, the present invention introduces a duty cycle adjustment circuit, which not only adjusts the duty cycle of the passive mixer output signal, but also plays a role in amplitude amplification. The key point is that the duty cycle adjustment circuit of the present invention includes a duty cycle calibration circuit, a duty cycle detection circuit, a charge pump and a loop filter. The charge pump charges and discharges the loop filter to adjust the duty cycle of the signal. The calibration speed is fast and the calibration time is less than 50ns. The existing full-digital frequency multiplier or frequency multiplier with digital calibration often adopts a clock controller, a clock calibration circuit and a clock frequency multiplier structure, which not only requires the introduction of an additional digital clock, but also requires the introduction of a DAC for compensation and calibration in the digital calibration module, and has extremely high requirements on the accuracy of the DAC. However, a high-precision DAC will bring speed and area problems. In comparison, the advantages of the full-analog frequency multiplication provided by the present invention are particularly obvious. The calibration time for the same duty cycle difference is as follows: Figure 7 As shown, Figure 7 This is a schematic diagram showing a comparison of calibration speeds provided by an embodiment of the present invention. The calibration time of the present invention is much shorter than that of a digital calibration solution. In addition, the core area of ​​the present invention is extremely compact, measuring only 24mm*0.082mm, which can reduce chip manufacturing costs. Therefore, the fully analog frequency multiplier proposed in this solution has obvious advantages in terms of fast calibration, low power consumption, and small area.

[0053] Second, in the prior art, due to process limitations, CMOS-process digital-analog hybrid frequency multipliers often use a frequency multiplication circuit consisting of a delay circuit and an XOR gate, and its calibration scheme is relatively complex. The traditional digital-analog hybrid frequency multiplier scheme consists of a duty cycle detection circuit, a DAC, and a two-stage low-voltage regulator. Its duty cycle detection circuit records the duration of high and low levels and outputs an amplitude signal proportional to the duty cycle to detect the input duty cycle. This detection method has a significant limitation on the operating frequency of its input signal, generally only operating within the range of 160MHz. The present invention proposes a new duty cycle adjustment circuit that detects the signal's duty cycle by directly reading the signal's common-mode voltage, thereby increasing the detection range of the detection circuit. In addition, the delay circuit is designed according to the input frequency band range to ensure that the frequency multiplier can operate stably and efficiently throughout its entire operating frequency band. Through this design, the frequency multiplier can not only overcome the challenges brought by process variations, but also ensure stability and efficiency within the target frequency band. The introduction of a delay circuit provides additional flexibility to the MOS passive mixer, making it a reliable and efficient frequency multiplication solution, particularly suitable for CMOS phase-locked loops. The use of a charge pump instead of DAC digital calibration also significantly increases the operating bandwidth. Overall, the proposed design significantly increases the operating frequency band of the frequency multiplier, reaching a maximum output multiplier frequency of 48 GHz.

[0054] In an optional embodiment of the present invention, the beneficial effects of a radio frequency millimeter wave frequency multiplier circuit provided by the above embodiment are verified through simulation experiments. Figure 8 As shown, Figure 8 This is a schematic diagram of the loop convergence process provided by an embodiment of the present invention. (a) shows the duty cycle calibration control voltage waveform, and (b) shows the duty cycle change. Among them, VCTRL_IN is the input signal duty cycle calibration voltage, and VCTRL_DOU is the doubler output duty cycle calibration voltage. The loop can reach steady state within 100ns. After calibration, the error of the signal duty cycle can be controlled within 0.3%. The time domain waveform of the quadrupler at a 12GHz input frequency is shown in FIG. Figure 9 As shown, Figure 9 This is a schematic diagram of the transient waveform of a 48 GHz output frequency multiplier provided by an embodiment of the present invention. (a) represents a 12 GHz signal input, (b) a calibrated 12 GHz signal, (c) a doubler output of 24 GHz, and (d) a 48 GHz quadruple output. The input signal duty cycle is calibrated from an asymmetric state to 50% before being used by the frequency multiplier. After processing by the duty cycle calibration circuit, it provides input to subsequent frequency multipliers, ultimately achieving an output frequency of 48 GHz. However, due to the influence of parasitic capacitance, the amplitude of the final output signal is not high, but its phase noise is not affected.

[0055] In this embodiment, see Figure 10 , Figure 10 This diagram shows the spectrum of the output signal of a frequency multiplier before and after duty cycle calibration, as provided by an embodiment of the present invention. When the doubler operates at a 12 GHz input, the 24 GHz output signal power is only 10 dB higher than the 12 GHz interference signal before duty cycle calibration. After calibration, spurious signal suppression improves to 21.5 dB. Meanwhile, the 48 GHz output of the quadrupler is already overwhelmed by spurious signals before calibration, rendering it unable to operate normally. After calibration, however, the quadrupler's output spurious signal suppression improves to 19.6 dB, fully demonstrating the necessity of the duty cycle calibration circuit.

[0056] Duty cycle calibration begins with duty cycle detection, a process closely related to signal power. This circuit employs a structure similar to an inverter, with transistors M25-M28 acting as inverting transistors and controlling the output current to below 20μA. This circuit converts the output current into a voltage signal via a large output capacitor. While precise duty cycle measurement is unnecessary, the difference in duty cycle between the differential signals VIN and VIP is measured. The duty cycle detection circuit achieves peak sensitivity in the 40%-60% duty cycle range, precisely meeting the requirements of practical applications.

[0057] When a MOS passive mixer is used as a frequency multiplier, a key requirement is a certain phase difference between the input signals. Therefore, to ensure the proper operation of the frequency multiplier, a delay circuit consisting of inverters is introduced into the design. Different inverters are used to adjust the delay to compensate for errors that may be introduced during the manufacturing process. Since the first-stage output of the frequency multiplier is designed to operate in the 12GHz to 24GHz frequency band, the corresponding input operating frequency range is 6GHz to 12GHz, and the input signal period is between 1 / 12ns and 1 / 6ns. Accordingly, the delay circuit is set to 20ps and 40ps delays to ensure that the frequency multiplier can operate stably and efficiently throughout its entire operating frequency band.

[0058] Simulation experiments show that the design proposed in the present invention greatly improves the operating frequency band of the frequency multiplier, and the maximum output multiplied frequency reaches 48 GHz.

[0059] It should be noted that, in this document, relational terms such as first and second are used solely to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations. Furthermore, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not explicitly listed. Without further limitation, an element defined by the phrase "comprising a..." does not preclude the presence of additional identical elements in the article or device comprising the element. Terms such as "connected" or "connected" are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. References to orientations or positional relationships, such as "upper," "lower," "left," and "right," are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate description and simplify the description of the present invention. They do not indicate or imply that the device or element referred to must have, be constructed, or operate in a specific orientation, and are therefore not to be construed as limiting the present invention.

[0060] In the description of this specification, the reference terms "one embodiment," "some embodiments," "example," "specific example," or "some examples" mean that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0061] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A radio frequency millimeter wave frequency multiplier circuit, characterized in that: include: a first duty cycle adjustment circuit, comprising a duty cycle calibration circuit, a duty cycle detection circuit, a charge pump, and a loop filter, wherein an input end of the duty cycle calibration circuit receives a first differential signal, and the duty cycle calibration circuit is configured to adjust the duty cycle of the first differential signal received at the current stage according to a feedback signal output by the previous stage, and output a second differential signal having the same duty cycle as the current stage; The output end of the duty cycle calibration circuit is electrically connected to the input end of the duty cycle detection circuit, and the duty cycle detection circuit is used to output a common mode voltage signal; The output end of the duty cycle detection circuit is electrically connected to the input end of the charge pump, and the charge pump is used to convert the common-mode voltage signal into a current signal; the output end of the charge pump is electrically connected to the input end of the loop filter, and the loop filter is used to adjust the current signal and convert it into a feedback signal; the output end of the loop filter is electrically connected to the input end of the duty cycle calibration circuit, and is used to output the feedback signal required for the next stage to the duty cycle calibration circuit; a first delay circuit, comprising a delay path consisting of two groups of inverter chains, an input end of the first delay circuit being electrically connected to an output end of the duty cycle calibration circuit, and the first delay circuit being configured to delay the second differential signal; A first frequency multiplier circuit, wherein the input end of the first frequency multiplier circuit is electrically connected to the output end of the first delay circuit and the output end of the duty cycle calibration circuit respectively, and the first frequency multiplier circuit is used to multiply the frequency of the second differential signal according to the delayed second differential signal.

2. The radio frequency millimeter wave frequency multiplier circuit according to claim 1, characterized in that: The present invention also includes a second duty cycle adjustment circuit, a second delay circuit, and a second frequency multiplier circuit, wherein the input end of the second duty cycle adjustment circuit is electrically connected to the output end of the first frequency multiplier circuit, the output end of the second duty cycle adjustment circuit is electrically connected to the input end of the second delay circuit, the output end of the second duty cycle adjustment circuit is also electrically connected to the input end of the second frequency multiplier circuit, and the output end of the second delay circuit is electrically connected to the input end of the second frequency multiplier circuit; Among them, the structure of the second duty cycle adjustment circuit is the same as that of the first duty cycle adjustment circuit, the structure of the second delay circuit is the same as that of the first delay circuit, and the structure of the second frequency multiplier circuit is the same as that of the first frequency multiplier circuit.

3. The radio frequency millimeter wave frequency multiplier circuit according to claim 1, characterized in that: The duty cycle calibration circuit includes a first input terminal, a first capacitor, a first transimpedance amplifier, a first two-stage inverter, and a first output terminal, wherein the first input terminal is electrically connected to the first terminal of the first capacitor, the second terminal of the first capacitor is electrically connected to the input terminal of the first transimpedance amplifier, the output terminal of the first transimpedance amplifier is electrically connected to the input terminal of the first two-stage inverter, and the output terminal of the first two-stage inverter is electrically connected to the first output terminal; wherein the first capacitor is used to AC-couple signal 1 in the first differential signal and filter out the DC portion, the first transimpedance amplifier is used to convert signal 1 in the processed first differential signal into a first square wave signal, the first two-stage inverter is used to add drive to the first square wave signal, and the first output terminal outputs signal 1 of the second differential signal; The duty cycle calibration circuit includes a second input terminal, a feedback signal input terminal, a second capacitor, a second transimpedance amplifier, a second two-stage inverter and a second output terminal, wherein the second input terminal is electrically connected to the first terminal of the second capacitor, the second terminal of the second capacitor is electrically connected to the input terminal of the second transimpedance amplifier, the feedback signal input terminal is electrically connected to the input terminal of the second transimpedance amplifier, the output terminal of the second transimpedance amplifier is electrically connected to the input terminal of the second two-stage inverter, and the output terminal of the second two-stage inverter is electrically connected to the second output terminal; wherein the second capacitor is used to AC-couple the second signal in the first differential signal and filter out the DC part, and the processed signal second in the first differential signal is added to the feedback signal outputted by the previous stage, the second transimpedance amplifier is used to convert the added signal into a second square wave signal, the second two-stage inverter is used to add drive to the second square wave signal, and the second output terminal outputs the second signal in the second differential signal.

4. The radio frequency millimeter wave frequency multiplier circuit according to claim 3, characterized in that: The duty cycle calibration circuit also includes a positive feedback circuit, the input end of the positive feedback circuit is electrically connected to the output end of the first two-stage inverter and the output end of the second two-stage inverter, respectively, and the positive feedback circuit is used to adjust the duty cycle error caused by the delay of the first two-stage inverter and the second two-stage inverter.

5. The radio frequency millimeter wave frequency multiplier circuit according to claim 1, characterized in that: The duty cycle detection circuit includes a first inverter, a second inverter, a third capacitor and a fourth capacitor, wherein the structure of the first inverter is the same as that of the second inverter; The first inverter is used to process signal 1 in the second differential signal, and the processed signal 1 in the second differential signal is used to charge the third capacitor. The second inverter is used to process signal 2 in the second differential signal, and the processed signal 2 in the second differential signal is used to charge the fourth capacitor to output a common-mode voltage signal.

6. The radio frequency millimeter wave frequency multiplier circuit according to claim 1, characterized in that: The charge pump includes an operational amplifier, which is used to amplify the common-mode voltage signal and then convert the amplified common-mode voltage signal into a current signal.

7. The radio frequency millimeter wave frequency multiplier circuit according to claim 1, characterized in that: The first delay circuit includes a first delay path composed of a first inverter chain and a second delay path composed of a second inverter chain; wherein a delay time of the first delay path is different from a delay time of the second delay path.

8. The radio frequency millimeter wave frequency multiplier circuit according to claim 7, characterized in that: The first delay path includes a third transimpedance amplifier device, a third two-stage inverter and a fourth transimpedance amplifier, the input end of the third transimpedance amplifier receives the second differential signal, the output end of the third transimpedance amplifier is electrically connected to the input end of the third two-stage inverter, and the output end of the third two-stage inverter is electrically connected to the input end of the fourth transimpedance amplifier.

9. The radio frequency millimeter wave frequency multiplier circuit according to claim 7, characterized in that: The second delay path includes a fifth transimpedance amplifier and a sixth transimpedance amplifier. The input end of the fifth transimpedance amplifier receives the second differential signal, and the output end of the fifth transimpedance amplifier is electrically connected to the input end of the sixth transimpedance amplifier.

10. The radio frequency millimeter wave frequency multiplier circuit according to claim 1, characterized in that: The first frequency multiplier circuit includes a passive mixer configured to double the frequency of the second differential signal according to the delayed second differential signal.

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