Multi-channel split-gate power MOSFET structure and manufacturing method
By adding the second groove in the splitting grid power MOSFET structure and forming additional conductivity, it solves the problem of high transmission resistance in existing device, and achieves higher current conduction capabilities and lower conduction resistors.
Patent Information
- Application Number
- CN202310889412.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-19
- Publication Date
- 2025-01-24
AI Technical Summary
The existing split gate power MOSFET devices have high on-resistance, which limits their current conduction capability.
In each functional unit of the traditional split grid power MOSFET structure, an additional conductivity channel is added to the second groove with a depth less than the first groove, which significantly increases the current conductivity.
By adding the second trench and the corresponding conductive channel, the on-resistance of the device is significantly reduced and the current conduction capability is improved.
Smart Images
Figure CN119364813A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor integrated circuit process technology, and in particular to a multi-channel split-gate power MOSFET structure and a manufacturing method. Background Art
[0002] Split-gate MOS (SGT) has a lower on-resistance than ordinary trench gate power MOSFET due to its unique charge balance mechanism, and has replaced traditional ordinary trench MOSFET in most medium and low voltage applications.
[0003] The main structural feature of the traditional split-gate power MOSFET is that each functional unit includes two deep trenches. Among them, a field plate-like structure composed of zero-potential polysilicon and oxide is provided in the lower part of the deep trench, forming a space charge region under reverse bias to bear the potential drop. A gate structure composed of polysilicon and oxide is provided in the upper part of the deep trench, and a conductive channel is formed on the sidewall of the deep trench at this position. In this way, a functional unit contains two conductive channels.
[0004] The above characteristics make the traditional split-gate power MOSFET structure have a lower on-resistance under the condition of obtaining the same withstand voltage. At the same time, how to further reduce the on-resistance of SGT devices to increase current conduction capability has also become a continuous pursuit. Summary of the invention
[0005] The purpose of the present invention is to overcome the above-mentioned defects in the prior art and provide a multi-channel split-gate power MOSFET structure and a manufacturing method.
[0006] To achieve the above object, the technical solution of the present invention is as follows:
[0007] The present invention provides a multi-channel split-gate power MOSFET structure, comprising:
[0008] a semiconductor layer of a first conductivity type disposed on the substrate;
[0009] Two first trenches are arranged in parallel from the surface of the semiconductor layer into the semiconductor layer, and a second trench is located between the two first trenches; a first gate and a second gate are arranged in sequence from the bottom in the first trench, a third gate is arranged in the second trench, and a dielectric layer is arranged between the first gate and the second gate and the inner wall of the first trench, between the first gate and the second gate, and between the third gate and the inner wall of the second trench;
[0010] A first doping region of a first conductivity type and a second doping region of a second conductivity type are sequentially arranged between the second trench and the first trenches on both sides from the surface of the semiconductor layer into the semiconductor layer;
[0011] A first channel is formed at least at a sidewall of the first trench corresponding to the second gate and facing the second doping region.
[0012] Furthermore, it also includes: a second channel formed at a side wall of the second trench corresponding to the third gate and facing the second doping region.
[0013] Furthermore, the second groove is located at a central position between two of the first grooves.
[0014] Further, along the depth direction of the first groove, the bottom of the second groove is located at a depth position between the first gate and the second gate, and / or the bottom of the third gate corresponds to the bottom of the second gate in depth position, and / or the bottom of the second groove passes through the bottom surface of the second doping region.
[0015] Further, the first doped region is a source region, the second doped region is a body region, the first gate is a shielding gate, the second gate is a control gate for forming the first channel, and the third gate is an auxiliary gate for forming a second channel at the side wall of the second trench corresponding to the third gate facing the second doped region, or the third gate is a structure used only to adjust power density.
[0016] Furthermore, it also includes: conductive contact holes extending from the surface of the semiconductor layer into the semiconductor layer and disposed between the second groove and the first grooves on both sides, and each of the conductive contact holes contacts the first doped region and the second doped region on the corresponding side.
[0017] The present invention also provides a method for manufacturing a multi-channel split-gate power MOSFET structure, comprising:
[0018] providing a substrate, and forming a semiconductor layer of a first conductivity type on the substrate;
[0019] Two parallel first trenches are formed from the surface of the semiconductor layer into the semiconductor layer, and a second trench is located between the two first trenches, a first gate and a second gate are formed in the first trenches in sequence from the bottom, a third gate is formed in the second trench, and a dielectric layer is formed between the first gate and the second gate and the inner wall of the first trench, between the first gate and the second gate, and between the third gate and the inner wall of the second trench;
[0020] A first doped region of a first conductivity type and a second doped region of a second conductivity type are formed from the surface of the semiconductor layer into the semiconductor layer, and are arranged in sequence between the second groove and the first grooves on both sides, so that a first channel is formed at least at the side wall of the first groove corresponding to the second gate facing the second doped region.
[0021] Further, by forming the first gate as a shielding gate and the second gate as a control gate, the first channel is formed at the side wall of the first groove corresponding to the second gate facing the second doping region; by forming the third gate as an auxiliary gate, the second channel is formed at the side wall of the second groove corresponding to the third gate facing the second doping region, or, by forming the third gate as a structure only for adjusting power density, the third gate is used only for adjusting power density without forming the second channel.
[0022] Furthermore, the method of forming the first trench to the second trench, the first gate to the third gate and the dielectric layer specifically includes:
[0023] Forming two parallel first grooves from the surface of the semiconductor layer into the semiconductor layer;
[0024] forming a first dielectric layer on the inner wall of the first trench, and filling the first trench within the first dielectric layer to form a first gate material layer;
[0025] Forming a second trench from the surface of the semiconductor layer into the semiconductor layer, centered between the two first trenches, and making the depth of the second trench smaller than the depth of the first trench;
[0026] Removing part of the first gate material layer to form a first gate, and making the top of the first gate lower than the bottom of the second trench;
[0027] Synchronously filling and forming a second dielectric layer in the first trench after removing a portion of the first gate material layer and in the second trench;
[0028] removing the second dielectric layer in the second trench, and simultaneously removing the second dielectric layer and the first dielectric layer in the first trench to corresponding depths, thereby forming a third trench in the first trench on top of the second dielectric layer and the first dielectric layer;
[0029] Synchronously forming a third dielectric layer on the inner wall of the third trench and the inner wall of the second trench, and filling the third trench and the second trench within the third dielectric layer with a second gate material layer to form a second gate in the third trench, and synchronously forming a third gate in the second trench;
[0030] The first dielectric layer to the third dielectric layer form the dielectric layer.
[0031] Further, the first doping region and the second doping region are formed by ion implantation and annealing processes, and the bottom surface of the second doping region is located above the bottom of the second gate and the bottom of the third gate;
[0032] Later also includes:
[0033] forming an interlayer dielectric layer on the surface of the semiconductor layer to cover the first trench, the second trench and the first doped region;
[0034] Forming a contact hole trench on the surface of the interlayer dielectric layer between the second trench and the first trench on both sides, the contact hole trench penetrating the surface of the semiconductor layer and having a bottom in contact with the second doping region;
[0035] Filling the contact hole trench to form a conductive contact hole;
[0036] forming a metal layer connected to the conductive contact hole on the surface of the interlayer dielectric layer;
[0037] A passivation layer is formed on the surface of the metal layer.
[0038] It can be seen from the above technical solution that the present invention forms two conductive channels (first channels) at the side walls of the two first channels by adding a second channel (third channel) whose depth is less than the first channel between the two first channels (deep channels) of each functional unit structure of the split-gate power MOSFET. On the basis of forming two conductive channels (first channels) at the side walls of the two first channels, an additional conductive channel (second channel) is formed by using the side walls of the second channel, thereby significantly increasing the current conduction capability and further reducing the on-resistance of the SGT device. Moreover, as needed, the second channel can also be used only as a structure for adjusting the power density, that is, there is no need to form an additional conductive channel on the side walls of the second channel. As a result, the present invention has significant advantages that are difficult to match with traditional SGT devices. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] Figure 1 A schematic diagram of a multi-channel split-gate power MOSFET structure according to a preferred embodiment of the present invention;
[0040] Figure 2-Figure 10The present invention is a process flow chart of a method for manufacturing a multi-channel split-gate power MOSFET structure according to a preferred embodiment of the present invention. DETAILED DESCRIPTION
[0041] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.
[0042] Unless otherwise specified below, the various parts of the MOSFET device can be made of materials known to those skilled in the art. Semiconductor materials may include, for example, III-V semiconductors, such as GaAs, InP, GaN, SiC, and IV semiconductors, such as Si, Ge, etc. The gate material may be formed of various materials that can conduct electricity, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi x 、Ni 3 Si, Pt, Ru, W, and combinations of the above conductive materials. The gate oxide layer (gate dielectric layer) can be made of SiO 2 Or the dielectric constant is greater than SiO 2 The gate oxide layer may be formed of materials such as oxides, nitrides, oxynitrides, silicates, aluminates, titanates, etc. Moreover, the gate oxide layer may be formed of not only materials known to those skilled in the art, but also materials for the gate oxide layer to be developed in the future.
[0043] The first doping type may be one of N-type and P-type, and the second doping type may be the other of N-type and P-type. N-type may be formed by injecting N-type dopants (e.g., P, As, etc.) into a semiconductor material. P-type may be formed by injecting P-type dopants (e.g., B, etc.) into a semiconductor material. The above may be understood with reference to known techniques.
[0044] The specific implementation modes of the present invention are further described in detail below in conjunction with the accompanying drawings.
[0045] refer to Figure 1 A multi-channel split-gate power MOSFET structure of the present invention includes a semiconductor layer 10 disposed on a substrate (not shown), two first trenches 30 (deep trenches) disposed in the semiconductor layer 10 and a second trench 52 disposed therebetween, and a first doping region 93 and a second doping region 94 disposed between the first trench 30 and the second trench 52.
[0046] The substrate may be a semiconductor substrate, such as a silicon-based, silicon carbide-based, gallium nitride-based or other compound semiconductor material substrates.
[0047] The semiconductor layer 10 may be an epitaxial semiconductor layer 10 of the first conductivity type disposed on the substrate surface (the upper surface in the figure). Taking the first doping type as N-type and the second doping type as P-type as an example, the semiconductor layer 10 may be an N-type epitaxial semiconductor layer 10 of the first conductivity type.
[0048] Two first trenches 30 are provided in the semiconductor layer 10 from the surface (the upper surface in the figure) downward and arranged in parallel. The two first trenches 30 and the area therebetween define a functional unit of the SGT device.
[0049] The second trench 52 is disposed in the semiconductor layer 10 from the surface of the semiconductor layer 10 downwards and is located between the two first trenches 30 .
[0050] In each first trench 30, a first gate 421 and a second gate 821 are sequentially arranged from the bottom of the first trench 30 upward. A third gate 822 is arranged in the second trench 52. The dielectric layer 80 is filled between the first gate 421 and the inner wall of the first trench 30, between the second gate 821 and the inner wall of the first trench 30, between the first gate 421 and the second gate 821, and between the third gate 822 and the inner wall of the second trench 52. The dielectric layer 80 between the first gate 421 and the inner wall of the first trench 30 can form a first gate dielectric layer 411; the dielectric layer 80 between the second gate 821 and the sidewall of the first trench 30 can form a second gate dielectric layer 812; and the dielectric layer 80 between the first gate 421 and the second gate 821 can form an isolation layer 611. The dielectric layer 80 between the third gate 822 and the inner wall of the second trench 52 can form a third gate dielectric layer 811.
[0051] The first doping region 93 and the second doping region 94 are respectively disposed between the second trench 52 and the first trenches 30 on both sides, and are sequentially disposed in the semiconductor layer 10 from the surface of the semiconductor layer 10 downward. Both sides of the first doping region 93 and the second doping region 94 on each side are connected to the sidewalls of the first trench 30 and the second trench 52, respectively.
[0052] The first doping region 93 may be an N+ type source region of the first conductivity type, and the second doping region 94 may be a P-type body region (P-body) of the second conductivity type.
[0053] A first channel is formed at least at the side wall of the first trench 30 corresponding to the second gate 821 facing the second doping region 94. That is, a first channel is formed at each of the opposite side walls of the two first trenches 30. Among them, the first gate 421 acts as a shielding gate, and forms a field plate structure similar to the first gate dielectric layer 411, and forms a space charge region under reverse bias to bear the potential drop, and the first gate dielectric layer 411 acts as a field plate oxide layer. The second gate 821 acts as a control gate and can be used to form a first channel. A conductive first channel can be formed under appropriate bias by combining the second gate 821 with the second gate dielectric layer 812 at the upper side wall of the first trench 30.
[0054] In some embodiments, the semiconductor layer 10 may be formed of a material homogeneous with the substrate. For example, the substrate may be a silicon substrate, and the semiconductor layer 10 may be an N-type epitaxial layer of homogeneous silicon material formed on the silicon substrate.
[0055] In some embodiments, the materials of the first gate 421 to the third gate 822 may be N+ doped polysilicon. The materials of the first gate dielectric layer 411 to the third gate dielectric layer 811 may be SiO 2 The material of the isolation layer 611 may be high density plasma deposited (HDP) oxide or thermal oxide, but is not limited thereto.
[0056] The second gate dielectric layer 812 may be placed between the isolation layer 611 and the second gate electrode 821. The first gate dielectric layer 411 may be disposed around the side of the isolation layer 611 and connected to the second gate dielectric layer 812. Therefore, the first gate dielectric layer 411 and the second gate dielectric layer 812 located between the first gate electrode 421 and the second gate electrode 821, together with the isolation layer 611, form isolation between the first gate electrode 421 and the second gate electrode 821.
[0057] refer to Figure 1 In some embodiments, a second channel is further formed at the sidewall of the second trench 52 corresponding to the third gate 822 facing the second doping region 94. A conductive second channel can be formed under appropriate bias by combining the third gate 822 with the third gate dielectric layer 811 at the sidewall of the second trench 52. That is, the third gate 822 can be used as an auxiliary gate for forming the second channel at the sidewall of the second trench 52.
[0058] A second channel may be formed at each side wall of the second trench 52. In this way, a device structure in which one SGT functional unit includes four conductive channels is realized. Alternatively, only one second channel may be formed at the side wall of the second trench 52. In this way, a device structure in which one SGT functional unit includes three conductive channels is realized. Therefore, by providing the second trench 52, the current conduction capability can be significantly increased, thereby further reducing the on-resistance of the SGT device.
[0059] In some embodiments, the second trench 52 may not be formed at the sidewalls of the second trench 52, and the second trench 52 (including the third gate 822 and the third gate dielectric layer 811) is used as a structure only for adjusting the power density. Thus, the function of the third gate 822 (second trench 52) can be adjusted according to the overall design requirements to meet a wider range of performance requirements.
[0060] The SGT with the second trench 52 added can achieve a functional unit size that is equal to or slightly larger than that of a conventional SGT functional unit.
[0061] refer to Figure 1 In some embodiments, the second groove 52 is disposed at a central position between the two first grooves 30 , that is, in a midline symmetrical relationship.
[0062] In some embodiments, in the direction along the depth of the first trench 30 (vertical direction to the surface of the semiconductor layer 10 ), the bottom of the second trench 52 is located at a depth position between the first gate 421 and the second gate 821 in the first trench 30 .
[0063] In some embodiments, the bottom of the third gate 822 corresponds to the bottom of the second gate 821 in depth position.
[0064] In some embodiments, the bottom of the second trench 52 passes through the bottom surface of the second doping region 94 (body region), so that the depth of the second trench 52 slightly exceeds the bottom surface of the body region (second doping region 94 ).
[0065] In some embodiments, an interlayer dielectric layer 92 (ILD) is further disposed on the surface of the semiconductor layer 10. The material of the interlayer dielectric layer 92 may be, for example, NSG (non-doped silicate glass) and / or BPSG (boron phospho-silicate glass).
[0066] Furthermore, a conductive contact hole 95 whose bottom is connected to the body region (second doping region 94) is provided on the surface of the interlayer dielectric layer 92. For example, a tungsten plug may be provided in the conductive contact hole 95. Two conductive contact holes 95 are provided between the second trench 52 and the first trenches 30 on both sides, and extend downward from the surface of the semiconductor layer 10 into the semiconductor layer 10, so that each conductive contact hole 95 contacts the source region (first doping region 93) and the body region (second doping region 94) on the corresponding side.
[0067] Furthermore, a metal layer 91 is provided on the surface of the interlayer dielectric layer 92 . The metal layer 91 is in contact with the top of the conductive contact hole 95 .
[0068] Furthermore, a passivation layer (not shown) is provided on the surface of the metal layer 91 to protect the device.
[0069] A method for manufacturing a multi-channel split-gate power MOSFET structure of the present invention is further described in detail below through specific implementations and in conjunction with the accompanying drawings.
[0070] refer to Figure 2-Figure 10 The present invention provides a method for manufacturing a multi-channel split-gate power MOSFET structure, which can be used to manufacture, for example, Figure 1 A multi-channel split-gate power MOSFET structure is shown, and may include the following steps:
[0071] Step S1: providing a substrate, and forming a semiconductor layer 10 of a first conductivity type on the substrate.
[0072] like Figure 2 As shown, a silicon substrate (not shown) can be used, for example, and an epitaxial process can be used to form a semiconductor layer 10 of the same material as the silicon substrate on the silicon substrate. For example, an N-type semiconductor layer 10 of a first conductivity type with a certain doping concentration and thickness can be epitaxially grown on the surface of an N-type silicon substrate.
[0073] Step S2: Two parallel first grooves 30 are formed from the surface of the semiconductor layer 10 into the semiconductor layer 10, and a second groove 52 is located between the two first grooves 30, a first gate 421 and a second gate 821 are formed in the first groove 30 in sequence from the bottom, a third gate 822 is formed in the second groove 52, and a dielectric layer 80 is formed between the first gate 421 and the second gate 821 and the inner wall of the first groove 30, between the first gate 421 and the second gate 821, and between the third gate 822 and the inner wall of the second groove 52.
[0074] like Figure 3As shown, a first photoresist layer is formed on the surface of the semiconductor layer 10 , and the first trench 30 region is photolithographically processed to form a first photoresist pattern 20 , and the first trench 30 region is defined by the first photoresist pattern 20 .
[0075] like Figure 4 As shown, dry etching is then performed to etch downwardly on the surface of the semiconductor layer 10 two parallel first trenches 30 meeting the morphology and size requirements.
[0076] like Figure 5 As shown, a first dielectric layer 41 of a certain thickness is formed on the inner wall of the first trench 30 by combining thermal oxidation and deposition. Then, a first gate material layer 42 is deposited in the first trench 30 within the first dielectric layer 41. The material of the first dielectric layer 41 can be SiO 2 The material of the first gate material layer 42 can be saturated doped N+ type polysilicon. After completion, chemical mechanical polishing (CMP) is performed to remove the redundant first gate material layer 42 and the first dielectric layer 41 on the surface of the semiconductor layer 10.
[0077] Then, a second photoresist layer is formed on the surface of the semiconductor layer 10 , and the second trench 52 region is photolithographically formed to form a second photoresist pattern 40 , and the second trench 52 region is defined by the second photoresist pattern 40 .
[0078] like Figure 6 As shown, dry etching is then performed to etch downwardly a second trench 52 that meets the morphology and size requirements on the surface of the semiconductor layer 10, and the second trench 52 is centered between the two first trenches 30. The depth of the formed second trench 52 is less than that of the first trench 30.
[0079] The second photoresist pattern 40 is removed, and then a third photoresist layer is formed on the surface of the semiconductor layer 10 to cover the second trench 52. Next, the first gate material layer 42 region in the first trench 30 is photoetched to form a third photoresist pattern 51, and the third photoresist pattern 51 defines the region where the first gate material layer 42 needs to be removed. The first gate material layer 42 is etched to a certain depth in the first trench 30. Thus, a first gate 421 formed by the first gate material layer 42 after the portion is removed is formed in the lower part of the first trench 30, and the top of the first gate 421 is lower than the bottom of the second trench 52.
[0080] like Figure 7As shown, the third photoresist pattern 51 is removed, and then, a high-density plasma deposition process is used to simultaneously fill the second dielectric layer 61 in the first trench 30 and the second trench 52 after removing part of the first gate material layer 42. The material of the second dielectric layer 61 can be a high-density plasma deposition (HDP) oxide or thermal oxide. Then, through high-temperature annealing and CMP, the excess second dielectric layer 61 on the surface of the semiconductor layer 10 is removed, so that the first trench 30 and the second trench 52 are filled with the second dielectric layer 61.
[0081] like Figure 8 As shown, next, a fourth photoresist layer is formed on the surface of the semiconductor layer 10, and the first groove 30 area and the second groove 52 area are photoetched to form a fourth photoresist pattern 71, and the first groove 30 and the second groove 52 areas are defined by the fourth photoresist pattern 71, that is, the area of the second dielectric layer 61 and the first dielectric layer 41 in the first groove 30 and the area of the second dielectric layer 61 in the second groove 52 are further etched.
[0082] Then, the second dielectric layer 61 in the second trench 52 is removed by etching, and the second dielectric layer 61 and the first dielectric layer 41 in the first trench 30 are removed synchronously to the corresponding depth, so that the tops of the second dielectric layer 61 and the first dielectric layer 41 in the first trench 30 are a certain distance away from the top of the first gate 421. Thus, a third trench 72 is formed in the first trench 30 on the tops of the second dielectric layer 61 and the first dielectric layer 41. Preferably, the tops of the second dielectric layer 61 and the first dielectric layer 41 in the first trench 30 are flush or substantially flush with the bottom of the second trench 52, that is, the bottom of the third trench 72 formed in the first trench 30 is flush or substantially flush with the bottom of the second trench 52. Thus, a first gate dielectric layer 411 made of the first dielectric layer 41 material and located between the first gate 421 and the inner wall of the first trench 30 and an isolation layer 611 made of the second dielectric layer 61 material and located on the top of the first gate 421 are formed in the lower portion of the first trench 30 .
[0083] like Fig. 9 As shown, the fourth photoresist pattern 71 is removed, and then, a third dielectric layer 81 is simultaneously formed on the inner wall of the third trench 72 and the inner wall of the second trench 52, and a second gate material layer 82 is simultaneously filled in the third trench 72 within the third dielectric layer 81 and in the second trench 52 within the third dielectric layer 81. The material of the third dielectric layer 81 can be SiO 2; The material of the second gate material layer 82 can be saturated doped N+ type polysilicon. After completion, the redundant second gate material layer 82 and the third dielectric layer 81 on the surface of the semiconductor layer 10 are removed by CMP. Thus, a second gate 821 formed by the second gate material layer 82 in the upper part of the first trench 30 above the first gate 421, a second gate dielectric layer 812 formed by the third dielectric layer 81 on the side wall of the first trench 30, and a third gate 822 formed synchronously in the second trench 52, and a third gate dielectric layer 811 formed by the third dielectric layer 81 on the inner wall of the second trench 52 are formed. It can be understood that the formed second gate dielectric layer 812 material is also cushioned between the isolation layer 611 and the second gate 821. And the first gate dielectric layer 411 surrounds the side of the isolation layer 611 and is connected to the second gate dielectric layer 812. Furthermore, by simultaneously (synchronously) processing the third gate dielectric layer 811 and the third gate electrode 822 in the second trench 52 and the second gate dielectric layer 812 and the second gate electrode 821 in the first trench 30, the thickness of the formed third gate dielectric layer 811 can correspond to that of the second gate dielectric layer 812, and the height (thickness) of the third gate electrode 822 can correspond to that of the second gate electrode 821, so that the performance of the SGT device can be accurately adjusted.
[0084] The first dielectric layer 41 to the third dielectric layer 81 together form Figure 1 The dielectric layer 80 in.
[0085] Step S3: A first doping region 93 of a first conductivity type and a second doping region 94 of a second conductivity type are formed from the surface of the semiconductor layer 10 into the semiconductor layer 10, which are arranged sequentially between the second groove 52 and the first grooves 30 on both sides, so that a first channel is formed at least at the side wall of the first groove 30 corresponding to the second gate 821 facing the second doping region 94.
[0086] like Fig.10 As shown, then, by using ion implantation and annealing processes, two second P-type doping regions 94 of the second conductivity type are formed at a certain depth in the semiconductor layer 10 from the surface of the semiconductor layer 10 downwards between the second trench 52 and the first trenches 30 on both sides, as body regions, and the bottom surface of the second doping region 94 is located above the bottom of the second trench 52, so that the bottom of the second trench 52 slightly exceeds the bottom surface of the second doping region 94, and the bottom surface of the second doping region 94 is located above the bottom of the second gate 821 and the bottom of the third gate 822. And by using ion implantation and annealing processes, a first N+ type doping region 93 of the first conductivity type is formed below the surface of the semiconductor layer 10 above the two second doping regions 94, as source regions.
[0087] By forming the first gate 421 as a shielding gate and the second gate 821 as a control gate, a first channel is formed at the side wall of the first trench 30 corresponding to the second gate 821 facing the second doping region 94. By forming the third gate 822 as an auxiliary gate, a second channel is formed at the side wall of the second trench 52 corresponding to the third gate 822 facing the second doping region 94. Alternatively, by forming the third gate 822 as a structure only for adjusting power density, the third gate 822 (second trench 52) is used only for adjusting power density without forming the second channel.
[0088] After that, it can further include:
[0089] like Fig.10 As shown, an interlayer dielectric layer 92 (ILD) can be formed on the surface of the semiconductor layer 10 by depositing NSG and / or BPSG on the surface of the semiconductor layer 10 and reflowing to cover the first trench 30 , the second trench 52 and the first doped region 93 .
[0090] Then, photolithography and etching processes can be used to form contact hole grooves downward on the surface of the interlayer dielectric layer 92 above each first doped region 93 between the second groove 52 and the first grooves 30 on both sides, and the bottom of the contact hole groove is in contact with the top surface of the second doped region 94. Next, Ti and TiN layers can be formed on the inner wall of the contact hole groove in sequence, and tungsten can be filled in the contact hole groove within the TiN layer. Then, by chemical mechanical polishing, the excess Ti, TiN and tungsten materials on the surface of the interlayer dielectric layer 92 outside the contact hole groove are removed, and a tungsten plug is formed in the contact hole groove, thereby forming a conductive contact hole 95 whose bottom is connected to the second doped region 94 (body region), and is also connected to the first doped region 93 (source region).
[0091] Finally, a sputtering process may be used to form, for example, an AlSiCu metal layer 91 on the surface of the interlayer dielectric layer 92 , and the AlSiCu metal layer 91 is in contact with the top of the tungsten plug of the conductive contact hole 95 .
[0092] Subsequently, the AlSiCu metal layer 91 may be patterned by photolithography and etching processes, and a passivation layer (not shown) may be formed on the surface of the interlayer dielectric layer 92 (metal layer 91). The passivation layer may be used to cover the metal layer 91 to protect the device.
[0093] In summary, the present invention forms two conductive channels (first channels) at the side walls of the two first grooves 30 (deep grooves) in each functional unit structure of the split-gate power MOSFET, and forms an additional conductive channel (second channel) by using the side walls of the second groove 52, thereby significantly increasing the current conduction capability and further reducing the on-resistance of the SGT device. Moreover, as needed, the second groove 52 can also be used only as a structure for adjusting the power density, that is, there is no need to form an additional conductive channel on the side walls of the second groove 52. As a result, the present invention has significant advantages that are difficult to match with traditional SGT devices.
[0094] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.
Claims
1. A multi-channel split-gate power MOSFET structure, characterized in that: include: a semiconductor layer of a first conductivity type disposed on the substrate; Two first grooves arranged in parallel from the surface of the semiconductor layer into the semiconductor layer, and a second groove located between the two first grooves; A first gate and a second gate are sequentially arranged in the first trench from the bottom, a third gate is arranged in the second trench, and a dielectric layer is arranged between the first gate, the second gate and the inner wall of the first trench, between the first gate and the second gate, and between the third gate and the inner wall of the second trench; A first doping region of a first conductivity type and a second doping region of a second conductivity type are sequentially arranged between the second trench and the first trenches on both sides from the surface of the semiconductor layer into the semiconductor layer; A first channel is formed at least at a sidewall of the first trench corresponding to the second gate and facing the second doping region.
2. The multi-channel split-gate power MOSFET structure according to claim 1, characterized in that: Also includes: A second channel is formed at a sidewall of the second trench corresponding to the third gate and facing the second doping region.
3. The multi-channel split-gate power MOSFET structure according to claim 1, characterized in that: The second groove is located at a central position between the two first grooves.
4. The multi-channel split-gate power MOSFET structure according to claim 1, characterized in that: Along the depth direction of the first groove, the bottom of the second groove is located at a depth position between the first gate and the second gate, and / or the bottom of the third gate corresponds to the bottom of the second gate in depth position, and / or the bottom of the second groove passes through the bottom surface of the second doping region.
5. The multi-channel split-gate power MOSFET structure according to claim 1, characterized in that: The first doped region is a source region, the second doped region is a body region, the first gate is a shielding gate, the second gate is a control gate for forming the first channel, the third gate is an auxiliary gate for forming a second channel at the side wall of the second trench corresponding to the third gate facing the second doped region, or the third gate is a structure only for adjusting power density.
6. The multi-channel split-gate power MOSFET structure according to claim 1, characterized in that: Also includes: Conductive contact holes are provided from the surface of the semiconductor layer to the semiconductor layer between the second trench and the first trenches on both sides, and each of the conductive contact holes contacts the first doping region and the second doping region on the corresponding side.
7. A method for manufacturing a multi-channel split-gate power MOSFET structure, characterized in that: include: providing a substrate, and forming a semiconductor layer of a first conductivity type on the substrate; Two parallel first trenches are formed from the surface of the semiconductor layer into the semiconductor layer, and a second trench is located between the two first trenches, a first gate and a second gate are formed in the first trenches in sequence from the bottom, a third gate is formed in the second trench, and a dielectric layer is formed between the first gate and the second gate and the inner wall of the first trench, between the first gate and the second gate, and between the third gate and the inner wall of the second trench; A first doped region of a first conductivity type and a second doped region of a second conductivity type are formed from the surface of the semiconductor layer into the semiconductor layer, and are arranged in sequence between the second groove and the first grooves on both sides, so that a first channel is formed at least at the side wall of the first groove corresponding to the second gate facing the second doped region.
8. The method for manufacturing a multi-channel split-gate power MOSFET structure according to claim 7, characterized in that: By forming the first gate as a shielding gate and the second gate as a control gate, the first channel is formed at a side wall of the first trench corresponding to the second gate facing the second doping region; By forming the third gate as an auxiliary gate, a second channel is formed at the side wall of the second groove corresponding to the third gate facing the second doping region, or by forming the third gate as a structure only for adjusting the power density, the third gate is only used to adjust the power density without forming the second channel.
9. The method for manufacturing a multi-channel split-gate power MOSFET structure according to claim 7, characterized in that: The method of forming the first trench to the second trench, the first gate to the third gate and the dielectric layer specifically includes: Forming two parallel first grooves from the surface of the semiconductor layer into the semiconductor layer; forming a first dielectric layer on the inner wall of the first trench, and filling the first trench within the first dielectric layer to form a first gate material layer; Forming a second trench from the surface of the semiconductor layer into the semiconductor layer, centered between the two first trenches, and making the depth of the second trench smaller than the depth of the first trench; Removing part of the first gate material layer to form a first gate, and making the top of the first gate lower than the bottom of the second trench; Synchronously filling and forming a second dielectric layer in the first trench after removing a portion of the first gate material layer and in the second trench; removing the second dielectric layer in the second trench, and simultaneously removing the second dielectric layer and the first dielectric layer in the first trench to corresponding depths, thereby forming a third trench in the first trench on top of the second dielectric layer and the first dielectric layer; Synchronously forming a third dielectric layer on the inner wall of the third trench and the inner wall of the second trench, and filling the third trench and the second trench within the third dielectric layer with a second gate material layer to form a second gate in the third trench, and synchronously forming a third gate in the second trench; The first dielectric layer to the third dielectric layer form the dielectric layer.
10. The method for manufacturing a multi-channel split-gate power MOSFET structure according to claim 7, characterized in that: Using ion implantation and annealing processes to form the first doping region and the second doping region, and making the bottom surface of the second doping region located above the bottom of the second gate and the bottom of the third gate; Later also includes: forming an interlayer dielectric layer on the surface of the semiconductor layer to cover the first trench, the second trench and the first doped region; Forming a contact hole trench on the surface of the interlayer dielectric layer between the second trench and the first trench on both sides, the contact hole trench penetrating the surface of the semiconductor layer and having a bottom in contact with the second doping region; Filling the contact hole trench to form a conductive contact hole; forming a metal layer connected to the conductive contact hole on the surface of the interlayer dielectric layer; A passivation layer is formed on the surface of the metal layer.