Monolithically integrated half-bridge gan hemt device with substrate coupling crosstalk suppression

Abstract

The application belongs to the technical field of power semiconductors, and relates to a single-chip integrated half-bridge GaN HEMT device with a substrate coupling crosstalk suppression function. The structure adds a Sub transistor in parallel with the lower transistor of the half-bridge and has the same switching state as the lower transistor. In the process of turning on the Sub transistor, the accumulated charge in the substrate is released, and the substrate potential is adjusted through the switching of the Sub transistor, thereby avoiding the accumulation of substrate charge in a long-time working state, realizing dynamic self-adaptive adjustment of the substrate bias state, reducing the substrate coupling crosstalk problem caused by single-chip integration, improving the stability of the half-bridge structure in the power conversion system, improving the energy conversion efficiency of the power supply system, and without the need of adding additional mask plates and process steps in the device manufacturing process, so that the structure is compatible with the conventional process and is conducive to the integration of the device.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor technology, specifically referring to a monolithic integrated half-bridge GaN HEMT device with substrate coupling crosstalk suppression function. Background Technology

[0002] GaN possesses a high critical breakdown electric field and high electron saturation drift velocity, and the two-dimensional electron gas (2DEG) generated by the polarization effect between AlGaN / GaN heterostructures exhibits high mobility and electron density. This makes GaN high electron mobility transistors (HEMTs) uniquely advantageous in high-frequency, high-efficiency, and high-power-density applications. With the development of electric vehicles and smart grids, the demand for high-efficiency, high-density power conversion equipment is increasing, and GaN half-bridge structures have been widely used in power conversion, DC motor drives, and other fields. Monolithically integrating the two transistors in a half-bridge structure can reduce the overall circuit area, achieve higher power density, and thus realize the miniaturization and integration of power supply systems.

[0003] However, monolithic integration of the half-bridge structure introduces substrate coupling crosstalk issues: ① When the substrate is connected to the source of the upper transistor, the substrate potential will reach a level close to the bus voltage when the upper transistor is on. This is equivalent to applying a forward bias voltage close to the bus voltage to the substrate, causing a significant substrate bias effect in the lower transistor. The acceptor traps in the lower transistor channel will be captured by the acceptor traps in the buffer layer. When the upper transistor is off, the substrate potential decreases, which is equivalent to removing the forward bias voltage of the substrate. At this time, the captured acceptor traps cannot be released in time, thus reducing the conduction capability of the lower transistor; ② When the substrate is connected to the source of the lower transistor, the substrate... The substrate potential remains near 0V. When the upper transistor is on, the relatively high voltage maintained by the upper transistor effectively applies a reverse bias voltage to the substrate, causing a substrate bias effect. This creates a current generated by a vertical electric field between the upper transistor and the substrate, reducing the current capability of the upper transistor. ③ When the substrate is floating, it experiences different potential differences with both the source and drain of the upper and lower transistors. These potential differences induce a certain amount of negative charge in the substrate. This unreleased negative charge accumulates in the substrate, leading to an increase in the dynamic on-resistance of both the upper and lower transistors. Therefore, improving the device structure to reduce substrate coupling crosstalk caused by GaN half-bridge monolithic integration is of great significance for improving the power system's energy conversion efficiency. Summary of the Invention

[0004] To address the aforementioned problems, this invention belongs to the field of power semiconductor technology and relates to a monolithically integrated half-bridge GaN HEMT device with substrate coupling crosstalk suppression. This structure achieves dynamic adaptive adjustment of the substrate bias state by adding a Sub transistor connected in parallel with the lower half-bridge transistor and having the same switching state as the lower half-bridge transistor. This reduces the substrate coupling crosstalk problem caused by monolithic integration, improves the stability of the half-bridge structure in power conversion systems, and enhances the energy conversion efficiency of the power system.

[0005] The technical solution of this invention is as follows:

[0006] A monolithic integrated half-bridge GaN HEMT device with substrate coupling crosstalk suppression includes a substrate layer 1, an AlN nucleation layer 2, a GaN buffer layer 3, a GaN channel layer 4, and a barrier layer 5 stacked sequentially from bottom to top along the vertical direction of the device.

[0007] The barrier layer 5 is characterized in that it has a first conductive material 14 and a fourth conductive material 9 at its two ends, respectively. The first conductive material 14 is disposed at one end of the barrier layer 5 along the longitudinal direction of the device, and a second conductive material 11 is disposed at the other end of the barrier layer 5 along the longitudinal direction of the device. There is a gap between the first conductive material 14 and the second conductive material 11. The middle part of the first conductive material 14 protrudes downward and the protruding part extends vertically to the upper layer of the substrate layer 1. A first isolation region 15 is provided in the barrier layer 5 between the first conductive material 14 and the second conductive material 11. The first isolation region 15 extends vertically to the upper layer of the GaN buffer layer 3.

[0008] A passivation layer 6 is provided on the upper surface of the barrier layer 5 between the first conductive material 14, the second conductive material 11 and the fourth conductive material 9.

[0009] A third conductive material 10 is provided in the middle of the barrier layer 5 between the first conductive material 14, the second conductive material 11 and the fourth conductive material 9. The two ends of the third conductive material 10 extend downward through the passivation layer 6 and are embedded in the upper layer of the barrier layer 5. A second isolation region 16 is provided between the two downwardly extending portions of the third conductive material 10. The upper end of the second isolation region 16 contacts the passivation layer 6, and the lower end of the second isolation region 16 extends downward along the vertical direction of the device to the upper layer of the GaN buffer layer 3.

[0010] A first gate structure is provided on the upper surface of the passivation layer 6 between the first conductive material 14, the second conductive material 11, and the third conductive material 10. The first gate structure is close to the first conductive material 14 and the second conductive material 11 and has a gap between it and the first conductive material 14 and the second conductive material 11. The first gate structure includes a first P-type GaN layer 7 and a fifth conductive material 13. The bottom of the first P-type GaN layer 7 is in contact with the upper surface of the barrier layer 5, and the bottom of the fifth conductive material 13 is in contact with the upper surface of the first P-type GaN layer 7. The passivation layer 6 covers the side of the first P-type GaN layer 7 and the surface not covered by the fifth conductive material 13.

[0011] A second gate structure is provided on the upper surface of the passivation layer 6 between the third conductive material 10 and the fourth conductive material 9. The second gate structure is close to the third conductive material 10 and has a gap between it and the third conductive material 10. The second gate structure includes a second P-type GaN layer 8 and a sixth conductive material 12. The bottom of the second P-type GaN layer 8 is in contact with the upper surface of the barrier layer 5, and the bottom of the sixth conductive material 12 is in contact with the upper surface of the second P-type GaN layer 8. The passivation layer 6 covers the side of the second P-type GaN layer 8 and the surface not covered by the sixth conductive material 12.

[0012] The contact between the first conductive material 14 and the barrier layer 5 is an ohmic contact, and the lead-out end is a substrate electrode; the contact between the third conductive material 10 and the barrier layer 5 is an ohmic contact, and the lead-out end is a switch electrode; the contact between the fourth conductive material 9 and the barrier layer 5 is an ohmic contact, and the lead-out end is a drain electrode; the contact between the second conductive material 11 and the barrier layer 5 is an ohmic contact, and the lead-out end is a source electrode; the leads-out ends of the fifth conductive material 13 and the sixth conductive material 12 are gate electrodes.

[0013] The longitudinal direction refers to the third dimension that is perpendicular to both the vertical and horizontal directions of the device.

[0014] Furthermore, on the side of the first gate structure away from the second gate structure in the lateral direction, a seventh conductive material 20, an eighth conductive material 17, and a ninth conductive material 21 are sequentially distributed. All of them are ohmic contacts with the barrier layer 5. The leads are sequentially the source electrode, the drain electrode of the Sub transistor, and the substrate electrode. The eighth conductive material 17 is electrically connected to the third conductive material 10. A third isolation region 22 is provided between the seventh conductive material 20 and the eighth conductive material 17. The upper end of the third isolation region 22 is in contact with the passivation layer 6, and the lower end of the third isolation region 22 extends into the GaN buffer layer 3 in the vertical direction of the device. The structure of the ninth conductive material (21) is the same as that of the first conductive material (14). The difference is that the ninth conductive material (21) penetrates the device in the longitudinal direction of the device.

[0015] Between the eighth conductive material 17 and the ninth conductive material 21, there is also a third gate structure. The third gate structure is close to the ninth conductive material 21 and has a gap. The third gate structure is the same as the first gate structure, including a third P-type GaN layer 19 and a tenth conductive material 18. The bottom of the third P-type GaN layer 19 is in contact with the upper surface of the barrier layer 5, and the bottom of the tenth conductive material 18 is in contact with the upper surface of the third P-type GaN layer 19. The passivation layer 6 wraps the side of the third P-type GaN layer 19 and the surface not covered by the tenth conductive material 18. The tenth conductive material 18 is electrically connected to the fifth conductive material 13.

[0016] Furthermore, the first isolation region 15, the second isolation region 16, and the third isolation region 22 are one of ion implantation isolation, trench isolation, and P-type GaN isolation.

[0017] Furthermore, the barrier layer 5 is made of one or more of AlN, AlGaN, InGaN, and InAlN; the GaN channel layer 4 and the barrier layer 5 form a heterojunction, and a 2DEG is generated at the heterojunction interface.

[0018] The beneficial effects of this invention are as follows:

[0019] The Sub transistor shares the same gate as the lower transistor of the half-bridge structure and has the same switching state. During the turn-on process of the Sub transistor, the charge accumulated in the substrate is released, and the substrate potential is regulated by the switching of the Sub transistor. This avoids the accumulation of substrate charge during long-term operation, reduces the substrate coupling crosstalk problem caused by monolithic integration, improves the stability of the half-bridge structure in the power conversion system, and improves the energy conversion efficiency of the power system. Attached Figure Description

[0020] Figure 1 This is a structural schematic diagram of Example 1;

[0021] Figure 2 This is a top view of Embodiment 1;

[0022] Figure 3 This is a cross-sectional view along AA' of Example 1;

[0023] Figure 4 This is a cross-sectional view along BB' of Example 1;

[0024] Figure 5 This is a cross-sectional view along CC' of Example 1;

[0025] Figure 6 This is a structural schematic diagram of Example 2;

[0026] Figure 7This is a schematic diagram of the structure of Example 3. Detailed Implementation

[0027] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings and embodiments:

[0028] Example 1

[0029] like Figure 1 As shown, a monolithic integrated half-bridge GaN HEMT device with substrate coupling crosstalk suppression includes a substrate layer 1, an AlN nucleation layer 2, a GaN buffer layer 3, a GaN channel layer 4, and a barrier layer 5 stacked sequentially from bottom to top along the vertical direction of the device.

[0030] The barrier layer 5 is made of AlGaN, and the GaN channel layer 4 and the barrier layer 5 form a heterojunction, with 2DEG generated at the heterojunction interface.

[0031] The barrier layer 5 is characterized by having three windows at its left end along the lateral direction, on its surface in the longitudinal direction, and in the middle along the longitudinal direction. The window at the left end along the lateral direction exposes the GaN buffer layer 3 and has an isolation region 15. The window in the middle along the longitudinal direction exposes the GaN buffer layer 3 and has an isolation region 16. The window at the left end along the longitudinal direction exposes the substrate layer 1 and has a substrate region filled with a first conductive material 14.

[0032] The isolation area is isolated by trenches, and the isolation area 15 and the isolation area 16 are filled with a passivation layer 6.

[0033] Above the AlGaN barrier layer 5 is a passivation layer 6, which has four windows at both ends and in the middle. In the left window, the window is divided longitudinally by an isolation region 15. A first conductive material 14 extends vertically downwards into the barrier layer 5 outside the substrate region, making an ohmic contact with the barrier layer 5. Its lead-out end is the substrate electrode. A second conductive material 11 extends vertically downwards into the barrier layer 5, also making an ohmic contact with the barrier layer 5. Its lead-out end is the source electrode. The two middle windows are on either side of the isolation region 16, connected by a third conductive material 10 extending vertically downwards into the barrier layer 5, making an ohmic contact with the barrier layer 5. Its lead-out end is the switch electrode. The right window contains a fourth conductive material 9 extending vertically downwards into the barrier layer 5, making an ohmic contact with the barrier layer 5. Its lead-out end is the drain electrode.

[0034] Gate structure 1 is located on the source electrode side, near the switch electrode side of the passivation layer window and connected to the isolation region 15, with a gap between it and the first conductive material 14 and the second conductive material 11; gate structure 2 is located on the middle passivation layer window, near the drain electrode side, with a gap between it and the third conductive material 10; the gate structure is composed of P-type GaN layers 7 and 8 stacked on the upper surface of the barrier layer 5, the fifth conductive material 13, the sixth conductive material 12 and the nearby passivation layer 6, the lead-out terminal of the fifth conductive material 13 is the gate electrode 1, and the lead-out terminal of the sixth conductive material 12 is the gate electrode 2.

[0035] The right end refers to the end of the drain electrode in the lateral direction, and the corresponding left end refers to the end away from the drain electrode.

[0036] The longitudinal direction refers to the third dimension that is perpendicular to both the vertical and horizontal directions of the device.

[0037] Working principle of the invention:

[0038] When the upper transistor of the half-bridge structure is turned on, the Sub transistor is turned off, and the substrate is floating. Due to the potential difference, negative charge begins to accumulate in the substrate, and the substrate potential gradually increases. When the half-bridge switches its operating state, the upper transistor is turned off and the lower transistor is turned on. At this time, the Sub transistor is turned on, and the substrate is connected to the circuit. The negative charge accumulated in the Sub transistor when it is turned off is released through the Sub transistor, avoiding charge accumulation in the substrate during long-term operation. This achieves dynamic adaptive adjustment of the substrate bias state, reduces substrate coupling crosstalk problems caused by monolithic integration, improves the stability of the half-bridge structure in the power conversion system, and improves the energy conversion efficiency of the power system.

[0039] Example 2

[0040] The difference between this example and Example 1 is that, in this example, the isolation region 22 of the monolithic integrated half-bridge GaN HEMT device with substrate coupling crosstalk suppression is located on the side of the seventh conductive material 20 away from the gate structure 1 in the lateral direction. The isolation region 22 on the side away from the seventh conductive material 20 has an eighth conductive material 17, which extends vertically downward into the barrier layer 5 outside the substrate region and has an ohmic contact with the barrier layer 5. The lead-out end is the drain electrode of the Sub transistor and is electrically connected to the switch electrode. There is a gap between the isolation region 22 and both the seventh conductive material 20 and the eighth conductive material 17. The ninth conductive material 21 is located at the left end of the device. The gate structure 3 is located on the side of the ninth conductive material 21 near the drain electrode of the Sub transistor and is spaced from the ninth conductive material 21. The gate structure consists of a P-type GaN layer 19, a tenth conductive material 18, and a nearby passivation layer 6 stacked on the upper surface of the barrier layer 5. The lead-out end of the tenth conductive material 18 is the gate electrode 3 and is electrically connected to the gate electrode 1. Compared to Example 1, the advantage of this example is that the Sub transistor has the same chip area as the lower transistor and has a higher charge control capability.

[0041] Example 3

[0042] The difference between this example and Example 1 is that the isolation method for isolation regions 15 and 16 of the monolithic integrated half-bridge GaN HEMT device with substrate coupling crosstalk suppression described in this example is P-type GaN. Compared to Example 1, the advantage of this example is that it eliminates the need for additional isolation steps, simplifying the process flow and improving process efficiency.

Claims

1. A monolithic integrated half-bridge GaN HEMT device with substrate coupling crosstalk suppression function, comprising a substrate layer (1), an AlN nucleation layer (2), a GaN buffer layer (3), a GaN channel layer (4), and a barrier layer (5) stacked sequentially from bottom to top along the vertical direction of the device. Its features are, The upper end of the barrier layer (5) has a first conductive material (14) and a fourth conductive material (9) respectively. The first conductive material (14) is disposed at one end of the upper layer of the barrier layer (5) along the longitudinal direction of the device, and the other end of the upper layer of the barrier layer (5) along the longitudinal direction of the device has a second conductive material (11). There is a gap between the first conductive material (14) and the second conductive material (11). The middle part of the first conductive material (14) protrudes downward and the protruding part extends vertically to the upper layer of the substrate layer (1). The barrier layer (5) between the first conductive material (14) and the second conductive material (11) has a first isolation region (15). The first isolation region (15) extends vertically to the upper layer of the GaN buffer layer (3). A passivation layer (6) is provided on the upper surface of the barrier layer (5) between the first conductive material (14), the second conductive material (11), and the fourth conductive material (9); A third conductive material (10) is provided in the middle of the barrier layer (5) between the first conductive material (14), the second conductive material (11), and the fourth conductive material (9). The two ends of the third conductive material (10) extend downward through the passivation layer (6) and are embedded in the upper layer of the barrier layer (5). A second isolation region (16) is provided between the two ends of the third conductive material (10). The upper end of the second isolation region (16) is in contact with the passivation layer (6), and the lower end of the second isolation region (16) extends downward along the vertical direction of the device to the upper layer of the GaN buffer layer (3). A first gate structure is provided on the upper surface of the passivation layer (6) between the first conductive material (14), the second conductive material (11), and the third conductive material (10). The first gate structure is close to the first conductive material (14) and the second conductive material (11) and has a gap between them. The first gate structure includes a first P-type GaN layer (7) and a fifth conductive material (13). The bottom of the first P-type GaN layer (7) is in contact with the upper surface of the barrier layer (5), and the bottom of the fifth conductive material (13) is in contact with the upper surface of the first P-type GaN layer (7). The passivation layer (6) covers the side of the first P-type GaN layer (7) and the surface not covered by the fifth conductive material (13). A second gate structure is provided on the upper surface of the passivation layer (6) between the third conductive material (10) and the fourth conductive material (9). The second gate structure is close to the third conductive material (10) and has a gap between it and the third conductive material (10). The second gate structure includes a second P-type GaN layer (8) and a sixth conductive material (12). The bottom of the second P-type GaN layer (8) is in contact with the upper surface of the barrier layer (5). The bottom of the sixth conductive material (12) is in contact with the upper surface of the second P-type GaN layer (8). The passivation layer (6) covers the side of the second P-type GaN layer (8) and the surface not covered by the sixth conductive material (12). The first conductive material (14) and the barrier layer (5) have an ohmic contact, and the lead-out end is the substrate electrode; the third conductive material (10) and the barrier layer (5) have an ohmic contact, and the lead-out end is the switch electrode; the fourth conductive material (9) and the barrier layer (5) have an ohmic contact, and the lead-out end is the drain electrode; the second conductive material (11) and the barrier layer (5) have an ohmic contact, and the lead-out end is the source electrode; the lead-out ends of the fifth conductive material (13) and the sixth conductive material (12) are the gate electrodes.

2. The monolithic integrated half-bridge GaN HEMT device with substrate coupling crosstalk suppression as described in claim 1, characterized in that, On the side of the first gate structure away from the second gate structure in the lateral direction, a seventh conductive material (20), an eighth conductive material (17), and a ninth conductive material (21) are distributed in sequence. The contacts with the barrier layer (5) are all ohmic contacts. The leads are the source electrode, the drain electrode of the Sub transistor, and the substrate electrode in sequence. The eighth conductive material (17) is electrically connected to the third conductive material (10). There is a third isolation region (22) between the seventh conductive material (20) and the eighth conductive material (17). The upper end of the third isolation region (22) is in contact with the passivation layer (6), and the lower end of the third isolation region (22) extends into the GaN buffer layer (3) in the vertical direction of the device. The structure of the ninth conductive material (21) is the same as that of the first conductive material (14). The difference is that the ninth conductive material (21) penetrates the device in the longitudinal direction of the device. Between the eighth conductive material (17) and the ninth conductive material (21), there is also a third gate structure. The third gate structure is close to the ninth conductive material (21) and has a gap. The third gate structure is the same as the first gate structure, including a third P-type GaN layer (19) and a tenth conductive material (18). The bottom of the third P-type GaN layer (19) is in contact with the upper surface of the barrier layer (5). The bottom of the tenth conductive material (18) is in contact with the upper surface of the third P-type GaN layer (19). The passivation layer (6) wraps the side of the third P-type GaN layer (19) and the surface not covered by the tenth conductive material (18). The tenth conductive material (18) is electrically connected to the fifth conductive material (13).

3. The monolithic integrated half-bridge GaN HEMT device with substrate coupling crosstalk suppression according to claim 2, characterized in that, The first isolation region (15), the second isolation region (16) and the third isolation region (22) are one of ion implantation isolation, trench isolation and P-type GaN isolation.

4. The monolithic integrated half-bridge GaN HEMT device with substrate coupling crosstalk suppression according to claim 1, characterized in that, The barrier layer (5) is made of one or more of AlN, AlGaN, InGaN, and InAlN; the GaN channel layer (4) and the barrier layer (5) form a heterojunction, and a 2DEG is generated at the heterojunction interface.

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