Thin film transistor, manufacturing method thereof and light-emitting substrate

Abstract

The embodiment of the invention provides a thin film transistor, a manufacturing method thereof and a light-emitting substrate, relates to the technical field of display, and aims to improve the floating body effect generated by the thin film transistor. The thin film transistor comprises a substrate, an active layer, a first grid electrode, a second grid electrode, a first pole and a second pole. The active layer comprises a channel, and a first heavily doped region and a second heavily doped region which are located at two sides of the channel. The first gate is located on one side of the active layer close to the substrate. The second grid electrode is located on the side, away from the first grid electrode, of the active layer, and the orthographic projection of the first grid electrode on the substrate and the orthographic projection of the second heavily doped region on the substrate are at least partially overlapped. The second pole includes a second body portion and a second via connection portion. The second via hole connecting part is electrically connected with the second main body part and is electrically connected with the second heavily doped region and the first grid electrode, and the orthographic projection of the second via hole connecting part on the substrate is located in the orthographic projection of the second heavily doped region on the substrate. The light-emitting substrate display panel is used for providing a display light image.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a thin film transistor and a manufacturing method thereof, and a light-emitting substrate. Background Art

[0002] Due to the defects of amorphous silicon (a-Si), such as low on-state current, low mobility and poor stability caused by many defect states, the application of amorphous silicon in many fields is limited. In order to make up for the defects of amorphous silicon itself and expand the application of related products in related fields, low-temperature polycrystalline silicon (LTPS, abbreviated as p-Si) technology came into being. Summary of the invention

[0003] The purpose of the embodiments of the present disclosure is to provide a thin film transistor and a manufacturing method thereof, and a light-emitting substrate, which are used to improve the floating body effect generated by the thin film transistor without increasing the size of the thin film transistor.

[0004] To achieve the above objectives, the embodiments of the present disclosure provide the following technical solutions:

[0005] In one aspect, a thin film transistor is provided. The thin film transistor substrate, active layer, first gate, second gate, first pole and second pole. The active layer is located on one side of the substrate, and the active layer includes a channel and a first heavily doped region and a second heavily doped region located on both sides of the channel. The first gate is located on a side of the active layer close to the substrate. The second gate is located on a side of the active layer away from the first gate, and the orthographic projection of the first gate on the substrate overlaps at least partially with the orthographic projection of the second heavily doped region on the substrate. The first pole includes a first main body and a first via connecting portion, and the second pole includes a second main body and a second via connecting portion. The first main body and the second main body are located on a side of the second gate away from the active layer. The first via connecting portion electrically connects the first main body and the first heavily doped region. The second via connecting portion electrically connects the second main body, is electrically connected to the second heavily doped region and the first gate, and the orthographic projection of the second via connecting portion on the substrate is located within the orthographic projection of the second heavily doped region on the substrate.

[0006] In the above-mentioned thin film transistor, the orthographic projection of the first gate on the substrate is set to at least partially overlap with the orthographic projection of the second heavily doped region on the substrate, and the orthographic projection of the second via connection portion on the substrate is located within the orthographic projection of the second heavily doped region on the substrate. It can be achieved that the second via connection portion can electrically connect the main body of the second electrode with the second heavily doped region and the first gate to improve the floating body effect generated by the thin film transistor. At the same time, it can also improve the problem of increasing the size of the thin film transistor due to the addition of the second via connection portion of the second electrode.

[0007] That is, the thin film transistor provided in the embodiment of the present disclosure can improve the floating body effect of the thin film transistor without increasing the size of the thin film transistor as much as possible, so as to improve the display quality of the display device while ensuring the pixel density of the display device.

[0008] In some embodiments, the second heavily doped region includes at least one via, one end of the second via connection portion is electrically connected to the second electrode, and the other end of the second via connection portion passes through the via and is electrically connected to the first gate.

[0009] In some embodiments, an orthographic projection of the first gate on the substrate does not overlap with an orthographic projection of the via on the substrate.

[0010] In some embodiments, a minimum distance between an orthographic projection of the first gate on the substrate and an orthographic projection of the via on the substrate is greater than or equal to 0.5 μm.

[0011] In some embodiments, the orthographic projection of the channel on the substrate is located within the orthographic projection of the first gate on the substrate, and the minimum spacing between the outer edge of the orthographic projection of the first gate on the substrate and the outer edge of the orthographic projection of the channel on the substrate is greater than or equal to 0.5 μm.

[0012] In some embodiments, the orthographic projection of the second heavily doped region on the substrate is located within the orthographic projection of the first gate on the substrate.

[0013] In some embodiments, along the first direction, the first gate includes a first side and a second side that are oppositely disposed, and the first side is located on a side of the second side close to the first via connection portion. The first direction is a direction from the first pole to the second pole. The minimum spacing between the orthographic projection of the second side of the first gate on the substrate and the orthographic projection of the third side of the second heavily doped region away from the first heavily doped region on the substrate is greater than or equal to 0.5 μm.

[0014] In some embodiments, a minimum distance between an orthographic projection of the second side of the first gate on the substrate and an orthographic projection of a third side of the second heavily doped region away from the first heavily doped region on the substrate is less than or equal to 10 μm.

[0015] In some embodiments, one end of the second via connection portion is electrically connected to the second main body portion of the second electrode, and the other end of the second via connection portion is electrically connected to the first gate through the second heavily doped region.

[0016] In some embodiments, a minimum distance between an outer edge of an orthographic projection of the first gate on the substrate and an outer edge of an orthographic projection of the channel on the substrate is greater than or equal to 0.5 μm.

[0017] In some embodiments, an orthographic projection of the active layer on the substrate is located within an orthographic projection of the first gate on the substrate.

[0018] In some embodiments, the orthographic projection of the channel on the substrate is located within the orthographic projection of the first gate on the substrate, and the minimum spacing between the outer edge of the orthographic projection of the first gate on the substrate and the outer edge of the orthographic projection of the active layer on the substrate is greater than or equal to 0.5 μm.

[0019] In some embodiments, a minimum distance between an outer edge of an orthographic projection of the first gate on the substrate and an outer edge of an orthographic projection of the active layer on the substrate is less than or equal to 10 μm.

[0020] In some embodiments, the active layer further includes a first low-doping region and a second low-doping region. The first low-doping region is located between the first heavily doped region and the channel, and the doping concentration of the first low-doping region is less than the doping concentration of the first heavily doped region. The second low-doping region is located between the second heavily doped region and the channel, and the doping concentration of the second low-doping region is less than the doping concentration of the second heavily doped region.

[0021] In some embodiments, a projection of the second gate on the substrate substantially coincides with a projection of the channel on the substrate.

[0022] In some embodiments, the thickness of the active layer ranges from

[0023] On the other hand, a method for manufacturing a thin film transistor is provided. The method for manufacturing the thin film transistor includes: forming a first gate on one side of a substrate. Forming an active layer on the side of the substrate away from the first gate, the active layer including a channel, and a first region to be doped and a second region to be doped located on both sides of the channel, the orthographic projection of the first gate on the substrate at least partially overlaps with the orthographic projection of the second region to be doped on the substrate. Forming a second gate on the side of the active layer away from the substrate. Conducting the first region to be doped and the second region to be doped to form corresponding first heavily doped regions and second heavily doped regions. Forming a first pole and a second pole on the side of the first gate away from the substrate, the first pole including a first via connection portion, the first via connection portion and the first heavily doped region being electrically connected. The second pole including a second via connection portion, the second via connection portion being electrically connected to the second heavily doped region and the first gate, and the orthographic projection of the second via connection portion on the substrate is located within the range of the orthographic projection of the second heavily doped region on the substrate.

[0024] In some embodiments, before forming the first electrode and the second electrode on the side of the first gate away from the substrate, the method further includes: forming a via hole in the second heavily doped region. And forming the second electrode includes: the second via hole connecting portion of the second electrode passes through the via hole and is electrically connected to the first gate.

[0025] On the other hand, a method for manufacturing a thin film transistor is provided. The method for manufacturing the thin film transistor includes: forming a first gate on one side of a substrate. An active layer is formed on a side of the substrate away from the first gate, the active layer includes a channel, and a first region to be doped and a second region to be doped located on both sides of the channel, the orthographic projection of the first gate on the substrate at least partially overlaps with the orthographic projection of the second region to be doped on the substrate, and the second region to be doped includes a third via connection portion, and the third via connection portion is electrically connected to the first gate. A second gate is formed on a side of the active layer away from the substrate. Conductorization is performed on the first region to be doped and the second region to be doped to form corresponding first heavily doped regions and second heavily doped regions. A first pole and a second pole are formed on a side of the first gate away from the substrate, the first pole includes a first via connection portion, and the first via connection portion is electrically connected to the first heavily doped region. The second pole includes a second via connection portion, the second via connection portion is electrically connected to the second heavily doped region, and the orthographic projection of the second via connection portion on the substrate is located within the range of the orthographic projection of the second heavily doped region on the substrate.

[0026] In another aspect, a light-emitting substrate is provided, wherein the light-emitting substrate comprises: a thin film transistor as described in any of the above embodiments.

[0027] The above-mentioned light-emitting substrate has the same structure and beneficial technical effects as the thin-film crystal provided in some of the above-mentioned embodiments, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0029] Figure 1 is a structural diagram of a display device according to some embodiments;

[0030] Figure 2 is a structural diagram of a light-emitting substrate according to some embodiments;

[0031] Figure 3 is a circuit diagram of a light emitting driving circuit according to some embodiments;

[0032] Figure 4 is a structural diagram of a thin film transistor according to some embodiments;

[0033] Figure 5 is a structural diagram of a thin film transistor according to some embodiments;

[0034] Figure 6 is a film layer diagram of a thin film transistor according to some embodiments;

[0035] Figure 7 is a structural diagram of a thin film transistor according to some other embodiments;

[0036] Figure 8 is a film layer diagram of a thin film transistor according to some other embodiments;

[0037] Fig. 9 is a film layer diagram of a thin film transistor according to some further embodiments;

[0038] Fig.10 is a film layer diagram of a thin film transistor according to some further embodiments;

[0039] Fig.11 is a flow chart of a method for manufacturing a thin film transistor according to some embodiments;

[0040] Fig.12 for Fig.11 The membrane structure diagram corresponding to the steps in the figure;

[0041] Fig.13 for Fig.11 Top view corresponding to some steps in the process;

[0042] Fig.14 for Fig.11 Top views corresponding to other steps in the process;

[0043] Fig.15 for Fig.11 The film layer structure diagram corresponding to step S14;

[0044] Fig.16 for Fig.11 The top view corresponding to step S14;

[0045] Fig.17 is a flow chart of a method for manufacturing a thin film transistor according to some other embodiments;

[0046] Fig.18 for Fig.17 The membrane structure diagram corresponding to the steps in the figure;

[0047] Fig.19 The diagram is a structural diagram of some steps of a method for manufacturing a thin film transistor according to some embodiments. DETAILED DESCRIPTION

[0048] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0049] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0050] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0051] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0052] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0053] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0054] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [a stated condition or event] is detected" are optionally interpreted to mean "upon determining that" or "in response to determining that" or "upon detecting [a stated condition or event]" or "in response to detecting [a stated condition or event]," depending on the context.

[0055] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0056] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0057] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0058] As used herein, "vertical" includes the conditions described and conditions similar to the conditions described, the range of which is within an acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "vertical" includes absolute vertical and approximate vertical, wherein the acceptable deviation range of approximate vertical can also be, for example, within 5° of deviation.

[0059] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0060] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are exaggerated for clarity. Therefore, variations in the shapes relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0061] Figure 1 is a structural diagram of a display device according to some embodiments.

[0062] Some embodiments of the present disclosure provide a display device. Figure 1 As shown, the display device 300 includes a light emitting substrate 200 .

[0063] In some examples, the display device 300 may be any device that displays an image, whether in motion (e.g., video) or stationary (e.g., still image), and whether textual or electronic. More specifically, it is contemplated that the embodiments described may be implemented in or associated with a variety of electronic devices, such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controls and / or displays, displays of camera views (e.g., displays of rear-view cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images for a piece of jewelry), and the like.

[0064] Exemplarily, the display device 300 can be a liquid crystal display device (full name in English: Liquid Crystal Display, abbreviated in English: LCD), a mini light-emitting display device (full name in English: Mini Light-Emitting Diode, abbreviated in English: Mini LED) and a micro light-emitting display device (full name in English: Micro Light-Emitting Diode, abbreviated in English: Micro LED).

[0065] In some embodiments, when the display device 300 is a liquid crystal display device, the display device 300 may include a cover glass, a liquid crystal display panel, and a backlight assembly. The backlight assembly is used to provide a light source for the liquid crystal display panel. The backlight assembly includes a light emitting substrate 200, which provides light for the liquid crystal display panel, so that the liquid crystal display panel can display a picture.

[0066] In some examples, the display device 300 may include an array substrate, an opposing substrate (which may be a color filter substrate) and a liquid crystal layer, wherein the opposing substrate and the array substrate are arranged opposite to each other, and the liquid crystal layer is located between the opposing substrate and the array substrate.

[0067] The array substrate is provided with a first polarizer, the counter substrate is provided with a second polarizer, and the polarization directions of the first polarizer and the second polarizer are perpendicular to each other. The liquid crystal molecules of the liquid crystal layer are twisted under the action of the driving electric field formed between the pixel electrode provided on the array substrate and the common electrode provided on the array substrate or the common electrode provided on the counter substrate, so as to control the polarization direction of the light, and control the transmittance of the light under the cooperation of the first polarizer and the second polarizer, so as to realize grayscale display.

[0068] In some embodiments, when the display device 300 is a Mini LED display device and a Micro LED display device, the display device 300 includes a light-emitting substrate 200, and the light-emitting substrate 200 can realize picture display. In some examples, the display device 300 may also include an anti-reflection film layer and a protective cover plate, and the anti-reflection film layer is located between the light-emitting substrate 200 and the protective cover plate. The anti-reflection film layer includes a polarizer, and the polarizer may be a circular polarizer. Here, the polarizer can reduce external light emission and prevent the light-emitting substrate 200 from reflecting ambient light and thus producing a glare effect.

[0069] Figure 2 is a structural diagram of a light-emitting substrate according to some embodiments.

[0070] In some embodiments, see Figure 2 As shown, the light emitting substrate 200 may include a driving circuit layer 100 and a light source O. The light source O may include a plurality of light emitting devices E, and the driving circuit layer 100 may include a plurality of light emitting driving circuits Q. The plurality of light emitting driving circuits Q in the driving circuit layer 100 are electrically connected to the plurality of light emitting devices E in the light source O, so as to drive the light emitting devices E to emit light by using the light emitting driving circuits Q.

[0071] In some examples, the above-mentioned multiple light-emitting driving circuits Q and multiple light-emitting devices E can be electrically connected in a one-to-one correspondence. In other examples, one light-emitting driving circuit Q can be coupled to multiple light-emitting devices E, or multiple light-emitting driving circuits Q can be coupled to one light-emitting device E. Hereinafter, it is described by taking the example that multiple light-emitting driving circuits Q and multiple light-emitting devices E can be electrically connected in a one-to-one correspondence.

[0072] In some examples, the light-emitting device E may be at least one of a light-emitting diode (English full name: Light-Emitting Diode, English abbreviation: LED), a micro light-emitting diode (English full name: Micro Light-Emitting Diode, English abbreviation: Micro LED), and a mini light-emitting diode (English full name: Mini Light-Emitting Diode, English abbreviation: MiniLED), but the present disclosure is not limited thereto. In the following, the light-emitting device E is described as a Micro LED as an example.

[0073] In some embodiments, the structure of the light-emitting driving circuit Q includes multiple structures, which can be selected and set according to actual needs. For example, the structure of the light-emitting driving circuit Q may include "8T2C" or "11T3C". Here, "T" represents a thin film transistor, and the number in front of "T" represents the number of thin film transistors; "C" represents a storage capacitor C, and the number in front of "C" represents the number of storage capacitors C.

[0074] Figure 3 is a circuit diagram of a light emitting driving circuit according to some embodiments.

[0075] In some embodiments, please combine Figure 2 and Figure 3 As shown, the structure of the light emitting driving circuit Q is "11T3C" as an example for description. Among them, "11T" can be 11 thin film transistors T.

[0076] The light-emitting driving circuit Q includes: a storage capacitor Cst, a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second reset transistor T7, a first regulating unit M1, and a second regulating unit M2. When working at different grayscales, the second light-emitting control transistor T6 is controlled by the first regulating unit M1 or the second regulating unit M2. Among them, the first regulating unit M1 includes a first writing transistor T8, a first regulating transistor T9, and a first capacitor C1. The second regulating unit M2 includes a second writing transistor T10, a second regulating transistor T11, and a second capacitor C2.

[0077] Among them, the first reset transistor T1, the compensation transistor T2, the driving transistor T3, the data writing transistor T4, the first light emission control transistor T5, the second light emission control transistor T6, the second reset transistor T7, the first writing transistor T8, the first regulating transistor T9, the second writing transistor T10 and the second regulating transistor T11 are all thin film transistors.

[0078] In some examples, the above-mentioned "11T" may be a P-type transistor. That is, the first reset transistor T1, the compensation transistor T2, the drive transistor T3, the data writing transistor T4, the first light emission control transistor T5, the second light emission control transistor T6, the second reset transistor T7, the first writing transistor T8, the first regulating transistor T9, the second writing transistor T10 and the second regulating transistor T11 may be P-type transistors.

[0079] In other examples, the above-mentioned "11T" may be an N-type transistor. That is, the first reset transistor T1, the compensation transistor T2, the driving transistor T3, the data writing transistor T4, the first light emission control transistor T5, the second light emission control transistor T6, the second reset transistor T7, the first writing transistor T8, the first regulating transistor T9, the second writing transistor T10 and the second regulating transistor T11 may be N-type transistors.

[0080] A first plate of the storage capacitor Cst is electrically connected to the first power signal line VDD, and a second plate of the storage capacitor Cst is electrically connected to the first node N1.

[0081] A control electrode of the first reset transistor T1 is electrically connected to the first reset signal line RST-A, a first electrode of the first reset transistor T1 is electrically connected to the first initialization signal line Vinit, and a second electrode of the first reset transistor T1 is electrically connected to the first node N1.

[0082] A control electrode of the compensation transistor T2 is electrically connected to the first scan signal line Gate, a first electrode of the compensation transistor T2 is electrically connected to the first node N1, and a second electrode of the compensation transistor T2 is electrically connected to the third node N3.

[0083] The control electrode of the driving transistor T3 is electrically connected to the first node N1 , the first electrode of the driving transistor T3 is electrically connected to the second node N2 , and the second electrode of the driving transistor T3 is electrically connected to the third node N3 .

[0084] The control electrode of the data writing transistor T4 is electrically connected to the first scanning signal line Gate, the first electrode of the data writing transistor T4 is electrically connected to the data writing signal line Data, and the second electrode of the data writing transistor T4 is electrically connected to the second node N2.

[0085] A control electrode of the first light emission control transistor T5 is electrically connected to the enable signal line EM, a first electrode of the first light emission control transistor T5 is electrically connected to the first power signal line VDD, and a second electrode of the first light emission control transistor T5 is electrically connected to the second node N2.

[0086] The control electrode of the second light emitting control transistor T6 is electrically connected to the first regulating unit M1 and the second regulating unit M2 respectively. The first electrode of the second light emitting control transistor T6 is electrically connected to the third node N3, and the second electrode of the second light emitting control transistor T6 is electrically connected to the fourth node N4. The fourth node N4 is also electrically connected to the light emitting device E.

[0087] The control electrode of the first write transistor T8 is electrically connected to the second reset signal line RST-B, the first electrode of the first write transistor T8 is electrically connected to the data write signal line Data, and the second electrode of the first write transistor T8 is electrically connected to the fifth node N5.

[0088] The control electrode of the first regulating transistor T9 is electrically connected to the fifth node N5 , the first electrode of the first regulating transistor T9 is electrically connected to the enable signal line EM, and the second electrode of the first regulating transistor T9 is electrically connected to the control electrode of the second light emitting control transistor T6 .

[0089] A first plate of the first capacitor C1 is electrically connected to the first initialization signal line Vinit, and a second plate of the first capacitor C1 is electrically connected to the fifth node N5.

[0090] A control electrode of the second write transistor T10 is electrically connected to the first reset signal line RST-A, a first electrode of the second write transistor T10 is electrically connected to the data write signal line Data, and a second electrode of the second write transistor T10 is electrically connected to the sixth node.

[0091] The control electrode of the second regulating transistor T11 is electrically connected to the sixth node N6, the first regulating signal line Hf is electrically connected to the second regulating transistor T11, and the second electrode of the second regulating transistor T11 is electrically connected to the control electrode of the second light emission control transistor T6.

[0092] A first plate of the second capacitor C2 is electrically connected to the first initialization signal line Vinit, and a second plate of the second capacitor C2 is electrically connected to the sixth node N6.

[0093] The inventors have found that when the light-emitting driving circuit (such as the light-emitting driving circuit Q) in the light-emitting substrate 200 drives the light-emitting device E to emit light and provide a light source for the display device 300, the display quality of the display device 300 is poor when the display device 300 displays a picture. In addition, the display quality of the display device 300 is even worse in a low grayscale state.

[0094] The inventors further discovered that this is because the multiple thin film transistors T in the light-emitting driving circuit Q use a top-gate structure. In thin film transistors using a top-gate structure, since the channel is floating relative to the substrate, this will cause a floating body effect.

[0095] Take the driving transistor T3 among the multiple thin film transistors T in the light emitting driving circuit Q as an example to introduce: when the light emitting driving circuit Q is working, the floating body effect of the driving transistor T3 will cause the driving current output by the light emitting driving circuit Q to the light emitting device E through the driving transistor T3 to be unstable, and will cause the control electrode potential difference of the corresponding driving transistor T3 to be small under different driving currents. Based on this, it will be impossible to achieve accurate and effective control of the opening or closing of the driving transistor T3, thereby affecting the display quality of the display device 300.

[0096] Furthermore, the display device 300 (return Figure 1 When the display device 300 is in a low grayscale state, the voltage value required for the control electrode of the driving transistor T3 is less than the voltage value required for the control electrode of the driving transistor T3 when the display device 300 is in a high grayscale state. Furthermore, when the display device 300 is in a low grayscale state, the corresponding control electrode potential difference of the driving transistor T3 under different driving currents is smaller, making it more difficult to achieve accurate and effective control of the opening or closing of the driving transistor T3.

[0097] Based on this, the floating body effect can be improved by improving the structure of the thin film transistor T, so as to realize accurate control of the thin film transistor. The following description takes the thin film transistor T as a driving transistor T3 as an example.

[0098] Figure 4 is a structural diagram of a thin film transistor according to some embodiments.

[0099] For some possible implementations, see Figure 4 As shown, the thin film transistor T includes a substrate 10 , and an active layer 20 , a first gate 30 , a second gate 40 , a first electrode 50 , and a second electrode 60 formed on the substrate 10 .

[0100] The first gate 30 and the second gate 40 are respectively located on both sides of the active layer 20. Take the first gate 30 as the bottom gate of the thin film transistor T, and the second gate 40 as the top gate of the thin film transistor T as an example for introduction. Based on this, the first gate 30 is located between the active layer 20 and the substrate 10, and the second gate 40 is located on the side of the active layer 20 away from the first gate 30.

[0101] One of the first electrode 50 and the second electrode 60 of the thin film transistor T is the source electrode of the thin film transistor T, and the other is the drain electrode of the thin film transistor. The following description is made by taking the first electrode 50 of the thin film transistor T as the drain electrode of the thin film transistor T and the second electrode 60 of the thin film transistor T as the source electrode of the thin film transistor T as an example. The second electrode 60 of the thin film transistor T is configured to have a constant voltage potential.

[0102] The first gate electrode 30 of the thin film transistor T is electrically connected to the second electrode 60 of the thin film transistor T, and the second electrode 60 of the thin film transistor T can be used to provide a constant voltage potential for the first gate electrode 30 of the thin film transistor T, so that the first gate electrode 30 of the thin film transistor T is kept at a fixed potential, thereby improving the floating body effect of the thin film transistor T, which is beneficial to improving the performance of the thin film transistor. Furthermore, the driving current output by the light emitting driving circuit Q to the light emitting device E via the driving transistor T3 can be stably output, thereby improving the display quality of the display device 300.

[0103] Furthermore, the thin film transistor T includes the first gate 30 and the second gate 40. Compared with the thin film transistor provided with only the second gate 40, the first gate 30 of the thin film transistor T can be kept at a fixed potential, and the first gate 30 can be used to increase the difficulty of the second gate 40 controlling the channel of the thin film transistor T. That is, the gate voltage value required when the thin film transistor T provided with the first gate 30 and the second gate 40 outputs the target current can be made greater than the gate voltage value required when the thin film transistor provided with only the second gate 40 outputs the target current.

[0104] Therefore, the control electrode potential difference of the corresponding driving transistor T3 under different driving currents can be increased, which is conducive to realizing accurate and effective control of the opening or closing of the driving transistor T3.

[0105] The inventors further discovered that when the first gate electrode 30 of the thin film transistor T is electrically connected to the second electrode 60 of the thin film transistor T, since the active layer 20 is located between the first gate electrode 30 of the thin film transistor T and the second electrode 60 of the thin film transistor T, a connecting portion F is required to bypass the active layer 20 to electrically connect the first gate electrode 30 of the thin film transistor T to the second electrode 60 of the thin film transistor T.

[0106] However, the connection portion will increase the size of the thin film transistor T. When it is subsequently applied to a backlight module and a display device 300 , it will affect the pixel density (Pixels Per Inch, PPI) of the display device 300 and the display effect of the display device 300 .

[0107] Figure 5 is a structural diagram of a thin film transistor according to some embodiments, Figure 6is a diagram of film layers of a thin film transistor according to some embodiments.

[0108] Based on the above problems, the present disclosure provides a thin film transistor T. Figure 5 and Figure 6 As shown, the thin film transistor T includes: a substrate 10 , an active layer 20 , a first gate 30 , a second gate 40 , a first electrode 50 and a second electrode 60 .

[0109] In some examples, the substrate 10 may be a flexible substrate. Exemplarily, the material of the substrate 10 may be an organic material. For example, the material of the substrate 10 may be any one of polyimide (full name in English: Polyimide, English abbreviation: PI), polycarbonate (full name in English: Polycarbonate, English abbreviation: PC) or polyvinyl chloride (full name in English: Polyvinyl Chloride, English abbreviation: PVC).

[0110] In other examples, the substrate 10 may be a rigid substrate, for example, a glass substrate or a polymethyl methacrylate (full name: Polymethyl methacrylate, abbreviated: PMMA) substrate.

[0111] The active layer 20 is located on one side of the substrate 10. The active layer 20 includes a channel 21 and a first heavily doped region 22 and a second heavily doped region 23 located on both sides of the channel 21. The first heavily doped region 22 may be a source contact region, and the second heavily doped region 23 may be a drain contact region.

[0112] In some examples, the material of the active layer 20 may include at least one of amorphous silicon, single crystal silicon or polycrystalline silicon semiconductor materials. The following description will be made by taking the material of the active layer 20 as polycrystalline silicon as an example.

[0113] In some examples, the thickness of the active layer 20 ranges from When the thickness of the active layer 20 is within the above range, the subsequent crystallization treatment of the active layer 20 can be guaranteed to improve the conductivity of the channel 21 in the active layer 20 without increasing the difficulty of the process.

[0114] When the thickness of the active layer 20 is equal to or close to When the active layer 20 is thin, the thickness of the active layer 20 is relatively thin, which can help reduce the difficulty of the process when forming the active layer 20, and can also ensure the subsequent crystallization treatment of the active layer 20 to improve the conductivity of the channel 21 in the active layer 20.

[0115] When the thickness of the active layer 20 is equal to or close to When the thickness of the active layer 20 is thicker, the requirements for the crystallization of the active layer 20 can be better met, which is beneficial to improving the conductivity of the channel 21 in the active layer 20, and can also meet the requirements of the corresponding process of the existing active layer 20.

[0116] In other examples, the thickness of the active layer 20 ranges from In some other examples, the thickness of the active layer 20 ranges from In some other examples, the thickness of the active layer 20 ranges from

[0117] Exemplarily, the thickness of the active layer 20 is approximately or However, the embodiments of the present disclosure are not limited thereto.

[0118] It should be noted that the thickness of the active layer 20 is about Taking the example of FIG. 1 as an example, due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), the thickness error of the active layer 20 fluctuates within a range of When the active layer 20 floats within the range, it can also be considered that the thickness of the active layer 20 satisfies

[0119] In addition, in other examples, due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), the thickness error of the active layer 20 fluctuates within a range of When the active layer 20 floats within the range, it can also be considered that the thickness of the active layer 20 satisfies

[0120] The first gate 30 is located on a side of the active layer 20 close to the substrate 10, and the second gate 40 is located on a side of the active layer 20 away from the first gate 30, and the orthographic projection of the first gate 30 on the substrate 10 at least partially overlaps with the orthographic projection of the second heavily doped region 23 on the substrate 10. That is, the first gate 30 and the second gate 40 are respectively located on both sides of the active layer 20, and the first gate 30 is closer to the substrate 10 than the second gate 40. The first gate 30 can be used as the bottom gate of the thin film transistor T, and the second gate 40 can be used as the top gate of the thin film transistor T.

[0121] In some examples, the material of the first gate 30 includes a conductive metal. The conductive metal may include at least one of aluminum, copper, and molybdenum, but the present disclosure is not limited thereto.

[0122] In some examples, the material of the second gate 40 may be the same as that of the first gate 30. In other examples, the material of the second gate 40 may be different from that of the first gate 30. The embodiments of the present disclosure are not limited thereto.

[0123] In some examples, the thin film transistor T may further include a buffer layer Buffer, which is located between the substrate 10 and the first gate 30 and is used to play a supporting and buffering role.

[0124] In some examples, the thin film transistor T further includes a first gate insulating layer (English full name: Gate Insulatelayer, English abbreviation: GI) 71, the first gate insulating layer 71 is located between the first gate 30 and the active layer 20, and the first gate insulating layer 71 insulates the first gate 30 from the active layer 20.

[0125] Exemplarily, the material of the first gate insulating layer 71 includes any one of inorganic insulating materials of silicon nitride, silicon oxynitride, and silicon oxide. The material of the first gate insulating layer 71 may include silicon dioxide, but the present disclosure is not limited thereto.

[0126] In some examples, the thin film transistor T further includes a second gate insulating layer (English full name: Gate Insulatelayer, English abbreviation: GI) 72, the second gate insulating layer 72 is located between the active layer 20 and the second gate 40, and the second gate insulating layer 72 insulates the second gate 40 from the active layer 20.

[0127] Exemplarily, the material of the second gate insulating layer 72 includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. The material of the second gate insulating layer 72 may include silicon dioxide, but the present disclosure is not limited thereto.

[0128] The first electrode 50 and the second electrode 60 are both located on the side of the first gate 30 away from the substrate 10. One of the first electrode 50 and the second electrode 60 is the source electrode of the thin film transistor T, and the other is the drain electrode of the thin film transistor. The following description is made by taking the first electrode 50 of the thin film transistor T as the drain electrode of the thin film transistor T and the second electrode 60 of the thin film transistor T as the source electrode of the thin film transistor T as an example. The second electrode 60 of the thin film transistor T is configured to have a constant voltage potential.

[0129] The first electrode 50 of the thin film transistor T includes a first via hole connection portion 51 and a main body portion 52, the main body portion 52 is located on the side of the first gate 30 away from the substrate 10, the first via hole connection portion 51 is located between the main body portion 52 of the first electrode 50 and the first gate 30, and the first via hole connection portion 51 is used to electrically connect the main body portion 52 of the first electrode 50 and the first heavily doped region 22. That is, the first electrode 50 is electrically connected to the first heavily doped region 22 in the active layer 20 using the first via hole connection portion 51.

[0130] The second electrode 60 of the thin film transistor T includes a second via connection portion 61 and a main body portion 62. The second via connection portion 61 is located between the main body portion 62 of the second electrode 60 and the first gate 30, and the orthographic projection of the second via connection portion 61 on the substrate 10 is located within the orthographic projection of the second heavily doped region 23 on the substrate 10. The main body portion 62 can be electrically connected to the second heavily doped region 23 through the second via connection portion 61, and the main body portion 62 can also be electrically connected to the first gate 30 using the second via connection portion 61. That is, the second electrode 60 can be electrically connected to the second heavily doped region 23 and the first gate 30 respectively using the second via connection portion 61. Among them, the second electrode 60 of the thin film transistor T is configured to have a constant voltage potential.

[0131] Based on this, the second electrode 60 of the thin film transistor T can be used to provide a constant voltage potential for the first gate electrode 30 of the thin film transistor T, and the first gate electrode 30 of the thin film transistor T can be kept at a fixed potential to improve the floating body effect of the thin film transistor T, which is beneficial to improving the performance of the thin film transistor. Furthermore, the driving current output by the light emitting driving circuit Q to the light emitting device E via the driving transistor T3 can be stably output, thereby improving the display quality of the display device 300.

[0132] In addition, since the second electrode 60 can be electrically connected to the second heavily doped region 23 and the first gate 30 by using the second via hole connection portion 61, the second electrode 60 and the first gate 30 can be electrically connected by using the second via hole connection portion 61 originally existing in the thin film transistor T for electrically connecting the second electrode 60 and the second heavily doped region 23. Based on this, there is no need to add a connection portion that needs to bypass the active layer 20 in the thin film transistor T, thereby improving the problem of the size of the thin film transistor T being enlarged due to the connection portion. In addition, the positive projection of the second via hole connection portion 61 on the substrate 10 is set to be located within the positive projection of the second heavily doped region 23 on the substrate 10. The longitudinal space between the main body 62 and the first gate 30 can be fully utilized, that is, the internal space of the thin film transistor T can be fully utilized, and the size of the thin film transistor T does not need to be increased. When it is subsequently applied to the light-emitting drive circuit Q, it will not be limited by the area size, and thus will not affect the pixel density of the display device 300.

[0133] In some examples, the thin film transistor T further includes an interlayer dielectric layer (full name in English: Inter-Layer Dielectric, English abbreviation: ILD) 73. The interlayer dielectric layer 73 is located between the first main body 52 of the first electrode 50 and the second main body 62 of the second electrode 60, and the second gate 40. The interlayer dielectric layer 73 insulates the first main body 52 of the first electrode 50 and the second main body 62 of the second electrode 60 from the second gate 40.

[0134] For example, the material of the interlayer dielectric layer 73 may be silicon oxide (SiOx). However, the embodiments of the present disclosure are not limited thereto.

[0135] It should be noted that the main body 52 of the first electrode 50 and the main body 62 of the second electrode 60 are located on the side of the first gate 30 away from the substrate 10. The first via hole connection portion 51 may be a structure formed between the main body 52 of the first electrode 50 and the first gate 30 when the thin film transistor T forms the first electrode 50, and the second via hole connection portion 61 may be a structure formed between the main body 52 of the second electrode 60 and the first gate 30 when the thin film transistor T forms the second electrode 60. The first via hole connection portion 51 and the second via hole connection portion 61 also need to penetrate the interlayer dielectric layer 73.

[0136] In summary, the thin film transistor T provided in the embodiment of the present disclosure is configured such that the orthographic projection of the first gate electrode 30 on the substrate 10 at least partially overlaps with the orthographic projection of the second heavily doped region 23 on the substrate 10, and the orthographic projection of the second via hole connection portion 61 on the substrate 10 is located within the orthographic projection of the second heavily doped region 23 on the substrate 10. It can be realized that the second via hole connection portion 61 can not only electrically connect the main body 62 of the second electrode 60 with the second heavily doped region 23 and the first gate electrode 30, but also improve the problem of increasing the size of the thin film transistor T due to the addition of the second via hole connection portion 61 of the second electrode 60. That is, the thin film transistor T provided in the embodiment of the present disclosure can improve the floating body effect of the thin film transistor T without changing the size of the thin film transistor T as much as possible, so as to improve the display quality of the display device 300 while ensuring the pixel density of the display device 300.

[0137] The “second via connection portion 61 is electrically connected to the first gate 30” may include two situations:

[0138] First, the second via connection portion 61 is directly electrically connected to the first gate 30 .

[0139] The second type is that the second via connection portion 61 is electrically connected to the first gate 30 indirectly.

[0140] The manner in which the second via hole connection portion 61 is electrically connected to the first gate 30 in the embodiment of the present disclosure is not limited thereto. The above two connection methods will be specifically described below in conjunction with the accompanying drawings. However, whether the second via hole connection portion 61 is electrically connected directly or indirectly to the first gate 30, the first gate 30 of the thin film transistor T and the second electrode 60 of the thin film transistor T can be electrically connected. First, the first connection method will be introduced below in conjunction with the relevant accompanying drawings.

[0141] In some embodiments, please combine Figure 5 and Figure 6As shown, the second heavily doped region 23 includes at least one via W, one end of the second via connection portion 61 is electrically connected to the second main body 62 of the second electrode 60 , and the other end of the second via connection portion 61 passes through the via W and is electrically connected to the first gate 30 .

[0142] Based on this, when forming the second pole 60, the other end of the second via connection portion 61 fills the via W of the second heavily doped region 23, and the via W that penetrates the second heavily doped region 23 extends to be electrically connected to the first gate 30 at the lower position. The second via connection portion 61 can be used to electrically connect the second heavily doped region 23 and the first gate 30 at the same time. Furthermore, there is no need to add a connection portion that needs to bypass the active layer 20 in the thin film transistor T, which can improve the problem of the increase in the size of the thin film transistor T caused by the connection portion. In addition, since the thin film transistor T is electrically connected to the second heavily doped region 23 and the first gate 30 by extending the second via connection portion 61, there is no need to increase the process of the thin film transistor T.

[0143] In addition, a hole is drilled in the second heavily doped region 23 in the thin film transistor T so that the second via connection portion 61 is electrically connected to the first gate 30 via the second heavily doped region 23, thereby fully utilizing the longitudinal area between the second heavily doped region 23 and the first gate 30, that is, fully utilizing the internal space of the thin film transistor T, without increasing the size of the thin film transistor T. When it is subsequently applied to the light emitting drive circuit Q, it will not be limited by the area size, and thus will not affect the pixel density of the display device 300.

[0144] In some examples, the second heavily doped region 23 may include a via W. At this time, one end of the second via connection portion 61 is electrically connected to the second body portion 62 of the second electrode 60 , and the other end of the second via connection portion 61 fills and penetrates the via W to be electrically connected to the first gate 30 .

[0145] In some examples, the second heavily doped region 23 may include a plurality of vias W. The orthographic projection of the second main body portion 62 of the second electrode 60 on the active layer 20 covers all the vias W in the second heavily doped region 23. The second via connecting portion 61 may include a plurality of sub-portions corresponding to the plurality of vias W one by one, and one sub-portion of the second via connecting portion 61 fills one via W and penetrates the via to be electrically connected to the first gate 30.

[0146] For example, Figure 5 The second heavily doped region 23 may include four via holes W. However, the number of the via holes W in the second heavily doped region 23 is not limited thereto in the embodiment of the present disclosure.

[0147] In some embodiments, please combine Figure 5 and Figure 6As shown, since the first gate electrode 30 is provided in the thin film transistor T and is electrically connected to the second electrode 60 of the thin film transistor T, the orthographic projection of the first gate electrode 30 on the substrate 10 can be set to have no overlap with the orthographic projection of the via W on the substrate 10. This is equivalent to setting the orthographic projection of the first gate electrode 30 on the substrate 10 to have no overlap with the orthographic projection of the second via hole connecting portion 61 on the substrate 10.

[0148] Based on this, a gap can be provided between the orthographic projection of the first gate 30 on the substrate 10 and the orthographic projection of the second via connection portion 61 on the substrate 10, so as to prevent the first via connection portion 51 in the first electrode 50 from being short-circuited with the first gate 30, thereby preventing the first electrode 50 and the second electrode 60 in the thin film transistor T from being short-circuited, thereby ensuring the characteristics of the thin film transistor T.

[0149] In some embodiments, please combine Figure 5 and Figure 6 As shown, on the basis of setting the orthographic projection of the first gate 30 on the substrate 10 to have no overlap with the orthographic projection of the via W on the substrate 10, the minimum distance D1 between the orthographic projection of the first gate 30 on the substrate 10 and the orthographic projection of the via W on the substrate 10 can be set to be greater than or equal to 0.5μm.

[0150] With the above structure, a minimum distance D1 can be provided between the orthographic projection of the first gate 30 on the substrate 10 and the orthographic projection of the second via connection portion 61 on the substrate 10, thereby preventing the first via connection portion 51 in the first electrode 50 from being short-circuited with the first gate 30, thereby preventing the first electrode 50 and the second electrode 60 in the thin film transistor T from being short-circuited, thereby ensuring the characteristics of the thin film transistor T.

[0151] In some examples, continue to combine Figure 5 and Figure 6 As shown, in the first direction X, the first gate 30 includes a first side L1 and a second side L2 that are oppositely disposed, and the first side L1 is located on a side of the second side L2 close to the first via connecting portion 51 . The first direction X is the direction from the first electrode 50 to the second electrode 60 .

[0152] On the basis of setting the minimum distance D1 between the orthographic projection of the first gate 30 on the substrate 10 and the orthographic projection of the via W on the substrate 10 to be greater than or equal to 0.5 μm, it is equivalent to setting the minimum distance D1 between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the via W on the substrate 10 to be greater than or equal to 0.5 μm.

[0153] When the minimum distance D1 between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the via W on the substrate 10 is equal to or close to 0.5 μm, the first via connection portion 51 in the first electrode 50 can be prevented from being short-circuited with the first gate 30, thereby preventing the first electrode 50 and the second electrode 60 in the thin film transistor T from being short-circuited.

[0154] Furthermore, since the minimum spacing D1 between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the via W on the substrate 10 is equal to or close to 0.5 μm, the minimum spacing D1 is small, and the minimum spacing between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the channel 21 in the active layer 20 on the substrate 10 can also be made longer. That is, the first gate 30 can be extended to the outside of the channel in the active layer 20 along the first direction X. Based on this, the problem of the first gate 30 causing the active layer 20 to be uneven can be prevented, and the problem of imperfect polysilicon generated in the active layer during the crystallization process can be prevented, so as to improve the conductivity of the channel 21 in the active layer 20.

[0155] In some embodiments, please combine Figure 5 and Figure 6 As shown, on the basis of setting the orthographic projection of the first gate 30 on the substrate 10 to have no overlap with the orthographic projection of the via W on the substrate 10, the minimum distance D1 between the orthographic projection of the first gate 30 on the substrate 10 and the orthographic projection of the via W on the substrate 10 can be set to be less than or equal to 5μm.

[0156] With the above structure, a minimum distance D1 can be provided between the orthographic projection of the first gate 30 on the substrate 10 and the orthographic projection of the second via hole connecting portion 61 on the substrate 10, and the minimum distance D1 is relatively large. Thus, the first via hole connecting portion 51 in the first electrode 50 and the first gate 30 can be better prevented from being short-circuited, which causes the first electrode 50 and the second electrode 60 in the thin film transistor T to be short-circuited, thereby ensuring the characteristics of the thin film transistor T.

[0157] In some examples, continue to combine Figure 5 and Figure 6 As shown, on the basis that the minimum distance D1 between the orthographic projection of the first gate 30 on the substrate 10 and the orthographic projection of the via W on the substrate 10 is less than or equal to 5μm, it is equivalent to setting the minimum distance D1 between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the via W on the substrate 10 to be less than or equal to 5μm.

[0158] When the minimum distance D1 between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the via W on the substrate 10 is equal to or close to 5 μm, the minimum distance D1 can be made larger, thereby better preventing the first via connection portion 51 in the first electrode 50 from being short-circuited with the first gate 30, thereby causing the first electrode 50 and the second electrode 60 in the thin film transistor T to be short-circuited.

[0159] Furthermore, since the minimum spacing D1 between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the via W on the substrate 10 is equal to or close to 5 μm, the minimum spacing D1 will not be too large, and a gap can be provided between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the channel 21 in the active layer 20 on the substrate 10. That is, the first gate 30 can be extended to the outside of the channel in the active layer 20 along the first direction X. Based on this, the problem of the first gate 30 causing the active layer 20 to be uneven can be prevented, and the problem of imperfect polysilicon being generated in the active layer during the crystallization process can be prevented, so as to improve the conductivity of the channel 21 in the active layer 20.

[0160] In some embodiments, please combine Figure 5 and Figure 6 As shown, the minimum distance D1 between the orthographic projection of the first gate 30 on the substrate 10 and the orthographic projection of the via W on the substrate 10 is in the range of 0.5 μm to 5 μm. Based on this, a gap can be provided between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the via W on the substrate 10 to prevent the first via hole connecting portion 51 in the first electrode 50 from being short-circuited with the first gate 30; and a gap can be provided between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the channel 21 in the active layer 20 on the substrate 10 to prevent the first gate 30 from causing the active layer 20 to be uneven.

[0161] In some other embodiments, the minimum distance D1 between the orthographic projection of the first gate 30 on the substrate 10 and the orthographic projection of the via W on the substrate 10 may be in the range of 0.5 μm to 3 μm. In some other embodiments, the minimum distance D1 between the orthographic projection of the first gate 30 on the substrate 10 and the orthographic projection of the via W on the substrate 10 may be in the range of 0.5 μm to 2 μm.

[0162] In some examples, the minimum distance D1 between the orthographic projection of the first gate 30 on the substrate 10 and the orthographic projection of the via W on the substrate 10 is about 0.5 μm, 0.8 μm, 1 μm, 1.5 μm, 2 μm, 3 μm, 4 μm or 5 μm. The embodiments of the present disclosure are not limited thereto.

[0163] It should be noted that, taking the example that the minimum spacing D1 between the orthographic projection of the first gate 30 on the substrate 10 and the orthographic projection of the via W on the substrate 10 is approximately 0.5μm: due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the error floating range of the minimum spacing D1 floats within the range of 10%×0.5μm, it can also be considered that the minimum spacing D1 satisfies equal to 0.5μm.

[0164] In addition, in other examples, due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the error fluctuation range of the minimum spacing D1 fluctuates within the range of 5%×0.5μm, it can also be considered that the minimum spacing D1 satisfies 0.5μm.

[0165] In some examples, continue to combine Figure 5 and Figure 6 As shown, the first gate 30 in the thin film transistor T is located at a layer of the active layer 20 close to the substrate 10. Furthermore, when manufacturing the thin film transistor T, the first gate 30 is first formed on the substrate 10, and then the active layer 20 is formed. When forming the active layer 20, an amorphous silicon layer needs to be first formed on the side of the first gate 30 away from the substrate 10, that is, an amorphous silicon layer is formed on the side of the first gate insulating layer 71 away from the substrate 10. Then, an excimer laser annealing process (full name in English: Eximer Laser Annealing, English abbreviation: ELA) is performed on the amorphous silicon layer to form the active layer 20 of polycrystalline silicon.

[0166] However, since the first gate 30 has a certain thickness, an amorphous silicon layer will be formed on an uneven surface when the active layer 20 is manufactured, which will further cause protrusions or steps to form on the surface of the amorphous silicon layer. When the amorphous silicon layer is subsequently subjected to an excimer laser annealing process, poor crystallization may easily occur, thereby reducing the quality of the subsequently formed polycrystalline silicon active layer 20.

[0167] Based on the above problems, in the embodiment of the present disclosure, the orthographic projection of the channel 21 in the thin film transistor T on the substrate 10 may be set to be within the orthographic projection of the first gate 30 on the substrate 10 .

[0168] Since the first heavily doped region 22 and the second heavily doped region 23 in the active layer 20 are formed by conductorization, when the first heavily doped region 22 and the second heavily doped region 23 in the active layer 20 are formed on an uneven surface, the impact on the performance of the first heavily doped region 22 and the second heavily doped region 23 in the active layer 20 is small.

[0169] Based on this, the orthographic projection of the channel 21 in the thin film transistor T on the substrate 10 is set to be located within the orthographic projection of the first gate 30 on the substrate 10. The step area formed at the edge of the first gate 30 can avoid the channel 21 in the active layer 20 to prevent the channel 21 of the active layer 20 from being formed on the uneven surface, so as to ensure the conductivity of the channel 21 of the active layer 20.

[0170] In some embodiments, the combination Figure 5 and Figure 6 As shown, on the basis that the orthographic projection of the channel 21 on the substrate 10 in the thin film transistor T is located within the orthographic projection of the first gate 30 on the substrate 10, a minimum spacing D2 between an outer edge of the orthographic projection of the first gate 30 on the substrate 10 and an outer edge of the orthographic projection of the channel 21 on the substrate 10 is set to be greater than or equal to 0.5 μm.

[0171] When the minimum distance D2 between the outer edge of the orthographic projection of the first gate 30 on the substrate 10 and the outer edge of the orthographic projection of the channel 21 on the substrate 10 is equal to or close to 0.5 μm, the first gate 30 can be expanded so that the step area formed at the edge of the first gate 30 avoids the channel 21 in the active layer 20 to prevent the channel 21 of the active layer 20 from being formed on an uneven surface to ensure the conductivity of the channel 21 of the active layer 20.

[0172] In another embodiment, a minimum distance D2 between an outer edge of an orthographic projection of the first gate 30 on the substrate 10 and an outer edge of an orthographic projection of the channel 21 on the substrate 10 is greater than or equal to 5 μm.

[0173] When the minimum distance D2 between the outer edge of the orthographic projection of the first gate 30 on the substrate 10 and the outer edge of the orthographic projection of the channel 21 on the substrate 10 is equal to or close to 5 μm, the first gate 30 can be expanded to a greater extent so that the step area formed at the edge of the first gate 30 can better avoid the channel 21 in the active layer 20, so as to prevent the channel 21 of the active layer 20 from being formed on an uneven surface, so as to ensure the conductivity of the channel 21 of the active layer 20.

[0174] Exemplarily, the minimum distance D2 between the outer edge of the orthographic projection of the first gate 30 on the substrate 10 and the outer edge of the orthographic projection of the channel 21 on the substrate 10 is about 0.5 μm, 1 μm or 2 μm. However, the embodiments of the present disclosure are not limited thereto.

[0175] It should be noted that, taking the example that the minimum spacing D2 between the outer edge of the orthographic projection of the first gate 30 on the substrate 10 and the outer edge of the orthographic projection of the channel 21 on the substrate 10 is approximately 0.5μm: due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the error floating range of the minimum spacing D2 floats within the range of 10%×0.5μm, it can also be considered that the minimum spacing D2 satisfies equal to 0.5μm.

[0176] In addition, in other examples, due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the error fluctuation range of the minimum spacing D2 fluctuates within the range of 5%×0.5μm, it can also be considered that the minimum spacing D2 satisfies 0.5μm.

[0177] It should be noted that, since the first gate 30 includes a first side L1 and a second side L2, the second side L2 is closer to the first via hole connection portion 51 than the first side L1. In order to prevent the first gate 30 from being short-circuited with the first electrode 50, it is necessary to set a minimum spacing D1 between the first gate 30 and the first via hole connection portion 51 (via W) (the above embodiment has been described and will not be repeated here). Based on this, the second side L2 of the first gate 30 needs to consider the extension range to ensure that the minimum spacing D1 is reserved.

[0178] The extent of the extension of the first side L1 of the first gate 30 will be described in detail below with reference to the accompanying drawings.

[0179] In the above embodiment, it is introduced that “the orthographic projection of the first gate 30 on the substrate 10 at least partially overlaps with the orthographic projection of the second heavily doped region 23 on the substrate 10 ” so that the second via connection portion 62 electrically connects the second heavily doped region 23 and the first gate 30 at the same time.

[0180] Among them, “the orthographic projection of the first gate 30 on the substrate 10 at least partially overlaps with the orthographic projection of the second heavily doped region 23 on the substrate 10” includes the following situations:

[0181] The first type: the orthographic projection of the first gate 30 on the substrate 10 partially overlaps with the orthographic projection of the second heavily doped region 23 on the substrate 10. Based on this, it is equivalent to extending the first side L1 of the first gate 30 to overlap with the orthographic projection of the second heavily doped region 23 on the substrate 10. In addition, the step area formed at the edge of the first gate 30 (the first side L1) can avoid the channel 21 in the active layer 20 to prevent the channel 21 of the active layer 20 from being formed on an uneven surface, so as to ensure the conductivity of the channel 21 of the active layer 20.

[0182] The second type: the orthographic projection of the second heavily doped region 23 on the substrate 10 is located within the orthographic projection of the first gate 30 on the substrate 10. Based on this, it is equivalent to extending the first side L1 of the first gate 30 to overlap with the orthographic projection of the edge of the second heavily doped region 23 away from the first heavily doped region 22 on the substrate 10. Alternatively, the first side L1 of the first gate 30 is extended to the outside of the second heavily doped region 23, so that the step area formed at the edge of the first gate 30 (the first side L1) can avoid the second heavily doped region 23 and the channel 21 in the active layer 20, so as to prevent the second heavily doped region 23 and the channel 21 of the active layer 20 from being formed on an uneven surface, so as to ensure the performance of the active layer 20.

[0183] In some embodiments, the combination Figure 5 and Figure 6 As shown, in the case where "the first side L1 of the first gate 30 extends to the outside of the second heavily doped region 23", the minimum distance D3 between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the third side L3 of the second heavily doped region 23 away from the first heavily doped region 22 on the substrate 10 can be set to be greater than or equal to 0.5μm.

[0184] When the minimum distance D3 between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the side L3 of the second heavily doped region 23 away from the first heavily doped region 22 on the substrate 10 is equal to or close to 0.5 μm, the step area formed at the edge of the first gate 30 (the first side L1) can avoid the second heavily doped region 23 and the channel 21 in the active layer 20, so as to prevent the second heavily doped region 23 and the channel 21 of the active layer 20 from being formed on the uneven surface, so as to ensure the performance of the active layer 20. In addition, at this time, the second side L2 of the first gate 30 has a small degree of expansion, which can be equivalent to not increasing the size of the thin film transistor T, so as to prevent it from being limited by the area size when it is subsequently applied to the light-emitting drive circuit Q, and thus will not affect the pixel density of the display device 300.

[0185] In some embodiments, the combination Figure 5 and Figure 6 As shown, the minimum distance D3 between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the third side L3 of the second heavily doped region 23 away from the first heavily doped region 22 on the substrate 10 is less than or equal to 10 μm.

[0186] When the minimum distance D3 between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the third side L3 of the second heavily doped region 23 on the side away from the first heavily doped region 22 on the substrate 10 is equal to or close to 10 μm, the second side L2 of the first gate 30 can be expanded to a greater extent, but the size of the thin film transistor T will not be greatly increased. At the same time, the step area formed at the edge of the first gate 30 (the first side L1) can better avoid the second heavily doped region 23 and the channel 21 in the active layer 20, so as to prevent the second heavily doped region 23 and the channel 21 of the active layer 20 from being formed on the uneven surface, so as to ensure the performance of the active layer 20.

[0187] In some embodiments, the combination Figure 5 and Figure 6 As shown, the minimum distance D3 between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the third side L3 of the second heavily doped region 23 away from the first heavily doped region 22 on the substrate 10 is in the range of 0.5 μm to 10 μm.

[0188] Based on this, the step area formed at the edge of the first gate 30 (the first side L1) can better avoid the second heavily doped region 23 and the channel 21 in the active layer 20 to prevent the second heavily doped region 23 and the channel 21 of the active layer 20 from being formed on an uneven surface to ensure the performance of the active layer 20; and it can also prevent the second side L2 of the first gate 30 from expanding too much and affecting the size of the thin film transistor T.

[0189] In some other embodiments, the minimum distance D3 between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the third side L3 of the second heavily doped region 23 on the side away from the first heavily doped region 22 on the substrate 10 is in the range of 0.5 μm to 5 μm. In some other embodiments, the minimum distance D3 between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the third side L3 of the second heavily doped region 23 on the side away from the first heavily doped region 22 on the substrate 10 is in the range of 0.5 μm to 3 μm.

[0190] Exemplarily, the minimum distance D3 between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the third side L3 of the second heavily doped region 23 away from the first heavily doped region 22 on the substrate 10 is approximately 0.5 μm, 1 μm, 2 μm, 3 μm, 5 μm, 7 μm or 10 μm. The embodiments of the present disclosure are not limited thereto.

[0191] It should be noted that, taking the example that the minimum spacing D3 between the orthographic projection of the second side L2 of the first gate 30 on the substrate 10 and the orthographic projection of the third side L3 of the second heavily doped region 23 on the side away from the first heavily doped region 22 on the substrate 10 is approximately 0.5μm: due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the error floating range of the minimum spacing D3 floats within the range of 10%×0.5μm, it can also be considered that the minimum spacing D1 satisfies equal to 0.5μm.

[0192] In addition, in other examples, due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the error fluctuation range of the minimum spacing D3 fluctuates within the range of 5%×0.5μm, it can also be considered that the minimum spacing D1 satisfies 0.5μm.

[0193] In some embodiments, in combination Figure 5 As shown, the first gate 30 further includes a fourth side L4 and a fifth side L5 which are arranged opposite to each other along the second direction Y. One side of the fourth side L4 is electrically connected to the first side L1, the other side of the fourth side L4 is electrically connected to the second side L3, one side of the fifth side L5 is electrically connected to the first side L1, and the other side of the fifth side L5 is electrically connected to the second side L3.

[0194] In some examples, for the above-mentioned case of “the first side L1 of the first gate 30 extends to the outside of the second heavily doped region 23 ”, the distance between the orthographic projection of the fourth side L4 on the substrate 10 and the orthographic projection of the second heavily doped region 23 on the substrate 10 is greater than or equal to 0.5 μm.

[0195] Based on this, the step area formed at the edge of the first gate 30 (the fourth side L4) can better avoid the second heavily doped region 23 and the channel 21 in the active layer 20 to prevent the second heavily doped region 23 and the channel 21 of the active layer 20 from being formed on an uneven surface to ensure the performance of the active layer 20; it can also prevent the second side L2 of the first gate 30 from expanding too much and affecting the size of the thin film transistor T.

[0196] In some examples, for the above-mentioned case of “the first side L1 of the first gate 30 extends to the outside of the second heavily doped region 23 ”, the distance between the orthographic projection of the fifth side L5 on the substrate 10 and the orthographic projection of the second heavily doped region 23 on the substrate 10 is greater than or equal to 0.5 μm.

[0197] Based on this, the step area formed at the edge of the first gate 30 (the fifth side L5) can better avoid the second heavily doped region 23 and the channel 21 in the active layer 20 to prevent the second heavily doped region 23 and the channel 21 of the active layer 20 from being formed on an uneven surface to ensure the performance of the active layer 20; it can also prevent the second side L2 of the first gate 30 from expanding too much and affecting the size of the thin film transistor T.

[0198] It should be noted that, for the definition of the distance between the fourth side L4 and the fifth side L5 and the orthographic projection of the second heavily doped region 23 on the substrate 10, reference can be made to the definition of the distance between the first side L1 and the orthographic projection of the second heavily doped region 23 on the substrate 10, which will not be repeated here.

[0199] The above mainly introduces the situation that the second via connection portion 61 is directly electrically connected to the first gate 30 in combination with the relevant drawings. The following will mainly introduce the second connection method between the second via connection portion 61 and the first gate 30 in combination with the relevant drawings: the second via connection portion 61 is indirectly electrically connected to the first gate 30.

[0200] Figure 7 is a structural diagram of a thin film transistor according to some other embodiments, Figure 8 1 is a film layer diagram of a thin film transistor according to some other embodiments.

[0201] In some embodiments, in combination Figure 7 and Figure 8 As shown, one end of the second via hole connecting portion 61 is electrically connected to the second main body portion 62 of the second electrode 60 , and the other end of the second via hole connecting portion 61 is electrically connected to the first gate 30 through the second heavily doped region 23 .

[0202] The second heavily doped region 23 may include a third via connection portion H, which penetrates the first gate insulating layer 71 to electrically connect the second medium doped region 23 to the first gate 30. Furthermore, the second electrode 60 may be electrically connected to the first gate 30 via the second via connection portion 61 and the second heavily doped region 23 in sequence. That is, the second electrode 60 may be indirectly electrically connected to the first gate 30 via the second via connection portion 61.

[0203] Based on this, there is no need to add a connection portion that needs to bypass the active layer 20 in the thin film transistor T, which can improve the problem of the size of the thin film transistor T being enlarged due to the connection portion. In addition, the longitudinal area between the second heavily doped region 23 and the first gate 30 can be fully utilized, that is, the internal space of the thin film transistor T is fully utilized, and there is no need to increase the size of the thin film transistor T. When it is subsequently applied to the light-emitting drive circuit Q, it will not be limited by the area size, and will not affect the pixel density of the display device 300.

[0204] In some embodiments, in combination Figure 7 and Figure 8 As shown, the first gate 30 in the thin film transistor T is located at a layer of the active layer 20 close to the substrate 10. Further, when manufacturing the thin film transistor T, the first gate 30 is first formed on the substrate 10, and then the active layer 20 is formed. When forming the active layer 20, an amorphous silicon layer needs to be first formed on the side of the first gate 30 away from the substrate 10, that is, an amorphous silicon layer is formed on the side of the first gate insulating layer 71 away from the substrate 10. Then, the amorphous silicon layer is subjected to an excimer laser annealing process to form the active layer 20 of polycrystalline silicon.

[0205] However, since the first gate 30 has a certain thickness, an amorphous silicon layer will be formed on an uneven surface when the active layer 20 is manufactured, which will further cause protrusions or steps to form on the surface of the amorphous silicon layer. When the amorphous silicon layer is subsequently subjected to an excimer laser annealing process, poor crystallization may easily occur, thereby reducing the quality of the subsequently formed polycrystalline silicon active layer 20.

[0206] Based on the above problems, in the embodiment of the present disclosure, the orthographic projection of the channel 21 in the thin film transistor T on the substrate 10 may be set to be within the orthographic projection of the first gate 30 on the substrate 10 .

[0207] Since the first heavily doped region 22 and the second heavily doped region 23 in the active layer 20 are formed by conductorization, and thus when the first heavily doped region 22 and the second heavily doped region 23 in the active layer 20 are formed on an uneven surface, the impact on the performance of the first heavily doped region 22 and the second heavily doped region 23 in the active layer 20 is small.

[0208] Based on this, the orthographic projection of the channel 21 in the thin film transistor T on the substrate 10 is set to be within the orthographic projection of the first gate 30 on the substrate 10. The step area formed at the edge of the first gate 30 can avoid the channel 21 in the active layer 20 to prevent the channel 21 of the active layer 20 from being formed on the uneven surface, so as to ensure the conductivity of the channel 21 of the active layer 20.

[0209] In some embodiments, the combination Figure 7 and Figure 8 As shown, on the basis that the orthographic projection of the channel 21 on the substrate 10 in the thin film transistor T is located within the orthographic projection of the first gate 30 on the substrate 10, the minimum spacing between the outer edge of the orthographic projection of the first gate 30 on the substrate 10 and the outer edge of the orthographic projection of the channel 21 on the substrate 10 is greater than or equal to 0.5 μm.

[0210] When the minimum distance D2 between the outer edge of the orthographic projection of the first gate 30 on the substrate 10 and the outer edge of the orthographic projection of the channel 21 on the substrate 10 is equal to or close to 0.5 μm, the first gate 30 can be expanded so that the step area formed at the edge of the first gate 30 avoids the channel 21 in the active layer 20 to prevent the channel 21 of the active layer 20 from being formed on an uneven surface to ensure the conductivity of the channel 21 of the active layer 20.

[0211] In another embodiment, a minimum distance D2 between an outer edge of an orthographic projection of the first gate 30 on the substrate 10 and an outer edge of an orthographic projection of the channel 21 on the substrate 10 is greater than or equal to 5 μm.

[0212] When the minimum distance D2 between the outer edge of the orthographic projection of the first gate 30 on the substrate 10 and the outer edge of the orthographic projection of the channel 21 on the substrate 10 is equal to or close to 5 μm, the first gate 30 can be expanded to a greater extent so that the step area formed at the edge of the first gate 30 can better avoid the channel 21 in the active layer 20, so as to prevent the channel 21 of the active layer 20 from being formed on an uneven surface, so as to ensure the conductivity of the channel 21 of the active layer 20.

[0213] Exemplarily, the minimum distance D2 between the outer edge of the orthographic projection of the first gate 30 on the substrate 10 and the outer edge of the orthographic projection of the channel 21 on the substrate 10 is about 0.5 μm, 1 μm or 2 μm. However, the embodiments of the present disclosure are not limited thereto.

[0214] In some embodiments, the combination Figure 7 and Figure 8 As shown, the orthographic projection of the active layer 20 on the substrate 10 is located within the orthographic projection of the first gate 30 on the substrate 10 .

[0215] Based on this, the orthographic projection of the channel 21 in the thin film transistor T on the substrate 10 is set to be located within the orthographic projection of the first gate 30 on the substrate 10. The step area formed at the edge of the first gate 30 can be made to avoid the active layer 20 to prevent the active layer 20 from being formed on an uneven surface, so as to ensure the performance of the active layer 20.

[0216] In some embodiments, the combination Figure 7 and Figure 8 As shown, a minimum distance D4 between an outer edge of an orthographic projection of the first gate 30 on the substrate 10 and an outer edge of an orthographic projection of the active layer 20 on the substrate 10 is greater than or equal to 0.5 μm.

[0217] When the minimum distance D4 between the outer edge of the orthographic projection of the first gate 30 on the substrate 10 and the outer edge of the orthographic projection of the active layer 20 on the substrate 10 is equal to or close to 0.5 μm, the first gate 30 can be expanded outward so that the step area formed at the edge of the first gate 30 avoids the active layer 20 to prevent the active layer 20 from being formed on an uneven surface, so as to ensure the performance of the active layer 20.

[0218] In another embodiment, a minimum distance D4 between an outer edge of an orthographic projection of the first gate 30 on the substrate 10 and an outer edge of an orthographic projection of the active layer 20 on the substrate 10 is greater than or equal to 5 μm.

[0219] When the minimum distance D4 between the outer edge of the orthographic projection of the first gate 30 on the substrate 10 and the outer edge of the orthographic projection of the active layer 20 on the substrate 10 is equal to or close to 5 μm, the first gate 30 can be expanded to a greater extent so that the step area formed at the edge of the first gate 30 can better avoid the active layer 20, so as to prevent the active layer 20 from being formed on an uneven surface, so as to ensure the performance of the active layer 20.

[0220] Exemplarily, the minimum distance D4 between the outer edge of the orthographic projection of the first gate 30 on the substrate 10 and the outer edge of the orthographic projection of the active layer 20 on the substrate 10 is about 0.5 μm, 1 μm or 2 μm. However, the embodiments of the present disclosure are not limited thereto.

[0221] It should be noted that, taking the example that the minimum spacing D4 between the outer edge of the orthographic projection of the first gate 30 on the substrate 10 and the outer edge of the orthographic projection of the active layer 20 on the substrate 10 is approximately 0.5μm: due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the error floating range of the minimum spacing D4 floats within the range of 10%×0.5μm, it can also be considered that the minimum spacing D4 satisfies equal to 0.5μm.

[0222] In addition, in other examples, due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the error fluctuation range of the minimum spacing D4 fluctuates within the range of 5%×0.5μm, it can also be considered that the minimum spacing D4 satisfies 0.5μm.

[0223] In some embodiments, the combination Figure 7 and Figure 8 As shown, a minimum distance D4 between an outer edge of an orthographic projection of the first gate 30 on the substrate 10 and an outer edge of an orthographic projection of the active layer 20 on the substrate 10 is less than or equal to 10 μm.

[0224] When the minimum distance D4 between the outer edge of the orthographic projection of the first gate 30 on the substrate 10 and the outer edge of the orthographic projection of the active layer 20 on the substrate 10 is equal to or close to 10 μm, the first gate 30 can be expanded to a greater extent, but the size of the thin film transistor T will not be greatly increased. At the same time, the step area formed at the edge of the first gate 30 can better avoid the active layer 20 to prevent the active layer 20 from being formed on an uneven surface, so as to ensure the performance of the active layer 20.

[0225] In some embodiments, the combination Figure 7 and Figure 8 As shown, the minimum distance D4 between the outer edge of the orthographic projection of the first gate 30 on the substrate 10 and the outer edge of the orthographic projection of the active layer 20 on the substrate 10 is in the range of 0.5 μm to 10 μm.

[0226] Based on this, the step area formed at the edge of the first gate 30 can better avoid the active layer 20 to prevent the active layer 20 from being formed on an uneven surface to ensure the performance of the active layer 20; it can also prevent the first gate 30 from expanding too much and affecting the size of the thin film transistor T.

[0227] In some other embodiments, the minimum distance D4 between the outer edge of the orthographic projection of the first gate 30 on the substrate 10 and the outer edge of the orthographic projection of the active layer 20 on the substrate 10 is in the range of 0.5 μm to 3 μm. In some other embodiments, the minimum distance D4 between the outer edge of the orthographic projection of the first gate 30 on the substrate 10 and the outer edge of the orthographic projection of the active layer 20 on the substrate 10 is in the range of 0.5 μm to 5 μm. The embodiments of the present disclosure are not limited thereto.

[0228] In some embodiments, the combination Figures 5 to 8 As shown, when forming the channel 21 in the active layer 20, the second gate 40 can be used as a mask to form the first heavily doped region 22 and the second heavily doped region 23 in the active layer 20. So that the projection of the second gate 40 on the substrate 10 roughly coincides with the projection of the channel 21 on the substrate 10.

[0229] Based on this, it is helpful to prevent the orthographic projection of the second gate 40 on the substrate 10 from overlapping with the orthographic projection of the first heavily doped region 22 and / or the second heavily doped region 23 on the substrate 10, thereby preventing the overlapping region from introducing parasitic capacitance and parasitic resistance. It is helpful to reduce the parasitic effect and signal delay problems in the thin film transistor T, so as to improve the performance of the thin film transistor T.

[0230] It should be noted that "substantially coincident" includes absolute coincidence and approximate coincidence. That is, the floating range of the gap between the projection of the second gate 40 on the substrate 10 and the projection of the channel 21 on the substrate 10 does not exceed the error threshold. It can also be considered that the projection of the second gate 40 on the substrate 10 and the edge of the projection of the channel 21 on the substrate 10 are relatively "coincident". The specific value of the error threshold is not limited in this disclosure.

[0231] Fig. 9 is a film layer diagram of a thin film transistor according to some other embodiments, Fig.10 FIG. 1 is a film layer diagram of a thin film transistor according to some other embodiments. Fig. 9 Corresponding to the thin film transistor in which the second via hole connecting portion 61 and the first gate 30 are electrically connected in the first manner (direct electrical connection), Fig.10 The thin film transistor corresponds to the second via hole connection portion 61 and the first gate 30 being electrically connected in the second manner (indirect electrical connection).

[0232] In some embodiments, see Fig. 9 and Fig.10 As shown, the active layer 20 also includes a first low-doped region (English full name: Lightly Doped Drain, English abbreviation: LDD) 24 and a second low-doped region (English full name: Lightly Doped Drain, English abbreviation: LDD) 25. The first low-doped region 24 is located between the first heavily doped region 22 and the channel 21, and the doping concentration of the first low-doped region 24 is less than the doping concentration of the first heavily doped region 22. The second low-doped region 25 is located between the second heavily doped region 23 and the channel 21, and the doping concentration of the second low-doped region 25 is less than the doping concentration of the second heavily doped region 23.

[0233] A first low-doped region 24 is provided between the first heavily doped region 22 and the channel 21, and a second low-doped region 25 is provided between the second heavily doped region 23 and the channel 21. That is, a region where the doping concentration of the low-doped region is one order of magnitude lower than that of the high-doped region is provided between the channel 21 and the heavily doped region. The low-doped region (the first low-doped region 24 and the second low-doped region 25) is equivalent to a large resistor connected in series between the source and drain (the first electrode 50 and the second electrode 60) of the thin film transistor T and the channel 21, which is beneficial to reducing the horizontal electric field of the channel 21 and reducing the hot carriers generated by the impact ionization caused by the electric field acceleration, and can effectively suppress the leakage current of two orders of magnitude.

[0234] Fig.11 is a flow chart of a method for manufacturing a thin film transistor according to some embodiments, Fig.12 for Fig.11 The membrane structure diagram corresponding to the steps in the figure. Fig.13 for Fig.11The top view of some steps in the process. Fig.14 for Fig.11 The top view corresponding to other steps in the figure. Fig.13 and Fig.14 The substrate is not shown.

[0235] In some embodiments, in combination Figure 11 to Figure 14 As shown, the present disclosure provides a method for manufacturing a thin film transistor, the manufacturing method comprising:

[0236] S11 : forming a first gate 30 on one side of the substrate 10 .

[0237] S12: An active layer 20 is formed on a side of the substrate 10 away from the first gate 30, wherein the active layer 20 includes a channel 21, and a first region to be doped 21A and a second region to be doped 21B located on both sides of the channel 21, and an orthographic projection of the first gate 30 on the substrate 10 at least partially overlaps with an orthographic projection of the second region to be doped 21B on the substrate 10.

[0238] S13 : forming a second gate 40 on a side of the active layer 20 away from the substrate 10 .

[0239] S14: Conducting the first region to be doped 21A and the second region to be doped 21B to form the corresponding first heavily doped region 22 and second heavily doped region 23. The first region to be doped 21A is conductorized to form the first heavily doped region 22 in the active layer 20, and the second region to be doped 21B is conductorized to form the second heavily doped region 23 by using a masking process.

[0240] S15: A first pole 50 and a second pole 60 are formed on a side of the first gate 30 away from the substrate 10, the first pole 50 includes a first via connection portion 51, and the first via connection portion 51 is electrically connected to the first heavily doped region 22; the second pole 60 includes a second via connection portion 61, and the second via connection portion 61 is electrically connected to the second heavily doped region 23 and the first gate 30, and the orthographic projection of the second via connection portion 61 on the substrate 10 is located within the range of the orthographic projection of the second heavily doped region 23 on the substrate 10.

[0241] In step S5, the first pole 50 formed includes a first via hole connection portion 51 and a first main body portion 52, and the second pole 60 formed includes a second via hole connection portion 61 and a second main body portion 62. The first main body portion 52 of the first pole 50 and the second main body portion 62 of the second pole 60 are formed on the side of the first gate 30 away from the substrate 10. The first via hole connection portion 51 of the first pole 50 and the second via hole connection portion 61 of the second pole 60 are formed between the main body portion (the first main body portion 52 and the second main body portion 52) and the first gate 30, so as to electrically connect the first main body portion 52 and the first heavily doped region 22 by using the first via hole connection portion 51. And, the second main body portion 62 is electrically connected to the second heavily doped region 23 and the first gate 30 by using the second via hole connection portion 61.

[0242] In summary, the method for manufacturing a thin film transistor provided in the embodiment of the present disclosure is to set the orthographic projection of the first gate 30 on the substrate 10 to at least partially overlap with the orthographic projection of the second heavily doped region 23 on the substrate 10, and the orthographic projection of the second via hole connection portion 61 on the substrate 10 is located within the orthographic projection of the second heavily doped region 23 on the substrate 10. It can be achieved that the second via hole connection portion 61 can not only electrically connect the main body 62 of the second pole 60 with the second heavily doped region 23 and the first gate 30, but also improve the problem of increasing the size of the thin film transistor T due to the addition of the second via hole connection portion 61 of the second pole 60. That is, the thin film transistor T provided in the embodiment of the present disclosure can improve the floating body effect of the thin film transistor T without changing the size of the thin film transistor T as much as possible, so as to improve the display quality of the display device 300 while ensuring the pixel density of the display device 300.

[0243] Fig.15 for Fig.11 The film layer structure diagram corresponding to step S14. Fig.16 for Fig.11 The top view corresponding to step S14 in FIG.

[0244] In some embodiments, please combine Fig.15 and Fig.16 As shown, step S14 in the method for manufacturing a thin film transistor, before step S15 , that is, before forming the first electrode 50 and the second electrode 60 on the side of the first gate 30 away from the substrate 10 , may further include: S141 : forming a via W in the second heavily doped region 23 .

[0245] Based on this, in step S15, forming the second pole 60 includes: the second via connection portion 61 of the second pole 60 passes through the via W and is electrically connected to the first gate 30. That is, when forming the second pole 60, the other end of the second via connection portion 61 fills the via W of the second heavily doped region 23, and the via W passing through the second heavily doped region 23 extends to be electrically connected to the first gate 30 at the lower position. The second via connection portion 61 is used to electrically connect the second heavily doped region 23 and the first gate 30 at the same time. Furthermore, there is no need to add a connection portion that needs to bypass the active layer 20 in the thin film transistor T, which can improve the problem of the size of the thin film transistor T being enlarged due to the connection portion. In addition, since the thin film transistor T is electrically connected to the second heavily doped region 23 and the first gate 30 by extending the second via connection portion 61, there is no need to increase the process of the thin film transistor T.

[0246] In addition, a hole is drilled in the second heavily doped region 23 in the thin film transistor T so that the second via connection portion 61 is electrically connected to the first gate 30 via the second heavily doped region 23, thereby fully utilizing the longitudinal area between the second heavily doped region 23 and the first gate 30, that is, fully utilizing the internal space of the thin film transistor T, without increasing the size of the thin film transistor T. When it is subsequently applied to the light emitting drive circuit Q, it will not be limited by the area size, and thus will not affect the pixel density of the display device 300.

[0247] Fig.17 is a flow chart of a method for manufacturing a thin film transistor according to some other embodiments, Fig.18 for Fig.17 The membrane layer structure diagram corresponding to the steps in the figure.

[0248] In some embodiments, please combine Fig.17 and Fig.18 As shown, a method for manufacturing a thin film transistor includes:

[0249] S21 : forming a first gate 30 on one side of the substrate 10 .

[0250] S22: An active layer 20 is formed on a side of the substrate 10 away from the first gate 30, the active layer 20 includes a channel 21, and a first region to be doped 21A and a second region to be doped 21B located on both sides of the channel 21, the orthographic projection of the first gate 30 on the substrate 10 at least partially overlaps with the orthographic projection of the second region to be doped 21B on the substrate 10, and the second region to be doped 21B includes a third via connection portion H, and the third via connection portion H is electrically connected to the first gate 30.

[0251] Before step S22 and after step S21 , the method may include forming a first gate insulating layer 71 on a side of the first gate 30 away from the substrate 10 , and forming a through hole in the first gate insulating layer 71 to expose the first gate 30 .

[0252] In step S22, an active layer 20 is formed on a side of the substrate 10 away from the first gate 30, that is, an active layer 20 is formed on a side of the first gate insulating layer 71 away from the first gate 30. When the active layer 20 is formed, the third via connection portion H of the second to-be-doped region 21B can fill the through hole in the first gate insulating layer 71, so that the third via connection portion H passes through the through hole and is electrically connected to the first gate 30.

[0253] It should be noted that in this step, only a through hole is formed in the first gate insulating layer 71 at a position corresponding to the second region to be doped 21B. That is, the first gate insulating layer 71 at a position corresponding to the first region to be doped 21A does not need to be punched.

[0254] Based on this, in the subsequent method for manufacturing a thin film transistor, when forming the first electrode 50, it will not extend to the first gate insulating layer 71, that is, it will not extend to the position of the first gate 30, and there will be a problem of short circuit with the first gate 30. Furthermore, when manufacturing the first gate 30 in the thin film transistor, there is no need to consider the problem of avoiding the first electrode 50, and the first gate 30 can be expanded as much as possible, so that the orthographic projection of the channel 21 in the subsequently formed active layer 20 on the substrate 10 is located within the orthographic projection of the first gate 30 on the substrate 10. The setting can make the orthographic projection of the subsequently formed active layer 20 on the substrate 10 located within the orthographic projection of the first gate 30 on the substrate 10.

[0255] With such configuration, the step area formed at the edge of the first gate 30 can avoid the active layer 20 (the channel 21 in the active layer 20 ) to prevent the active layer 20 from being formed on an uneven surface, thereby ensuring the performance of the active layer 20 .

[0256] S23 : forming a second gate 40 on a side of the active layer 20 away from the substrate 10 .

[0257] S24: Conducting the first to-be-doped region 21A and the second to-be-doped region 21B to form corresponding first heavily doped region 22 and second heavily doped region 23 .

[0258] S25: A first pole 50 and a second pole 60 are formed on a side of the first gate 30 away from the substrate 10, the first pole 50 includes a first via connection portion 51, and the first via connection portion 51 is electrically connected to the first heavily doped region 22; the second pole 60 includes a second via connection portion 61, and the second via connection portion 61 is electrically connected to the second heavily doped region 23, and the orthographic projection of the second via connection portion 61 on the substrate 10 is located within the range of the orthographic projection of the second heavily doped region 23 on the substrate 10.

[0259] In summary, in the method for manufacturing a thin film transistor provided by the embodiment of the present disclosure, the second heavily doped region 23 may include a third via connection portion H, and the third via connection portion H penetrates the first gate insulating layer 71, so that the second medium doped region 23 is electrically connected to the first gate 30. Furthermore, the second electrode 60 may be electrically connected to the first gate 30 through the second via connection portion 61 and the second heavily doped region 23 in sequence. That is, the second electrode 60 may be indirectly electrically connected to the first gate 30 through the second via connection portion 61.

[0260] Based on this, there is no need to add a connection portion that needs to bypass the active layer 20 in the thin film transistor T, which can improve the problem of the size of the thin film transistor T being enlarged due to the connection portion. In addition, the longitudinal area between the second heavily doped region 23 and the first gate 30 can be fully utilized, that is, the internal space of the thin film transistor T is fully utilized, and there is no need to increase the size of the thin film transistor T. When it is subsequently applied to the light-emitting drive circuit Q, it will not be limited by the area size, and will not affect the pixel density of the display device 300.

[0261] Fig.19 The diagram is a structural diagram of some steps of a method for manufacturing a thin film transistor according to some embodiments.

[0262] In some embodiments, please combine Fig.19 As shown, and Fig.12 or Fig.18 As shown, in step S12 (as Fig.12 As shown) or step S22 (as shown Fig.18 In the embodiment shown in FIG. 1 , “forming an active layer 20 on a side of the substrate 10 away from the first gate 30” may include:

[0263] S101 : forming an amorphous silicon layer 201 on a side of the substrate 10 away from the first gate 30 .

[0264] S102: performing an excimer laser annealing process (full name in English: Eximer Laser Annealing, English abbreviation: ELA) on the amorphous silicon layer 201 to form an initial active layer 202 of polycrystalline silicon.

[0265] S103 : etching the initial active layer 202 of polysilicon to form an active layer 20 .

[0266] However, since the first gate 30 has a certain thickness, an amorphous silicon layer will be formed on an uneven surface when the active layer 20 is manufactured, which will further cause protrusions or steps to form on the surface of the amorphous silicon layer. When the amorphous silicon layer is subsequently subjected to an excimer laser annealing process, poor crystallization may easily occur, thereby reducing the quality of the subsequently formed polycrystalline silicon active layer 20.

[0267] Based on the above problems, in the embodiment of the present disclosure, the orthographic projection of the channel 21 in the thin film transistor T on the substrate 10 can be set to be located within the orthographic projection of the first gate 30 on the substrate 10. The step area formed at the edge of the first gate 30 can be made to avoid the channel 21 in the active layer 20 to prevent the channel 21 of the active layer 20 from being formed on an uneven surface, so as to ensure the conductivity of the channel 21 of the active layer 20.

[0268] In some embodiments, see Fig.12 or Fig.18 As shown, in step S14 (as Fig.12 As shown) or step S24 (as shown Fig.18 In the method of “using a mask process to perform a conductor process on the first to-be-doped region 21A and the second to-be-doped region 21B to form a corresponding first heavily doped region 22 and a second heavily doped region 23”, the method may include:

[0269] By using a self-alignment process, the first gate 30 is used as a mask to perform a conductor process on the first region to be doped 21A and the second region to be doped 21B to form the corresponding first heavily doped region 22 and the second heavily doped region 23. Based on this, the projection of the second gate 40 on the substrate 10 can be roughly overlapped with the projection of the channel 21 on the substrate 10.

[0270] As described above, not only does it not require a separate mask plate, but it can also help prevent the orthographic projection of the second gate 40 on the substrate 10 from overlapping with the orthographic projection of the first heavily doped region 22 and / or the second heavily doped region 23 on the substrate 10, thereby preventing the overlapping region from introducing parasitic capacitance and parasitic resistance. This can help reduce the parasitic effects and signal delays in the thin film transistor T, so as to improve the performance of the thin film transistor T.

[0271] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A thin film transistor, characterized in that: include: substrate; An active layer, located on one side of the substrate, the active layer comprising a channel and a first heavily doped region and a second heavily doped region located on both sides of the channel; A first gate, located on a side of the active layer close to the substrate; a second gate, located at a side of the active layer away from the first gate, and an orthographic projection of the first gate on the substrate at least partially overlaps with an orthographic projection of the second heavily doped region on the substrate; A first electrode and a second electrode, the first electrode comprising a first main body portion and a first via-hole connecting portion, the second electrode comprising a second main body portion and a second via-hole connecting portion; the first main body portion and the second main body portion are located on a side of the second gate away from the active layer; The first via connection portion electrically connects the first main body portion and the first heavily doped region; the second via connection portion electrically connects the second main body portion, the second heavily doped region and the first gate, and the orthographic projection of the second via connection portion on the substrate is located within the orthographic projection of the second heavily doped region on the substrate.

2. The thin film transistor according to claim 1, characterized in that: The second heavily doped region includes at least one via hole, one end of the second via hole connecting portion is electrically connected to the second electrode, and the other end of the second via hole connecting portion passes through the via hole and is electrically connected to the first gate.

3. The thin film transistor according to claim 2, characterized in that: The orthographic projection of the first gate on the substrate does not overlap with the orthographic projection of the via on the substrate.

4. The thin film transistor according to claim 1, characterized in that: A minimum distance between an orthographic projection of the first gate on the substrate and an orthographic projection of the via hole on the substrate is greater than or equal to 0.5 μm.

5. The thin film transistor according to claim 1, characterized in that: The orthographic projection of the channel on the substrate is located within the orthographic projection of the first gate on the substrate, and the minimum distance between the outer edge of the orthographic projection of the first gate on the substrate and the outer edge of the orthographic projection of the channel on the substrate is greater than or equal to 0.5 μm.

6. The thin film transistor according to claim 5, characterized in that: The orthographic projection of the second heavily doped region on the substrate is located within the orthographic projection of the first gate on the substrate.

7. The thin film transistor according to claim 6, characterized in that: Along the first direction, the first gate includes a first side and a second side that are arranged opposite to each other, and the first side is located on a side of the second side close to the first via connecting portion; the first direction is the direction from the first pole to the second pole; A minimum distance between an orthographic projection of the second side of the first gate on the substrate and an orthographic projection of a third side of the second heavily doped region away from the first heavily doped region on the substrate is greater than or equal to 0.5 μm.

8. The thin film transistor according to claim 7, characterized in that: A minimum distance between an orthographic projection of the second side of the first gate on the substrate and an orthographic projection of a third side of the second heavily doped region away from the first heavily doped region on the substrate is less than or equal to 10 μm.

9. The thin film transistor according to claim 1, characterized in that: One end of the second via connection portion is electrically connected to the second main body portion of the second electrode, and the other end of the second via connection portion is electrically connected to the first gate through the second heavily doped region.

10. The thin film transistor according to claim 9, characterized in that: The orthographic projection of the channel on the substrate is located within the orthographic projection of the first gate on the substrate, and the minimum distance between the outer edge of the orthographic projection of the first gate on the substrate and the outer edge of the orthographic projection of the channel on the substrate is greater than or equal to 0.5 μm.

11. The thin film transistor according to claim 9, characterized in that: The orthographic projection of the active layer on the substrate is located within the orthographic projection of the first gate on the substrate.

12. The thin film transistor according to claim 9, characterized in that: A minimum distance between an outer edge of an orthographic projection of the first gate on the substrate and an outer edge of an orthographic projection of the active layer on the substrate is greater than or equal to 0.5 μm.

13. The thin film transistor according to claim 12, characterized in that: A minimum distance between an outer edge of an orthographic projection of the first gate on the substrate and an outer edge of an orthographic projection of the active layer on the substrate is less than or equal to 10 μm.

14. The thin film transistor according to claim 1, characterized in that: The active layer further includes a first low-doping region and a second low-doping region; The first low-doped region is located between the first heavily-doped region and the channel, and the doping concentration of the first low-doped region is less than the doping concentration of the first heavily-doped region; The second low-doped region is located between the second heavily-doped region and the channel, and a doping concentration of the second low-doped region is less than a doping concentration of the second heavily-doped region.

15. The thin film transistor according to claim 1, characterized in that: The projection of the second gate on the substrate substantially coincides with the projection of the channel on the substrate.

16. The thin film transistor according to claim 1, characterized in that: The thickness of the active layer ranges from 17. A method for manufacturing a thin film transistor, characterized in that: include: forming a first gate on one side of the substrate; An active layer is formed on a side of the substrate away from the first gate, the active layer comprising a channel, and a first region to be doped and a second region to be doped located on both sides of the channel, and an orthographic projection of the first gate on the substrate at least partially overlaps with an orthographic projection of the second region to be doped on the substrate; forming a second gate on a side of the active layer away from the substrate; Conducting the first region to be doped and the second region to be doped to form a first heavily doped region and a second heavily doped region; A first pole and a second pole are formed on a side of the first gate away from the substrate, the first pole includes a first via connection portion, the first via connection portion is electrically connected to the first heavily doped region; the second pole includes a second via connection portion, the second via connection portion is electrically connected to the second heavily doped region and the first gate, and the orthographic projection of the second via connection portion on the substrate is located within the range of the orthographic projection of the second heavily doped region on the substrate.

18. The manufacturing method according to claim 17, characterized in that: Before forming the first pole and the second pole on the side of the first gate away from the substrate, the method further comprises: forming a via hole in the second heavily doped region; Forming the second electrode includes: the second via hole connecting portion of the second electrode passes through the via hole and is electrically connected to the first gate.

19. A method for manufacturing a thin film transistor, characterized in that: include: forming a first gate on one side of the substrate; An active layer is formed on a side of the substrate away from the first gate, the active layer comprising a channel, and a first region to be doped and a second region to be doped located on both sides of the channel, an orthographic projection of the first gate on the substrate at least partially overlaps with an orthographic projection of the second region to be doped on the substrate, and the second region to be doped comprises a third via connection portion, and the third via connection portion is electrically connected to the first gate; forming a second gate on a side of the active layer away from the substrate; Conducting the first region to be doped and the second region to be doped to form a first heavily doped region and a second heavily doped region; A first pole and a second pole are formed on a side of the first gate away from the substrate, the first pole includes a first via connection portion, the first via connection portion is electrically connected to the first heavily doped region; the second pole includes a second via connection portion, the second via connection portion is electrically connected to the second heavily doped region, and the orthographic projection of the second via connection portion on the substrate is located within the range of the orthographic projection of the second heavily doped region on the substrate.

20. A light-emitting substrate, characterized in that: include: The thin film transistor according to any one of claims 1 to 16.

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