Solar cell and preparation method thereof

Abstract

The invention discloses a solar cell. The solar cell comprises a semiconductor substrate; the semiconductor substrate is provided with two opposite surfaces; the first transparent conducting layer, the metal seed layer and the second transparent conducting layer are sequentially arranged on at least one surface side of the semiconductor substrate in a stacked mode, the second transparent conducting layer is provided with a plurality of grid line grooves arranged at intervals, and the grid line grooves penetrate through the second transparent conducting layer in the stacking direction; and the metal electrode layer is filled in the grid line groove and is electrically connected with the metal seed layer to form an electrode structure together. The invention also discloses a preparation method of the solar cell.

Description

Technical Field

[0001] The present invention relates to the field of solar cells, and in particular to a solar cell and a preparation method thereof. Background Art

[0002] At present, the mainstream transparent conductive film materials for heterojunction battery technology are tin-doped indium oxide (ITO), tungsten-doped indium oxide (IWO) and cerium-doped indium oxide (ICO). However, as a rare metal, indium is expensive, resulting in high costs for heterojunction batteries, which to some extent limits the large-scale mass production of heterojunction battery technology.

[0003] On the other hand, the silver paste consumption of heterojunction cells is much higher than that of other types of solar cells, and the low-temperature silver paste used is imported, which makes the non-silicon cost of heterojunction cells high. The industry has tried to use other transparent conductive and metal materials to replace existing conventional materials, but there are problems with the mismatch with the cells, resulting in reduced conversion efficiency and performance degradation.

[0004] Therefore, designing and developing a new electrode structure that can reduce material costs while improving its conductivity and avoiding reduced efficiency is an urgent problem to be solved in this field. Summary of the invention

[0005] The present invention aims to solve one of the technical problems in the related art to a certain extent. To this end, the present invention provides a method for preparing a solar cell and a solar cell.

[0006] In order to achieve the above object, as a first aspect of the present invention, a solar cell is disclosed, the solar cell comprising:

[0007] A semiconductor substrate; the semiconductor substrate having two opposite surfaces;

[0008] A first transparent conductive layer, a metal seed layer, and a second transparent conductive layer are sequentially stacked on at least one surface side of the semiconductor substrate; the second transparent conductive layer has a plurality of gate line grooves arranged at intervals, and the gate line grooves penetrate the second transparent conductive layer along the stacking direction;

[0009] Metal electrode layer; the metal electrode layer is filled in the gate line groove and is electrically connected to the metal seed layer to form an electrode structure.

[0010] Further,

[0011] The material of the metal seed layer includes: at least one of silver, copper, gold, nickel, tin, titanium, and aluminum;

[0012] The material of the metal electrode layer includes at least one of silver, copper, gold, nickel, tin, titanium and aluminum; wherein,

[0013] The metal activity of the metal seed layer is greater than the metal activity of the metal electrode layer.

[0014] Furthermore, there is a contact interface between the metal electrode layer and the metal seed layer extending along the stacking direction and / or towards the second transparent conductive layer.

[0015] Further, the thickness of the metal seed layer is between 5nm and 80nm;

[0016] The thickness of the first transparent conductive layer is between 20nm and 120nm;

[0017] The thickness of the second transparent conductive layer is between 5 nm and 30 nm.

[0018] Furthermore, the first transparent conductive layer, the metal seed layer, the second transparent conductive layer and the metal electrode layer are respectively disposed on two opposite surface sides of the semiconductor substrate.

[0019] Furthermore, the semiconductor substrate includes: a first doped semiconductor layer, a first intrinsic semiconductor layer, a silicon substrate, a second intrinsic semiconductor layer and a second doped semiconductor layer which are stacked in sequence.

[0020] As a second aspect of the present invention, a method for preparing a solar cell is disclosed, comprising:

[0021] Providing a semiconductor substrate having two opposite surfaces;

[0022] Forming a first transparent conductive layer, a metal seed layer and an initial second transparent conductive layer stacked in sequence on at least one surface side of the semiconductor substrate;

[0023] Patterning the initial second transparent conductive layer to form a second transparent conductive layer having a plurality of gate line grooves; the plurality of gate line grooves are arranged at intervals and penetrate the second transparent conductive layer along a stacking direction;

[0024] A metal electrode layer is formed to fill the gate line grooves; the metal electrode layer is electrically connected to the metal seed layer, and the two together constitute an electrode structure, thereby preparing the above solar cell.

[0025] Furthermore, the step of forming a metal electrode layer that fills the gate line grooves includes:

[0026] The structure obtained after forming the second transparent conductive layer is immersed in a metal salt solution of a preset concentration to perform a chemical and / or electrochemical reaction to grow the metal electrode layer based on the surface of the metal seed layer; wherein,

[0027] The metal ions in the metal salt solution correspond to the metal of the metal electrode layer;

[0028] The metal activity of the metal seed layer is greater than the metal activity of the metal electrode layer.

[0029] Furthermore, the step of patterning the initial second transparent conductive layer to form a second transparent conductive layer having a plurality of gate line grooves includes:

[0030] Forming a patterned mask on the initial second transparent conductive layer, wherein the patterned mask comprises an opening area and a protection area, and the opening area corresponds to a formation position of the gate line groove;

[0031] The initial second transparent conductive layer in the opening area is removed to form a plurality of spaced gate line grooves to obtain the second transparent conductive layer, wherein the opening width of the gate line grooves is between 10 μm and 20 μm; and the thickness of the second transparent conductive layer is between 5 nm and 30 nm.

[0032] Furthermore, the semiconductor substrate comprises: a first doped semiconductor layer, a first intrinsic semiconductor layer, a silicon substrate, a second intrinsic semiconductor layer and a second doped semiconductor layer which are stacked in sequence; the preparation method further comprises:

[0033] The first transparent conductive layer, the metal seed layer, the second transparent conductive layer and the metal electrode layer are respectively formed on the surfaces of the first doped semiconductor layer and the second doped semiconductor layer facing away from the silicon substrate.

[0034] The solar cell structure of the present invention is characterized in that a first transparent conductive layer, a metal seed layer, and a second transparent conductive layer are sequentially stacked on the surface of a semiconductor substrate, and a metal electrode layer is arranged and filled in a plurality of grid line grooves arranged at intervals and penetrating the second transparent conductive layer, and is electrically connected to the metal seed layer exposed from the grid line grooves, thereby forming a multi-level mixed embedded electrode structure. This structure can reduce the thickness of the transparent conductive layer on the one hand, and will not cause a decrease in the conductive performance due to the reduction in the thickness of the transparent conductive layer. The key lies in the use of a metal composite electrode structure embedded between two transparent conductive layers, which can significantly improve the lateral and longitudinal carrier transmission and improve the conductivity.

[0035] On the other hand, the second transparent conductive layer can cover and protect the metal seed layer, and can also protect the side of the metal electrode layer to prevent lateral oxidation or corrosion of the electrode. In addition, embedding this composite metal electrode between the transparent conductive layers not only protects the metal electrode, but also resists oxidation and corrosion, etc., and can significantly increase the contact area between the metal electrode and the transparent conductive layer. Compared with the conventional battery structure, the side wall of the gate line groove structure provides more contact area between the metal and the transparent conductive layer, and the upper and lower surfaces of the metal seed layer are in contact with the transparent conductive layer, which is much higher than the contact area between the conventional metal and the transparent conductive layer. The series resistance is significantly reduced and the conductive performance is further improved.

[0036] In addition, the gate line grooves of the second transparent conductive layer are transformed into metal electrode formation positions of the subsequent metal electrode layer, and the metal electrodes are filled in the gate line grooves, which can improve the morphology of the metal electrodes, make the gate line size more uniform, and make the morphology smoother. In addition, the gate line grooves of the second transparent conductive layer can be super-fine to reduce the line width of the metal electrode, reduce the shielding area, and improve the conversion efficiency.

[0037] The metal electrode layer is electrically connected to the metal seed layer. The upper metal electrode layer further protects the metal seed layer, and can use low-cost metal to replace conventional silver paste as the metal seed layer, and can avoid the oxidation problem of low-cost metal, improve the service life and reliability of solar cells, and significantly reduce costs. In addition, the composite metal structure itself has higher conductivity than a single metal electrode.

[0038] By adopting the solar cell preparation method of the present invention, the usage of indium and precious metal electrodes is significantly reduced, and the non-silicon cost of heterojunction batteries is reduced; the upper metal electrode layer and the second transparent conductive layer protect the lower metal seed layer, reducing the risk of power attenuation caused by oxidation and other problems, and the metal seed layer can use low-cost metal without worrying about its easy oxidation problem; the conductive patterning treatment of the second transparent conductive layer can be transformed into the formation position of the metal electrode of the metal electrode layer, thereby regulating and reducing the metal electrode line width, reducing the shielding area, and improving the battery conversion efficiency; in addition, the gate line groove, the metal electrode layer and the metal seed layer can increase the contact area between the metal electrode and the transparent conductive layer, reduce the series resistance, and improve the short-circuit current, fill factor and battery conversion efficiency of the heterojunction battery.

[0039] These features and advantages of the present invention will be disclosed in detail in the following specific embodiments and drawings. The best embodiments or means of the present invention will be described in detail in conjunction with the drawings, but they are not intended to limit the technical solutions of the present invention. In addition, there are multiple features, elements, and components that appear in each of the following texts and drawings, and different symbols or numbers are marked for convenience, but they all represent components with the same or similar structures or functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The present invention will be further described below in conjunction with the accompanying drawings:

[0041] Figure 1 It is a structural schematic diagram of an implementation mode of a solar cell provided by the present invention;

[0042] Figure 2 is a schematic structural diagram of another embodiment of a solar cell provided by the present invention;

[0043] FIG3( a ) is an enlarged schematic diagram of a partial structure of a solar cell provided by the present invention;

[0044] FIG3( b ) is an enlarged schematic diagram of another embodiment of the local structure of a solar cell provided by the present invention;

[0045] Figure 4 is a flow chart of an implementation method of a solar cell preparation method provided by the present invention;

[0046] Figure 5 This is a structural flow chart of an embodiment of the solar cell preparation method provided by the present invention

[0047] Figure 6 It is a schematic structural diagram of another embodiment of the solar cell provided by the present invention.

[0048] Description of Reference Numerals

[0049] 1: Solar cell; 10: Semiconductor substrate; 11: First transparent conductive layer

[0050] 12: metal seed layer; 13: second transparent conductive layer; 131: gate line groove

[0051] 14: Metal electrode layer; 141: Metal electrode

[0052] 13a: Initial second transparent conductive layer

[0053] 21: silicon substrate; 22a: first intrinsic semiconductor layer; 22b: second intrinsic semiconductor layer; 23: first doped semiconductor layer; 24: second doped semiconductor layer DETAILED DESCRIPTION

[0054] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments in the implementation manner are intended to be used to explain the present invention and should not be construed as limiting the present invention.

[0055] References to "one embodiment" or "an example" or "an example" in this specification mean that a particular feature, structure, or characteristic described in conjunction with the embodiment itself may be included in at least one embodiment disclosed in the present application. The appearance of the phrase "in one embodiment" in various places in the specification does not necessarily refer to the same embodiment.

[0056] It should be pointed out that in the present invention, “inner side” refers to the side close to the initial substrate, and “outer side” refers to the side away from the initial substrate.

[0057] As a first aspect of the present invention, a solar cell is disclosed, such as Figure 1 As shown, the solar cell 1 comprises:

[0058] A semiconductor substrate 10;

[0059] A first transparent conductive layer 11, a metal seed layer 12, and a second transparent conductive layer 13 are stacked on at least one surface of a semiconductor substrate 10, wherein the second transparent conductive layer 13 includes a plurality of gate line grooves 131 arranged at intervals, and the gate line grooves 131 penetrate the second transparent conductive layer 13 along a stacking direction;

[0060] The metal electrode layer 14 is filled in the gate line groove 131 and is electrically connected to the metal seed layer 12 to form an electrode structure. As an optional embodiment, the metal electrode layer 14 includes a plurality of metal electrodes 141, and the plurality of metal electrodes 141 correspond one-to-one to the plurality of gate line grooves 131. The metal electrodes 141 are located in the corresponding gate line grooves 131 and are electrically connected to the metal seed layer 12.

[0061] The solar cell structure of the present invention comprises a first transparent conductive layer, a metal seed layer, and a second transparent conductive layer stacked in sequence on the surface of a semiconductor substrate, and a plurality of metal electrodes of the metal electrode layer are arranged in a plurality of grid line grooves that are arranged at intervals and penetrate the second transparent conductive layer. The metal electrodes correspond to the grid line grooves one by one and are electrically connected to the metal seed layer exposed from the grid line grooves, thereby forming a multi-level hybrid embedded electrode structure.

[0062] On the one hand, the above structure can reduce the thickness of the transparent conductive layer, and the conductivity will not decrease due to the reduction of the thickness of the transparent conductive layer. The key is to use a metal composite electrode structure embedded between the two transparent conductive layers, which can significantly improve the lateral and longitudinal carrier transmission and improve the conductivity. The present invention does not specifically limit the thickness of the first transparent conductive layer and the second transparent conductive layer, which can be consistent with the thickness of the conventional transparent conductive layer, or further reduce its thickness. Preferably, the thickness of the first transparent conductive layer is between 20nm and 120nm, and the thickness of the second transparent conductive layer is between 5nm and 30nm. The thickness of the conventional transparent conductive layer is generally above 100nm. The present invention divides the transparent conductive layer into two layers and designs and embeds a metal composite electrode between them, which can significantly reduce its thickness. As a further preference, the sum of the thickness of the first transparent conductive layer, the metal seed layer and the second transparent conductive layer is between 30nm and 140nm. The present invention does not specifically limit the material of the transparent conductive layer, as long as it meets the transparent conductivity. Preferably, the first transparent conductive layer and the second transparent conductive layer include at least one of ITO, IWO, ICO, and AZO. In order to ensure light transmittance while satisfying electrical properties, preferably, the thickness of the metal seed layer is between 5 nm and 80 nm.

[0063] On the other hand, the second transparent conductive layer can cover and protect the metal seed layer, and can also protect the side of the metal electrode layer to prevent lateral oxidation or corrosion of the electrode. In addition, embedding this composite metal electrode between the transparent conductive layers not only protects the metal electrode, but also resists oxidation and corrosion, etc., and can significantly increase the contact area between the metal electrode and the transparent conductive layer. Compared with the conventional battery structure, the side wall of the gate line groove structure provides more metal and TCO contact area, and the upper and lower surfaces of the metal seed layer are in contact with the transparent conductive layer, which is much higher than the contact area between the conventional metal and the transparent conductive layer. The series resistance is significantly reduced and the conductive performance is further improved.

[0064] The metal electrode layer is electrically connected to the metal seed layer, and the upper metal electrode layer further protects the metal seed layer, and can use low-cost metal to replace conventional silver paste as the metal seed layer, and can avoid the oxidation problem of low-cost metal, improve the service life and reliability of solar cells, and significantly reduce costs. In addition, the composite metal structure itself has a higher electrical conductivity than a single metal electrode. Preferably, the metal seed layer and the metal electrode layer include at least one of silver, copper, gold, nickel, tin, titanium, and aluminum. Preferably, the metal seed layer can be made of copper, which has the same conductivity as silver but lower cost, but copper is easily oxidized. The structure of the present invention can effectively avoid copper oxidation. The metal electrode layer can be made of silver, which has stronger oxidation resistance and is suitable as the upper metal electrode layer. In addition, copper, as the first layer of metal, has a higher light transmittance, thereby increasing the light absorption of the battery.

[0065] In some embodiments, the activity of the metal in the metal seed layer 12 is greater than the activity of the metal in the metal electrode layer 14, so that the metal electrode layer 14 is formed in situ on the surface of the metal seed layer 12 through chemical and / or electrochemical reactions. The advantage of this method of forming a metal electrode layer is that the metal electrode layer is formed and grown in situ, can be firmly combined with the metal seed layer, improves adhesion, and is in full contact with the metal seed layer, reducing the pores and defects at the interface between the two metal layers, increasing the contact area, and thus improving the electrical conductivity. The present invention does not specifically limit the metal material. Preferably, the metal seed layer and the metal electrode layer include at least one of silver, copper, gold, nickel, tin, titanium, and aluminum.

[0066] In addition, the width of the metal electrode formed in situ is consistent with the width of the gate line groove. The gate line groove of the second transparent conductive layer is transformed into the position where the metal electrode of the subsequent metal electrode layer is formed and grown in situ, and the metal electrode is formed in situ and filled in the gate line groove. The gate line groove can improve the morphology of the metal electrode, make the gate line size more uniform, and the morphology is flat. The gate line groove of the second transparent conductive layer can be thinned to reduce the line width of the metal electrode, reduce the shielding area, and improve the conversion efficiency. Preferably, the width of the gate line groove is between 10μm and 15μm, and the corresponding metal electrode width is also between 10μm and 15μm, which is much lower than the metal electrode line width (more than 25μm) in the existing metallization technology.

[0067] The present invention does not specifically limit the thickness of the metal electrode. For example, the height of the metal electrode is the same as the height of the second transparent conductive layer. For another example, the height of the metal electrode is higher than the height of the second transparent conductive layer. In order to allow the height of the sidewall of the gate line groove to be sufficient to protect the metal electrode and have a sufficient contact area, preferably, the height of the surface of the second transparent conductive layer away from the semiconductor substrate matches the height of the surface of the metal electrode away from the semiconductor substrate.

[0068] In some embodiments, as shown in FIG. 3(a) and FIG. 3(b), the metal electrode layer undergoes a chemical reaction with the metal seed layer, such as a replacement reaction, so that the metal of the metal seed layer is consumed. In this case, the thickness of the metal seed layer corresponding to the gate line groove is less than the thickness of the metal seed layer covered by the second transparent conductive layer, which makes the metal electrode layer and the metal seed layer have a contact interface extending along the stacking direction and / or toward the second transparent conductive layer, further increasing the contact area between the metals, and improving the adhesion and conductivity between the two metals. In other embodiments, when forming the gate line groove, the metal seed layer can be partially etched in a small amount, which can also increase the contact area between the metals.

[0069] In some embodiments, after the electrode structure is formed, a sintering process is performed. Sintering can reduce the pores of the metal, make the metal denser, and further increase the adhesion and conductivity.

[0070] The present invention does not impose any special restrictions on the position of the electrode structure, which can be a top electrode, a bottom electrode, or a top-bottom electrode. As an optional embodiment, the solar cell provided by the present invention is as follows: Figure 2 As shown, the solar cell 1 is provided with a first transparent conductive layer 11 , a metal seed layer 12 , a second transparent conductive layer 13 and a metal electrode layer 14 on two opposite surfaces of a semiconductor substrate 10 .

[0071] As a second aspect of the present invention, a method for preparing a solar cell is disclosed, such as Figure 4 As shown, the steps include:

[0072] Step S100, providing a semiconductor substrate, wherein the semiconductor substrate has two opposite surfaces;

[0073] Step S110, forming a first transparent conductive layer, a metal seed layer and an initial second transparent conductive layer stacked in sequence on at least one surface side of the semiconductor substrate;

[0074] Step S120, patterning the initial second transparent conductive layer to form a second transparent conductive layer having a plurality of gate line grooves, wherein the plurality of gate line grooves are arranged at intervals and penetrate the second transparent conductive layer along a stacking direction;

[0075] Step S130 , forming a metal electrode layer that fills the gate line grooves, the metal electrode layer is electrically connected to the metal seed layer, and the two together constitute an electrode structure, thereby preparing the above-mentioned solar cell.

[0076] In step S100, the present invention does not specifically limit the type of semiconductor substrate, and it only needs to satisfy that it is a solar cell without electrode preparation. For example, the semiconductor substrate can be a tunnel oxide passivated contact cell (TOPCon), an intrinsic thin film heterojunction cell (HJT), an emitter and back passivated cell (PERC) and is not limited to a crystalline silicon cell, but can also be other types of cells and stacked cells using the above cells, such as perovskite stacked cells, etc. The present invention does not specifically limit the method of obtaining the semiconductor substrate, for example, it can be obtained by purchasing. For another example, it can be obtained by a preparation method.

[0077] For ease of understanding, the structural flow chart of the solar cell preparation method of the present invention is as follows Figure 5 shown.

[0078] In step S110, the electrode structure of the present invention can be prepared on the front and / or back of the battery. As an optional embodiment, a first transparent conductive layer 11, a metal seed layer 12, an initial second transparent conductive layer 13a and a metal electrode layer are formed on the front and back surfaces of the semiconductor substrate 10. Figure 5 shown.

[0079] In step S120, the present invention does not specifically limit how to form the gate line groove. For example, the gate line groove can be formed by selectively etching the initial second transparent conductive layer by laser burning, or by selectively removing the initial second transparent conductive layer by setting a graphic mask plate to form the gate line groove.

[0080] Preferably, patterning the initial second transparent conductive layer to form a second transparent conductive layer having a plurality of gate line grooves comprises:

[0081] S121, forming a patterned mask on the initial second transparent conductive layer, wherein the patterned mask includes an opening area and a protection area, the opening area corresponds to the position of the gate line groove area, and the width of the opening area is between 10μm and 20μm. Specifically, the opening area of ​​the patterned mask corresponds to the formation area of ​​the gate line. It can be understood that such a setting transforms the unblocked area (i.e., the opening area) of the patterned mask into the subsequent gate line formation position, and the morphology and width of the gate line are affected by the shape and width of the opening area of ​​the patterned mask. In some embodiments, the patterned mask is formed by screen printing, and the screen used is completely different from the screen for conventionally printed metal electrodes, and its opening area and non-opening area are different from the conventional screen. The patterned mask is completely opposite to the patterned mask, which makes it unnecessary to worry about the slurry being blocked by the screen during the printing process, because the unopened area of ​​the screen provided in the embodiment of the present invention corresponds to the formation position of the gate line, thereby reducing the difficulty of printing, having a large process window and being easy to operate. The width of the unopened area of ​​the screen can be super-fine, thereby further refining the width of the opening area of ​​the patterned mask. Preferably, the width of the opening area of ​​the patterned mask is between 10 μm and 20 μm, so that the width of the metal electrode formed is also between 10 μm and 20 μm, which is much lower than the electrode width of conventional screen printing (more than 25 μm). In addition, the acid ink is easier to print and form than the metal paste;

[0082] The present invention does not specifically limit the formation method of the patterned mask. The patterned mask can be formed on the initial second transparent conductive layer by at least one of screen printing ink, spraying ink, and photoresist development and exposure. Preferably, the patterned mask is formed on the initial second transparent conductive layer by screen printing acid ink. This method has lower cost, higher printing accuracy, and smaller line width.

[0083] S122, removing the initial second transparent conductive layer in the opening area to form a plurality of spaced gate line grooves to obtain a second transparent conductive layer. Specifically, the second transparent conductive layer can be removed by at least one of wet etching, dry etching, and laser etching. The transparent conductive layer is generally a metal oxide. In order to make it easier to remove, it is preferably removed by etching with an acidic solution. The acidic solution can be at least one of hydrochloric acid, sulfuric acid, nitric acid, phosphoric acid, and hydrofluoric acid. The concentration is between 5wt% and 20wt%, the corrosion temperature is 20 to 50°C, and the corrosion time is in the range of 30s to 6000s. The method of removing the initial second transparent conductive layer by acid corrosion has lower cost and high work efficiency. In addition, the acid has poor isotropy on TCO (Transparent Conductive Oxides) materials, its lateral corrosion distance is short, and the gate line groove size accuracy is higher.

[0084] In some embodiments, a patterned acidic ink is used to form an initial second transparent conductive layer. In order to facilitate the subsequent removal of the acidic ink, an alkaline solution is used for removal. The alkaline solution can be at least one of KOH, NaOH, and NH4OH, and the concentration is between 3wt% and 12wt%. Hydrogen peroxide can also be used to assist in removing the acidic ink. The concentration of hydrogen peroxide is between 0.5wt% and 6wt%, the removal temperature is between 20 and 60°C, and the removal time is between 50s and 500s.

[0085] In step S130, the present invention does not specifically limit how the metal electrode layer is formed, and the metal electrode layer can be formed by at least one of chemical plating, electroplating, laser transfer, and screen printing. Preferably, chemical plating or electroplating is used as an optional implementation method, and the resulting structure after forming the second transparent conductive layer is immersed in a metal salt solution of a preset concentration, and a chemical and / or electrochemical reaction is performed within a set time to grow a metal electrode layer based on the surface of the metal seed layer, wherein the metal ions in the metal salt solution correspond to the metal in the metal electrode layer. Preferably, the concentration is set between 0.05 mol / L and 5 mol / L, and the set time is the reaction time, which is determined by the height of the metal electrode layer and can be adjusted according to specific performance requirements. For example, in order to allow the height of the sidewall of the gate line groove to be sufficient to protect the metal electrode and have a sufficient contact area, preferably, the reaction time is set to match the height of the metal electrode with the height of the second transparent conductive layer.

[0086] In order to increase the reaction rate, the pH of the solution may be adjusted, or an electroplating device may be added to perform a joint reaction of chemical plating and electroplating to increase the generation rate and content of the reaction product.

[0087] In order to obtain the structural advantage of in-situ formation, the metal activity of the metal seed layer is made greater than the metal activity of the metal electrode layer, so that the metal salt solution can undergo a chemical replacement reaction with the metal seed layer. In some embodiments, the metal seed layer is a copper layer, and the metal salt solution is a silver nitrate solution. Where the copper contacts the silver nitrate solution, the silver layer becomes thicker and thicker as time goes by until the metal copper layer in the electrode area is completely wrapped, thereby increasing the contact area and the adhesion of the silver layer, and at the same time, the copper layer can be completely and comprehensively protected from oxidation. In addition, since the metal salt solution undergoes a chemical reaction with the metal seed layer, such as a replacement reaction, so that the metal of the metal seed layer is consumed, in this case, the thickness of the metal seed layer at the gate line groove is less than the thickness of the metal seed layer at the part covered by the second transparent conductive layer, which makes the metal electrode layer and the metal seed layer have a contact interface extending along the stacking direction and / or toward the second transparent conductive layer, further increasing the contact area between the metals, and improving the adhesion and conductivity. In other embodiments, when forming the gate line groove, the metal seed layer can be partially etched in a small amount, which can also increase the contact area between the metals.

[0088] In addition, the conventional screen printing preparation method cannot further reduce the line width, while this in-situ formation of the metal electrode can make the width of the metal electrode consistent with the width of the gate line groove, thereby reducing the line width of the gate line groove through a more sophisticated preparation method, thereby reducing the width of the metal electrode accordingly, reducing the shielding area, and improving the conversion efficiency. Preferably, the width of the gate line groove is between 10μm and 15μm, and the corresponding metal electrode width is also between 10μm and 15μm, which is much lower than the metal electrode line width (above 25μm) in the existing metallization technology.

[0089] In some embodiments, forming a metal electrode layer in the gate line groove of the second transparent conductive layer further comprises:

[0090] The metal electrode layer is sintered to make the metal electrode layer and the metal seed layer more compact. Sintering can reduce the pores of the metal, making the metal more compact, and further increasing the adhesion and conductivity.

[0091] The present invention does not impose any special restrictions on the position of the electrode structure, which may be a top electrode, a bottom electrode, or both a top and a bottom electrode. In some embodiments, a first transparent conductive layer, a metal seed layer, a second transparent conductive layer, and a metal electrode layer are formed on two opposite surfaces of a semiconductor substrate to form a solar cell having electrodes of the above structure on both the front and back sides.

[0092] The present invention will be further explained below in conjunction with the embodiments.

[0093] Example 1

[0094] S1. Providing a semiconductor substrate, wherein the specific steps of providing the semiconductor substrate include:

[0095] Provide N-type silicon substrates with chain or tubular phosphorus diffusion and doping treatment, size 182*105mm, and texturing treatment on silicon wafers to form double-sided pyramid structures. The texturing agent includes 1.5wt% NaOH solution and 0.5wt% texturing additives. The temperature is 82℃, the texturing time is 450s, and the additive is Shichuang TS53V01. After texturing treatment, the weight of the silicon substrate is reduced by 0.4g, the reflectivity is 10%, the pyramid side is 1.7μm, the height is 1.6μm, and the specific surface area is 1.6m 2 / g, the velvet surface of the silicon substrate has 250,000 pyramids per unit area / mm 2 ;

[0096] The first intrinsic semiconductor layer is deposited on the front surface and the second intrinsic semiconductor layer is deposited on the back surface by chemical vapor deposition equipment after the texturing and cleaning. The specific process is to use RF radio frequency power to deposit intrinsic amorphous silicon and hydrogen-rich amorphous silicon in sequence, which effectively improves the passivation effect. The total thickness of the first intrinsic semiconductor layer on the front side is 3nm, and the total thickness of the second intrinsic semiconductor layer on the back side is 5nm.

[0097] A first process gas is introduced to chemically vapor deposit an N-type microcrystalline silicon oxide layer as a first doped semiconductor layer on the surface of the first intrinsic semiconductor layer on the front side using a VHF very high frequency power supply, wherein the process temperature is set to 190°C and the power density of the power supply is 200mW·cm -2 , the process pressure is 5mbar, the first process gas includes CO2, H2, PH3 and SiH4, wherein the gas flow ratio of CO2, H2, PH3 and SiH4 is 0.6:200:0.036:1, and the film thickness of the N-type microcrystalline silicon oxide layer is 15nm; the second process gas is introduced to chemically vapor deposit the second intrinsic semiconductor layer on the back of the passivated silicon wafer to form a P-type microcrystalline silicon oxide layer as the second doped semiconductor layer, wherein the process temperature is set to 170°C, and the power density of the power supply is 250mW·cm -2 , process pressure 7mbar, the second process gas includes H2, B2H6 and SiH4, wherein the gas flow ratio of H2, B2H6 and SiH4 is 200:0.005:1, and the film thickness of the P-type doped microcrystalline layer is 25nm;

[0098] S2, forming a first transparent conductive layer, a metal seed layer and an initial second transparent conductive layer on the surface of the semiconductor substrate, specifically comprising:

[0099] A third process gas is introduced to stack a first transparent conductive layer, a metal seed layer, and an initial second transparent conductive layer on the front and back surfaces of the microcrystalline silicon oxide film in a direction away from the silicon substrate, wherein the first transparent conductive layer includes at least one of ITO, IWO, ICO, and AZO, and has a thickness of 60 nm, the metal seed layer is a base metal film, which can be a metal with good conductivity such as copper, aluminum, and nickel, and has a thickness of 20 nm, the initial second transparent conductive layer includes at least one of ITO, IWO, ICO, and AZO, and has a thickness of 10 nm, the process temperature is set to 180° C., the power supply is 10 KW, the process pressure is 0.6 pa, and the process gas includes Ar, O2, and H2, wherein the flow ratio of Ar, O2, and H2 is 1:0.04:0.02;

[0100] S3, patterning the initial second transparent conductive layer to form a plurality of spaced-apart gate line grooves, wherein the gate line grooves penetrate the initial second transparent conductive layer along the stacking direction to form a second transparent conductive layer, and obtaining a first substrate, specifically comprising:

[0101] Acid ink is screen-printed on the surface of the initial second transparent conductive layer, with a printing height of 10 μm, screen parameters are conventional screen parameters, and the printing pattern corresponds to the metal electrode pattern, that is, the opening area of ​​the printing screen is the non-grid line area, the non-opening area of ​​the printing screen corresponds to the grid line formation area, and the width of the non-opening area is 10-15 μm, which is much lower than the metal electrode line width (more than 25 μm) of the existing metallization technology;

[0102] The printed silicon wafer is placed in an inorganic acid solution to selectively remove the initial second transparent conductive layer not covered by the ink. The etching solution is hydrochloric acid with a mass concentration of 15wt%, and the treatment time is 300s at room temperature. The industrial camera confirms that the initial second transparent conductive layer not covered by the ink is etched cleanly.

[0103] S4, forming a metal electrode layer in the gate line groove of the second transparent conductive layer, wherein the metal electrode layer includes a plurality of metal electrodes, the plurality of metal electrodes correspond to the plurality of gate line grooves one by one, and the metal electrodes are located in the corresponding gate line grooves and are electrically connected to the metal seed layer, to prepare a solar cell, specifically, including:

[0104] The etched silicon wafer is placed in a 0.1 mol / L silver nitrate solution for replacement reaction, the metal seed layer is used as an anode, and an electrochemical device is used to form a plurality of metal electrodes at the gate line groove, so that the thickness of the metal seed layer is close to the thickness of the metal seed layer at the portion covered by the second transparent conductive layer, thereby preparing a metal electrode layer;

[0105] The above silicon wafer was placed in an alkaline mixed solution to remove the ink, wherein the alkaline mixed solution had a KOH concentration of 6wt% and a hydrogen peroxide concentration of 2.7wt%, and was treated at 50°C for 150s. After standard sintering (210°C, 30min) and light injection (210°C, 70s), a solar cell 1 was finally prepared, having a structure as shown in FIG. Figure 6 As shown, it includes, stacked in sequence from top to bottom: a second transparent conductive layer 13 and a metal electrode layer 14, a metal seed layer 12, a first transparent conductive layer 11, a first doped semiconductor layer 23, a first intrinsic semiconductor layer 22a, a silicon substrate 21, a second intrinsic semiconductor layer 22b, a second doped semiconductor layer 24, a first transparent conductive layer 11, a metal seed layer 12, a metal electrode layer 14 and a second transparent conductive layer 13.

[0106] Comparative Example 1

[0107] The solar cell is prepared by the same preparation method as in Example 1, except that a transparent conductive layer and a metal electrode are stacked on the surface of the semiconductor substrate, specifically comprising:

[0108] A transparent conductive layer is prepared by magnetron sputtering on the front and back surfaces of the microcrystalline silicon oxide film in a direction away from the silicon substrate, the process temperature is set to 180°C, the power supply power is 10kW, the process pressure is 0.6pa, the process gas includes Ar, O2, H2, wherein the flow ratio of Ar, O2 and H2 is 1:0.04:0.02, and the thickness of the transparent conductive layer is 90nm;

[0109] A metal electrode was prepared on the surface of the transparent conductive layer by screen printing, curing and light injection to obtain a conventional solar cell with a line width of 35 μm.

[0110] Comparative Example 2

[0111] The solar cell was prepared by the same preparation method as in Comparative Example 1, except that the metal electrode used a silver-clad copper structure with a silver content of 54%.

[0112] Test Case

[0113] The embodiments and comparative examples were tested using a Halm high-precision IV tester according to the STC standard. The electrical performance test items included photoelectric conversion efficiency (Eff), open circuit voltage (Uoc), short circuit current (Isc), and fill factor (FF). The test conditions were: solar irradiance was 1000W / m 2 , the spectrum is AM1.5 (atmospheric mass), the temperature of the solar cell is 25°C, and the test results are shown in Table 1. It can be obtained that the solar cell prepared by the preparation method of the present invention has better short-circuit current, fill factor and power conversion efficiency.

[0114] Table 1

[0115] Battery Eff Uoc / V Isc / A FF Example 1 26.22 0.754 7.72 86.10 Comparative Example 1 26.10 0.755 7.68 86.00 Comparative Example 2 26.09 0.755 7.69 85.92

[0116] It is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Those skilled in the art should understand that the present invention includes but is not limited to the contents described in the drawings and the above specific embodiments. Any modification that does not deviate from the functional and structural principles of the present invention will be included in the scope of the claims.

Claims

1. A solar cell, characterized in that: The solar cell comprises: A semiconductor substrate having two opposite surfaces; A first transparent conductive layer, a metal seed layer, and a second transparent conductive layer are sequentially stacked on at least one surface side of the semiconductor substrate, wherein the second transparent conductive layer has a plurality of gate line grooves arranged at intervals, and the gate line grooves penetrate the second transparent conductive layer along a stacking direction; A metal electrode layer is filled in the gate line groove and is electrically connected to the metal seed layer to form an electrode structure.

2. The solar cell according to claim 1, characterized in that: The material of the metal seed layer includes: at least one of silver, copper, gold, nickel, tin, titanium, and aluminum; The material of the metal electrode layer includes at least one of silver, copper, gold, nickel, tin, titanium and aluminum; wherein, The metal activity of the metal seed layer is greater than the metal activity of the metal electrode layer.

3. The solar cell according to claim 2, characterized in that: There is a contact interface between the metal electrode layer and the metal seed layer extending along the stacking direction and / or toward the second transparent conductive layer.

4. The solar cell according to any one of claims 1 to 3, characterized in that: The first transparent conductive layer, the metal seed layer, the second transparent conductive layer and the metal electrode layer are respectively disposed on two opposite surface sides of the semiconductor substrate.

5. The solar cell according to any one of claims 1 to 3, characterized in that: The thickness of the metal seed layer is between 5nm and 80nm; The thickness of the first transparent conductive layer is between 20nm and 120nm; The thickness of the second transparent conductive layer is between 5 nm and 30 nm.

6. The solar cell according to any one of claims 1 to 3, characterized in that: The semiconductor substrate comprises: a first doped semiconductor layer, a first intrinsic semiconductor layer, a silicon substrate, a second intrinsic semiconductor layer and a second doped semiconductor layer which are stacked in sequence.

7. A method for preparing a solar cell, characterized in that: include: Providing a semiconductor substrate having two opposite surfaces; Forming a first transparent conductive layer, a metal seed layer and an initial second transparent conductive layer stacked in sequence on at least one surface side of the semiconductor substrate; Patterning the initial second transparent conductive layer to form a second transparent conductive layer having a plurality of gate line grooves, wherein the plurality of gate line grooves are arranged at intervals and penetrate the second transparent conductive layer along a stacking direction; A metal electrode layer is formed to fill the gate line grooves. The metal electrode layer is electrically connected to the metal seed layer, and the two together form an electrode structure.

8. The preparation method according to claim 7, characterized in that: The step of forming a metal electrode layer that fills the gate line groove comprises: The structure obtained after forming the second transparent conductive layer is immersed in a metal salt solution of a preset concentration to perform a chemical and / or electrochemical reaction to grow the metal electrode layer based on the surface of the metal seed layer; wherein, The metal ions in the metal salt solution correspond to the metal of the metal electrode layer; The metal activity of the metal seed layer is greater than the metal activity of the metal electrode layer.

9. The preparation method according to claim 7, characterized in that: The step of patterning the initial second transparent conductive layer to form a second transparent conductive layer having a plurality of gate line grooves comprises: Forming a patterned mask on the initial second transparent conductive layer, wherein the patterned mask comprises an opening area and a protection area, and the opening area corresponds to a formation position of the gate line groove; The initial second transparent conductive layer in the opening area is removed to form a plurality of gate line grooves arranged at intervals to obtain the second transparent conductive layer; wherein, The opening width of the gate line groove is between 10 μm and 20 μm; The thickness of the second transparent conductive layer is between 5 nm and 30 nm.

10. The preparation method according to any one of claims 7 to 9, characterized in that: The semiconductor substrate comprises: a first doped semiconductor layer, a first intrinsic semiconductor layer, a silicon substrate, a second intrinsic semiconductor layer, and a second doped semiconductor layer which are stacked in sequence; the preparation method further comprises: The first transparent conductive layer, the metal seed layer, the second transparent conductive layer and the metal electrode layer are respectively formed on the surfaces of the first doped semiconductor layer and the second doped semiconductor layer facing away from the silicon substrate.

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