Wafer carrying table

Abstract

A wafer mounting table 10 includes an upper base 20, a lower base 30, a through hole 36, a screw hole 24, and a screw member 50. The upper substrate (20) is provided with a ceramic substrate (21) having a built-in electrode (22), and has a wafer placement surface (21a) on the upper surface of the ceramic substrate (21). The lower substrate (30) is disposed on a surface of the upper substrate (20) on the opposite side from the wafer placement surface (21a), and is provided with a refrigerant flow channel groove (34) that constitutes a side wall and a bottom of the refrigerant flow channel (32). The through hole 36 passes through the lower base 30 in the vertical direction so as to intersect the refrigerant flow path 32. The screw hole (24) is provided at a position facing the through hole (36) on the lower surface of the upper base material (20). The screw member (50) is inserted into the through hole (36) from the lower surface of the lower base material (30) and is screwed into the screw hole (24). The refrigerant is configured so as not to leak from the through-hole 36 to the lower surface of the lower base material 30.

Description

Technical Field

[0001] The present invention relates to a wafer loading platform. Background Art

[0002] Conventionally, there is known a wafer stage, which includes: a ceramic substrate having a wafer placement surface and having electrodes built therein; and a metal plate disposed on the surface of the ceramic substrate opposite to the wafer placement surface. In Patent Document 1, based on the above-mentioned wafer placement stage, a plurality of through holes are provided in the metal plate, and screw holes are provided at positions on the lower surface of the ceramic substrate that are opposite to the through holes, and screw members are inserted into the through holes from the lower surface of the metal plate and screwed into the screw holes, so that the ceramic substrate and the metal plate are fastened.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: International Publication No. 2018 / 038044 Pamphlet Summary of the invention

[0006] In the wafer placing table of the above structure, it is considered to set a coolant flow path on the metal plate to improve the cooling efficiency of the wafer. In this case, when the coolant flow path is set in a way to avoid the screw component, the design freedom of the coolant flow path is reduced, and the part where the screw component is set is not easy to be cooled. Therefore, there is a problem that it is difficult to set the in-plane temperature distribution of the wafer to the desired temperature distribution.

[0007] The present invention has been made to solve the above-mentioned problems, and its main object is to easily set the in-plane temperature distribution of a wafer to a desired temperature distribution based on a wafer placing table in which an upper substrate and a lower substrate are fastened by screw members.

[0008] [1] The wafer stage of the present invention comprises:

[0009] An upper substrate, the upper substrate comprising a ceramic substrate having electrodes built therein, and a wafer placement surface on an upper surface of the ceramic substrate;

[0010] a lower substrate, which is arranged on a surface of the upper substrate opposite to the wafer placement surface and has a coolant flow path for circulating a coolant or a coolant flow path groove constituting a side wall and a bottom of the coolant flow path;

[0011] a through hole penetrating the lower substrate in a vertical direction in a manner intersecting the coolant flow path or the coolant flow path groove;

[0012] a screw hole disposed on the lower surface of the upper substrate at a position opposite to the through hole;

[0013] a threaded component, the threaded component being inserted into the through hole from the lower surface of the lower substrate and being screwed into the screw hole; and

[0014] A refrigerant leakage preventing member prevents the refrigerant from leaking from the through hole into which the screw member is inserted to the lower surface of the lower base.

[0015] In the wafer carrier, the upper substrate and the lower substrate are fastened by a threaded component. The lower substrate is provided with a coolant flow path or a coolant flow path groove. The threaded component is inserted from the lower surface of the lower substrate into a through hole that penetrates the lower substrate in the vertical direction in a manner that intersects with the coolant flow path or the coolant flow path groove and is screwed into the screw hole of the upper substrate. In addition, a coolant leakage component is utilized to prevent the coolant from leaking out of the through hole into which the threaded component is inserted. Accordingly, it is not necessary to bypass the threaded component to set the coolant flow path, and therefore, the design freedom of the coolant flow path or the coolant flow path groove is improved. In addition, since the threaded component is cooled by the coolant, the portion where the threaded component is provided is also easily cooled. As a result, according to the wafer carrier of the present invention, it is easy to set the in-plane temperature distribution of the wafer to a desired temperature distribution.

[0016] It should be noted that in this specification, up and down, left and right, front and back, etc. are sometimes used to explain the present invention, but up and down, left and right, front and back are only relative positional relationships. Therefore, when the orientation of the wafer stage is changed, up and down may become left and right or left and right may become up and down, and such a situation is also included in the technical scope of the present invention.

[0017] [2] In the chip carrier of the present invention (the chip carrier described in [1] above), the lower substrate may have the coolant flow path groove, and the upper substrate may have: the ceramic substrate; a top substrate, which is arranged on the lower side of the ceramic substrate and constitutes the top of the coolant flow path; and a metal bonding layer, which bonds the ceramic substrate and the top substrate.

[0018] [3] In the wafer stage of the present invention (the wafer stage described in [2] above), the absolute value of the difference in linear thermal expansion coefficient between the top substrate and the ceramic substrate at 40 to 400° C. may be 1.5×10 -6 / K or less. As a result, the thermal expansion difference between the ceramic substrate and the top substrate is small, so that the warping and breakage of the upper substrate caused by thermal stress can be suppressed. It should be noted that in this specification, the linear thermal expansion coefficient obtained by measuring the length at 40°C and 400°C is referred to as the linear thermal expansion coefficient of 40 to 400°C.

[0019] [4] In the wafer stage of the present invention (the wafer stage described in [2] or [3] above), the top substrate may be made of a composite material of metal and ceramic. The composite material of metal and ceramic can reduce the absolute value of the difference in linear thermal expansion coefficient between the composite material and the ceramic substrate, and has higher toughness than ceramic materials, so it is not easily damaged even if thermal stress is generated.

[0020] [5] In the wafer stage of the present invention (the wafer stage described in any one of [1] to [4] above), a heat sink may be disposed between the lower surface of the upper substrate and the upper surface of the lower substrate. Accordingly, the upper substrate and the lower substrate are fastened by a screw member so that the heat sink is firmly attached to the upper substrate and the lower substrate, so that the heat of the upper substrate is easily and quickly conducted to the lower substrate. As a result, the efficiency of cooling the wafer is improved.

[0021] [6] In the wafer stage of the present invention (the wafer stage described in any one of [1] to [5] above), the lower substrate may be made of an easily machinable material. Thus, a coolant flow path or a coolant flow path groove can be easily formed in the lower substrate, thereby reducing the processing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a longitudinal cross-sectional view of the wafer stage 10 installed in the chamber 94 .

[0023] Figure 2 yes Figure 1 A partial enlarged view of .

[0024] Figure 3 It is a plan view of the wafer stage 10 .

[0025] Figure 4 This is a cross-sectional view when a cut surface of the wafer stage 10 cut between the upper base 20 and the lower base 30 is viewed from above.

[0026] Figure 5 It is a manufacturing process diagram of the wafer stage 10 (manufacturing process of the upper substrate 20 ).

[0027] Figure 6 It is a manufacturing process diagram of the wafer stage 10 (manufacturing process of the lower substrate 30 ).

[0028] Figure 7 It is a manufacturing process diagram of the wafer stage 10 (assembly process of the wafer stage 10).

[0029] Figure 8 It is a longitudinal cross-sectional view when the screw member 50 is sealed with the O-ring 53 .

[0030] Fig. 9It is a longitudinal cross-sectional view when the screw member 50 is sealed with the O-ring 58 .

[0031] Fig.10 It is a longitudinal cross-sectional view of the wafer placement table 110 .

[0032] Fig.11 It is a longitudinal cross-sectional view of the wafer placement table 210 .

[0033] Fig.12 It is an explanatory diagram showing a portion of the refrigerant flow path 32 where the screw member 50 exists. DETAILED DESCRIPTION

[0034] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Figure 1 1 is a longitudinal cross-sectional view of the wafer stage 10 provided in the chamber 94 (a cross-sectional view when cut along a plane including the central axis of the wafer stage 10). Figure 2 yes Figure 1 A partial enlarged view of Figure 3 is a plan view of the wafer stage 10, Figure 4 This is a cross-sectional view when the wafer stage 10 is cut between the upper substrate 20 and the lower substrate 30 as viewed from above. In the present specification, "to" indicating a numerical range is used to mean that the numerical values ​​described before and after it are included as the lower limit and the upper limit.

[0035] The wafer stage 10 is a component used to perform CVD, etching, etc. on the wafer W using plasma, and is fixed to a setting plate 96 provided inside a chamber 94 for semiconductor processes. The wafer stage 10 includes an upper substrate 20, a lower substrate 30, a heat sink 40, and a screw member 50.

[0036] The upper substrate 20 includes: a ceramic substrate 21; a top substrate 23 disposed on the lower side of the ceramic substrate 21 and constituting the top of the coolant flow path 32; and a metal bonding layer 25 bonding the ceramic substrate 21 and the top substrate 23. In consideration of strength, the thickness of the upper substrate 20 is preferably 8 mm or more and 10 mm or more; in consideration of cooling efficiency, the thickness is preferably 25 mm or less.

[0037] The ceramic substrate 21 has a circular wafer loading surface 21a. A wafer W is loaded on the wafer loading surface 21a. The ceramic substrate 21 is formed of a ceramic material represented by aluminum oxide, aluminum nitride, etc. The ceramic substrate 21 has a built-in wafer adsorption electrode 22 on the side close to the wafer loading surface 21a. The wafer adsorption electrode 22 is formed of a material containing, for example, W, Mo, WC, MoC, etc. The wafer adsorption electrode 22 is a disk-shaped or mesh-shaped monopolar electrostatic electrode. The layer of the ceramic substrate 21 that is above the wafer adsorption electrode 22 functions as a dielectric layer. The wafer adsorption DC power supply 52 is connected to the wafer adsorption electrode 22 via a power supply terminal 54. The power supply terminal 54 is configured to pass through an insulating tube 55 arranged in a hole that penetrates the lower substrate 30, the top substrate 23, and the metal bonding layer 25 in the up-down direction and reach the wafer adsorption electrode 22 from the lower surface of the ceramic substrate 21. A low-pass filter (LPF) 57 is provided between the wafer adsorption DC power supply 52 and the wafer adsorption electrode 22 .

[0038] The top substrate 23 is a circular plate that is slightly larger than the ceramic substrate 21 and is made of a conductive material. As conductive materials, for example, composite materials, metals, etc. can be cited. As composite materials, composite materials of metals and ceramics can be cited. As composite materials of metals and ceramics, metal matrix composites (MMC) and ceramic matrix composites (CMC) can be cited. Specific examples of the above composite materials include materials containing Si, SiC and Ti, and materials obtained by impregnating a SiC porous body with Al and / or Si. The material containing Si, SiC and Ti is referred to as SiSiCTi, the material obtained by impregnating a SiC porous body with Al is referred to as AlSiC, and the material obtained by impregnating a SiC porous body is referred to as SiSiC. As metals, Mo and the like can be cited. The absolute value of the difference in linear thermal expansion coefficient between the material used for the top substrate 23 and the ceramic material used for the ceramic substrate 21 at 40 to 400°C is preferably 1.5×10 -6 / K or less, more preferably 1.0×10 -6 / K or less, more preferably 0.5×10 -6 Considering the strength, the thickness of the top substrate 23 is preferably 3 mm or more and 6 mm or more. Considering the cooling efficiency, the thickness is preferably 20 mm or less.

[0039] A plurality of screw holes 24 are provided on the lower surface of the top substrate 23. The screw holes 24 are provided at positions opposite to the through holes 36 described later. The screw holes 24 are formed by providing a cylindrical hole on the lower surface of the top substrate 23 and directly providing a thread groove in the cylindrical hole, but are not particularly limited thereto. For example, a spiral screw sleeve can be inserted into the cylindrical hole to form the screw hole 24, or a terminal with an internal thread (such as a bag nut, etc.) of patent document 1 can be inserted into the cylindrical hole and brazed to form the screw hole 24. The interval between the centers of two adjacent screw holes 24 is not particularly limited, and is preferably, for example, less than 100 mm. Accordingly, the upper substrate 20 and the lower substrate 30 can be tightened more tightly, and thus, the thermal conductivity performance of the heat sink 40 is improved.

[0040] The metal bonding layer 25 bonds the lower surface of the ceramic substrate 21 and the upper surface of the top substrate 23. The metal bonding layer 25 may be, for example, a layer formed of solder or metal brazing material. For example, the metal bonding layer 25 is formed by TCB (Thermal Compression Bonding). TCB refers to a well-known method of sandwiching a metal bonding material between two components to be bonded, and bonding the two components under pressure while heating them to a temperature below the solidus temperature of the metal bonding material.

[0041] The lower substrate 30 is a disc member made of a material that is easy to process. In the present embodiment, the outer diameter of the lower substrate 30 is the same as the outer diameter of the top substrate 23. A coolant flow path groove 34 is provided on the upper surface of the lower substrate 30. The coolant flow path groove 34 constitutes the side wall and the bottom of the coolant flow path 32. The coolant flow path groove 34 is formed in a vortex shape (from the inlet 32a to the outlet 32b of the coolant flow path 32 in a one-stroke manner) in a manner that covers the entire area where the ceramic substrate 21 is arranged. Figure 4 ). The inlet 32a and outlet 32b of the coolant flow path 32 penetrate the lower surface of the lower substrate 30 and the bottom surface of the coolant flow path groove 34. The inlet 32a and outlet 32b of the coolant flow path 32 are connected to a coolant cooling device not shown in the figure. After the coolant discharged from the outlet 32b is temperature-adjusted in the coolant cooling device, it returns to the inlet 32a again and is supplied to the coolant flow path 32. The coolant circulating in the coolant flow path 32 is preferably a liquid, and preferably electrically insulating. As an electrically insulating liquid, for example, a fluorine-based inactive liquid can be cited. The easy-to-process material used for the lower substrate 30 is preferably a material that is easier to process than the top substrate 23. As an indicator of processability, for example, the machinability index given in JIS B 0170 (2020) can be used. As an easy-to-process material, it is preferably a material with a machinability index of 40 or more, more preferably a material with a machinability index of 100 or more, and further preferably a material with a machinability index of 140 or more. Examples of the easily machinable material include aluminum, aluminum alloys, and stainless steel (SUS material).

[0042] The lower substrate 30 is connected to the RF power supply 62 via the power supply terminal 64. Therefore, the lower substrate 30 also functions as a high frequency (RF) electrode for plasma generation. A high pass filter (HPF) 63 is disposed between the lower substrate 30 and the RF power supply 62.

[0043] The lower substrate 30 has a plurality of through holes 36. The through holes 36 penetrate the lower substrate 30 in the vertical direction in a manner intersecting the coolant flow path 32 (coolant flow path groove 34). Figure 2 As shown, the through hole 36 is a stepped hole that penetrates the lower surface of the lower substrate 30 and the bottom of the coolant flow path 32. The through hole 36 has a large diameter portion 36a that accommodates the head 50a of the screw member 50 and a small diameter portion 36b that allows the foot 50b of the screw member 50 to pass but the head 50a cannot pass.

[0044] The heat sink 40 is arranged between the lower surface of the upper substrate 20 and the upper surface of the lower substrate 30. In the present embodiment, the heat sink 40 is arranged between the lower surface of the top substrate 23 and the portion of the upper surface of the lower substrate 30 where the refrigerant flow groove 34 is not provided and the sealing components 42 and 44 are not provided. The heat sink 40 is sandwiched between the upper substrate 20 and the lower substrate 30 and is compressed in the up and down directions. Accordingly, the heat sink 40 is firmly attached to the lower surface of the upper substrate 20 and the upper surface of the lower substrate 30, so that the heat of the upper substrate 20 is quickly conducted to the lower substrate 30. The thermal resistance of the heat sink 40 is preferably 0.35K·cm 2 / W or less, more preferably 0.1K·cm 2 / W or less. The Young's modulus of the heat sink 40 is preferably 100 MPa or less, more preferably 20 MPa or less, and further preferably 5 MPa or less. For example, the thermal resistance can be measured according to ASTM D5470. Specifically, the heat sink 40 is preferably a sheet containing carbon and resin. As carbon, graphite, carbon fiber, carbon nanotube, etc. can be mentioned; as resin, silicone resin, etc. can be mentioned. In the case of graphite, it is preferably arranged in a manner that the surface direction of graphene constituting graphite is along the up-down direction; in the case of carbon fiber and carbon nanotube, it is preferably arranged in a manner that the axial direction is along the up-down direction. As a material for the heat sink 40, for example, a thermal interface material (TIM) can be used. As specific examples of the heat sink 40, EX20000C4S (manufactured by Dexerials), GraphitePAD, GraphiteTIM (registered trademark) (all manufactured by Panasonic) and the like can be mentioned. The Poisson's ratio of the heat sink 40 is preferably 0.4 or less, more preferably 0.3 or less, and further preferably 0.2 or less. The smaller the Poisson's ratio of the heat sink 40, the more evenly the fastening force of the screw member 50 is transmitted over the entire surface of the heat sink 40, and the less likely it is to escape in the lateral direction. Therefore, the heat sink 40 is firmly attached to the top substrate 23 and the lower substrate 30 over its entire surface. Therefore, the wafer W can be cooled more uniformly. The Shore OO hardness of the heat sink 40 can be 50 or more and 80 or less. The thickness of the heat sink 40 is preferably, for example, 0.05 mm or more and 1 mm or less, and more preferably 0.1 mm or more and 0.3 mm or less.

[0045] like Figure 2As shown, the threaded component 50 has a head 50a with a large diameter and a foot 50b with a small diameter. The threaded component 50 is inserted into the through hole 36 from the lower surface of the lower substrate 30, and is screwed into the screw hole 24 of the top substrate 23 through the coolant flow path 32 (coolant flow path groove 34). The material of the threaded component 50 is preferably a material with good electrical and thermal conductivity, for example, preferably stainless steel. An O-ring 51 is arranged between the head 50a of the threaded component 50 and the step portion (the boundary between the large diameter portion 36a and the small diameter portion 36b) of the through hole 36. The head 50a of the threaded component 50 is accommodated in the large diameter portion 36a in a manner that does not protrude downward from the lower surface of the lower substrate 30. By screwing the threaded component 50 into the screw hole 24, the upper substrate 20 and the lower substrate 30 are fastened in a state where the heat sink 40, the sealing components 42, and 44 are sandwiched. Accordingly, the heat sink 40, the sealing components 42, 44 are compressed in the vertical direction. The sealing component 42 is a metal or resin ring whose outer diameter is slightly smaller than the diameter of the lower substrate 30. It is compressed in the vertical direction to exert sealing properties, thereby preventing the refrigerant from leaking out of the refrigerant flow path 32 to the outer peripheral side. The sealing component 44 is a metal or resin ring inserted into the outside of the insulating tube 55, and is compressed in the vertical direction to exert sealing properties. The O-ring 51 is compressed along the vertical direction between the head 50a of the threaded component 50 and the step portion of the through hole 36, thereby exerting sealing properties. Accordingly, the O-ring 51 prevents the refrigerant in the refrigerant flow path 32 from leaking out of the through hole 36 into which the threaded component 50 is inserted to the lower surface of the lower substrate 30. The width of the refrigerant flow path 32 (refrigerant flow path groove 34) is set to a size that the refrigerant flow will not be retained by the foot 50b.

[0046] The side surfaces (peripheral surfaces) of the metal bonding layer 25, the upper surface and side surfaces of the top substrate 23, and the side surfaces of the lower substrate 30 may be covered with an insulating film as required. Examples of the insulating film include sprayed films of aluminum oxide, yttrium trioxide, and the like.

[0047] Next, use Figures 4 to 6 , a manufacturing example of the wafer placement table 10 is described. Figures 4 to 6 is a manufacturing process diagram of the wafer stage 10. Figure 4 2 shows the manufacturing process of the upper substrate 20. Figure 5 2 shows the manufacturing process of the lower substrate 30. Figure 6 The following is a diagram showing the assembly process of the wafer stage 10 .

[0048] For example, the upper substrate 20 is manufactured as follows. First, a molded body of ceramic powder is hot-pressed and fired to manufacture a ceramic substrate 21 ( Figure 5 (A)). The ceramic substrate 21 has a wafer adsorption electrode 22 built therein. Next, a hole 21b is provided from the lower surface of the ceramic substrate 21 to the wafer adsorption electrode 22 ( Figure 5(B)), the power supply terminal 54 is inserted into the hole 21b, and the power supply terminal 54 and the chip adsorption electrode 22 are joined ( Figure 5 (C)).

[0049] At the same time, a disk-shaped top substrate 23 ( Figure 5 (D)), a through hole 23b is formed in the top substrate 23 to penetrate in the up-down direction, and a screw hole 24 is formed at a predetermined position on the lower surface of the top substrate 23 ( Figure 5 (E)). When the ceramic substrate 21 is made of alumina, the top substrate 23 is preferably made of SiSiCTi or AlSiC. This is because SiSiCTi or AlSiC can make the thermal expansion coefficient substantially the same as that of alumina.

[0050] For example, the top substrate 23 made of SiSiCTi can be made as follows. First, silicon carbide, metal Si and metal Ti are mixed to make a powder mixture. Next, the obtained powder mixture is molded by uniaxial pressure molding to make a disk-shaped molded body, and the molded body is hot-pressed and sintered in an inert atmosphere to obtain the top substrate 23 made of SiSiCTi.

[0051] Next, a circular metal bonding material is arranged on the upper surface of the top substrate 23. A through hole connected to the through hole 23b of the top substrate 23 is pre-set in the metal bonding material. Then, the power supply terminal 54 of the ceramic substrate 21 is inserted into the through hole of the metal bonding material and the through hole 23b of the top substrate 23, and the ceramic substrate 21 is placed on the metal bonding material. Thus, a stacked body is obtained in which the top substrate 23, the metal bonding material and the ceramic substrate 21 are stacked in this order starting from the bottom. The stacked body is heated and pressurized (TCB) to obtain the upper substrate 20 ( Figure 5 (F) The upper substrate 20 is obtained by bonding a ceramic substrate 21 to the upper surface of a top substrate 23 via a metal bonding layer 25 .

[0052] For example, TCB is performed as follows. That is, the stack is pressurized and bonded at a temperature below the solidus temperature of the metal bonding material (for example, a temperature above the solidus temperature minus 20°C and below the solidus temperature), and then returned to room temperature. Accordingly, the metal bonding material becomes a metal bonding layer (or a conductive bonding layer). As the metal bonding material at this time, Al-Mg bonding materials and Al-Si-Mg bonding materials can be used. For example, in the case of TCB using Al-Si-Mg bonding materials, the stack is pressurized in a heated state under a vacuum atmosphere. The metal bonding material preferably uses a material with a thickness of about 100 μm.

[0053] In addition, while manufacturing the upper substrate 20, a disk-shaped lower substrate 30 ( Figure 6 (A)). Next, a terminal hole 30b is formed to penetrate the lower substrate 30 in the vertical direction, and a coolant flow path groove 34 is formed on the upper surface of the lower substrate 30. In addition, an inlet 32a and an outlet 32b of the coolant flow path 32 are formed at one end and the other end of the coolant flow path groove 34, and a through hole 36 having a large diameter portion 36a and a small diameter portion 36b is formed at a desired position in the coolant flow path groove 34. Figure 6 (B)).

[0054] Next, the upper substrate 20 and the lower substrate 30 are fastened together using the screw member 50, thereby manufacturing the wafer placement table 10. Specifically, first, as Figure 7 As shown in (A), a heat sink 40 is arranged on the upper surface of the lower substrate 30. The heat sink 40 is obtained by cutting off a portion that coincides with the opening of the refrigerant flow path groove 34 from a circular sheet having the same diameter as the lower substrate 30. The portion of the heat sink 40 where the sealing components 42 and 44 are to be arranged is also cut off. Next, the sealing component 42 is arranged along the outer periphery of the lower substrate 30, and the sealing component 44 is arranged along the opening edge of the terminal hole 30b. Next, the power supply terminal 54 of the upper substrate 20 is inserted into the terminal hole 30b, and the upper substrate 20 is placed on the heat sink 40 and the sealing components 42 and 44 arranged on the upper surface of the lower substrate 30. Next, the threaded component 50 is inserted into each through hole 36 from the lower surface of the lower substrate 30 and screwed into the screw hole 24 of the upper substrate 20. Accordingly, the heat sink 40 is compressed between the upper substrate 20 and the lower substrate 30, and a high thermal conductivity performance is exerted. In addition, the sealing members 42 and 44 are compressed between the upper substrate 20 and the lower substrate 30 to provide sealing performance. Then, an insulating tube 55 ( Figure 7 (B)). Thus, the wafer placement table 10 can be obtained.

[0055] Next, use Figure 1, an example of using the wafer carrier 10 is described. First, the wafer carrier 10 is set on the setting plate 96 of the chamber 94. Specifically, first, the sealing components 80, 82a, and 82b are arranged between the upper surface of the setting plate 96 and the lower surface of the lower substrate 30. The sealing component 80 is a metal or resin ring whose outer diameter is slightly smaller than the diameter of the lower substrate 30, and can be compressed in the up and down directions. The sealing components 82a and 82b are metal or resin rings arranged along the opening edges of the inlet 32a and the outlet 32b of the coolant flow path 32, and can be compressed in the up and down directions. Next, the threaded component 70 is screwed into the screw hole 38 provided on the lower surface of the lower substrate 30 through the screw insertion hole 97 from the lower surface of the setting plate 96. Accordingly, the sealing components 82a and 82b are compressed in the up and down directions, exerting sealing properties, thereby preventing the coolant from leaking out of the sealing components 82a and 82b to the outside.

[0056] A disc-shaped wafer W is placed on the wafer placing surface 21a of the wafer placing table 10 provided on the setting plate 96. In this state, a DC voltage of a DC power supply 52 for wafer adsorption is applied to the wafer adsorption electrode 22, so that the wafer W is adsorbed on the wafer placing surface 21a. In addition, a temperature-regulated refrigerant is supplied to the inlet 32a of the refrigerant flow path 32, and the refrigerant is discharged from the outlet 32b. Then, the interior of the chamber 94 is set to a predetermined vacuum atmosphere (or reduced pressure atmosphere), and while a process gas is supplied from the nozzle 98, an RF voltage from an RF power supply 62 is applied to the lower substrate 30. Thus, plasma is generated between the wafer W and the nozzle 98. Then, the wafer W is subjected to CVD film formation or etching using the plasma.

[0057] In the wafer stage 10 described above, the upper substrate 20 and the lower substrate 30 are fastened by the screw member 50. The lower substrate 30 is provided with a coolant flow path groove 34. The screw member 50 is inserted from the lower surface of the lower substrate 30 into the through hole 36 that penetrates the lower substrate 30 in the vertical direction in a manner intersecting the coolant flow path 32 (coolant flow path groove 34) and is screwed into the screw hole 24 of the upper substrate 20. In addition, the coolant is prevented from leaking from the through hole 36 into which the screw member 50 is inserted by using an O-ring 51 (a coolant leakage prevention member). Accordingly, it is not necessary to bypass the screw member 50 to set the coolant flow path 32, so the design freedom of the coolant flow path 32 (coolant flow path groove 34) is improved. In addition, since the screw member 50 is cooled by the coolant, the portion where the screw member 50 is provided is also easily cooled. As a result, according to the wafer stage 10, it is easy to set the in-plane temperature distribution of the wafer W to a desired temperature distribution.

[0058] In addition, the absolute value of the difference in linear thermal expansion coefficient between the top substrate 23 and the ceramic substrate 21 at 40 to 400° C. is preferably 1.5×10 -6 / K or less. As a result, the difference in thermal expansion between the ceramic substrate 21 and the top substrate 23 is small, so that the warping and damage of the upper substrate 20 caused by thermal stress can be suppressed, and the metal bonding layer 25 bonding the ceramic substrate 21 and the top substrate 23 can also be suppressed from being damaged. In addition, the metal bonding layer 25 makes the thermal conduction between the ceramic substrate 21 and the top substrate 23 better than that of the resin.

[0059] In addition, the top substrate 23 is preferably made of a composite material of metal and ceramic. The composite material of metal and ceramic can reduce the absolute value of the difference in linear thermal expansion coefficient between the metal and ceramic substrate 21, and has higher toughness than ceramic materials, so it is not easy to break even if thermal stress occurs. In addition, since the above composite material has conductivity, it can also be used as an RF electrode.

[0060] In addition, a heat sink 40 is disposed between the lower surface of the upper substrate 20 and the upper surface of the lower substrate 30. The upper substrate 20 and the lower substrate 30 are fastened by the screw member 50, so that the heat sink 40 is firmly attached to the upper substrate 20 and the lower substrate 30. Therefore, the heat of the upper substrate 20 is easily and quickly conducted to the lower substrate 30. As a result, the efficiency of cooling the wafer W is improved.

[0061] Furthermore, the lower substrate 30 is made of a material that is easy to process. As a result, the coolant flow channel 34 can be easily formed in the lower substrate 30, thereby reducing processing costs. In addition, compared with the case where the lower substrate 30 is formed of a composite material of metal and ceramic (such as MMC, CMC), the material cost can be suppressed to a lower level.

[0062] In addition, the heat sink 40 has electrical conductivity. As a result, the potential of the lower substrate 30 is the same as that of the top substrate 23 and the metal bonding layer 25. Therefore, the top substrate 23 and the metal bonding layer 25 can be used as RF electrodes, and plasma can be easily generated above the wafer W. It should be noted that a conductive screw member 50 can be used to make the lower substrate 30 and the top substrate 23 have the same potential via the screw member 50.

[0063] It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be implemented in various forms as long as they fall within the technical scope of the present invention.

[0064] In the above-mentioned embodiment, an O-ring 51 as a refrigerant leakage prevention member is arranged between the head 50a of the screw member 50 and the step portion of the through hole 36, but the refrigerant leakage prevention member is not limited to the O-ring 51. Figure 8As shown, the O-ring 53 can be arranged between the inner peripheral surface of the small diameter portion 36b of the through hole 36 and the outer peripheral surface of the foot portion 50b of the threaded component 50. In this case, the O-ring 53 is sandwiched between the inner peripheral surface of the small diameter portion 36b of the through hole 36 and the outer peripheral surface of the foot portion 50b of the threaded component 50 and compressed, thereby exerting sealing properties. Therefore, the O-ring 53 prevents the refrigerant from leaking out of the through hole 36. Alternatively, as Fig. 9 As shown, an O-ring 58 can be arranged at the opening edge of the large diameter portion 36a of the through hole 36 at the lower surface of the lower substrate 30, and the circular plate member 56 covering the lower surface of the lower substrate 30 can be fastened to the lower substrate 30 by screws. In this case, the O-ring 58 is sandwiched between the lower surface of the lower substrate 30 and the upper surface of the circular plate member 56 and compressed, thereby exerting sealing properties. Therefore, the O-ring 58 prevents the refrigerant from leaking to the outside from the through hole 36. It should be noted that Figure 8 and Fig. 9 In the present invention, the same components as those in the above-described embodiment are denoted by the same reference numerals.

[0065] In the above-mentioned embodiment, the upper substrate 20 is obtained by bonding the ceramic substrate 21 and the top substrate 23 by using the metal bonding layer 25, but it is not particularly limited to this. Fig.10 The upper substrate 120 is set as a single layer of a ceramic substrate like the wafer placing table 110 shown in FIG. Fig.10 In the present invention, the same components as those in the above-described embodiment are denoted by the same reference numerals.

[0066] In the above-mentioned embodiment, the wafer stage 10 obtained by fastening the upper substrate 20 and the lower substrate 30 by means of the screw member 50 is set on the setting plate 96 of the chamber 94, but the present invention is not particularly limited to this. Fig.11 The lower substrate 30 is used as the installation plate 96 of the chamber 94 as in the wafer placement table 210 shown in FIG. Fig.11 In the present invention, the same components as those in the above-described embodiment are denoted by the same reference numerals.

[0067] In the above-mentioned embodiment, regardless of whether the screw member 50 has the foot portion 50b or not, the width of the coolant flow path 32 (coolant flow path groove 34) is made constant, but the invention is not particularly limited thereto. For example, in order to make the in-plane temperature distribution of the wafer W a desired temperature distribution, the width of the coolant flow path 32 (coolant flow path groove 34) where the foot portion 50b of the screw member 50 exists may be made wider (see Fig.12 (A)) or narrowing (refer to Fig.12 (B)).

[0068] In the above-mentioned embodiment, the lower base 30 has the coolant flow channel groove 34 on the upper surface, but the present invention is not particularly limited thereto. For example, the lower base 30 may have the coolant flow channel 32 built therein.

[0069] In the above-mentioned embodiment, the heat sink 40 is arranged in the gap between the lower surface of the upper substrate 20 and the upper surface of the lower substrate 30, but it is not particularly limited to this. For example, the arrangement of the heat sink 40 can be omitted. In this case, the refrigerant enters to replace the heat sink 40, but the refrigerant entering the gap between the lower surface of the upper substrate 20 and the upper surface of the lower substrate 30 is not easy to flow and is often retained in the original place. Therefore, it is difficult to use the gap to allow the heat of the upper substrate 20 to escape to the lower substrate 30. Therefore, it is preferred to arrange a heat sink 40 with low thermal resistance (good heat conduction) in the gap as in the above-mentioned embodiment.

[0070] In the above-described embodiment, all the screw components 50 are disposed in the coolant flow path 32 . However, some of the screw components 50 may be disposed in the coolant flow path 32 and the remaining screw components 50 may be disposed outside the coolant flow path 32 .

[0071] In the above-mentioned embodiment, the heat sink 40 is exemplified as a heat sink having conductivity, but the heat sink 40 may be an insulating heat sink.

[0072] In the above-mentioned embodiment, the electrode 22 for wafer adsorption is built into the ceramic substrate 21, but an RF electrode for plasma generation may be built in instead of or in addition to it. In this case, the high-frequency power supply is connected to the RF electrode instead of the lower substrate 30. In addition, the ceramic substrate 21 may have a heater electrode (resistive heating element) built in. In this case, the heater power supply is connected to the heater electrode. The ceramic substrate 21 may have one layer of electrodes built in, or may have two or more layers of electrodes built in.

[0073] In the above embodiment, the coolant flow path 32 is provided in a spiral shape from the inlet 32a to the outlet 32b, but the shape of the coolant flow path 32 is not particularly limited. In addition, in the above embodiment, one coolant flow path 32 is provided, but a plurality of coolant flow paths 32 may be provided.

[0074] In the above-mentioned embodiment, the ceramic substrate 21 is produced by hot pressing and sintering a ceramic powder molded body. However, the molded body in this case may be produced by stacking multiple pieces of cast-molded bodies, by die casting, or by compacting ceramic powder.

[0075] In the above embodiment, the lower substrate 30 is made of an easily machinable material, but the present invention is not particularly limited thereto. For example, the lower substrate 30 may be made of a composite material of metal and ceramic. However, if material cost is taken into consideration, it is preferred to use an easily machinable material such as aluminum or aluminum alloy.

[0076] In the wafer stage 10 of the above-described embodiment, a hole penetrating the wafer stage 10 may be provided from the lower surface of the lower substrate 30 to the wafer placement surface 21a. Examples of such holes include a gas supply hole for supplying a heat-conducting gas (e.g., He gas) to the back surface of the wafer W, and a lift pin hole for inserting a lift pin for moving the wafer W up and down relative to the wafer placement surface 21a.

[0077] Industrial Applicability

[0078] The wafer stage of the present invention is used in, for example, a semiconductor manufacturing apparatus.

[0079] Explanation of symbols

[0080] 10 wafer placing table, 20 upper substrate, 21 ceramic substrate, 21a wafer placing surface, 21b hole, 22 wafer adsorption electrode, 23 top substrate, 23b through hole, 24 screw hole, 25 metal bonding layer, 30 lower substrate, 30b terminal hole, 32 coolant flow path, 32a inlet, 32b outlet, 34 coolant flow path groove, 36 through hole, 36a large diameter portion, 36b small diameter portion, 38 screw hole, 40 heat sink, 42, 44 sealing components, 50 threaded component, 50a head, 50b foot, 51 O-ring, 52 DC power supply for chip adsorption, 53 O-ring, 54 power supply terminal, 55 insulating tube, 56 circular plate component, 58 O-ring, 62 RF power supply, 64 power supply terminal, 70 threaded component, 80, 82a, 82b sealing component, 94 chamber, 96 setting plate, 97 screw insertion hole, 98 nozzle, 110 chip placement table, 120 upper substrate, 210 chip placement table.

Claims

1. A wafer loading platform, wherein: have: An upper substrate, the upper substrate comprising a ceramic substrate having electrodes built therein, and a wafer placement surface on an upper surface of the ceramic substrate; a lower substrate, which is arranged on a surface of the upper substrate opposite to the wafer placement surface and has a coolant flow path for circulating a coolant or a coolant flow path groove constituting a side wall and a bottom of the coolant flow path; a through hole penetrating the lower substrate in a vertical direction in a manner intersecting the coolant flow path or the coolant flow path groove; a screw hole disposed on the lower surface of the upper substrate at a position opposite to the through hole; a threaded component, the threaded component being inserted into the through hole from the lower surface of the lower substrate and being screwed into the screw hole; and A refrigerant leakage preventing member prevents the refrigerant from leaking from the through hole into which the screw member is inserted to the lower surface of the lower base.

2. The wafer stage according to claim 1, wherein: The lower substrate includes the coolant flow groove. The upper substrate includes: the ceramic substrate; a top substrate that is disposed on the lower side of the ceramic substrate and forms a top portion of the coolant flow path; and a metal bonding layer that bonds the ceramic substrate and the top substrate.

3. The wafer stage according to claim 2, wherein: The absolute value of the difference in linear thermal expansion coefficient between the top substrate and the ceramic substrate at 40 to 400° C. is 1.5×10 -6 / K or less.

4. The wafer stage according to claim 3, wherein: The top substrate is made of a composite material of metal and ceramic.

5. The wafer stage according to any one of claims 1 to 4, wherein: A heat sink is disposed between the lower surface of the upper substrate and the upper surface of the lower substrate.

6. The wafer stage according to any one of claims 1 to 4, wherein: The lower substrate is made of a material that is easy to process.

Images