Power semiconductor device online junction temperature detection method and system based on delay time

Abstract

The invention discloses a power semiconductor device online junction temperature detection method and system based on delay time, and the method comprises the steps: carrying out the edge collection of the delay time, and then synthesizing a delay time narrow pulse signal; based on the delay time narrow pulse signal, integral output signals are output at different integral speeds within and outside the delay time; and comparing the integral output signals, and generating an output wide pulse signal of which the pulse width is a fixed multiple of the delay time narrow pulse signal for online junction temperature detection of a power semiconductor device. The junction temperature of the power semiconductor device can be detected in real time, a basis is provided for thermal management of the power semiconductor device, the reliability of the power semiconductor device is improved, and reliable operation of a power electronic device is guaranteed.

Description

Background Art

[0002] Power semiconductor devices, as the core of power electronic devices, are one of the main causes of failure of power electronic devices. The failure of power semiconductor devices is dominated by thermal failure, among which overtemperature and temperature fluctuation are the two main causes of thermal failure of power semiconductor devices. By detecting the junction temperature of power semiconductor devices in real time, the working conditions of power semiconductor devices can be monitored in real time, providing a basis for the thermal management of power semiconductor devices, improving the reliability of power semiconductor devices, and ensuring the reliable operation of power electronic devices.

[0003] There are four existing methods for online junction temperature detection, namely physical contact measurement method, optical method, thermal impedance model method and thermistor electrical parameter method. Among them, the thermistor electrical parameter method uses the parameters of the device under test itself as the temperature detection index to detect the junction temperature of the power semiconductor device. That is to say, the device under test itself is a thermal sensor. Therefore, this method has fast response speed, high accuracy and easy integration. For example, for the delay time type thermistor electrical parameters, the turn-on delay time is the time from the gate-source voltage of the device under test to the drain-source current. The turn-on delay time becomes shorter as the junction temperature of the device under test increases; the turn-off delay time is the time from the gate-source voltage of the device under test to the drain-source voltage. The turn-off delay time becomes longer as the junction temperature of the device under test increases. However, with the development of power semiconductor device technology, especially the emergence of wide bandgap semiconductor devices, the thermal sensitivity of power semiconductor device characteristics has become lower, which puts higher requirements on the detection circuit. Since the turn-on delay time and turn-off delay time are very short (ns level) and have low sensitivity to temperature changes (ps / ℃ level), the accuracy of directly collecting the delay time to infer the junction temperature is very low. The existing online junction temperature detection methods based on delay time all require increasing the driving resistance of the power semiconductor device to slow down the switching speed, extend the delay time, and improve the delay time sensitivity. However, this approach will greatly extend the switching process of the device under test, increase the switching loss of the device under test, and thus affect the normal operation of the power electronic device. Summary of the invention

[0004] The technical problem to be solved by the present invention is to address the deficiencies in the above-mentioned prior art and to provide an online junction temperature detection method and system for power semiconductor devices based on delay time. The method amplifies the pulse width of a narrow pulse signal with a delay time without increasing the driving resistance of the device under test, prolonging the switching process of the device under test, or causing an increase in the switching loss of the device under test, thereby solving the technical problems of short delay time and low sensitivity of power semiconductor devices.

[0005] The present invention adopts the following technical solutions: The method for detecting the online junction temperature of a power semiconductor device based on a delay time comprises the following steps: Perform edge acquisition on the delay time, and then synthesize the delay time narrow pulse signal; Based on the delay time narrow pulse signal, the integral output signal is output at different integral speeds within the delay time and outside the delay time; The integrated output signals are compared to generate an output wide pulse signal whose pulse width is a fixed multiple of the delay time narrow pulse signal, which is used for online junction temperature detection of power semiconductor devices.

[0006] Preferably, the synthetic delay time narrow pulse signal is specifically: Detecting the start and end time of the delay time of the electrical signal of the device under test, and generating corresponding edge signals; A delay signal narrow pulse signal is generated based on the edge signal at the start time of the delay time and the edge signal at the end time of the delay time.

[0007] Preferably, the electrical signal of the device under test includes a gate-source voltage, a drain-source voltage and a drain-source current.

[0008] Preferably, the delay time narrow pulse signal changes from a low level to a high level at the start of the delay time, and changes from a high level to a low level at the end of the delay time, and the pulse width of the delay time narrow pulse signal is the length of the delay time.

[0009] Preferably, the delay time narrow pulse signal changes from a high level to a low level at the start time of the delay time, and changes from a low level to a high level at the end time, and the pulse width of the delay time narrow pulse signal is the length of the delay time.

[0010] Preferably, the integrated output signal is generated at different integration speeds during and outside the delay time; When the integral output signal rises within the delay time, the moment when the integral output signal starts to rise is detected, and its level is V, which is used as the starting time of outputting the wide pulse signal; outside the delay time, when the integral output signal falls, the moment when the integral output signal falls to level V is detected, which is used as the ending time of outputting the wide pulse signal.

[0011] Preferably, the integrated output signal is generated at different integration speeds during and outside the delay time; When the integral output signal decreases within the delay time, the moment when the integral output signal starts to decrease is detected, and its level is V, which is used as the starting time of outputting the wide pulse signal; outside the delay time, when the integral output signal rises, the moment when the integral output signal rises to level V is detected, which is used as the ending time of outputting the wide pulse signal.

[0012] Preferably, the output wide pulse signal having a pulse width that is a fixed multiple of the delay time narrow pulse signal is generated specifically as follows: The output wide pulse signal is generated according to the output wide pulse signal start time and end time, and the pulse width of the output wide pulse signal is the length of the delay time amplified G times.

[0013] In a second aspect, an embodiment of the present invention provides an online junction temperature detection system for a power semiconductor device based on a delay time, comprising: The acquisition module performs edge acquisition on the delay time and then synthesizes the delay time narrow pulse signal; An integration module, based on a delay time narrow pulse signal, outputs an integration output signal at different integration speeds within the delay time and outside the delay time; The detection module compares the integrated output signal and generates an output wide pulse signal whose pulse width is a fixed multiple of the delay time narrow pulse signal, which is used for online junction temperature detection of power semiconductor devices.

[0014] Preferably, the integrated output signal is generated at different integration speeds during and outside the delay time; When the integral output signal rises within the delay time, the moment when the integral output signal starts to rise is detected, and its level is V, which is used as the start time of outputting the wide pulse signal; when the integral output signal falls outside the delay time, the moment when the integral output signal falls to level V is detected, which is used as the end time of outputting the wide pulse signal; Generate an integral output signal at different integral speeds within and outside the delay time; When the integral output signal decreases within the delay time, the moment when the integral output signal starts to decrease is detected, and its level is V, which is used as the start time of outputting the wide pulse signal; when the integral output signal rises outside the delay time, the moment when the integral output signal rises to level V is detected, which is used as the end time of outputting the wide pulse signal; The specific output wide pulse signal whose pulse width is a fixed multiple of the delay time narrow pulse signal is: The output wide pulse signal is generated according to the output wide pulse signal start time and end time, and the pulse width of the output wide pulse signal is the length of the delay time amplified G times.

[0015] In a third aspect, a computer device comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above-mentioned delay time-based online junction temperature detection method for power semiconductor devices when executing the computer program.

[0016] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, including a computer program, which, when executed by a processor, implements the steps of the above-mentioned method for online junction temperature detection of a power semiconductor device based on delay time.

[0017] Compared with the prior art, the present invention has at least the following beneficial effects: The invention discloses an online junction temperature detection method for power semiconductor devices based on delay time. Without increasing the driving resistance and affecting the operation of the device under test, the delay time narrow pulse signal is detected and generated. By outputting the integrated output signal at different integration speeds within and outside the delay time, an output wide pulse signal with a pulse width that is a fixed multiple of the delay time narrow pulse signal is generated based on the integrated output signal. The method is used for online junction temperature detection of power semiconductor devices. By amplifying the pulse width of the delay time narrow pulse signal, the problems of short delay time and low sensitivity are solved. The driving resistance of the device under test is not increased, the switching process of the device under test is not prolonged, and the switching loss of the device under test is not increased.

[0018] Furthermore, two sets of edge detection circuits are used to respectively detect the start time and the shutdown time of the delay time to synthesize a delayed narrow pulse signal, thereby avoiding the edge detection circuit from detecting two edges within a short period of delay time, thereby reducing the burden on the detection circuit. At the same time, the application of two sets of approximate edge detection circuits can also make the signal transmission delays caused by the edge detection circuits offset each other, thereby improving the accuracy of the generated delayed narrow pulse signal.

[0019] Furthermore, by adopting different integration speeds during and outside the delay time, the pulse width of the delay time can be amplified without increasing the driving resistance, solving the problem of short delay time and low sensitivity, without increasing the driving resistance of the device under test, prolonging the switching process of the device under test, and causing no increase in the switching loss of the device under test. The gain of the pulse width amplification can be flexibly adjusted by adjusting the integration speed.

[0020] Furthermore, by inputting the integrated output signal into the comparator to generate an output wide pulse signal, the pulse width of the pulse signal is less susceptible to interference than the level of the level signal, and no analog-to-digital converter is required, which is more convenient for the processor to collect and process. The pulse width and pulse width sensitivity of the output wide pulse signal are much greater than the delay time narrow pulse signal, and can be directly collected.

[0021] It can be understood that the beneficial effects of the second aspect mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here.

[0022] In summary, the present invention can detect the junction temperature of the power semiconductor device in real time, provide a basis for the thermal management of the power semiconductor device, improve the reliability of the power semiconductor device, and ensure the reliable operation of the power electronic device.

[0023] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings to be used in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 It is a flow chart of the process of the present invention; Figure 2 It is a schematic diagram of the signals of each detection step; Figure 3 Schematic diagram of generating a delay time start edge signal for an edge detector; Figure 4 A schematic diagram of generating a delayed time narrow pulse signal for a signal synthesizer; Figure 5 Schematic diagram for generating integrated output signal for subtractor and in-phase integrator; Figure 6 A schematic diagram for generating an integrated output signal for a subtractive integrator; Figure 7 A schematic diagram of generating an integrated output signal for a switch-switched integrated voltage type integrator; Figure 8 A schematic diagram of generating an integrated output signal for a switch-switching time constant type integrator; Fig. 9 Schematic diagram of generating an integral output signal for the output comparator; Fig.10 A schematic diagram of a computer device provided by an embodiment of the present invention.

[0026] Fig.11 The present invention is a block diagram of an electronic device provided according to an embodiment. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] In the description of the present invention, it should be understood that the terms “include” and “comprises” indicate the presence of described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or collections thereof.

[0029] It should also be understood that the terms used in the present specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the present specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0030] It should be further understood that the term "and / or" used in the present specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in the present invention generally indicates that the associated objects are in an "or" relationship.

[0031] It should be understood that, although the terms first, second, third, etc. may be used to describe preset ranges, etc. in the embodiments of the present invention, these preset ranges should not be limited to these terms. These terms are only used to distinguish preset ranges from each other. For example, without departing from the scope of the embodiments of the present invention, the first preset range may also be referred to as the second preset range, and similarly, the second preset range may also be referred to as the first preset range.

[0032] The word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to determining" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)", depending on the context.

[0033] Various structural schematic diagrams of the embodiments disclosed in the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0034] The present invention provides an online junction temperature detection method for power semiconductor devices based on delay time. The existing online junction temperature detection method for power semiconductor devices based on delay time increases the delay time length and temperature sensitivity by increasing the driving resistance, which will greatly slow down the switching speed of the device under test, affect the switching process of the device under test, and increase the switching loss of the device under test. The present invention detects and generates a delay time narrow pulse signal without increasing the driving resistance and affecting the operation of the device under test, and generates an output wide pulse signal with a pulse width of a fixed multiple of the delay time narrow pulse signal based on the integrated output signal by outputting an integrated output signal at different integration speeds during and outside the delay time, and is used for online junction temperature detection of power semiconductor devices. By amplifying the pulse width of the delay time narrow pulse signal, the technical problems of short delay time and low sensitivity are solved, without increasing the driving resistance of the device under test, without prolonging the switching process of the device under test, and without causing an increase in the switching loss of the device under test.

[0035] See also Figure 1 The present invention provides an online junction temperature detection device, including an edge detector, a signal synthesizer, an integrator and an output comparator; wherein: The edge detector is used to complete the edge acquisition of the delay time, and then the delay time narrow pulse signal is synthesized through the signal synthesizer. Based on the delay time narrow pulse signal, the integrator outputs the integral output signal at different integration speeds during and outside the delay time. Finally, the output comparator compares the integral output signal to generate an output wide pulse signal whose pulse width is a fixed multiple of the delay time narrow pulse signal. Since the pulse width is amplified proportionally, the pulse width of the output wide pulse signal is still linearly related to the junction temperature, but the pulse width of the output wide pulse signal and the sensitivity of the pulse width are much larger than those of the delay time narrow pulse signal, and can be directly collected.

[0036] Taking the shutdown delay time as an example, the signal waveform in the detection process of the present invention is as follows: Figure 2 shown.

[0037] The present invention provides a method for detecting the online junction temperature of a power semiconductor device based on a delay time, comprising the following steps: S1, inputting the electrical signal of the device under test (such as gate-source voltage, drain-source voltage and drain-source current) into the edge detector to detect the start and end time of the delay time; Taking the turn-off delay time as an example, if the start time of the turn-off delay time is defined as the time when the gate-source voltage drops to 90% of the high level of the gate-source voltage (such as Figure 2 middle t 0), the delay time start edge signal generated by the edge detector will be t At time 0, it changes from low level to high level (or from high level to low level); At the same time, if the end time of the turn-off delay time is defined as the time when the drain-source voltage rises to 10% of the high level of the drain-source voltage (such as Figure 2 middle t 1), the edge detector generates a delay time end edge signal at t 1 changes from low level to high level (or from high level to low level).

[0038] S2. The signal synthesizer generates a delay time narrow pulse signal based on the delay time start edge signal and the delay time end edge signal generated by the edge detector. The delay time narrow pulse signal changes from a low level to a high level at the start time of the delay time, and changes from a high level to a low level at the end time of the delay time (or changes from a high level to a low level at the start time, and changes from a low level to a high level at the end time of the delay time). The pulse width of the delay time narrow pulse signal is the length of the delay time. Take the shutdown delay time as an example. Figure 2 As shown, the narrow pulse signal of the delayed signal is t 0 becomes high level at the same time t 1 moment becomes low level, t 1- t 0 is the turn-off delay time.

[0039] S3, sending the delayed time narrow pulse signal to the integrator to generate an integrated output signal; Take the shutdown delay time as an example. Figure 2 As shown, the integral output signal rises linearly with a slope α during the delay time. t 0 to t 1. The integral output signal rises from 0 to the maximum value Vmax. After the delay time ends (at t 1), the integral output signal decreases linearly with a slope of α / (G-1) until t 2 After that, the voltage of the integral output signal is less than 0. At this time, the time t 2- t 0 is equal to G( t 1- t 0).

[0040] The integral output signal may also decrease linearly during the delay time and increase linearly after the delay time.

[0041] S4, inputting the integrated output signal into the output comparator to generate an output wide pulse signal, the output comparator detects the moment when the integrated output signal starts to rise (if the integrated output signal decreases linearly within the delay time, it is the moment when it starts to decrease), and changes the output wide pulse signal from a low level to a high level; At the same time, the output comparator will detect the same level when the integral output signal drops (if the integral output signal rises linearly after the delay time, it is rising), and change the output wide pulse signal from high level to low level (it can also be changed from high level to low level first, and then from low level to high level). At this time, the pulse width of the output wide pulse signal is the length of the delay time magnified by G times.

[0042] Take the shutdown delay time as an example. Figure 2 As shown, the output comparator detects the moment when the integral output signal starts to rise from 0V. t At time 0, the output wide pulse signal changes from low level to high level, and when the integral output signal drops, the moment when it reaches 0V is detected. t At time 2, the output wide pulse signal changes from high level to low level. At this time, the pulse width of the output wide pulse signal is t 2- t 0, equal to G( t 1- t 0), which is G times the turn-off delay time.

[0043] Therefore, the pulse width of the delay time narrow pulse signal, that is, the length of the delay time, is successfully amplified by G times, and the sensitivity of the delay time to temperature change is also amplified by G times. At this time, the accuracy of calculating the junction temperature based on the pulse width of the output wide pulse signal becomes higher, and this method does not need to increase the driving resistance of the device under test, will not affect the switching process of the device under test, and will not increase the switching loss of the device under test.

[0044] It will be appreciated by those skilled in the art that various aspects of the present invention may be implemented as systems, methods or program products. Therefore, various aspects of the present invention may be specifically implemented in the following forms, namely: complete hardware implementation, complete software implementation (including firmware, microcode, etc.), or a combination of hardware and software implementations, which may be collectively referred to herein as "circuits", "modules" or "platforms".

[0045] In another embodiment of the present invention, a system for detecting online junction temperature of a power semiconductor device based on delay time is provided. The system can be used to implement the above-mentioned method for detecting online junction temperature of a power semiconductor device based on delay time. Specifically, the system for detecting online junction temperature of a power semiconductor device based on delay time includes an acquisition module, an integration module and a detection module.

[0046] Among them, the acquisition module performs edge acquisition on the delay time and then synthesizes the delay time narrow pulse signal; An integration module, based on a delay time narrow pulse signal, outputs an integration output signal at different integration speeds within the delay time and outside the delay time; Generate an integral output signal at different integral speeds within and outside the delay time; When the integral output signal rises within the delay time, the moment when the integral output signal starts to rise is detected, and its level is V, which is used as the start time of outputting the wide pulse signal; when the integral output signal falls outside the delay time, the moment when the integral output signal falls to level V is detected, which is used as the end time of outputting the wide pulse signal; Generate an integral output signal at different integral speeds within and outside the delay time; When the integral output signal decreases within the delay time, the moment when the integral output signal starts to decrease is detected, and its level is V, which is used as the start time of outputting the wide pulse signal; when the integral output signal rises outside the delay time, the moment when the integral output signal rises to level V is detected, which is used as the end time of outputting the wide pulse signal; The specific output wide pulse signal whose pulse width is a fixed multiple of the delay time narrow pulse signal is: The output wide pulse signal is generated according to the output wide pulse signal start time and end time, and the pulse width of the output wide pulse signal is the length of the delay time amplified G times.

[0047] The detection module compares the integrated output signal and generates an output wide pulse signal whose pulse width is a fixed multiple of the delay time narrow pulse signal, which is used for online junction temperature detection of power semiconductor devices.

[0048] In another embodiment of the present invention, a terminal device is provided, the terminal device includes a processor and a memory, the memory is used to store a computer program, the computer program includes program instructions, and the processor is used to execute the program instructions stored in the computer storage medium. The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc., which are the computing core and control core of the terminal, which are suitable for implementing one or more instructions, and are specifically suitable for loading and executing one or more instructions to implement the corresponding method flow or corresponding functions; the processor described in the embodiment of the present invention can be used for the operation of the online junction temperature detection method of the power semiconductor device based on the delay time, including: The delay time is edge sampled, and then a delay time narrow pulse signal is synthesized; based on the delay time narrow pulse signal, an integral output signal is output at different integral speeds within and outside the delay time; the integral output signals are compared to generate an output wide pulse signal whose pulse width is a fixed multiple of the delay time narrow pulse signal, which is used for online junction temperature detection of power semiconductor devices.

[0049] In another embodiment of the present invention, the present invention also provides a storage medium, specifically a computer-readable storage medium (Memory), which is a memory device in a terminal device for storing programs and data. It is understandable that the computer-readable storage medium here can include both the built-in storage medium in the terminal device and the extended storage medium supported by the terminal device, and can be any tangible medium containing or storing a program, which can be used by an instruction execution system, device or device or used in combination with it. The computer-readable storage medium provides a storage space, which stores the operating system of the terminal. In addition, one or more instructions suitable for being loaded and executed by the processor are also stored in the storage space, and these instructions can be one or more computer programs (including program codes). It should be noted that more specific examples (non-exhaustive list) of the computer-readable storage medium here include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0050] Computer readable storage media also include data signals propagated in baseband or as part of a carrier wave, which carry readable program codes. Such propagated data signals can take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The readable storage medium can also be any readable medium other than a readable storage medium, which can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, device, or device. The program code contained on the readable storage medium can be transmitted using any appropriate medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination of the above.

[0051] Program code for performing the operations of the present invention may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., through the Internet using an Internet service provider).

[0052] The processor may load and execute one or more instructions stored in a computer-readable storage medium to implement the corresponding steps of the method for detecting online junction temperature of a power semiconductor device based on delay time in the above embodiment; the processor may load and execute the following steps: The delay time is edge sampled, and then a delay time narrow pulse signal is synthesized; based on the delay time narrow pulse signal, an integral output signal is output at different integral speeds within and outside the delay time; the integral output signals are compared to generate an output wide pulse signal whose pulse width is a fixed multiple of the delay time narrow pulse signal, which is used for online junction temperature detection of power semiconductor devices.

[0053] See also Fig.10 , the terminal device is a computer device, and the computer device 60 of this embodiment includes: a processor 61, a memory 62, and a computer program 63 stored in the memory 62 and executable on the processor 61. When the computer program 63 is executed by the processor 61, the online junction temperature detection method of the power semiconductor device based on the delay time in the embodiment is implemented. To avoid repetition, it is not described one by one here. Alternatively, when the computer program 63 is executed by the processor 61, the functions of each model / unit in the online junction temperature detection system of the power semiconductor device based on the delay time in the embodiment are implemented. To avoid repetition, it is not described one by one here.

[0054] The computer device 60 may be a computing device such as a desktop computer, a notebook, a PDA, or a cloud server. The computer device 60 may include, but is not limited to, a processor 61 and a memory 62. Those skilled in the art will appreciate that Fig.10This is only an example of the computer device 60 and does not constitute a limitation of the computer device 60. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, the computer device may also include input and output devices, network access devices, buses, etc.

[0055] The processor 61 may be a central processing unit (CPU), or other general-purpose processors, central processing units, graphics processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, data processing logic based on quantum computing, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

[0056] The memory 62 may be an internal storage unit of the computer device 60, such as a hard disk or memory of the computer device 60. The memory 62 may also be an external storage device of the computer device 60, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc., equipped on the computer device 60.

[0057] Furthermore, the memory 62 may include both an internal storage unit of the computer device 60 and an external storage device. The memory 62 is used to store computer programs and other programs and data required by the computer device. The memory 62 may also be used to temporarily store data that has been output or is to be output.

[0058] Any reference to a memory, database or other medium used in the embodiments provided in the present application may include at least one of a non-volatile and a volatile memory. Non-volatile memory may include a read-only memory (ROM), a magnetic tape, a floppy disk, a flash memory, an optical memory, a high-density embedded non-volatile memory, a resistive random access memory (ReRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), a phase change memory (PCM), a graphene memory, etc. Volatile memory may include a random access memory (RAM) or an external cache memory, etc. As an illustration and not limitation, RAM may be in various forms, such as a static random access memory (SRAM) or a dynamic random access memory (DRAM), etc.

[0059] The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. The non-relational database may include a distributed database based on blockchain, etc., but is not limited thereto. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but is not limited thereto.

[0060] See also Fig.11 The terminal device 600 is an electronic device, and the electronic device is in the form of a general computing device. The components of the electronic device may include but are not limited to: at least one processing unit 610, at least one storage unit 620, a bus 630 connecting different platform components (including the storage unit 620 and the processing unit 610), a display unit 640, etc.

[0061] The storage unit stores program codes, which can be executed by the processing unit 610, so that the processing unit 610 performs the steps according to various exemplary embodiments of the present invention described in the above method section of this specification. For example, the processing unit 610 can perform the following steps: Figure 1 Follow the steps shown in .

[0062] The storage unit 620 may include a readable medium in the form of a volatile storage unit, such as a random access memory unit (RAM) 6201 and / or a cache memory unit 6202 , and may further include a read-only memory unit (ROM) 6203 .

[0063] The storage unit 620 may also include a program / utility 6204 having a set (at least one) of program modules 6205, such program modules 6205 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0064] Bus 630 may represent one or more of several types of bus structures, including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

[0065] The electronic device 600 may also communicate with one or more external devices 700 (e.g., keyboards, pointing devices, Bluetooth devices, etc.), may also communicate with one or more devices that enable a user to interact with the electronic device 600, and / or communicate with any device that enables the electronic device 600 to communicate with one or more other computing devices (e.g., routers, modems, etc.). Such communication may be performed via an input / output (I / O) interface 650. Furthermore, the electronic device 600 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 660. The network adapter 660 may communicate with other modules of the electronic device 600 via a bus 630. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device 600, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage platforms, etc.

[0066] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. The components of the embodiments of the present invention described and shown in the drawings here can usually be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0067] Taking the shutdown time as an example, specific implementation cases of each step in this method are listed below.

[0068] First is the edge detector, such as Figure 3 As shown, the gate-source voltage V GS After passing through the signal attenuator, it is input to the reverse input terminal of the comparator. The signal attenuator can be a voltage divider network composed of passive devices (resistors and capacitors, etc.), or a follower circuit composed of an operational amplifier. After being attenuated x times by the signal attenuator, the gate-source voltage is attenuated to the input voltage range that the comparator can tolerate. At the same time, the comparison threshold is set according to the definition of the start time of the delay time, and input to the in-phase terminal of the comparator. For example, the start time of the shutdown delay time is defined as the gate-source voltage drops to 90% of the high level, and the comparison threshold can be set to 90% of the high level after the gate-source voltage is attenuated x times. At this time, after the gate-source voltage drops to 90% of the high level, the output voltage of the comparator, that is, the delay time start edge signal changes from a low level to a high level, such as Figure 2 As shown. The circuit for the edge detector to generate the delay time end edge signal is similar. The drain-source voltage is attenuated by y times and then input into the non-inverting terminal of the comparator. The comparison threshold is set according to the definition of the shutdown delay time and input into the inverting terminal of the comparator. For example, if the end time of the shutdown delay time is defined as the drain-source voltage rising to 10% of the high level, then the comparison threshold is set to 10% of the high level after the drain-source voltage is attenuated by y times. At this time, the delay time end edge signal generated by the edge detector changes from a low level to a high level after the drain-source voltage rises to 10% of the high level, as shown in Figure 1. Figure 2 At the same time, a comparator with a latch function can be selected and controlled by a latch control signal, such as Figure 3 As shown, after the comparator output signal detects the start and end time of the delay time and acts, the latch control signal is used to enable the latch function of the comparator. At this time, the output of the comparator remains constant. At this time, during the on-time of the device under test, when the latch function of the comparator of the edge detector is disabled, the output signal of the comparator immediately changes from a high level to a low level. If the two comparators of the edge detector are disabled at the same time, the delay time start edge signal and the delay time end edge signal can change from a high level to a low level at the same time, as shown in FIG. Figure 2 shown.

[0069] In the signal synthesizer, the delay time narrow pulse signal is mainly generated by the delay time start edge signal and the delay time end edge signal generated by the edge detector. Under the premise that the edge detector uses a comparator with a latch function to generate the delay time start edge signal and the delay time end edge signal that change from high level to low level at the same time, the signal synthesizer can be directly constructed using an exclusive OR gate. Figure 4As shown, the delay time start edge signal and the delay time end edge signal are directly input into the XOR gate. The output signal of the XOR gate will output a high level when the input signal levels are different, and a low level at other times. Therefore, Figure 2 As shown, the output signal of the XOR gate changes from low level to high level when the edge signal becomes high level at the beginning of the delay time, and changes from high level to low level when the edge signal becomes high level at the end of the delay time. Therefore, the output signal of the XOR gate, that is, the output signal of the signal synthesizer, is a delay time narrow pulse signal, and its pulse width is the length of the shutdown delay time.

[0070] The function of the integrator is to have different integral slopes within and outside the delay time. There are four different implementation methods, as follows: Implementation 1: Different integration speeds are generated by different integration voltages. The circuit can be implemented in the form of a subtractor plus a common-phase integrator, such as Figure 5 As shown, the subtractor is used to generate the integrated signal, and then the integrated signal is input into the integrator to generate the integrated output signal. In the subtractor, the delayed time narrow pulse signal is subtracted from the delayed time start edge signal attenuated by G times (Note that the high level voltages of the delayed time narrow pulse signal and the delayed time start edge signal are the same). V h ), at this time the subtractor output signal changes from t 0 to t 1 The voltage between is (1-1 / G) V h ,from t 1 to t 3 is - V h / G, this signal is the integrated signal. Input this signal into the in-phase integrator, then t 0 to t 1, the voltage of the integrated signal is positive, and the integrator output voltage rises linearly. t 1 to t 3, the voltage of the integrated signal is negative, and the output voltage of the integrator decreases linearly. t 0 to t The absolute value of the integrated signal voltage between 1 is t 1 to t 3 is G-1 times the absolute value of the integrated signal voltage. Therefore, the absolute value of the rising slope of the integrated output signal is G-1 times the absolute value of the falling slope. At this time, the time t 2- t 0 is equal to G( t 1- t 0).

[0071] Implementation 2: Use an integrating circuit that includes a subtraction function, such as Figure 6 The subtracting integrator is shown in Figure 1. In this circuit: (1) in: (2) Furthermore, according to Kirchhoff's current law and the virtual short and virtual open of the operational amplifier, the output voltage can be obtained as: (3) Among them, V L is the voltage of the integrated output signal, V I is the voltage of the delayed narrow pulse signal, V J It is the voltage of the edge signal at the start of the delay time.

[0072] set up: (4) Then the output voltage is: (5) Converted to time domain expression: (6) Among them, G = m / n. From formula (6), it can be seen that the integrated signal is the delayed time narrow pulse signal minus the delayed time start edge signal attenuated by G times, which is the integrated signal generated by the subtractor in implementation method 1. In other words, Figure 6 The circuit in is an integration circuit that successfully integrates the subtractor function. Therefore, similarly, this subtraction integrator can generate the same integrated output signal by integrating the integrated signal.

[0073] Implementation 3: Use switch to set different integral voltages, such as Figure 7 As shown. Among them, the polarity of the integral voltage A is opposite to that of the integral voltage B, and the absolute value of the integral voltage A is G-1 times the absolute value of the integral voltage B. At this time, t 0 to t 1. Switch S2 is turned on, switch S3 is turned off, and the integral voltage A is integrated; t 1 to t 3. Switch S3 is turned on, switch S2 is turned off, and the integrated voltage B is integrated. Since the absolute value of the integrated voltage A is G-1 times the absolute value of the integrated voltage B, t 0 to t 1 The absolute value of the slope of the integral output signal is obtained from t 1 to t 3 The absolute value of the integral output signal slope is G-1 times.

[0074] Implementation 4: Different time constants can be used to generate different integration speeds, such as Figure 8 This method can select two integral voltages A and B with the same absolute value but opposite polarity. t 0 to t 1. Switch S2 is turned on, switch S3 is turned off, and the integral voltage A is integrated; t 1 to t 3. Switch S3 is turned on, switch S2 is turned off, and the integral voltage B is integrated. At this time, if the resistor R 82 Set to be resistor R 81 G-1 times, then from t 0 to t 1 The absolute value of the slope of the integral output signal is obtained from t 1 to t 3 The absolute value of the integral output signal slope is G-1 times.

[0075] Based on the above four implementation methods, the integral output signal needs to be cleared after each detection to restore to the state before the detection. Therefore, if Figures 5 to 8 As shown in Figure 1, analog switches are connected in parallel to the integral capacitors. When the analog switches are turned on, the integral capacitors are short-circuited and discharged, and the integral output signal is cleared. Figure 2 As shown, at time t4, the analog switch is turned on, the integral capacitor is short-circuited, and the integral output signal becomes 0V.

[0076] The final integrated output signal is input into the output comparator to generate the final output signal, that is, the output wide pulse signal. The output comparator circuit based on the single power supply comparator is as follows: Fig. 9 As shown. Since the integral output signal is an AC signal, it cannot be directly input into the single-power comparator in the output comparator. Therefore, the integral output signal and the reference voltage are input into the non-inverting terminal of the single-power comparator through a resistor network. At this time, the integral output signal will be raised to the DC level Vpb, thereby converting the integral output signal into a DC signal. At the same time, the threshold voltage is input into the inverting terminal of the single-power comparator, and the threshold voltage is set to be slightly higher than the DC level Vpb. At this time, when the integral output signal begins to rise, the output wide pulse signal output by the output comparator changes from a low level to a high level; when the integral output signal changes to 0V during the decline process, the output wide pulse signal changes from a high level to a low level, as shown in FIG. Figure 2 As shown. At this time, the pulse width of the output wide pulse signal is t 2- t 0, which is equal to G( t 1- t 0), which is G times the turn-off delay time.

[0077] In summary, the present invention provides a method and system for detecting the online junction temperature of a power semiconductor device based on delay time, which amplifies the length of the delay time proportionally without increasing the driving resistance of the device under test, and solves the problem of short delay time and low sensitivity, while not affecting the switching waveform of the device under test, nor causing an increase in the switching loss of the device under test.

[0078] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0079] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0080] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed in the present invention can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0081] In the embodiments provided by the present invention, it should be understood that the disclosed devices / terminals and methods can be implemented in other ways. For example, the device / terminal embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0082] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0083] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0084] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present invention implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium, etc. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electric carrier signals and telecommunication signals.

[0085] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1A device that provides the functions specified in a block or multiple blocks.

[0086] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0087] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0088] The above contents are only for explaining the technical idea of ​​the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the claims of the present invention.

Claims

1. A method for detecting online junction temperature of a power semiconductor device based on delay time, characterized in that: The following steps are involved: Perform edge acquisition on the delay time, and then synthesize the delay time narrow pulse signal; Based on the delay time narrow pulse signal, the integral output signal is output at different integral speeds within the delay time and outside the delay time; The integrated output signals are compared to generate an output wide pulse signal whose pulse width is a fixed multiple of the delay time narrow pulse signal, which is used for online junction temperature detection of power semiconductor devices.

2. The method for detecting online junction temperature of a power semiconductor device based on delay time according to claim 1, characterized in that: The synthetic delay time narrow pulse signal is specifically: Detecting the start and end time of the delay time of the electrical signal of the device under test, and generating corresponding edge signals; A delay signal narrow pulse signal is generated based on the edge signal at the start time of the delay time and the edge signal at the end time of the delay time.

3. The method for detecting online junction temperature of a power semiconductor device based on delay time according to claim 2, characterized in that: The electrical signals of the device under test include gate-source voltage, drain-source voltage and drain-source current.

4. The method for detecting online junction temperature of a power semiconductor device based on delay time according to claim 2, characterized in that: The delay time narrow pulse signal changes from a low level to a high level at the start time of the delay time, and changes from a high level to a low level at the end time of the delay time. The pulse width of the delay time narrow pulse signal is the length of the delay time.

5. The method for detecting online junction temperature of a power semiconductor device based on delay time according to claim 2, characterized in that: The delay time narrow pulse signal changes from high level to low level at the start time of the delay time, and changes from low level to high level at the end time. The pulse width of the delay time narrow pulse signal is the length of the delay time.

6. The method for detecting online junction temperature of a power semiconductor device based on delay time according to claim 1, characterized in that: Generate an integral output signal at different integral speeds within and outside the delay time; When the integral output signal rises within the delay time, the moment when the integral output signal starts to rise is detected, and its level is V, which is used as the starting time of outputting the wide pulse signal; outside the delay time, when the integral output signal falls, the moment when the integral output signal falls to level V is detected, which is used as the ending time of outputting the wide pulse signal.

7. The method for detecting online junction temperature of a power semiconductor device based on delay time according to claim 1, characterized in that: Generate an integral output signal at different integral speeds within and outside the delay time; When the integral output signal decreases within the delay time, the moment when the integral output signal starts to decrease is detected, and its level is V, which is used as the starting time of outputting the wide pulse signal; outside the delay time, when the integral output signal rises, the moment when the integral output signal rises to level V is detected, which is used as the ending time of outputting the wide pulse signal.

8. The method for detecting online junction temperature of a power semiconductor device based on delay time according to claim 6 or 7, characterized in that: The specific output wide pulse signal whose pulse width is a fixed multiple of the delay time narrow pulse signal is: The output wide pulse signal is generated according to the output wide pulse signal start time and end time, and the pulse width of the output wide pulse signal is the length of the delay time amplified G times.

9. A power semiconductor device online junction temperature detection system based on delay time, characterized in that: include: The acquisition module performs edge acquisition on the delay time and then synthesizes the delay time narrow pulse signal; An integration module, based on a delay time narrow pulse signal, outputs an integration output signal at different integration speeds within the delay time and outside the delay time; The detection module compares the integrated output signal and generates an output wide pulse signal whose pulse width is a fixed multiple of the delay time narrow pulse signal, which is used for online junction temperature detection of power semiconductor devices.

10. The power semiconductor device online junction temperature detection system based on delay time according to claim 9, characterized in that: Generate an integral output signal at different integral speeds within and outside the delay time; When the integral output signal rises within the delay time, the moment when the integral output signal starts to rise is detected, and its level is V, which is used as the start time of outputting the wide pulse signal; when the integral output signal falls outside the delay time, the moment when the integral output signal falls to level V is detected, which is used as the end time of outputting the wide pulse signal; Generate an integral output signal at different integral speeds within and outside the delay time; When the integral output signal decreases within the delay time, the moment when the integral output signal starts to decrease is detected, and its level is V, which is used as the start time of outputting the wide pulse signal; when the integral output signal rises outside the delay time, the moment when the integral output signal rises to level V is detected, which is used as the end time of outputting the wide pulse signal; The specific output wide pulse signal whose pulse width is a fixed multiple of the delay time narrow pulse signal is: The output wide pulse signal is generated according to the output wide pulse signal start time and end time, and the pulse width of the output wide pulse signal is the length of the delay time amplified G times.

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