Grid impedance characteristic testing device of field effect transistor

Abstract

The invention relates to the technical field of transistor testing, and particularly provides a grid impedance characteristic testing device for a field effect transistor, and the device comprises a reference resistor which is used for connecting a grid of the field effect transistor; the excitation signal generation unit is connected with the driving unit and is used for inputting a first excitation signal to the driving unit when the driving unit inputs a turn-off signal to the grid electrode of the field effect transistor so as to add alternating current excitation to the turn-off signal output by the driving unit; the grid state acquisition unit is connected with the two ends of the reference resistor and is used for acquiring voltage signals at the two ends of the reference resistor and converting the voltage signals to generate resolving signals; and the processing unit is connected with the grid state acquisition unit and is used for receiving the resolving signal and generating a grid impedance model of the field effect transistor based on the resolving signal. In this way, the grid impedance testing precision of the field effect transistor can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of transistor testing, and in particular to a gate impedance characteristic testing device for a field effect transistor. Background Art

[0002] Field effect transistor refers to Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Field effect transistors are widely used in power electronics, power transmission systems, wind power, photovoltaics, energy storage, charging piles, electric vehicles, charging piles, motor vehicles, robots, servers, industrial equipment and other fields. Due to its high switching speed, low on-resistance, high input impedance and other characteristics, it plays an important role in various fields.

[0003] However, the accuracy of current methods for testing the gate impedance characteristics of field effect transistors is low, resulting in large errors in the performance evaluation of field effect transistors.

[0004] Therefore, how to improve the accuracy of gate impedance characteristic testing of field effect transistors has become a technical problem that needs to be solved urgently. Summary of the invention

[0005] In view of this, the present application provides a gate impedance characteristic testing device for a field effect transistor, which can improve the gate impedance testing accuracy of the field effect transistor.

[0006] In order to solve the above technical problems, on the one hand, an embodiment of the present application provides a gate impedance characteristic testing device of a field effect transistor, comprising: A driving unit connected to the field effect transistor and used to input a driving signal to the field effect transistor to control the field effect transistor to turn on or off; wherein the driving unit includes a reference resistor, and the reference resistor is used to connect the gate of the field effect transistor; An excitation signal generating unit connected to the driving unit, and configured to input a first excitation signal to the driving unit when the driving unit inputs a shutdown signal to the gate of the field effect transistor, so as to add an AC excitation to the shutdown signal output by the driving unit; The gate state acquisition unit is connected to the two ends of the reference resistor, and is used to acquire the voltage signal at the two ends of the reference resistor, and convert the voltage signal to generate a solution signal; The processing unit is connected to the gate state acquisition unit, and is used to receive the solution signal and generate a gate impedance model of the field effect transistor based on the solution signal.

[0007] According to some embodiments of the present application, the excitation signal generating unit includes: A signal generator, used for outputting an initial excitation signal; A first filter is connected to the signal generator and is used to filter the initial excitation signal to generate a first smooth signal; The first DC blocking capacitor is connected to the first filter and is used to isolate the DC bias in the first smooth signal to generate a first excitation signal.

[0008] According to some embodiments of the present application, the excitation signal generating unit includes: A signal generator, configured to output an initial excitation signal, wherein the initial excitation signal includes an orthogonal first initial signal and a second initial signal; A first filter, connected to the signal generator, is used to filter the first initial signal to generate a first smoothed signal; A second filter is connected to the signal generator and is used to filter the second initial signal to generate a second smooth signal; A third filter is connected to the signal generator and is used to filter the first initial signal to generate a third smooth signal; A first DC blocking capacitor connected to the first filter and used to isolate the DC bias in the first smooth signal to generate a first excitation signal; A second DC blocking capacitor is connected to the second filter and the gate state acquisition unit and is used to isolate the DC bias in the second smooth signal to generate a first sampling signal; The third DC blocking capacitor is connected to the third filter and the gate state acquisition unit and is used to isolate the DC bias in the third smooth signal to generate a second sampling signal.

[0009] According to some embodiments of the present application, the excitation signal generating unit includes: A signal generator, configured to output an initial excitation signal, wherein the initial excitation signal includes an orthogonal first initial signal and a second initial signal; A first filter, connected to the signal generator, is used to filter the first initial signal to generate a first smoothed signal; A second filter is connected to the signal generator and is used to filter the second initial signal to generate a second smooth signal; A third filter is connected to the signal generator and is used to filter the first initial signal to generate a third smooth signal; A first amplitude modulator, connected to the first filter, for performing amplitude proportional modulation on the first smoothed signal to generate a first intermediate signal with a first preset amplitude; A first DC blocking capacitor connected to the first amplitude modulator and used to isolate a DC bias in the first intermediate signal to generate a first excitation signal; A second amplitude modulator, connected to the second filter, for performing amplitude proportional modulation on the second smoothed signal to generate a second intermediate signal with a second preset amplitude; A second DC blocking capacitor is connected to the second amplitude modulator and the gate state acquisition unit, and is used to isolate the DC bias in the second intermediate signal to generate a first sampling signal; A third amplitude modulator, connected to the third filter, for performing amplitude proportional modulation on the third smoothed signal to generate a third intermediate signal with a third preset amplitude; The third DC blocking capacitor is connected to the third amplitude modulator and the gate state acquisition unit, and is used to isolate the DC bias in the third intermediate signal to generate a second sampling signal.

[0010] According to some embodiments of the present application, the solution signal includes a first solution value, a second solution value, a third solution value and a fourth solution value, and the gate state acquisition unit includes the following four acquisition submodules: A first acquisition submodule is connected to the first end of the reference resistor and the second DC blocking capacitor, and is used to acquire a voltage signal and a first sampling signal at the first end of the reference resistor, and process the voltage signal and the first sampling signal at the first end of the reference resistor to generate a first solution value; A second acquisition submodule is connected to the first end of the reference resistor and the third DC blocking capacitor, and is used to acquire a voltage signal and a second sampling signal at the first end of the reference resistor, and process the voltage signal and the second sampling signal at the first end of the reference resistor to generate a second solution value; A third acquisition submodule is connected to the second end of the reference resistor and the second DC blocking capacitor, and is used to collect the voltage signal at the second end of the reference resistor and the first sampling signal, and process the voltage signal at the second end of the reference resistor and the first sampling signal to generate a third solution value; The fourth acquisition submodule is connected to the second end of the reference resistor and the third DC blocking capacitor, and is used to collect the voltage signal and the second sampling signal at the second end of the reference resistor, process the voltage signal and the second sampling signal at the second end of the reference resistor, and generate a fourth solution value.

[0011] According to some embodiments of the present application, each acquisition submodule includes: The operational amplifier follower module is connected to one end of the reference resistor and is used to collect the voltage signal at one end of the reference resistor; The DC removal module is connected to the operational amplifier follower module and is used to remove the DC component in the voltage signal to generate a voltage signal to be solved; A multiplier is connected to the DC-removing module and the second DC-isolating capacitor or the third DC-isolating capacitor, and is used to resolve the voltage signal to be resolved and the first sampling signal or the second sampling signal to generate a first process voltage signal; a fourth filter connected to the multiplier, and configured to filter the first process voltage signal to generate a second process voltage signal; A differential conversion module, connected to the second filter, for performing differential conversion on the second process voltage signal to generate a third process voltage signal; The digital-to-analog conversion module is connected to the differential conversion module and is used to perform analog-to-digital conversion on the third process voltage signal to generate a first solution value, a second solution value, a third solution value or a fourth solution value.

[0012] According to some embodiments of the present application, the step of generating a gate impedance model of a field effect transistor based on a solution signal includes: The first solution value, the second solution value, the third solution value and the fourth solution value are combined to determine the amplitude and phase of the voltage signal across the reference resistor; A gate impedance model is constructed based on the amplitude and phase of the voltage signal across the reference resistor.

[0013] According to some embodiments of the present application, the solution signal includes a fifth solution value and a sixth solution value, and the gate state acquisition unit includes the following two acquisition submodules: a fifth acquisition submodule, connected to the first end of the reference resistor, for acquiring a voltage signal at the first end of the reference resistor, and processing the voltage signal at the first end of the reference resistor to generate a fifth solution value; The sixth acquisition submodule is connected to the second end of the reference resistor and is used to acquire a voltage signal at the second end of the reference resistor and process the voltage signal at the second end of the reference resistor to generate a sixth solution value.

[0014] According to some embodiments of the present application, each acquisition submodule includes: The operational amplifier follower module is connected to one end of the reference resistor and is used to collect the voltage signal at one end of the reference resistor; The DC removal module is connected to the operational amplifier follower module and is used to remove the DC component in the voltage signal to generate a voltage signal to be solved; A differential conversion module, connected to the descaling module, is used to perform differential conversion on the voltage signal to be resolved to generate a fourth process voltage signal; The digital-to-analog conversion module is connected to the differential conversion module and is used to perform analog-to-digital conversion on the fourth process voltage signal to generate a fifth solution value or a sixth solution value.

[0015] According to some embodiments of the present application, the step of generating a gate impedance model of a field effect transistor based on a solution signal includes: Based on the first sampling signal and the second sampling signal output by the excitation signal generating unit, the fifth solution value and the sixth solution value are solved to obtain the first operation value, the second operation value, the third operation value and the fourth operation value; The first operation value, the second operation value, the third operation value and the fourth operation value are combined to determine the amplitude and phase of the voltage signal across the reference resistor; A gate impedance model is constructed based on the amplitude and phase of the voltage signal across the reference resistor.

[0016] According to some embodiments of the present application, the processing unit is further used to connect to the excitation signal generating unit, and when the driving unit inputs a shutdown signal to the gate of the field effect transistor, the excitation signal generating unit is triggered to input a first excitation signal to the driving unit.

[0017] The above technical solution of the present application has at least one of the following beneficial effects: An excitation signal is input to the field effect transistor through an excitation signal generating unit to apply AC excitation to the gate of the field effect transistor to create a test environment. Then, a resistor externally connected to the gate of the field effect transistor is used as a reference resistor, and the gate impedance characteristics of the field effect transistor are obtained by collecting the voltage signal across the reference resistor. The above method can test the gate impedance characteristics of the field effect transistor in real time, thereby improving the accuracy of the gate impedance characteristics test of the field effect transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Schematic diagram of the connection between the gate impedance characteristic testing device of the field effect transistor and the field effect transistor according to an embodiment of the present application Figure 1 ; Figure 2 Schematic diagram of the connection between the gate impedance characteristic testing device of the field effect transistor and the field effect transistor according to an embodiment of the present application Figure 2 ; Figure 3 Schematic diagram of the connection between the gate impedance characteristic testing device of the field effect transistor and the field effect transistor according to an embodiment of the present application Figure 3 ; Figure 4 Schematic diagram of a gate impedance characteristic testing device for a field effect transistor according to an embodiment of the present application Figure 1 ; Figure 5 Schematic diagram of a gate impedance characteristic testing device for a field effect transistor according to an embodiment of the present application Figure 2 ; Figure 6 A schematic diagram of the connection between a gate state acquisition unit and a reference resistor, a second DC blocking capacitor, and a third DC blocking capacitor in a gate impedance characteristic test device for a field effect transistor according to an embodiment of the present application; Figure 7 A schematic diagram of the connection between the acquisition submodule in the gate state acquisition unit and the reference resistor, the processing unit, and the second / third DC blocking capacitor in the gate impedance characteristic test device of the field effect transistor according to an embodiment of the present application; Figure 8 A schematic diagram of the connection between a gate state acquisition unit and a reference resistor in a gate impedance characteristic testing device for a field effect transistor according to an embodiment of the present application; Fig. 9 This is a schematic diagram of the connection between the acquisition submodule in the gate state acquisition unit, the reference resistor, and the processing unit in the gate impedance characteristic test device of the field effect transistor according to one embodiment of the present application; Fig.10 A schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0019] The specific implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present application but are not intended to limit the scope of the present application.

[0020] Field effect transistor refers to Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Field effect transistors are widely used in power electronics, power transmission systems, wind power, photovoltaics, energy storage, charging piles, electric vehicles, charging piles, motor vehicles, robots, servers, industrial equipment and other fields. Due to its high switching speed, low on-resistance, high input impedance and other characteristics, it plays an important role in various fields.

[0021] However, the accuracy of current methods for testing the gate impedance characteristics of field effect transistors is low, resulting in large errors in the performance evaluation of field effect transistors.

[0022] Therefore, how to improve the accuracy of gate impedance characteristic testing of field effect transistors has become a technical problem that needs to be solved urgently.

[0023] In order to solve the above technical problems, the embodiment of the present application proposes a gate impedance characteristic test device of a field effect transistor, which inputs an excitation signal to the field effect transistor through an excitation signal generating unit to apply AC excitation to the gate of the field effect transistor to create a test environment. Then, the resistor externally connected to the gate of the field effect transistor is used as a reference resistor, and the gate impedance characteristic of the field effect transistor is obtained by analyzing the voltage signal at both ends of the reference resistor. The above method can test the gate impedance characteristic of the field effect transistor in real time, thereby improving the accuracy of the gate impedance characteristic test of the field effect transistor.

[0024] The following is a detailed description of the gate impedance characteristic test device of the field effect transistor proposed in the embodiment of the present application. Figure 1As shown, the gate impedance characteristic testing device 100 of a field effect transistor may include: a driving unit 110 , an excitation signal generating unit 120 , a gate state collecting unit 130 and a processing unit 140 .

[0025] The driving unit 110 is connected to the field effect transistor and is used to input a driving signal to the field effect transistor to control the field effect transistor to turn on or off. The driving unit 110 includes a reference resistor 111, which is used to connect the gate of the field effect transistor.

[0026] Specifically, the driving unit 110 may include a shutdown circuit, and the reference resistor 111 may be placed in the path between the shutdown circuit and the gate of the field effect transistor. The "shutdown circuit" refers to the circuit portion of the driving unit 110 that controls the field effect transistor to shut down, which is used to output a shutdown signal (generally a negative level) to the gate of the field effect transistor to control the field effect transistor to shut down. It can be understood that the driving unit 110 can be a conventional module in the technical field for controlling the field effect transistor to turn on or off, and it will not be described or limited in detail here.

[0027] The excitation signal generating unit 120 is connected to the driving unit 110, and is used to input a first excitation signal to the driving unit 110 when the driving unit 110 inputs a shutdown signal to the gate of the field effect transistor, so as to add an AC excitation to the shutdown signal output by the driving unit 110. The first excitation signal may be a sine signal or a cosine signal.

[0028] The gate state acquisition unit 130 is connected to both ends of the reference resistor 111 , and is used to acquire voltage signals at both ends of the reference resistor 111 , and convert the voltage signals to generate a solution signal.

[0029] The processing unit 140 is connected to the gate state acquisition unit 130 and is used to receive the solution signal and generate a gate impedance model of the field effect transistor based on the solution signal.

[0030] In one example, the processing unit 140 may be a field programmable gate array (FPGA), a microcontroller unit (MCU), or a digital signal processing unit (DSP), etc. The type of the processing unit 140 is not limited herein.

[0031] The gate impedance characteristic test device 100 proposed in this embodiment includes a driving unit 110, a gate state acquisition unit 130, an excitation signal generating unit 120 and a processing unit 140. An excitation signal is input to the field effect transistor through the excitation signal generating unit 120 to apply AC excitation to the gate of the field effect transistor to create a test environment. Then, the resistor externally connected to the gate of the field effect transistor is used as a reference resistor 111, and the gate impedance characteristic of the field effect transistor is obtained by reverse analysis by collecting the voltage signal at both ends of the reference resistor 111. In this way, the accuracy of the gate impedance characteristic test of the field effect transistor can be improved. In addition, by reflecting the impedance characteristics of the field effect transistor through the reference resistor 111, real-time online detection can be achieved, and test efficiency and flexibility can be improved.

[0032] In one embodiment, if Figure 2 As shown, the processing unit 140 is further used to connect with the excitation signal generating unit 120, and when the driving unit 110 inputs a shut-off signal to the gate of the field effect transistor, the excitation signal generating unit 120 is triggered to input the first excitation signal to the driving unit 110. Specifically, when the field effect transistor is turned off, the processing unit 140 may issue an instruction to the excitation signal generating unit 120 through the communication interface, so that the excitation signal generating unit 120 inputs the first excitation signal.

[0033] In one embodiment, if Figure 3 As shown, the excitation signal generating unit 120 may include: a signal generator (DDS, Direct Digital Synthesizer) 121 , a first filter 122 , and a first DC blocking capacitor 123 .

[0034] The signal generator 121 is used to output an initial excitation signal. The first filter 122 is connected to the signal generator 121 and is used to filter the initial excitation signal to generate a first smoothed signal. The first DC blocking capacitor 123 is connected to the first filter 122 and is used to isolate the DC bias in the first smoothed signal to generate a first excitation signal.

[0035] In one example, the first filter 122 may be a fourth-order Butterworth filter. In other examples, the first filter 122 may be other types of filters, which are not limited herein.

[0036] In another embodiment, if Figure 4 As shown, the excitation signal generating unit 120 may include: a signal generator 121 , a first filter 122 , a second filter 125 , a third filter 126 , a first DC blocking capacitor 123 , a second DC blocking capacitor 124 and a third DC blocking capacitor 127 .

[0037] The signal generator 121 is used to output an initial excitation signal, wherein the initial excitation signal includes an orthogonal first initial signal and a second initial signal. It can be understood that in one example, the first initial signal can be a sine signal, and the second initial signal can be a cosine signal; in another example, the first initial signal can be a cosine signal, and the second initial signal can be a sine signal.

[0038] The first filter 122 is connected to the signal generator 121, and is used to filter the first initial signal to generate a first smoothed signal. The second filter 125 is connected to the signal generator 121, and is used to filter the second initial signal to generate a second smoothed signal. The third filter 126 is connected to the signal generator 121, and is used to filter the first initial signal to generate a third smoothed signal.

[0039] The first DC blocking capacitor 123 is connected to the first filter 122, and is used to isolate the DC bias in the first smooth signal to generate a first excitation signal. The second DC blocking capacitor 124 is connected to the second filter 125 and the gate state acquisition unit 130, and is used to isolate the DC bias in the second smooth signal to generate a first sampling signal. The third DC blocking capacitor 127 is connected to the third filter 126 and the gate state acquisition unit 130, and is used to isolate the DC bias in the third smooth signal to generate a second sampling signal.

[0040] It can be understood that, in one example, the first sampling signal can be a sine signal, and the second sampling signal can be a cosine signal; in another example, the first sampling signal can be a cosine signal, and the second sampling signal can be a sine signal. The amplitudes of the first excitation signal, the first sampling signal, and the second sampling signal can be the same or different, which is not limited here.

[0041] The excitation signal generating unit 120 is used to output a first excitation signal to the driving unit 110, so as to add an AC excitation to the shutdown signal output by the driving unit 110. At the same time, the excitation signal generating unit 120 is also used to output a first sampling signal and a second sampling signal to the gate state acquisition unit 130, so that the gate state acquisition unit 130 uses the first sampling signal and the second sampling signal to solve the gate impedance characteristics of the field effect transistor reflected by the reference resistor 111. Specifically, the processing unit 140 can be connected to the signal generator 121, which is used to issue an instruction to the signal generator 121 when the field effect transistor is turned off, so as to trigger the signal generator 121 to output an initial excitation signal. Then, the first initial signal is processed by the first filter 122 and the first DC blocking capacitor 123 to generate a first excitation signal. The second filter 125 and the second DC blocking capacitor 124 process the second initial signal to generate a first sampling signal. The third filter 126 and the third DC blocking capacitor 127 process the first initial signal to generate a second sampling signal.

[0042] In one example, the solution signal generated by the gate state acquisition unit 130 can be used to characterize the correlation between the voltage signal across the acquisition resistor and the first sampling signal and the second sampling signal. The voltage signal across the acquisition resistor can be further inferred by the solution signal and the known first sampling signal and the second sampling signal.

[0043] In one embodiment, when the initial excitation signal output by the signal generator 121 contains only a single sine signal or cosine signal, the first filter 122 and the third filter 126 can be used to filter the initial excitation signal to generate a corresponding first smoothed signal and a third smoothed signal. A phase shift circuit can be set between the second filter 125 and the signal generator 121, wherein the phase shift circuit is used to perform phase shift processing on the initial excitation signal to generate a signal orthogonal to the initial excitation signal. For example, the initial excitation signal is a sine signal, and the phase shift circuit outputs a cosine signal; the initial excitation signal is a cosine signal, and the phase shift circuit outputs a sine signal. The second filter 125 is used to filter the signal output by the phase shift circuit to generate a corresponding second smoothed signal. On this basis, the first DC blocking capacitor 123, the second DC blocking capacitor 124 and the third DC blocking capacitor 127 are used to perform subsequent processing on the first smoothed signal, the second smoothed signal and the third smoothed signal in turn, thereby generating a first excitation signal, a first sampling signal and a second sampling signal.

[0044] In yet another embodiment, Figure 5 As shown, the excitation signal generating unit 120 may include: a signal generator 121, a first filter 122, a second filter 125, a third filter 126, a first amplitude modulator 128, a first DC blocking capacitor 123, a second amplitude modulator 129, a second DC blocking capacitor 124, a third amplitude modulator 1210, and a third DC blocking capacitor 127.

[0045] The signal generator 121 is used to output an initial excitation signal, wherein the initial excitation signal includes an orthogonal first initial signal and a second initial signal. The first filter 122 is connected to the signal generator 121, and is used to filter the first initial signal to generate a first smoothed signal. The second filter 125 is connected to the signal generator 121, and is used to filter the second initial signal to generate a second smoothed signal. The third filter 126 is connected to the signal generator 121, and is used to filter the first initial signal to generate a third smoothed signal.

[0046] The first amplitude modulator 128 is connected to the first filter 122, and is used to perform amplitude proportional modulation on the first smoothed signal to generate a first intermediate signal with a first preset amplitude. The first DC blocking capacitor 123 is connected to the first amplitude modulator 128, and is used to isolate the DC bias in the first intermediate signal to generate a first excitation signal.

[0047] The second amplitude modulator 129 is connected to the second filter 125, and is used to perform amplitude proportional modulation on the second smoothed signal to generate a second intermediate signal with a second preset amplitude. The second DC blocking capacitor 124 is connected to the second amplitude modulator 129 and the gate state acquisition unit 130, and is used to isolate the DC bias in the second intermediate signal to generate a first sampling signal.

[0048] The third amplitude modulator 1210 is connected to the third filter 126, and is used to perform amplitude proportional modulation on the third smoothed signal to generate a third intermediate signal with a third preset amplitude. The third DC blocking capacitor 127 is connected to the third amplitude modulator 1210 and the gate state acquisition unit 130, and is used to isolate the DC bias in the third intermediate signal to generate a second sampling signal.

[0049] In one example, a first initial signal and a second initial signal can be generated by a signal generator 121, and the first initial signal is filtered by two fourth-order Butterworth filters to obtain a first smoothed signal and a third smoothed signal, and the second initial signal is filtered by a fourth-order Butterworth filter to obtain a second smoothed signal. The first smoothed signal is modulated into a first intermediate signal with a DC bias of 0.3V amplitude by a first amplitude modulator 128, and then a first excitation signal without DC bias of 0.3V amplitude is obtained by a first DC blocking capacitor 123, and the first excitation signal is injected into the driving unit 110, so that an AC excitation is generated in the shutdown signal output by the driving unit 110. At the same time, the second smoothed signal is modulated into a second intermediate signal with a DC bias of 1V amplitude by a second amplitude modulator 129, and a first sampling signal without DC bias of 1V amplitude is obtained by a second DC blocking capacitor 124, and is input into the gate state acquisition unit 130. The third smoothed signal is modulated into a third intermediate signal with a DC bias and an amplitude of 1V by the third amplitude modulator 1210 , and then a second sampling signal with an amplitude of 1V and no DC bias is obtained by the third DC blocking capacitor 127 , and is input into the gate state acquisition unit 130 .

[0050] It can be understood that the amplitudes of the first excitation signal, the first sampling signal and the second sampling signal can be the same or different, which is not limited here. The values ​​of the first preset amplitude, the second preset amplitude and the third preset amplitude can also be set according to actual conditions, which is not limited here.

[0051] In one embodiment, the solution signal may include a first solution value, a second solution value, a third solution value and a fourth solution value, such as Figure 6 As shown, the gate state acquisition unit 130 may include the following four acquisition submodules: a first acquisition submodule 131 , a second acquisition submodule 132 , a third acquisition submodule 133 and a fourth acquisition submodule 134 .

[0052] The first acquisition submodule 131 is connected to the first end of the reference resistor 111 and the second DC blocking capacitor 124, and is used to collect the voltage signal and the first sampling signal at the first end of the reference resistor 111, and process the voltage signal and the first sampling signal at the first end of the reference resistor 111 to generate a first solution value.

[0053] The second acquisition submodule 132 is connected to the first end of the reference resistor 111 and the third DC blocking capacitor 127, and is used to collect the voltage signal and the second sampling signal at the first end of the reference resistor 111, process the voltage signal and the second sampling signal at the first end of the reference resistor 111, and generate a second solution value.

[0054] The third acquisition submodule 133 is connected to the second end of the reference resistor 111 and the second DC blocking capacitor 124, and is used to collect the voltage signal at the second end of the reference resistor 111 and the first sampling signal, and process the voltage signal at the second end of the reference resistor 111 and the first sampling signal to generate a third solution value.

[0055] The fourth acquisition submodule 134 is connected to the second end of the reference resistor 111 and the third DC blocking capacitor 127, and is used to collect the voltage signal and the second sampling signal at the second end of the reference resistor 111, process the voltage signal and the second sampling signal at the second end of the reference resistor 111, and generate a fourth solution value.

[0056] This embodiment can greatly improve the efficiency of sampling and processing by collecting and processing voltage signals in parallel through the above four collection submodules, thereby improving the efficiency of gate impedance characteristic testing.

[0057] In one embodiment, if Figure 7 As shown, each acquisition submodule may include: an operational amplifier follower module 210, a de-straightening module 220, a multiplier 230, a fourth filter 240, a differential conversion module 250 and a digital-to-analog conversion module 260 (ADC, Analog-to-Digital Converter).

[0058] The operational amplifier follower module 210 is connected to one end of the reference resistor 111, and is used to collect the voltage signal at one end of the reference resistor 111. The DC removal module 220 is connected to the operational amplifier follower module 210, and is used to remove the DC component in the voltage signal and generate a voltage signal to be solved. The multiplier 230 is connected to the DC removal module 220 and the second DC blocking capacitor 124 or the third DC blocking capacitor 127, and is used to solve the voltage signal to be solved and the first sampling signal or the second sampling signal to generate a first process voltage signal. The fourth filter 240 is connected to the multiplier 230, and is used to filter the first process voltage signal to generate a second process voltage signal. The differential conversion module 250 is connected to the fourth filter 240, and is used to perform differential conversion on the second process voltage signal to generate a third process voltage signal. The digital-to-analog conversion module 260 is connected to the differential conversion module 250, and is used to perform analog-to-digital conversion on the third process voltage signal to generate a first solution value, a second solution value, a third solution value, or a fourth solution value.

[0059] In one example, the fourth filter 240 may be a sixth-order low-pass filter, and the destraightening module 220 may be a subtractor. In other examples, the fourth filter 240 may be other types of filters, and the destraightening module 220 may be other types of devices, which are not limited here.

[0060] Specifically, each acquisition submodule first acquires the voltage signal at one end of the reference resistor 111, and maintains high input impedance and high drive output capability through the operational amplifier follower module 210. Then, a subtractor is used to remove the DC component in the voltage signal to obtain a voltage signal to be solved. The multiplier 230 is used to perform hardware solution on the voltage signal to be solved, and then a sixth-order low-pass filter is used to filter the first process voltage signal obtained after the solution to generate a second process voltage signal. Finally, the second process voltage signal is given to the digital-to-analog conversion module 260 through the differential conversion module 250, and the digital-to-analog conversion module 260 uses the communication interface to send the first solution value, the second solution value, the third solution value or the fourth solution value to the processing unit 140.

[0061] In this embodiment, the step of generating the gate impedance model of the field effect transistor based on the solution signal performed by the processing unit 140 may specifically include: combining the first solution value, the second solution value, the third solution value and the fourth solution value to determine the amplitude and phase of the voltage signal across the reference resistor 111. The gate impedance model is constructed based on the amplitude and phase of the voltage signal across the reference resistor 111. It can be understood that the gate impedance model can be constructed based on the amplitude and phase of the voltage signal using a conventional algorithm in the technical field, and the algorithm for constructing the gate impedance model is not described in detail or limited in the embodiment of the present application.

[0062] Specifically, the first solution value in this embodiment may include a relationship between the voltage signal at the first end of the reference resistor 111 and the first sampling signal, the second solution value may include a relationship between the voltage signal at the first end of the reference resistor 111 and the second sampling signal, the third solution value may include a relationship between the voltage signal at the second end of the reference resistor 111 and the first sampling signal, and the fourth solution value may include a relationship between the voltage signal at the second end of the reference resistor 111 and the second sampling signal.

[0063] In one example, the first solution value, the second solution value, the third solution value, and the fourth solution value may be respectively , where A 1 A refers to the amplitude of the voltage signal at the first end of the reference resistor 111. 2 A refers to the amplitude of the voltage signal at the second end of the reference resistor 111. 3 refers to the amplitude of the first sampling signal and the second sampling signal, refers to the phase of the voltage signal at the first end of the reference resistor 111, Refers to the phase of the voltage signal at the second end of the reference resistor 111. By combining the first solution value, the second solution value, the third solution value and the fourth solution value, the amplitude (A) of the voltage signal at both ends of the reference resistor 111 can be determined. 1 , A 2 ) and phase ( ). Then, the gate impedance model is constructed based on the amplitude and phase of the voltage signal across the reference resistor 111.

[0064] In another embodiment, if Figure 8 As shown, the solution signal may include a fifth solution value and a sixth solution value, and the gate state acquisition unit 130 includes a fifth acquisition submodule 135 and a sixth acquisition submodule 136 .

[0065] The fifth acquisition submodule 135 is connected to the first end of the reference resistor 111, and is used to acquire the voltage signal of the first end of the reference resistor 111, and process the voltage signal of the first end of the reference resistor 111 to generate the fifth solution value. The sixth acquisition submodule 136 is connected to the second end of the reference resistor 111, and is used to acquire the voltage signal of the second end of the reference resistor 111, and process the voltage signal of the second end of the reference resistor 111 to generate the sixth solution value.

[0066] like Fig. 9 As shown, each acquisition submodule may include: an operational amplifier follower module 210 , a de-straightening module 220 , a differential conversion module 250 and a digital-to-analog conversion module 260 .

[0067] The operational amplifier follower module 210 is connected to one end of the reference resistor 111, and is used to collect the voltage signal at one end of the reference resistor 111. The DC removal module 220 is connected to the operational amplifier follower module 210, and is used to remove the DC component in the voltage signal to generate a voltage signal to be solved. The differential conversion module 250 is connected to the DC removal module 220, and is used to perform differential conversion on the voltage signal to be solved to generate a fourth process voltage signal. The digital-to-analog conversion module 260 is connected to the differential conversion module 250, and is used to perform analog-to-digital conversion on the fourth process voltage signal to generate a fifth solution value or a sixth solution value.

[0068] In one example, the destrapping module 220 may be a subtractor. In other examples, the destrapping module 220 may be other types of devices, which are not limited here.

[0069] Specifically, each acquisition submodule first acquires the voltage signal at one end of the reference resistor 111, and maintains high input impedance and high drive output capability through the operational amplifier follower module 210. Then, a subtractor is used to remove the DC component in the voltage signal to obtain a voltage signal to be solved. Finally, the voltage signal to be solved is given to the digital-to-analog conversion module 260 through the differential conversion module 250, and the digital-to-analog conversion module 260 uses the communication interface to send the fifth solution value and the sixth solution value to the processing unit 140.

[0070] In this embodiment, the step of generating the gate impedance model of the field effect transistor based on the solution signal performed by the processing unit 140 may specifically include: solving the fifth solution value and the sixth solution value based on the first sampling signal and the second sampling signal output by the excitation signal generating unit 120 to obtain the first operation value, the second operation value, the third operation value and the fourth operation value. The first operation value, the second operation value, the third operation value and the fourth operation value are combined to determine the amplitude and phase of the voltage signal across the reference resistor 111. Based on the amplitude and phase of the voltage signal across the reference resistor 111, a gate impedance model is constructed.

[0071] In this embodiment, the module for implementing hardware solution composed of the multiplier 230 and the fourth filter 240 in the above embodiment is deleted, and the hardware solution function is implemented by the processing unit 140. Specifically, the first operation value in this embodiment may include the relationship between the voltage signal at the first end of the reference resistor 111 and the first sampling signal, the second operation value may include the relationship between the voltage signal at the first end of the reference resistor 111 and the second sampling signal, the third operation value may include the relationship between the voltage signal at the second end of the reference resistor 111 and the first sampling signal, and the fourth operation value may include the relationship between the voltage signal at the second end of the reference resistor 111 and the second sampling signal. It can be understood that the steps of respectively solving the first solution value, the second solution value, the third solution value and the fourth solution value to obtain the first solution value, the second solution value, the third solution value and the fourth solution value are equivalent to the functions implemented by the multiplier 230 and the fourth filter 240 in the above embodiment, and are not repeated here.

[0072] It should be noted that the gate impedance characteristic test device 100 of the field effect transistor provided in the above embodiment, when realizing its function, only uses the division of the above functional modules as an example. In actual application, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the device provided in the above embodiment and the corresponding method embodiment belong to the same concept, and the specific implementation process is detailed in the corresponding method embodiment, which will not be repeated here.

[0073] An embodiment of the present application also provides an electronic device, such as Fig.10 As shown, the electronic device 10 includes the gate impedance characteristic testing device 100 of the field effect transistor provided in the above embodiment, and the gate impedance characteristic testing device 100 of the field effect transistor is not described in detail here.

[0074] The above is a preferred embodiment of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A gate impedance characteristic testing device for a field effect transistor, characterized in that: include: A driving unit connected to the field effect transistor, and used to input a driving signal to the field effect transistor to control the field effect transistor to turn on or off; wherein the driving unit includes a reference resistor, and the reference resistor is used to connect the gate of the field effect transistor; an excitation signal generating unit connected to the driving unit, and configured to input a first excitation signal to the driving unit when the driving unit inputs a shutdown signal to the gate of the field effect transistor, so as to add an AC excitation to the shutdown signal output by the driving unit; A gate state acquisition unit connected to both ends of the reference resistor, used to acquire voltage signals at both ends of the reference resistor, and convert the voltage signals to generate a solution signal; A processing unit is connected to the gate state acquisition unit, and is used to receive the solution signal and generate a gate impedance model of the field effect transistor based on the solution signal.

2. The gate impedance characteristic testing device according to claim 1, characterized in that: The excitation signal generating unit comprises: A signal generator, used for outputting an initial excitation signal; A first filter, connected to the signal generator, for filtering the initial excitation signal to generate a first smooth signal; A first DC blocking capacitor is connected to the first filter and is used to isolate a DC bias in the first smoothed signal to generate the first excitation signal.

3. The gate impedance characteristic testing device according to claim 1, characterized in that: The excitation signal generating unit comprises: A signal generator, configured to output an initial excitation signal, wherein the initial excitation signal comprises an orthogonal first initial signal and a second initial signal; A first filter, connected to the signal generator, configured to filter the first initial signal to generate a first smoothed signal; A second filter, connected to the signal generator, for filtering the second initial signal to generate a second smoothed signal; a third filter, connected to the signal generator, configured to filter the first initial signal to generate a third smoothed signal; a first DC blocking capacitor connected to the first filter and used to isolate a DC bias in the first smoothed signal to generate the first excitation signal; a second DC blocking capacitor connected to the second filter and the gate state acquisition unit, and used for isolating a DC bias in the second smooth signal to generate a first sampling signal; A third DC blocking capacitor is connected to the third filter and the gate state acquisition unit, and is used to isolate the DC bias in the third smooth signal to generate a second sampling signal.

4. The gate impedance characteristic testing device according to claim 1, characterized in that: The excitation signal generating unit comprises: A signal generator, configured to output an initial excitation signal, wherein the initial excitation signal comprises an orthogonal first initial signal and a second initial signal; A first filter, connected to the signal generator, configured to filter the first initial signal to generate a first smoothed signal; A second filter, connected to the signal generator, for filtering the second initial signal to generate a second smoothed signal; a third filter, connected to the signal generator, configured to filter the first initial signal to generate a third smoothed signal; A first amplitude modulator, connected to the first filter, for performing amplitude proportional modulation on the first smoothed signal to generate a first intermediate signal with a first preset amplitude; a first DC blocking capacitor connected to the first amplitude modulator and configured to isolate a DC bias in the first intermediate signal to generate the first excitation signal; A second amplitude modulator, connected to the second filter, for performing amplitude proportional modulation on the second smoothed signal to generate a second intermediate signal with a second preset amplitude; a second DC blocking capacitor connected to the second amplitude modulator and the gate state acquisition unit, and used for isolating a DC bias in the second intermediate signal to generate a first sampling signal; A third amplitude modulator, connected to the third filter, for performing amplitude proportional modulation on the third smoothed signal to generate a third intermediate signal with a third preset amplitude; A third DC blocking capacitor is connected to the third amplitude modulator and the gate state acquisition unit, and is used to isolate the DC bias in the third intermediate signal to generate a second sampling signal.

5. The gate impedance characteristic testing device according to claim 3 or 4, characterized in that: The solution signal includes a first solution value, a second solution value, a third solution value and a fourth solution value, and the gate state acquisition unit includes the following four acquisition submodules: a first acquisition submodule, connected to the first end of the reference resistor and the second DC blocking capacitor, for acquiring a voltage signal at the first end of the reference resistor and the first sampling signal, and processing the voltage signal at the first end of the reference resistor and the first sampling signal to generate the first solution value; a second acquisition submodule, connected to the first end of the reference resistor and the third DC blocking capacitor, for acquiring a voltage signal at the first end of the reference resistor and the second sampling signal, processing the voltage signal at the first end of the reference resistor and the second sampling signal, and generating the second solution value; a third acquisition submodule, connected to the second end of the reference resistor and the second DC blocking capacitor, configured to acquire a voltage signal at the second end of the reference resistor and the first sampling signal, process the voltage signal at the second end of the reference resistor and the first sampling signal, and generate the third solution value; The fourth acquisition submodule is connected to the second end of the reference resistor and the third DC blocking capacitor, and is used to collect the voltage signal at the second end of the reference resistor and the second sampling signal, process the voltage signal at the second end of the reference resistor and the second sampling signal, and generate the fourth solution value.

6. The gate impedance characteristic testing device according to claim 5, characterized in that: Each of the acquisition submodules includes: An operational amplifier follower module is connected to one end of the reference resistor and is used to collect a voltage signal at one end of the reference resistor; A DC removal module, connected to the operational amplifier follower module, for removing the DC component in the voltage signal to generate a voltage signal to be solved; a multiplier connected to the DC removal module and the second DC blocking capacitor or the third DC blocking capacitor, and configured to solve the voltage signal to be solved and the first sampling signal or the second sampling signal to generate a first process voltage signal; a fourth filter, connected to the multiplier, and configured to filter the first process voltage signal to generate a second process voltage signal; a differential conversion module, connected to the second filter, and configured to perform differential conversion on the second process voltage signal to generate a third process voltage signal; The digital-to-analog conversion module is connected to the differential conversion module and is used to perform analog-to-digital conversion on the third process voltage signal to generate the first solution value, the second solution value, the third solution value or the fourth solution value.

7. The gate impedance characteristic testing device according to claim 6, characterized in that: The step of generating a gate impedance model of the field effect transistor based on the solution signal comprises: Determine the amplitude and phase of the voltage signal across the reference resistor by combining the first solution value, the second solution value, the third solution value and the fourth solution value; The gate impedance model is constructed based on the amplitude and phase of the voltage signal across the reference resistor.

8. The gate impedance characteristic testing device according to claim 1, characterized in that: The solution signal includes a fifth solution value and a sixth solution value, and the gate state acquisition unit includes the following two acquisition submodules: a fifth acquisition submodule, connected to the first end of the reference resistor, for acquiring a voltage signal at the first end of the reference resistor, and processing the voltage signal at the first end of the reference resistor to generate the fifth solution value; The sixth acquisition submodule is connected to the second end of the reference resistor, and is used to acquire the voltage signal at the second end of the reference resistor, and process the voltage signal at the second end of the reference resistor to generate the sixth solution value.

9. The gate impedance characteristic testing device according to claim 8, characterized in that: Each of the acquisition submodules includes: An operational amplifier follower module is connected to one end of the reference resistor and is used to collect a voltage signal at one end of the reference resistor; A DC removal module, connected to the operational amplifier follower module, for removing the DC component in the voltage signal to generate a voltage signal to be solved; A differential conversion module, connected to the descaling module, for performing differential conversion on the voltage signal to be resolved to generate a fourth process voltage signal; The digital-to-analog conversion module is connected to the differential conversion module and is used to perform analog-to-digital conversion on the fourth process voltage signal to generate the fifth solution value or the sixth solution value.

10. The gate impedance characteristic testing device according to claim 9, characterized in that: The step of generating a gate impedance model of the field effect transistor based on the solution signal comprises: Based on the first sampling signal and the second sampling signal output by the excitation signal generating unit, the fifth solution value and the sixth solution value are solved to obtain a first operation value, a second operation value, a third operation value and a fourth operation value; Combine the first operation value, the second operation value, the third operation value and the fourth operation value to determine the amplitude and phase of the voltage signal across the reference resistor; The gate impedance model is constructed based on the amplitude and phase of the voltage signal across the reference resistor.

11. The gate impedance characteristic testing device according to claim 1, characterized in that: The processing unit is further configured to be connected to the excitation signal generating unit, and to trigger the excitation signal generating unit to input the first excitation signal to the driving unit when the driving unit inputs the shutdown signal to the gate of the field effect transistor.

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