A testing device for the gate impedance characteristics of a field-effect transistor

Abstract

This application relates to the technical field of transistor testing, and specifically provides a device for testing the gate impedance characteristics of a field-effect transistor. The device for testing the gate impedance characteristics includes: a reference resistor for connecting to the gate of the field-effect transistor; an excitation signal generating unit connected to the driving unit, configured to input a first excitation signal to the driving unit when the driving unit inputs a turn-off signal to the gate of the field-effect transistor, so as to add an AC excitation to the turn-off signal output by the driving unit; a gate state acquisition unit connected to both ends of the reference resistor, configured to acquire the voltage signal across the reference resistor and perform conversion processing on the voltage signal to generate a resolution signal; and a processing unit connected to the gate state acquisition unit, configured to receive the resolution signal and generate a gate impedance model of the field-effect transistor based on the resolution signal. In this way, this application can improve the accuracy of the gate impedance test of the field-effect transistor.

Description

Technical Field

[0001] This application relates to the technical field of transistor testing, and particularly to a device for testing the gate impedance characteristics of a field effect transistor. Background Art

[0002] A field effect transistor refers to a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Field effect transistors are widely used in the fields of power electronics, power transmission systems, wind power, photovoltaics, energy storage, charging piles, electric vehicles, charging piles, bullet trains, robots, servers, industrial equipment, etc. Due to their characteristics such as high switching speed, low on-resistance, and high input impedance, they play an important role in various fields.

[0003] However, currently, the accuracy of the gate impedance characteristic testing methods for field effect transistors is relatively low, resulting in a large error in the performance evaluation of field effect transistors.

[0004] Therefore, how to improve the accuracy of the gate impedance characteristic testing of field effect transistors has become an urgent technical problem to be solved. Summary of the Invention

[0005] In view of this, this application provides a device for testing the gate impedance characteristics of a field effect transistor, which can improve the gate impedance testing accuracy of the field effect transistor.

[0006] To solve the above technical problems, on the one hand, an embodiment of this application provides a device for testing the gate impedance characteristics of a field effect transistor, including:

[0007] A driving unit, connected to the field effect transistor, for inputting a driving signal to the field effect transistor to control the field effect transistor to turn on or off; wherein, the driving unit includes a reference resistor for connecting to the gate of the field effect transistor;

[0008] An excitation signal generating unit, connected to the driving unit, for inputting a first excitation signal to the driving unit when the driving unit inputs a turn-off signal to the gate of the field effect transistor, so as to add an AC excitation to the turn-off signal output by the driving unit;

[0009] A gate state acquisition unit, connected to both ends of the reference resistor, for acquiring the voltage signal across the reference resistor and performing conversion processing on the voltage signal to generate a solution signal;

[0010] A processing unit, connected to the gate state acquisition unit, for receiving the solution signal and generating a gate impedance model of the field effect transistor based on the solution signal.

[0011] According to some embodiments of the present application, the excitation signal generating unit includes:

[0012] A signal generator for outputting an initial excitation signal;

[0013] A first filter connected to the signal generator for filtering the initial excitation signal to generate a first smoothed signal;

[0014] A first DC-blocking capacitor connected to the first filter for isolating the DC bias in the first smoothed signal to generate a first excitation signal.

[0015] According to some embodiments of the present application, the excitation signal generating unit includes:

[0016] A signal generator for outputting an initial excitation signal, wherein the initial excitation signal includes orthogonal first and second initial signals;

[0017] A first filter connected to the signal generator for filtering the first initial signal to generate a first smoothed signal;

[0018] A second filter connected to the signal generator for filtering the second initial signal to generate a second smoothed signal;

[0019] A third filter connected to the signal generator for filtering the first initial signal to generate a third smoothed signal;

[0020] A first DC-blocking capacitor connected to the first filter for isolating the DC bias in the first smoothed signal to generate a first excitation signal;

[0021] A second DC-blocking capacitor connected to the second filter and the gate state acquisition unit for isolating the DC bias in the second smoothed signal to generate a first sampling signal;

[0022] A third DC-blocking capacitor connected to the third filter and the gate state acquisition unit for isolating the DC bias in the third smoothed signal to generate a second sampling signal.

[0023] According to some embodiments of the present application, the excitation signal generating unit includes:

[0024] A signal generator for outputting an initial excitation signal, wherein the initial excitation signal includes orthogonal first and second initial signals;

[0025] A first filter connected to the signal generator for filtering the first initial signal to generate a first smoothed signal;

[0026] A second filter connected to the signal generator for filtering the second initial signal to generate a second smoothed signal;

[0027] A third filter, connected to the signal generator, for filtering the first initial signal to generate a third smoothed signal;

[0028] A first amplitude modulator, connected to the first filter, for performing amplitude ratio modulation on the first smoothed signal to generate a first intermediate signal at a first preset amplitude;

[0029] A first DC-blocking capacitor, connected to the first amplitude modulator, for isolating the DC bias in the first intermediate signal to generate a first excitation signal;

[0030] A second amplitude modulator, connected to the second filter, for performing amplitude ratio modulation on the second smoothed signal to generate a second intermediate signal at a second preset amplitude;

[0031] A second DC-blocking capacitor, connected to the second amplitude modulator and the gate state acquisition unit, for isolating the DC bias in the second intermediate signal to generate a first sampling signal;

[0032] A third amplitude modulator, connected to the third filter, for performing amplitude ratio modulation on the third smoothed signal to generate a third intermediate signal at a third preset amplitude;

[0033] A third DC-blocking capacitor, connected to the third amplitude modulator and the gate state acquisition unit, for isolating the DC bias in the third intermediate signal to generate a second sampling signal.

[0034] According to some embodiments of the present application, the resolution signal includes a first resolution value, a second resolution value, a third resolution value, and a fourth resolution value. The gate state acquisition unit includes the following four acquisition sub-modules:

[0035] A first acquisition sub-module, connected to the first end of the reference resistor and the second DC-blocking capacitor, for acquiring the voltage signal at the first end of the reference resistor and the first sampling signal, and processing the voltage signal at the first end of the reference resistor and the first sampling signal to generate a first resolution value;

[0036] A second acquisition sub-module, connected to the first end of the reference resistor and the third DC-blocking capacitor, for acquiring the voltage signal at the first end of the reference resistor and the second sampling signal, and processing the voltage signal at the first end of the reference resistor and the second sampling signal to generate a second resolution value;

[0037] A third acquisition sub-module, connected to the second end of the reference resistor and the second DC-blocking capacitor, for acquiring the voltage signal at the second end of the reference resistor and the first sampling signal, and processing the voltage signal at the second end of the reference resistor and the first sampling signal to generate a third resolution value;

[0038] The fourth acquisition submodule is connected to the second end of the reference resistor and the third DC blocking capacitor, and is used to collect the voltage signal and the second sampling signal at the second end of the reference resistor, process the voltage signal and the second sampling signal at the second end of the reference resistor, and generate a fourth solution value.

[0039] According to some embodiments of the present application, each acquisition submodule includes:

[0040] The operational amplifier follower module is connected to one end of the reference resistor and is used to collect the voltage signal at one end of the reference resistor;

[0041] The DC removal module is connected to the operational amplifier follower module and is used to remove the DC component in the voltage signal to generate a voltage signal to be solved;

[0042] A multiplier is connected to the DC-removing module and the second DC-isolating capacitor or the third DC-isolating capacitor, and is used to resolve the voltage signal to be resolved and the first sampling signal or the second sampling signal to generate a first process voltage signal;

[0043] a fourth filter connected to the multiplier, and configured to filter the first process voltage signal to generate a second process voltage signal;

[0044] A differential conversion module, connected to the second filter, for performing differential conversion on the second process voltage signal to generate a third process voltage signal;

[0045] The analog-to-digital conversion module is connected to the differential conversion module and is used to perform analog-to-digital conversion on the third process voltage signal to generate a first solution value, a second solution value, a third solution value or a fourth solution value.

[0046] According to some embodiments of the present application, the step of generating a gate impedance model of a field effect transistor based on a solution signal includes:

[0047] The first solution value, the second solution value, the third solution value and the fourth solution value are combined to determine the amplitude and phase of the voltage signal across the reference resistor;

[0048] A gate impedance model is constructed based on the amplitude and phase of the voltage signal across the reference resistor.

[0049] According to some embodiments of the present application, the solution signal includes a fifth solution value and a sixth solution value, and the gate state acquisition unit includes the following two acquisition submodules:

[0050] a fifth acquisition submodule, connected to the first end of the reference resistor, for acquiring a voltage signal at the first end of the reference resistor, and processing the voltage signal at the first end of the reference resistor to generate a fifth solution value;

[0051] The sixth acquisition sub-module, connected to the second end of the reference resistor, is configured to acquire the voltage signal at the second end of the reference resistor and process the voltage signal at the second end of the reference resistor to generate a sixth calculation value.

[0052] According to some embodiments of the present application, each acquisition sub-module includes:

[0053] An operational amplifier follower module, connected to one end of the reference resistor, is configured to acquire the voltage signal at one end of the reference resistor;

[0054] A DC removal module, connected to the operational amplifier follower module, is configured to remove the DC component in the voltage signal to generate a voltage signal to be calculated;

[0055] A differential conversion module, connected to the DC removal module, is configured to perform differential conversion on the voltage signal to be calculated to generate a fourth process voltage signal;

[0056] An analog-to-digital conversion module, connected to the differential conversion module, is configured to perform analog-to-digital conversion on the fourth process voltage signal to generate a fifth calculation value or a sixth calculation value.

[0057] According to some embodiments of the present application, the steps of generating the gate impedance model of the field effect transistor based on the calculation signal include:

[0058] Based on the first sampling signal and the second sampling signal output by the excitation signal generation unit, perform calculations on the fifth calculation value and the sixth calculation value to obtain a first calculation value, a second calculation value, a third calculation value, and a fourth calculation value;

[0059] Simultaneously solve the first calculation value, the second calculation value, the third calculation value, and the fourth calculation value to determine the amplitude and phase of the voltage signal across the reference resistor;

[0060] Based on the amplitude and phase of the voltage signal across the reference resistor, construct the gate impedance model.

[0061] According to some embodiments of the present application, the processing unit is further configured to be connected to the excitation signal generation unit, and when the driving unit inputs a turn-off signal to the gate of the field effect transistor, trigger the excitation signal generation unit to input a first excitation signal to the driving unit.

[0062] At least one of the above technical solutions of the present application has the following beneficial effects:

[0063] An excitation signal is input to the field effect transistor through the excitation signal generating unit to apply an AC excitation to the gate of the field effect transistor, creating a test environment. Then, the resistor externally connected to the gate of the field effect transistor is used as a reference resistor, and the gate impedance characteristic of the field effect transistor is analyzed by collecting the voltage signal across the reference resistor. In this way, the gate impedance characteristic of the field effect transistor can be tested in real time, improving the accuracy of the gate impedance characteristic test of the field effect transistor. Description of the Drawings

[0064] Figure 1 Schematic connection diagram of the gate impedance characteristic test device of the field effect transistor according to an embodiment of the present application and the field effect transistor Figure 1 ;

[0065] Figure 2 Schematic connection diagram of the gate impedance characteristic test device of the field effect transistor according to an embodiment of the present application and the field effect transistor Figure 2 ;

[0066] Figure 3 Schematic connection diagram of the gate impedance characteristic test device of the field effect transistor according to an embodiment of the present application and the field effect transistor Figure 3 ;

[0067] Figure 4 Schematic diagram of the gate impedance characteristic test device of the field effect transistor according to an embodiment of the present application Figure 1 ;

[0068] Figure 5 Schematic diagram of the gate impedance characteristic test device of the field effect transistor according to an embodiment of the present application Figure 2 ;

[0069] Figure 6 Schematic connection diagram of the gate state acquisition unit in the gate impedance characteristic test device of the field effect transistor according to an embodiment of the present application with the reference resistor, the second DC blocking capacitor, and the third DC blocking capacitor;

[0070] Figure 7 Schematic connection diagram of the acquisition sub-module in the gate state acquisition unit in the gate impedance characteristic test device of the field effect transistor according to an embodiment of the present application with the reference resistor, the processing unit, and the second / third DC blocking capacitor;

[0071] Figure 8 Schematic connection diagram of the gate state acquisition unit in the gate impedance characteristic test device of the field effect transistor according to an embodiment of the present application with the reference resistor;

[0072] Figure 9 Schematic connection diagram of the acquisition sub-module in the gate state acquisition unit in the gate impedance characteristic test device of the field effect transistor according to an embodiment of the present application with the reference resistor and the processing unit;

[0073] Figure 10 Schematic diagram of the electronic device according to the embodiment of the present application. Specific embodiments

[0074] The following will further describe in detail the specific embodiments of the present application in conjunction with the accompanying drawings and embodiments. The following embodiments are used to illustrate the present application, but are not used to limit the scope of the present application.

[0075] A field-effect transistor refers to a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Field-effect transistors are widely used in the fields of power electronics, power transmission systems, wind power, photovoltaic, energy storage, charging piles, electric vehicles, charging piles, bullet trains, robots, servers, industrial equipment, etc. Due to their high switching speed, low on-resistance, high input impedance and other characteristics, they play an important role in various fields.

[0076] However, the accuracy of the current test methods for the gate impedance characteristics of field-effect transistors is relatively low, resulting in a large error in the performance evaluation of field-effect transistors.

[0077] Therefore, how to improve the accuracy of the test for the gate impedance characteristics of field-effect transistors has become an urgent technical problem to be solved at present.

[0078] To solve the above technical problems, the embodiment of the present application proposes a test device for the gate impedance characteristics of a field-effect transistor. An excitation signal generating unit inputs an excitation signal to the field-effect transistor to apply an AC excitation to the gate of the field-effect transistor to create a test environment. Then, the resistor externally connected to the gate of the field-effect transistor is used as a reference resistor, and the gate impedance characteristics of the field-effect transistor are analyzed by collecting the voltage signal across the reference resistor. Through the above method, the gate impedance characteristics of the field-effect transistor can be tested in real time, and the accuracy of the test for the gate impedance characteristics of the field-effect transistor can be improved.

[0079] The following will introduce in detail the test device for the gate impedance characteristics of the field-effect transistor proposed in the embodiment of the present application. As Figure 1 shown, the test device 100 for the gate impedance characteristics of a field-effect transistor may include: a driving unit 110, an excitation signal generating unit 120, a gate state acquisition unit 130, and a processing unit 140.

[0080] The driving unit 110 is connected to the field-effect transistor, and is used to input a driving signal to the field-effect transistor to control the field-effect transistor to turn on or off. Among them, the driving unit 110 includes a reference resistor 111, and the reference resistor 111 is used to connect to the gate of the field-effect transistor.

[0081] Specifically, the driving unit 110 may include a turn-off circuit, and the reference resistor 111 may be placed on the path between the turn-off circuit and the gate of the field-effect transistor. The "turn-off circuit" refers to the circuit part in the driving unit 110 that controls the turn-off of the field-effect transistor, which is used to output a turn-off signal (generally a negative level) to the gate of the field-effect transistor to control the turn-off of the field-effect transistor. It can be understood that the driving unit 110 may be a conventional module in the technical field for controlling the turn-on or turn-off of the field-effect transistor, and details and limitations thereof will not be elaborated herein.

[0082] The excitation signal generating unit 120 is connected to the driving unit 110, and is used to input a first excitation signal to the driving unit 110 when the driving unit 110 inputs a turn-off signal to the gate of the field-effect transistor, so as to add an AC excitation to the turn-off signal output by the driving unit 110. Among them, the first excitation signal may be a sine signal or a cosine signal.

[0083] The gate state acquisition unit 130 is connected to both ends of the reference resistor 111, and is used to acquire the voltage signal at both ends of the reference resistor 111 and perform conversion processing on the voltage signal to generate a resolution signal.

[0084] The processing unit 140 is connected to the gate state acquisition unit 130, and is used to receive the resolution signal and generate a gate impedance model of the field-effect transistor based on the resolution signal.

[0085] In an example, the processing unit 140 may be a field programmable gate array (FPGA, Field Programmable Gate Array), a microcontroller unit (MCU, Microcontroller Unit), a digital signal processing unit (DSP, Digital Signal Processor), etc., and the type of the processing unit 140 is not limited herein.

[0086] The gate impedance characteristic test device 100 proposed in this embodiment includes a driving unit 110, a gate state acquisition unit 130, an excitation signal generating unit 120, and a processing unit 140. An excitation signal is input to the field-effect transistor through the excitation signal generating unit 120 to apply an AC excitation to the gate of the field-effect transistor to create a test environment. Then, the resistor externally connected to the gate of the field-effect transistor is used as the reference resistor 111, and the gate impedance characteristic of the field-effect transistor is inversely analyzed by collecting the voltage signal at both ends of the reference resistor 111. In this way, the accuracy of the gate impedance characteristic test of the field-effect transistor can be improved. Moreover, by using the reference resistor 111 to reflect the impedance characteristic of the field-effect transistor, real-time online detection can be realized, and the test efficiency and flexibility can be improved.

[0087] In one embodiment, asFigure 2 As shown, the processing unit 140 is further configured to be connected to the excitation signal generating unit 120, and when the driving unit 110 inputs a turn-off signal to the gate of the field-effect transistor, trigger the excitation signal generating unit 120 to input a first excitation signal to the driving unit 110. Specifically, when the field-effect transistor is turned off, the processing unit 140 can issue an instruction to the excitation signal generating unit 120 through the communication interface, so that the excitation signal generating unit 120 inputs the first excitation signal.

[0088] In one embodiment, as Figure 3 shown, the excitation signal generating unit 120 may include: a signal generator (DDS, Direct Digital Synthesizer) 121, a first filter 122, and a first DC-blocking capacitor 123.

[0089] The signal generator 121 is configured to output an initial excitation signal. The first filter 122 is connected to the signal generator 121 and is configured to filter the initial excitation signal to generate a first smoothed signal. The first DC-blocking capacitor 123 is connected to the first filter 122 and is configured to isolate the DC bias in the first smoothed signal to generate a first excitation signal.

[0090] In one example, the first filter 122 may be a fourth-order Butterworth filter. In other examples, the first filter 122 may also be other types of filters, which are not limited herein.

[0091] In another embodiment, as Figure 4 shown, the excitation signal generating unit 120 may include: a signal generator 121, a first filter 122, a second filter 125, a third filter 126, a first DC-blocking capacitor 123, a second DC-blocking capacitor 124, and a third DC-blocking capacitor 127.

[0092] The signal generator 121 is configured to output an initial excitation signal, where the initial excitation signal includes orthogonal first and second initial signals. It can be understood that, in one example, the first initial signal may be a sine signal and the second initial signal may be a cosine signal; in another example, the first initial signal may be a cosine signal and the second initial signal may be a sine signal.

[0093] The first filter 122 is connected to the signal generator 121 and is configured to filter the first initial signal to generate a first smoothed signal. The second filter 125 is connected to the signal generator 121 and is configured to filter the second initial signal to generate a second smoothed signal. The third filter 126 is connected to the signal generator 121 and is configured to filter the first initial signal to generate a third smoothed signal.

[0094] The first DC-blocking capacitor 123 is connected to the first filter 122, and is used to isolate the DC bias in the first smoothed signal to generate a first excitation signal. The second DC-blocking capacitor 124 is connected to the second filter 125 and the gate state acquisition unit 130, and is used to isolate the DC bias in the second smoothed signal to generate a first sampling signal. The third DC-blocking capacitor 127 is connected to the third filter 126 and the gate state acquisition unit 130, and is used to isolate the DC bias in the third smoothed signal to generate a second sampling signal.

[0095] Understandably, in one example, the first sampling signal may be a sine signal, and the second sampling signal may be a cosine signal; in another example, the first sampling signal may be a cosine signal, and the second sampling signal may be a sine signal. The amplitudes of the first excitation signal, the first sampling signal, and the second sampling signal may be the same or different, which is not limited herein.

[0096] The excitation signal generation unit 120 is configured to output the first excitation signal to the driving unit 110 to add an AC excitation to the turn-off signal output by the driving unit 110. At the same time, the excitation signal generation unit 120 is further configured to output the first sampling signal and the second sampling signal to the gate state acquisition unit 130, so that the gate state acquisition unit 130 uses the first sampling signal and the second sampling signal to calculate the gate impedance characteristics of the field effect transistor reflected by the reference resistor 111. Specifically, the processing unit 140 may be connected to the signal generator 121, and is configured to send an instruction to the signal generator 121 to trigger the signal generator 121 to output an initial excitation signal when the field effect transistor is turned off. Then, the first initial signal is processed by the first filter 122 and the first DC-blocking capacitor 123 to generate the first excitation signal. The second filter 125 and the second DC-blocking capacitor 124 process the second initial signal to generate the first sampling signal. The third filter 126 and the third DC-blocking capacitor 127 process the first initial signal to generate the second sampling signal.

[0097] In one example, the calculation signal generated by the gate state acquisition unit 130 can be used to characterize the relationship between the voltage signal across the acquisition resistor and the first sampling signal and the second sampling signal. By the calculation signal and the known first sampling signal and second sampling signal, the voltage signal across the acquisition resistor can be further deduced.

[0098] In one embodiment, when the initial excitation signal output by the signal generator 121 only contains a single sine signal or cosine signal, the first filter 122 and the third filter 126 can be used to filter the initial excitation signal to generate corresponding first smoothed signal and third smoothed signal. A phase shift circuit can be arranged between the second filter 125 and the signal generator 121, and the phase shift circuit is used to perform phase shift processing on the initial excitation signal to generate a signal orthogonal to the initial excitation signal. For example, when the initial excitation signal is a sine signal, the phase shift circuit outputs a cosine signal; when the initial excitation signal is a cosine signal, the phase shift circuit outputs a sine signal. The second filter 125 is used to filter the signal output by the phase shift circuit to generate a corresponding second smoothed signal. On this basis, the first DC blocking capacitor 123, the second DC blocking capacitor 124, and the third DC blocking capacitor 127 are used to perform subsequent processing on the first smoothed signal, the second smoothed signal, and the third smoothed signal in sequence, so as to generate a first excitation signal, a first sampling signal, and a second sampling signal.

[0099] In another embodiment, as Figure 5 shown, the excitation signal generating unit 120 may include: a signal generator 121, a first filter 122, a second filter 125, a third filter 126, a first amplitude modulator 128, a first DC blocking capacitor 123, a second amplitude modulator 129, a second DC blocking capacitor 124, a third amplitude modulator 1210, and a third DC blocking capacitor 127.

[0100] The signal generator 121 is used to output an initial excitation signal, where the initial excitation signal includes orthogonal first initial signal and second initial signal. The first filter 122 is connected to the signal generator 121, and is used to filter the first initial signal to generate a first smoothed signal. The second filter 125 is connected to the signal generator 121, and is used to filter the second initial signal to generate a second smoothed signal. The third filter 126 is connected to the signal generator 121, and is used to filter the first initial signal to generate a third smoothed signal.

[0101] The first amplitude modulator 128 is connected to the first filter 122, and is used to perform amplitude ratio modulation on the first smoothed signal to generate a first intermediate signal at a first preset amplitude. The first DC blocking capacitor 123 is connected to the first amplitude modulator 128, and is used to isolate the DC bias in the first intermediate signal to generate a first excitation signal.

[0102] The second amplitude modulator 129 is connected to the second filter 125, and is used to perform amplitude ratio modulation on the second smoothed signal to generate a second intermediate signal at a second preset amplitude. The second DC blocking capacitor 124 is connected to the second amplitude modulator 129 and the gate state acquisition unit 130, and is used to isolate the DC bias in the second intermediate signal to generate a first sampling signal.

[0103] The third amplitude modulator 1210 is connected to the third filter 126, and is used for performing amplitude ratio modulation on the third smoothed signal to generate a third intermediate signal at a third preset amplitude. The third DC blocking capacitor 127 is connected to the third amplitude modulator 1210 and the gate state acquisition unit 130, and is used for isolating the DC bias in the third intermediate signal to generate a second sampling signal.

[0104] In one example, the first initial signal and the second initial signal can be generated by the signal generator 121. The first initial signal is filtered by two fourth-order Butterworth filters respectively to obtain a first smoothed signal and a third smoothed signal, and the second initial signal is filtered by a fourth-order Butterworth filter to obtain a second smoothed signal. The first smoothed signal is modulated by the first amplitude modulator 128 into a first intermediate signal with a DC bias and an amplitude of 0.3V, and then a first excitation signal without DC bias and with an amplitude of 0.3V is obtained through the first DC blocking capacitor 123, and the first excitation signal is injected into the driving unit 110 so that an AC excitation is generated in the turn-off signal output by the driving unit 110. At the same time, the second smoothed signal is modulated by the second amplitude modulator 129 into a second intermediate signal with a DC bias and an amplitude of 1V, a first sampling signal without DC bias and with an amplitude of 1V is obtained through the second DC blocking capacitor 124, and is input into the gate state acquisition unit 130. The third smoothed signal is modulated by the third amplitude modulator 1210 into a third intermediate signal with a DC bias and an amplitude of 1V, and then a second sampling signal without DC bias and with an amplitude of 1V is obtained through the third DC blocking capacitor 127, and is input into the gate state acquisition unit 130.

[0105] It can be understood that the amplitudes of the first excitation signal, the first sampling signal and the second sampling signal can be the same or different, which is not limited herein. The values of the first preset amplitude, the second preset amplitude and the third preset amplitude can also be set according to actual situations, which is not limited herein.

[0106] In one embodiment, the solution signal may include a first solution value, a second solution value, a third solution value and a fourth solution value. As Figure 6 shown, the gate state acquisition unit 130 may include the following four acquisition sub-modules: a first acquisition sub-module 131, a second acquisition sub-module 132, a third acquisition sub-module 133 and a fourth acquisition sub-module 134.

[0107] The first acquisition sub-module 131 is connected to the first end of the reference resistor 111 and the second DC blocking capacitor 124, and is used for acquiring the voltage signal at the first end of the reference resistor 111 and the first sampling signal, and processing the voltage signal at the first end of the reference resistor 111 and the first sampling signal to generate a first solution value.

[0108] The second acquisition sub-module 132 is connected to the first end of the reference resistor 111 and the third DC-blocking capacitor 127. It is used to acquire the voltage signal at the first end of the reference resistor 111 and the second sampling signal, and process the voltage signal at the first end of the reference resistor 111 and the second sampling signal to generate a second calculation value.

[0109] The third acquisition sub-module 133 is connected to the second end of the reference resistor 111 and the second DC-blocking capacitor 124. It is used to acquire the voltage signal at the second end of the reference resistor 111 and the first sampling signal, and process the voltage signal at the second end of the reference resistor 111 and the first sampling signal to generate a third calculation value.

[0110] The fourth acquisition sub-module 134 is connected to the second end of the reference resistor 111 and the third DC-blocking capacitor 127. It is used to acquire the voltage signal at the second end of the reference resistor 111 and the second sampling signal, and process the voltage signal at the second end of the reference resistor 111 and the second sampling signal to generate a fourth calculation value.

[0111] In this embodiment, by using the above four acquisition sub-modules to parallelly acquire and process voltage signals, the efficiency of sampling and processing can be greatly improved, and thus the efficiency of gate impedance characteristic testing can be improved.

[0112] In one embodiment, as Figure 7 shown, each acquisition sub-module may include: an operational amplifier follower module 210, a DC-removing module 220, a multiplier 230, a fourth filter 240, a differential conversion module 250, and an analog-to-digital conversion module 260 (ADC, Analog-to-Digital Converter).

[0113] The operational amplifier follower module 210 is connected to one end of the reference resistor 111 and is used to acquire the voltage signal at one end of the reference resistor 111. The DC-removing module 220 is connected to the operational amplifier follower module 210 and is used to remove the DC component in the voltage signal to generate a voltage signal to be calculated. The multiplier 230 is connected to the DC-removing module 220 and the second DC-blocking capacitor 124 or the third DC-blocking capacitor 127, and is used to calculate the voltage signal to be calculated and the first sampling signal or the second sampling signal to generate a first process voltage signal. The fourth filter 240 is connected to the multiplier 230 and is used to filter the first process voltage signal to generate a second process voltage signal. The differential conversion module 250 is connected to the fourth filter 240 and is used to perform differential conversion on the second process voltage signal to generate a third process voltage signal. The analog-to-digital conversion module 260 is connected to the differential conversion module 250 and is used to perform analog-to-digital conversion on the third process voltage signal to generate a first calculation value, a second calculation value, a third calculation value, or a fourth calculation value.

[0114] In one example, the fourth filter 240 may be a sixth-order low-pass filter, and the destraightening module 220 may be a subtractor. In other examples, the fourth filter 240 may be other types of filters, and the destraightening module 220 may be other types of devices, which are not limited here.

[0115] Specifically, each acquisition submodule first acquires the voltage signal at one end of the reference resistor 111, and maintains high input impedance and high drive output capability through the operational amplifier follower module 210. Then, a subtractor is used to remove the DC component in the voltage signal to obtain a voltage signal to be solved. The multiplier 230 is used to perform hardware solution on the voltage signal to be solved, and then a sixth-order low-pass filter is used to filter the first process voltage signal obtained after the solution to generate a second process voltage signal. Finally, the second process voltage signal is given to the analog-to-digital conversion module 260 through the differential conversion module 250, and the analog-to-digital conversion module 260 uses the communication interface to send the first solution value, the second solution value, the third solution value or the fourth solution value to the processing unit 140.

[0116] In this embodiment, the step of generating the gate impedance model of the field effect transistor based on the solution signal performed by the processing unit 140 may specifically include: combining the first solution value, the second solution value, the third solution value and the fourth solution value to determine the amplitude and phase of the voltage signal across the reference resistor 111. The gate impedance model is constructed based on the amplitude and phase of the voltage signal across the reference resistor 111. It can be understood that the gate impedance model can be constructed based on the amplitude and phase of the voltage signal using a conventional algorithm in the technical field, and the algorithm for constructing the gate impedance model is not described in detail or limited in the embodiment of the present application.

[0117] Specifically, the first solution value in this embodiment may include a relationship between the voltage signal at the first end of the reference resistor 111 and the first sampling signal, the second solution value may include a relationship between the voltage signal at the first end of the reference resistor 111 and the second sampling signal, the third solution value may include a relationship between the voltage signal at the second end of the reference resistor 111 and the first sampling signal, and the fourth solution value may include a relationship between the voltage signal at the second end of the reference resistor 111 and the second sampling signal.

[0118] In one example, the first solution value, the second solution value, the third solution value, and the fourth solution value may be respectively , wherein A1 refers to the amplitude of the voltage signal at the first end of the reference resistor 111, A2 refers to the amplitude of the voltage signal at the second end of the reference resistor 111, A3 refers to the amplitude of the first sampling signal, and A4 refers to the amplitude of the second sampling signal. refers to the phase of the voltage signal at the first end of the reference resistor 111, Refers to the phase of the voltage signal at the second end of the reference resistor 111. By combining the first solution value, the second solution value, the third solution value and the fourth solution value, the amplitude (A1, A2) and the phase ( ). Then, the gate impedance model is constructed based on the amplitude and phase of the voltage signal across the reference resistor 111, wherein A3 and A4 are known quantities.

[0119] In another embodiment, if Figure 8 As shown, the solution signal may include a fifth solution value and a sixth solution value, and the gate state acquisition unit 130 includes a fifth acquisition submodule 135 and a sixth acquisition submodule 136 .

[0120] The fifth acquisition submodule 135 is connected to the first end of the reference resistor 111, and is used to acquire the voltage signal of the first end of the reference resistor 111, and process the voltage signal of the first end of the reference resistor 111 to generate the fifth solution value. The sixth acquisition submodule 136 is connected to the second end of the reference resistor 111, and is used to acquire the voltage signal of the second end of the reference resistor 111, and process the voltage signal of the second end of the reference resistor 111 to generate the sixth solution value.

[0121] like Figure 9 As shown, each acquisition submodule may include: an operational amplifier follower module 210 , a de-straightening module 220 , a differential conversion module 250 and an analog-to-digital conversion module 260 .

[0122] The operational amplifier follower module 210 is connected to one end of the reference resistor 111, and is used to collect the voltage signal at one end of the reference resistor 111. The DC removal module 220 is connected to the operational amplifier follower module 210, and is used to remove the DC component in the voltage signal to generate a voltage signal to be solved. The differential conversion module 250 is connected to the DC removal module 220, and is used to perform differential conversion on the voltage signal to be solved to generate a fourth process voltage signal. The analog-to-digital conversion module 260 is connected to the differential conversion module 250, and is used to perform analog-to-digital conversion on the fourth process voltage signal to generate a fifth solution value or a sixth solution value.

[0123] In one example, the destrapping module 220 may be a subtractor. In other examples, the destrapping module 220 may be other types of devices, which are not limited here.

[0124] Specifically, each acquisition submodule first acquires the voltage signal at one end of the reference resistor 111, and maintains high input impedance and high drive output capability through the operational amplifier follower module 210. Then, a subtractor is used to remove the DC component in the voltage signal to obtain a voltage signal to be solved. Finally, the voltage signal to be solved is given to the analog-to-digital conversion module 260 through the differential conversion module 250, and the analog-to-digital conversion module 260 uses the communication interface to send the fifth solution value and the sixth solution value to the processing unit 140.

[0125] In this embodiment, the step of generating the gate impedance model of the field effect transistor based on the solution signal performed by the processing unit 140 may specifically include: solving the fifth solution value and the sixth solution value based on the first sampling signal and the second sampling signal output by the excitation signal generating unit 120 to obtain the first operation value, the second operation value, the third operation value and the fourth operation value. The first operation value, the second operation value, the third operation value and the fourth operation value are combined to determine the amplitude and phase of the voltage signal across the reference resistor 111. Based on the amplitude and phase of the voltage signal across the reference resistor 111, a gate impedance model is constructed.

[0126] In this embodiment, the module for implementing hardware solution composed of the multiplier 230 and the fourth filter 240 in the above embodiment is deleted, and the hardware solution function is implemented by the processing unit 140. Specifically, the first operation value in this embodiment may include the relationship between the voltage signal at the first end of the reference resistor 111 and the first sampling signal, the second operation value may include the relationship between the voltage signal at the first end of the reference resistor 111 and the second sampling signal, the third operation value may include the relationship between the voltage signal at the second end of the reference resistor 111 and the first sampling signal, and the fourth operation value may include the relationship between the voltage signal at the second end of the reference resistor 111 and the second sampling signal. It can be understood that the steps of respectively solving the first solution value, the second solution value, the third solution value and the fourth solution value to obtain the first solution value, the second solution value, the third solution value and the fourth solution value are equivalent to the functions implemented by the multiplier 230 and the fourth filter 240 in the above embodiment, and are not repeated here.

[0127] It should be noted that the gate impedance characteristic test device 100 of the field effect transistor provided in the above embodiment, when realizing its function, only uses the division of the above functional modules as an example. In actual application, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the device provided in the above embodiment and the corresponding method embodiment belong to the same concept, and the specific implementation process is detailed in the corresponding method embodiment, which will not be repeated here.

[0128] An embodiment of the present application further provides an electronic device, such as Figure 10 As shown, the electronic device 10 includes the gate impedance characteristic testing device 100 of the field effect transistor provided in the above embodiment, and the gate impedance characteristic testing device 100 of the field effect transistor will not be elaborated here.

[0129] The above is the preferred embodiment of the present application. It should be noted that for those of ordinary skill in the art, without departing from the principle described in the present application, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present application.

Claims

1. A gate impedance characteristic testing device for a field effect transistor, characterized in that: include: A driving unit connected to the field effect transistor, and used to input a driving signal to the field effect transistor to control the field effect transistor to turn on or off; wherein the driving unit includes a reference resistor, and the reference resistor is used to connect the gate of the field effect transistor; an excitation signal generating unit connected to the driving unit and used to input a first excitation signal to the driving unit when the driving unit inputs a shutdown signal to the gate of the field effect transistor, so as to add an AC excitation to the shutdown signal output by the driving unit, wherein the excitation signal generating unit comprises: a signal generator, used to output an initial excitation signal, wherein the initial excitation signal comprises an orthogonal first initial signal and a second initial signal; a first filter, connected to the signal generator, used to filter the first initial signal to generate a first smoothed signal; a second filter, connected to the signal generator, used to filter the second initial signal to generate a second smoothed signal; and a a third filter connected to the signal generator, used for filtering the first initial signal to generate a third smoothed signal; a first DC blocking capacitor connected to the first filter, used for isolating the DC bias in the first smoothed signal to generate the first excitation signal; a second DC blocking capacitor connected to the second filter and the gate state acquisition unit, used for isolating the DC bias in the second smoothed signal to generate a first sampling signal; a third DC blocking capacitor connected to the third filter and the gate state acquisition unit, used for isolating the DC bias in the third smoothed signal to generate a second sampling signal; and a gate state acquisition unit connected to both ends of the reference resistor to acquire the DC bias in the reference resistor. The gate state acquisition unit includes the following four acquisition submodules: a first acquisition submodule, connected to the first end of the reference resistor and the second DC blocking capacitor, for acquiring the voltage signal at the first end of the reference resistor and the first sampling signal, and processing the voltage signal at the first end of the reference resistor and the first sampling signal to generate the first solution value; a second acquisition submodule, connected to the first end of the reference resistor and the third DC blocking capacitor, for acquiring the voltage signal at the first end of the reference resistor and the second sampling signal to generate the first solution value; and a sampling signal, processing the voltage signal at the first end of the reference resistor and the second sampling signal to generate the second solution value; a third acquisition submodule, connected to the second end of the reference resistor and the second DC blocking capacitor, for collecting the voltage signal at the second end of the reference resistor and the first sampling signal, processing the voltage signal at the second end of the reference resistor and the first sampling signal to generate the third solution value; a fourth acquisition submodule, connected to the second end of the reference resistor and the third DC blocking capacitor, for collecting the voltage signal at the second end of the reference resistor and the second sampling signal, processing the voltage signal at the second end of the reference resistor and the second sampling signal to generate the fourth solution value; a processing unit connected to the gate state acquisition unit, configured to receive the solution signal and generate a gate impedance model of the field effect transistor based on the solution signal; The first solution value, the second solution value, the third solution value and the fourth solution value may be respectively , wherein A1 refers to the amplitude of the voltage signal at the first end of the reference resistor, A2 refers to the amplitude of the voltage signal at the second end of the reference resistor, A3 refers to the amplitude of the first sampling signal, and A4 refers to the amplitude of the second sampling signal, refers to the phase of the voltage signal at the first end of the reference resistor, Refers to the phase of the voltage signal at the second end of the reference resistor. By combining the first solution value, the second solution value, the third solution value and the fourth solution value, the amplitude (A1, A2) and phase ( ), a gate impedance model is constructed based on the amplitude and phase of the voltage signal across the reference resistor.

2. The gate impedance characteristic testing device according to claim 1, characterized in that: The excitation signal generating unit comprises: A signal generator, configured to output an initial excitation signal, wherein the initial excitation signal comprises an orthogonal first initial signal and a second initial signal; A first filter, connected to the signal generator, configured to filter the first initial signal to generate a first smoothed signal; A second filter, connected to the signal generator, for filtering the second initial signal to generate a second smoothed signal; a third filter, connected to the signal generator, configured to filter the first initial signal to generate a third smoothed signal; A first amplitude modulator, connected to the first filter, for performing amplitude proportional modulation on the first smoothed signal to generate a first intermediate signal with a first preset amplitude; a first DC blocking capacitor connected to the first amplitude modulator and configured to isolate a DC bias in the first intermediate signal to generate the first excitation signal; A second amplitude modulator, connected to the second filter, for performing amplitude proportional modulation on the second smoothed signal to generate a second intermediate signal with a second preset amplitude; a second DC blocking capacitor connected to the second amplitude modulator and the gate state acquisition unit, and used for isolating a DC bias in the second intermediate signal to generate a first sampling signal; A third amplitude modulator, connected to the third filter, for performing amplitude proportional modulation on the third smoothed signal to generate a third intermediate signal with a third preset amplitude; A third DC blocking capacitor is connected to the third amplitude modulator and the gate state acquisition unit, and is used to isolate the DC bias in the third intermediate signal to generate a second sampling signal.

3. The gate impedance characteristic testing device according to claim 1, characterized in that: Each of the acquisition submodules includes: An operational amplifier follower module is connected to one end of the reference resistor and is used to collect a voltage signal at one end of the reference resistor; A DC removal module, connected to the operational amplifier follower module, for removing the DC component in the voltage signal to generate a voltage signal to be solved; a multiplier connected to the DC removal module and the second DC blocking capacitor or the third DC blocking capacitor, and configured to solve the voltage signal to be solved and the first sampling signal or the second sampling signal to generate a first process voltage signal; a fourth filter, connected to the multiplier, and configured to filter the first process voltage signal to generate a second process voltage signal; a differential conversion module, connected to the second filter, and configured to perform differential conversion on the second process voltage signal to generate a third process voltage signal; The analog-to-digital conversion module is connected to the differential conversion module and is used to perform analog-to-digital conversion on the third process voltage signal to generate the first solution value, the second solution value, the third solution value or the fourth solution value.

4. The gate impedance characteristic testing device according to claim 3, characterized in that: The step of generating a gate impedance model of the field effect transistor based on the solution signal comprises: Determine the amplitude and phase of the voltage signal across the reference resistor by combining the first solution value, the second solution value, the third solution value and the fourth solution value; The gate impedance model is constructed based on the amplitude and phase of the voltage signal across the reference resistor.

5. The gate impedance characteristic testing device according to claim 1, characterized in that: The solution signal includes a fifth solution value and a sixth solution value, and the gate state acquisition unit includes the following two acquisition submodules: a fifth acquisition submodule, connected to the first end of the reference resistor, for acquiring a voltage signal at the first end of the reference resistor, and processing the voltage signal at the first end of the reference resistor to generate the fifth solution value; The sixth acquisition submodule is connected to the second end of the reference resistor, and is used to acquire the voltage signal at the second end of the reference resistor, and process the voltage signal at the second end of the reference resistor to generate the sixth solution value.

6. The gate impedance characteristic testing device according to claim 5, characterized in that: Each of the acquisition submodules includes: An operational amplifier follower module is connected to one end of the reference resistor and is used to collect a voltage signal at one end of the reference resistor; A DC removal module, connected to the operational amplifier follower module, for removing the DC component in the voltage signal to generate a voltage signal to be solved; A differential conversion module, connected to the descaling module, for performing differential conversion on the voltage signal to be resolved to generate a fourth process voltage signal; The analog-to-digital conversion module is connected to the differential conversion module and is used to perform analog-to-digital conversion on the fourth process voltage signal to generate the fifth solution value or the sixth solution value.

7. The gate impedance characteristic testing device according to claim 6, characterized in that: The step of generating a gate impedance model of the field effect transistor based on the solution signal comprises: Based on the first sampling signal and the second sampling signal output by the excitation signal generating unit, the fifth solution value and the sixth solution value are solved to obtain a first operation value, a second operation value, a third operation value and a fourth operation value; Combine the first operation value, the second operation value, the third operation value and the fourth operation value to determine the amplitude and phase of the voltage signal across the reference resistor; The gate impedance model is constructed based on the amplitude and phase of the voltage signal across the reference resistor.

8. The gate impedance characteristic testing device according to claim 1, characterized in that: The processing unit is further configured to be connected to the excitation signal generating unit, and to trigger the excitation signal generating unit to input the first excitation signal to the driving unit when the driving unit inputs the shutdown signal to the gate of the field effect transistor.

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