A Method and Platform for Leakage Current Test and Analysis of a Low-Power Chip

Abstract

The present invention discloses a method and platform for leakage current test and analysis of a low-power chip, belonging to the field of semiconductor testing. The method includes: collecting chip characteristic data of a target low-power chip to determine multiple environmental parameter test ranges and working voltage test ranges of the target low-power chip; generating an environmental test sequence and a voltage test sequence, combining the environmental test sequence and the voltage test sequence to generate an adaptive test scheme; constructing a leakage current data matrix based on the adaptive test scheme; obtaining a first analysis result; obtaining a second analysis result; and obtaining an evaluation result of the leakage current characteristics of the target low-power chip based on the first analysis result and the second analysis result. This application solves the technical problem in the prior art that the leakage current test conditions are single, and it is difficult to comprehensively evaluate the characteristics of a low-power chip under multiple environmental parameters and voltage conditions, resulting in insufficient accuracy and applicability of the test results.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor testing, and particularly to a method and platform for leakage current testing and analysis of low-power chips. Background Art

[0002] With the popularization of electronic devices and the diversification of application scenarios, low-power chips play an important role in fields such as the Internet of Things, mobile devices, and smart wearables. The application of low-power chips requires the device to maintain low power consumption while working efficiently, in order to extend the battery life of the device or reduce energy consumption.

[0003] Currently, the leakage current testing of low-power chips mostly relies on standardized testing methods, that is, testing is carried out in the laboratory with fixed environmental parameters and working voltage ranges. Although this method can basically meet the needs of product testing, it is difficult to cover the variable environments of the chip in actual application scenarios. And traditional testing schemes often cannot flexibly adapt to these changes, resulting in limited practical reference value of the test results. Therefore, there is an urgent need for a method and platform for leakage current testing and analysis of low-power chips to solve the technical problems in the prior art that the leakage current testing conditions are single, it is difficult to comprehensively evaluate the characteristics of low-power chips under multiple environmental parameters and voltage conditions, resulting in insufficient accuracy and applicability of the test results. Summary of the Invention

[0004] This application provides a method and platform for leakage current testing and analysis of low-power chips, aiming to solve the technical problems in the prior art that the leakage current testing conditions are single, it is difficult to comprehensively evaluate the characteristics of low-power chips under multiple environmental parameters and voltage conditions, resulting in insufficient accuracy and applicability of the test results.

[0005] In view of the above problems, this application provides a method and platform for leakage current testing and analysis of low-power chips.

[0006] In the first aspect disclosed in the present application, a method for testing and analyzing the leakage current of a low-power chip is provided. The method includes collecting chip characteristic data of a target low-power chip, determining multiple environmental parameter test ranges and a working voltage test range of the target low-power chip according to the chip characteristic data, where the multiple environmental parameter test ranges include a temperature test range, a humidity test range, and an electromagnetic interference test range; generating an environmental test sequence according to the multiple environmental parameter test ranges, generating a voltage test sequence according to the working voltage test range, combining the environmental test sequence and the voltage test sequence to generate an adaptive test scheme; setting environmental parameters and applying a working voltage based on the adaptive test scheme, obtaining leakage current test data of the target low-power chip through a current sensor, and constructing a leakage current data matrix from the leakage current test data; sequentially extracting row vector data of the leakage current data matrix, analyzing the voltage-leakage current characteristics under the same environmental parameter conditions to obtain a first analysis result; sequentially extracting column vector data of the leakage current data matrix, analyzing the environmental-leakage current characteristics under the same working voltage conditions to obtain a second analysis result; and performing an association evaluation on the target low-power chip based on the first analysis result and the second analysis result to obtain an evaluation result of the leakage current characteristics of the target low-power chip.

[0007] In another aspect disclosed in the present application, a platform for testing and analyzing the leakage current of a low-power chip is provided. The platform includes a chip characteristic data acquisition module: used for collecting chip characteristic data of a target low-power chip, determining multiple environmental parameter test ranges and a working voltage test range of the target low-power chip according to the chip characteristic data, where the multiple environmental parameter test ranges include a temperature test range, a humidity test range, and an electromagnetic interference test range; an environmental test sequence generation module: used for generating an environmental test sequence according to the multiple environmental parameter test ranges, generating a voltage test sequence according to the working voltage test range, and combining the environmental test sequence and the voltage test sequence to generate an adaptive test scheme; a leakage current test data acquisition module: used for setting environmental parameters and applying a working voltage based on the adaptive test scheme, obtaining leakage current test data of the target low-power chip through a current sensor, and constructing a leakage current data matrix from the leakage current test data; a first analysis result acquisition module: used for sequentially extracting row vector data of the leakage current data matrix, analyzing the voltage-leakage current characteristics under the same environmental parameter conditions to obtain a first analysis result; a second analysis result acquisition module: used for sequentially extracting column vector data of the leakage current data matrix, analyzing the environmental-leakage current characteristics under the same working voltage conditions to obtain a second analysis result; and an association evaluation module: used for performing an association evaluation on the target low-power chip based on the first analysis result and the second analysis result to obtain an evaluation result of the leakage current characteristics of the target low-power chip.

[0008] One or more technical solutions provided in this application have at least the following technical effects or advantages:

[0009] Due to the technical solution of determining multiple environmental parameter test ranges and working voltage test ranges based on chip feature data and generating an adaptive test plan, the influence of environmental changes and voltage fluctuations on the test results during the leakage current test of low-power chips is solved, achieving the technical effect of improving the accuracy and stability of test data by precisely controlling test conditions, thereby realizing a comprehensive evaluation of the leakage current characteristics of low-power chips.

[0010] The above description is only an overview of the technical solution of this application. In order to be able to understand the technical means of this application more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features and advantages of this application more obvious and understandable, the following specifically gives the specific implementation manners of this application. Brief Description of the Drawings

[0011] Figure 1 It is a schematic flowchart of a method for analyzing leakage current of a low-power chip provided by an embodiment of this application.

[0012] Figure 2 It is a schematic structural diagram of a platform for analyzing leakage current of a low-power chip provided by an embodiment of this application.

[0013] Description of the reference numerals: Chip feature data acquisition module 11, environmental test sequence generation module 12, leakage current test data acquisition module 13, first analysis result acquisition module 14, second analysis result acquisition module 15, correlation evaluation module 16. Detailed Embodiments

[0014] The general idea of the technical solution provided in this application is as follows:

[0015] An embodiment of this application provides a method and a platform for analyzing leakage current of a low-power chip. By collecting the feature data of the low-power chip, determining the test ranges of its environmental parameters and working voltage, and generating an adaptive test plan. This plan comprehensively considers factors such as temperature, humidity, electromagnetic interference, and voltage changes to conduct leakage current tests, ensuring the accuracy of the test process and the reliability of chip performance evaluation.

[0016] After introducing the basic principle of this application, the following will specifically introduce various non-limiting implementation manners of this application in conjunction with the drawings of the specification.

[0017] Embodiment 1, as Figure 1 shown, an embodiment of this application provides a method for analyzing leakage current of a low-power chip, and the method includes:

[0018] Step S100: Collect the chip characteristic data of the target low-power chip, and determine multiple environmental parameter test ranges and working voltage test ranges for the target low-power chip according to the chip characteristic data, where the multiple environmental parameter test ranges include a temperature test range, a humidity test range, and an electromagnetic interference test range.

[0019] Specifically, chip characteristic data refers to the data describing aspects such as chip performance, structure, and usage conditions, including chip design information, material properties, manufacturing process parameters, etc. It reflects the basic working principle and characteristics of the chip and is the basis for formulating the test plan. The environmental parameter test range represents the range values of the environmental parameters simulated when testing the chip. For example, the upper and lower limit ranges under temperature, humidity, and electromagnetic interference conditions. Different test ranges are used to evaluate the leakage current characteristics of the chip under various environmental change conditions. The working voltage test range refers to the voltage range applied to the chip during testing, usually including the upper and lower fluctuation ranges of the chip's rated working voltage. It is used to evaluate the leakage current performance of the chip under different voltage conditions.

[0020] First, collect the characteristic data of the chip and analyze the chip's working performance under specific conditions with the help of this data. To obtain accurate test ranges, the chip characteristic data can be compared and analyzed with the historical data of multiple similar chips stored in the operation database. Using data analysis tools (such as data processing libraries like Pandas and NumPy in Python), a set of chip samples with similar characteristics can be screened out from the database, and statistical analysis can be performed on the temperature, humidity, and electromagnetic interference conditions experienced by these samples in the actual working environment, so as to determine a reasonable environmental parameter test range. Similarly, by analyzing the concentration intervals of humidity and electromagnetic interference, other environmental parameter test ranges can be obtained.

[0021] Then, use the data analysis tool to set the test range of the working voltage, and the upper and lower limits of the voltage can be calculated by screening and sorting the working voltage data of similar chips. To ensure that the test conditions are close to the actual working environment of the chip.

[0022] By determining the test ranges of the chip's environmental parameters and working voltage, the test plan can simulate the leakage current performance under real working conditions according to the characteristics of the target chip, thereby improving the accuracy and applicability of the test, and making the test results more able to reflect the actual performance of the chip under different environmental and voltage conditions.

[0023] Step S200: Generate an environmental test sequence according to the multiple environmental parameter test ranges, generate a voltage test sequence according to the working voltage test range, and combine the environmental test sequence and the voltage test sequence to generate an adaptive test plan.

[0024] Specifically, an environmental test sequence refers to an ordered set of test points generated based on the test range of environmental parameters (such as temperature, humidity, electromagnetic interference, etc.). These test points are used to simulate different environmental conditions one by one in order to comprehensively evaluate the performance of the chip. For example, the temperature test points may include multiple values such as -20°C, 0°C, 25°C, and 85°C. The voltage test sequence is an ordered set of test points generated based on the operating voltage test range of the chip, covering voltage values from low to high. The voltage test sequence can be used to apply different voltages to observe the change in leakage current of the chip under different voltage conditions, such as multiple voltage points between 0.9V and 1.2V. The adaptive test scheme refers to a test plan formed by combining the environmental test sequence and the voltage test sequence. It contains multiple combinations of environmental and voltage conditions and can flexibly adapt to the characteristics of the chip and environmental changes.

[0025] First, generate their respective test sequences according to the test range of environmental parameters. The test range of environmental parameters usually includes temperature, humidity, and electromagnetic interference ranges. In order to generate the test sequence, each parameter range can be divided.

[0026] Subsequently, arrange and combine these environmental test points to form all possible environmental combination sequences. For the voltage test range, it is also divided into multiple voltage test points, and a voltage test sequence arranged in ascending order is generated.

[0027] Next, combine the environmental test sequence and the voltage test sequence to form an adaptive test scheme in a matrix manner. The rows of the matrix can represent different environmental combinations, the columns represent different voltage conditions, and each element of the matrix represents a combination of environment and voltage. In this way, a test matrix covering the full range is generated to ensure that the tests of the chip under different voltage conditions for each set of environmental parameters are recorded.

[0028] Through the adaptive test scheme, the test system can comprehensively evaluate the leakage current characteristics of the chip under various environmental and voltage conditions. This scheme ensures the extensiveness and representativeness of the test, enabling the leakage current data to reflect the true performance of the chip under different actual conditions, thus providing reliable data support for the quality evaluation and optimization of the chip.

[0029] Step S300: Based on the adaptive test scheme, set the environmental parameters and apply the operating voltage, obtain the leakage current test data of the target low-power chip through a current sensor, and construct a leakage current data matrix with the leakage current test data.

[0030] Specifically, the adaptive test scheme is a test scheme generated according to the specific test requirements of the target chip, which combines different combinations of environmental parameters and operating voltages. The adaptive test scheme aims to simulate the performance of the chip under various actual operating conditions in order to more accurately test the leakage current characteristics of the chip. Environmental parameters refer to the external environmental conditions set during the test, such as temperature, humidity, electromagnetic interference, etc. These parameters will affect the operating state and leakage current performance of the chip. The operating voltage refers to the voltage applied to the chip during operation, which is usually one of the basic driving parameters for chip operation. The leakage current of the chip will vary at different voltages. The current sensor is a sensing device used to detect the operating current of the chip. The leakage current data matrix is a table or matrix structure used to store the leakage current data measured under different environmental parameters and voltage conditions. The rows and columns of the matrix represent different environmental conditions and voltage values respectively, making the data organization clearer and facilitating analysis.

[0031] First, set the environmental parameters and operating voltages according to the adaptive test scheme. For example, when testing the temperature parameter, set the environmental temperature to vary between 0°C, 25°C, and 50°C; the humidity to vary between 40%, 60%, and 80%, and the voltage to vary between 1.0V, 1.1V, and 1.2V. The combination of environment and voltage is the test condition in the adaptive test scheme. Each combination will simulate a different operating environment to help reveal the current performance of the target chip in actual use.

[0032] Next, set each combination of conditions one by one, and measure the leakage current data of the chip under these conditions through the current sensor. The use of the current sensor can be combined with measuring devices such as oscilloscopes or multimeters to collect accurate leakage current readings through high-precision sensors.

[0033] After obtaining the test data for each item, fill these leakage current data into the leakage current data matrix according to different environmental and voltage conditions. Each row in the matrix represents the leakage current data at different voltages under the same environmental conditions, and each column represents the leakage current data at different environments under the same voltage conditions. Such an organized matrix makes the data presentation clear at a glance, facilitating subsequent analysis and chart display.

[0034] Constructing the leakage current data matrix brings intuitive data information, which can clearly show the leakage current performance of the chip under different conditions. Through the analysis of the matrix data, the sensitivity of the leakage current to specific environmental parameters or voltages can be found, helping designers to optimize the chip design targeted, reduce power consumption, and improve the reliability and energy efficiency of the chip in actual applications.

[0035] Step S400: Sequentially extract the row vector data of the leakage current data matrix, analyze the voltage-leakage current characteristics under the same environmental parameter conditions, and obtain the first analysis result.

[0036] Specifically, a row vector refers to the data set of each row in a matrix, representing the variation of leakage current measurement values with voltage under specific environmental parameters. By extracting the row vector, the influence of voltage on leakage current can be observed. The voltage-leakage current characteristic refers to the relationship curve of the leakage current of a chip varying with the operating voltage under fixed environmental parameters. Analyzing this characteristic helps to understand the power consumption trend of the chip at different voltages and to identify abnormal current behaviors. The first analysis result is the preliminary result obtained based on the voltage-leakage current characteristic, revealing the current performance of the chip under different environmental parameters and contributing to subsequent power consumption optimization.

[0037] First, row vector data is extracted row by row from the leakage current data matrix, that is, under the same environmental parameters (such as fixed temperature and humidity), the leakage current values of the chip under different voltage conditions are obtained. Next, based on these row vectors, the voltage-leakage current characteristic curve is plotted. This can be done using data processing tools such as Matplotlib in Python or Excel, which plot each row vector data as a curve on a graph to visually display the relationship curve between voltage and leakage current. Generally, as the voltage increases, the leakage current shows a specific upward trend. However, if there are obvious deviations or abnormal points in the curve (such as a sudden increase or instability of the leakage current), it may reflect the working reliability problem of the chip under this condition.

[0038] By analyzing the voltage-leakage current characteristic through row vectors, the leakage current performance and voltage response characteristics of the chip under different environmental parameters can be visually identified. This analysis helps to identify the power consumption bottlenecks and reliability problems of the chip and provides an optimization direction.

[0039] Step S500: Sequentially extract the column vector data of the leakage current data matrix, analyze the environment-leakage current characteristic under the same operating voltage condition, and obtain the second analysis result.

[0040] Specifically, in the column vector data, a column vector refers to each column of data extracted from the leakage current data matrix. Each column represents the leakage current data under different environmental conditions under the same voltage condition. The environment-leakage current characteristic refers to the performance of the leakage current varying with the environment

[0041] under different environmental conditions. It helps to understand the influence of different environments on the leakage current performance of the chip. The second analysis result is the analysis conclusion obtained based on the column vector data (that is, analyzing the influence of different environmental conditions on the leakage current under the same operating voltage condition). It helps to understand the environmental sensitivity of the chip's leakage current under the same voltage condition and provides data support for further optimization.

[0042] First, it is necessary to extract the column vector data of the leakage current data matrix. The leakage current data matrix contains the leakage current test data under different environmental and voltage conditions. Each column corresponds to a different voltage test point, and each row corresponds to a different environmental condition.

[0043] Next, analyze the environment-leakage current characteristics under the same operating voltage condition. This analysis means focusing on the data in the same column and comparing the trend of the leakage current changing with the environment under different environmental conditions. This process is usually completed by methods such as statistical analysis or curve fitting. For example, by plotting the curve of the leakage current changing with temperature, the changing trend of the leakage current at different temperatures can be intuitively seen. If the leakage current increases significantly with the increase of temperature, it indicates that the leakage current of the chip is more sensitive to temperature. The analysis process can be carried out using statistical analysis tools or data processing software (such as MATLAB, NumPy, SciPy libraries in Python, etc.). For example, in Python, NumPy can be used to process the data matrix. By extracting the column vector and performing numerical analysis, the relationship between the leakage current and the environmental conditions can be found.

[0044] The generation of the second analysis result is based on the summary of the analysis results of the column vector data, usually the curve of the leakage current changing with the environmental conditions or a comprehensive evaluation. Through this analysis result, the stability of the chip under different environments can be understood, and possible optimization directions can be found.

[0045] By sequentially extracting the column vector data of the leakage current data matrix and analyzing the environmental characteristics of the leakage current under the same voltage condition, the performance fluctuations of the chip under different environmental conditions can be revealed. Through this analysis, the sensitivity of the chip to environmental changes at a specific voltage can be clarified, which provides an important basis for the design optimization and application scenario selection of the chip.

[0046] Step S600: Based on the first analysis result and the second analysis result, conduct a correlation evaluation on the target low-power chip to obtain the evaluation result of the leakage current characteristics of the target low-power chip.

[0047] Specifically, the correlation evaluation combines the first analysis result and the second analysis result for comprehensive analysis to obtain a more comprehensive evaluation result of the leakage current characteristics. It can reveal the comprehensive behavior of the leakage current under different environmental and voltage conditions, thereby helping to evaluate the overall performance of the target low-power chip. The evaluation result of the leakage current characteristics is the final conclusion after combining the first analysis result and the second analysis result, evaluating the leakage current performance of the target chip. This evaluation result usually includes the fluctuations of the leakage current under various environmental and voltage conditions, as well as the stability and reliability of the chip.

[0048] First, a correlation assessment needs to be performed based on the first analysis result and the second analysis result. First, the first analysis result provides the characteristics of the leakage current varying with voltage under different environmental conditions; while the second analysis result provides the influence of environmental factors on the leakage current under the same voltage condition. Combining these two analysis results can comprehensively evaluate the performance of the chip in a complex environment.

[0049] Integrate the first and second analysis results. First, match and integrate the results obtained from the voltage-leakage current characteristic analysis under environmental parameter conditions and the environment-leakage current characteristic analysis under the same operating voltage condition. For example, if the first analysis result shows that the leakage current will increase significantly in a high-temperature environment, and the second analysis result shows that the leakage current will also increase in a high-humidity environment, then these factors can be combined to evaluate the overall performance of the chip.

[0050] By correlating the two analysis results, we can obtain the comprehensive characteristics of the leakage current under different environments and voltages. This process can adopt methods such as weighted calculation, regression analysis, or multi-dimensional data analysis.

[0051] Through this correlation assessment step, the evaluation result of the leakage current characteristics of the target chip can be accurately obtained. This evaluation result helps to provide a direction for the optimization of the chip. Especially in the design stage, potential problems can be discovered in advance, such as excessive leakage current or too high sensitivity to the environment, so as to optimize the materials and design of the chip to make it more adaptable to various environmental conditions in actual applications.

[0052] Furthermore, determine multiple environmental parameter test ranges and operating voltage test ranges for the target low-power chip according to the chip characteristic data. Among them, the multiple environmental parameter test ranges include a temperature test range, a humidity test range, and an electromagnetic interference test range, including: constructing a retrieval constraint according to the chip characteristic data, performing data retrieval in the chip operation database based on the retrieval constraint, and obtaining a set of similar chip operation samples, including multiple similar chip operation samples. Among them, each similar chip operation sample has corresponding chip operation environment data and chip operating voltage data; performing a centralized interval analysis on multiple environmental parameters in the chip operation environment data of multiple similar chip operation samples, obtaining a centralized interval of multiple environmental parameters, and forming an environmental parameter test range, where the multiple environmental parameters at least include temperature, humidity, and electromagnetic interference; performing a centralized interval analysis on the chip operating voltage data of multiple similar chip operation samples to obtain an operating voltage test range.

[0053] Specifically, retrieval constraints refer to the rules or conditions for screening data that meet specific conditions from a database. These constraints are usually formulated based on the characteristic data of the chip (such as design parameters or processes) and are used to lock in chip data samples that are similar to the target chip characteristics. The set of similar chip operation samples refers to a group of chip data screened out from the database that are similar to the target chip in terms of performance, process, or operating conditions. These samples contain the operation data of this type of chip under different environmental and voltage conditions and are an important reference for setting the subsequent test scope. Central interval analysis refers to determining the interval where data is concentrated by statistically analyzing the distribution range of a certain parameter of similar chips in the operating environment. The central interval represents the actual operating condition range of most chips and provides a reference basis for formulating the test scope.

[0054] First, based on the characteristic data of the target chip (such as manufacturing process, operating frequency, etc.), retrieval constraint conditions are set to screen out a set of similar chip operation samples that meet specific conditions. Retrieval tools usually use database query statements (such as SQL queries) to extract chip data that meet the conditions from the chip operation database. Suppose the design process of the target chip is 28nm and the operating frequency is 1GHz, then the retrieval condition can be "process = 28nm AND frequency = 1GHz" to screen out chip sample data with similar processes and frequencies.

[0055] Next, based on the screened similar chip samples, central interval analysis is performed on the chip operating environment data to determine a reasonable test range for environmental parameters. Central interval analysis can be achieved through statistical tools (such as the statistical libraries Pandas, SciPy, etc. in Python). Taking the temperature parameter as an example, suppose the operating temperature of similar chips mainly concentrates between 0°C and 70°C, then 0°C to 70°C can be used as the temperature test range. Similarly, by statistically analyzing the distribution of humidity and electromagnetic interference, appropriate humidity and electromagnetic interference test ranges can be obtained.

[0056] For the central interval analysis of the operating voltage data, the operating voltage data of the screened similar chips is usually sorted and statistically analyzed to obtain the voltage range.

[0057] The test ranges of environmental parameters and voltage obtained by this method can be closer to the actual operating environment of the chip, enhancing the applicability and accuracy of the test scheme, enabling the leakage current characteristic test of the target chip to more effectively reflect its performance under real operating conditions, improving the reliability of the test results, and providing accurate reference data for subsequent chip optimization.

[0058] Furthermore, perform a centralized interval analysis on the chip operating voltage data of multiple similar chip operation samples to obtain the operating voltage test range, including: sorting the chip operating voltage data of multiple similar chip operation samples from largest to smallest in terms of value to obtain the voltage data sorting result, and determining the voltage median according to the voltage data sorting result; extracting the maximum voltage value in the voltage data sorting result, and obtaining the median between the voltage median and the maximum voltage value as the test voltage upper limit value; extracting the minimum voltage value in the voltage data sorting result, and obtaining the median between the minimum voltage value and the voltage median as the test voltage lower limit value; generating the operating voltage test range according to the test voltage upper limit value and the test voltage lower limit value.

[0059] Specifically, the voltage data sorting result refers to the data set obtained by arranging the operating voltage data of multiple chip samples from largest to smallest or from smallest to largest in terms of value. It can better understand the voltage distribution. The median refers to the data value in the middle position in the sorted data set. The median is often used to eliminate the influence of extreme values on the analysis result. The test voltage upper limit value is the middle value between the voltage median and the maximum voltage value; the lower limit value is the middle value between the voltage median and the minimum voltage value.

[0060] First, we extract the operating voltage data of similar chips from the database and sort these data from largest to smallest. The sorting can be achieved through programming tools. For example, in Python, the sorted() function is used to sort the data. After sorting, find the median of the voltage according to the sorting result in the data set. Then, extract the maximum and minimum values from the sorting result, and calculate the median between the median and the maximum value, as well as the median between the median and the minimum value respectively.

[0061] Finally, use the calculated upper limit value and lower limit value as the boundary values of the test voltage to generate the voltage test range, which will be used for subsequent leakage current characteristic tests to be closer to the actual working environment of the chip.

[0062] The voltage test range obtained by this method can focus the test on the voltage interval where the chip actually operates, avoiding meaningless extreme values. This not only improves the test efficiency but also can more accurately reflect the leakage current characteristics of the chip within the true voltage range, providing efficient data support for the reliability analysis and optimization of the chip.

[0063] Further, an environmental test sequence is generated according to the multiple environmental parameter test ranges, and a voltage test sequence is generated according to the operating voltage test range. The environmental test sequence and the voltage test sequence are combined to generate an adaptive test scheme, including: dividing the temperature test range into multiple temperature test points according to a temperature step size, dividing the humidity test range into multiple humidity test points according to a humidity step size, and dividing the electromagnetic interference test range into multiple electromagnetic interference test points according to an electromagnetic interference step size; performing permutation and combination on the multiple temperature test points, multiple humidity test points, and multiple electromagnetic interference test points to generate an environmental parameter combination set; screening the environmental parameter combination set based on a preset environmental parameter combination constraint to obtain an effective environmental parameter combination set, and generating the environmental test sequence, where the environmental parameter combination constraint is a combination restriction condition set based on physical laws, actual application scenarios, and chip characteristic data; dividing the operating voltage test range into multiple voltage test points according to a voltage step size, and generating the voltage test sequence in ascending order; combining the environmental test sequence and the voltage test sequence in matrix form to generate the adaptive test scheme.

[0064] Specifically, the temperature test range, humidity test range, and electromagnetic interference test range are parameter ranges set to simulate the operating conditions of the chip under different environmental conditions. The temperature test range indicates the temperature range within which the test is conducted, the humidity test range indicates the humidity range of the test environment, and the electromagnetic interference test range indicates the intensity range of the electromagnetic interference applied during the test. The temperature step size, humidity step size, and electromagnetic interference step size are interval values used to divide the test range into several test points. The environmental parameter combination set is a data set obtained by performing permutation and combination on the test points of multiple environmental parameters such as temperature, humidity, and electromagnetic interference. These combinations represent various situations for testing the chip under different environmental conditions. The environmental parameter combination constraint is used to screen out combinations that are meaningful for evaluating the chip performance from the environmental parameter combination set. These constraint conditions are set based on the physical characteristics of the chip design, environmental changes in the actual application scenario, and the operating characteristics of the chip. The voltage test range refers to the range of operating voltages that the chip can withstand, and the voltage test sequence divides this range into multiple test points according to a certain step size to gradually apply different voltages for testing. The adaptive test scheme combines the environmental test sequence and the voltage test sequence in matrix form to generate a scheme covering all necessary test conditions. It can adaptively perform leakage current tests according to environmental changes and voltage changes.

[0065] First, based on the test ranges of temperature, humidity, and electromagnetic interference, divide these ranges into multiple test points at a predetermined step size. For example, if the temperature test range is from -20°C to 80°C and the temperature step size is 10°C, then the temperature test points will include -20°C, 0°C, 10°C, 20°C, etc., up to 80°C. Similarly, if the humidity range is from 20% to 90% and the humidity step size is 10%, multiple humidity test points are obtained.

[0066] Then, arrange and combine the test points of temperature, humidity, and electromagnetic interference to obtain a set of environmental parameter combinations. For example, assume there are 4 temperature test points, 3 humidity test points, and 2 electromagnetic interference test points. Then, arranging and combining the test points of these three parameters can result in 4×3×2 = 24 different environmental combinations. These combinations will simulate the working conditions of the chip under various environmental conditions.

[0067] Next, based on the preset constraints of environmental parameter combinations, filter out the effective environmental combinations that are practically meaningful for testing. For example, if certain environmental combinations (such as high humidity at extremely low temperatures) have no significant impact on the performance of the chip, or the occurrence frequency of these environmental combinations is low, then these combinations can be excluded, and finally a valid environmental test sequence is obtained. At the same time, the voltage test range will be divided into multiple test points according to the voltage step size.

[0068] Finally, combine the environmental test sequence and the voltage test sequence in matrix form. For example, each row can represent an environmental combination, and each column represents the tests at different voltage points under that environmental combination. In this way, all necessary environmental and voltage conditions can be covered in a unified test plan.

[0069] This step ensures that the leakage current performance of the low-power chip can be fully tested under various environmental and voltage conditions by generating a comprehensive adaptive test plan. This method not only improves the test coverage but also avoids unnecessary redundant tests through the fine division of environmental parameters and voltage, thus saving time and cost. By screening the effective environmental combinations, the test conditions can be further optimized, making the leakage current test of the chip more accurate and efficient. Ultimately, this will enhance the stability of the chip against environmental changes and voltage fluctuations in practical applications and ensure its reliability under various working conditions.

[0070] Further, successively extract the row vector data of the leakage current data matrix, analyze the voltage-leakage current characteristics under the same environmental parameter conditions, and obtain the first analysis result, including: obtaining the expected voltage-leakage current characteristics under different environmental parameter conditions, generating multiple expected voltage-leakage current curves; extracting the first expected voltage-leakage current curve under the first environmental parameter conditions; according to the leakage current data matrix, extracting the row vector data under the first environmental parameter conditions to obtain the corresponding actual voltage-leakage current characteristics, and generating the first actual voltage-leakage current curve; based on the expected voltage-leakage current curve, performing deviation evaluation on the actual voltage-leakage current curve to obtain the first curve evaluation result, and adding it to the multiple curve evaluation results; according to the multiple curve evaluation results, generating the first analysis result.

[0071] Specifically, the expected voltage-leakage current characteristic is a voltage-leakage current curve based on theory or design expectation, which is used to compare with the actual measurement result. It represents the ideal leakage current performance of the chip under a certain specific environmental parameter. The actual voltage-leakage current characteristic is the data obtained based on actual tests, which represents the relationship between the voltage and leakage current of the chip in the actual test environment. The deviation evaluation is to compare the actual voltage-leakage current curve with the expected voltage-leakage current curve, calculate the difference between the two, and evaluate the performance deviation of the chip under actual conditions. The curve evaluation result is the data obtained after summarizing the deviation evaluation results between the expected curve and the actual curve, which reflects the deviation degree of the chip leakage current characteristic.

[0072] First, a leakage current data matrix is established. By testing the leakage current under different environmental conditions (such as temperature, humidity, electromagnetic interference) and voltages, a data matrix is generated. For example, assume the temperature is 25°C, the humidity is 60%, and the voltage changes from 0V to 3.3V in steps of 0.3V. Finally, a matrix is generated, and each row represents the leakage current data under a certain environmental condition.

[0073] Next, extract the row vector data: successively extract the data of each row from the matrix. For example, if the current environmental condition is a temperature of 25°C and a humidity of 60%, then extract all the voltage points and the corresponding leakage current values that match this environmental condition to form a set of data. Then, generate the expected voltage-leakage current curve: according to the theoretical design or expected performance of the chip, generate an expected voltage-leakage current curve. This expected curve represents the ideal performance of the chip in a normal environment. For example, assume the expected curve is an approximate linear or exponential relationship, which describes how the leakage current should change at each voltage point.

[0074] Next, extract the actual voltage - leakage current characteristics: Extract the row vector data that conforms to the actual test conditions from the leakage current data matrix. Based on this data, plot the actual voltage - leakage current curve. Then, compare the actual voltage - leakage current curve with the expected voltage - leakage current curve. By calculating the difference between the two curves, a deviation evaluation result can be obtained, reflecting the deviation between the chip's actual working environment and its expected performance.

[0075] Finally, generate the first analysis result: By evaluating the deviations between the expected curves and the actual curves under multiple environmental conditions, summarize all the evaluation results to generate the first analysis result. This result can provide detailed information about the chip's performance, identify potential problems, and optimize them.

[0076] This step, by extracting the leakage current data matrix and conducting a detailed analysis, can help developers deeply understand the chip's working characteristics, especially the leakage current characteristics, under various environmental conditions. By comparing with the expected voltage - leakage current curve, problems in the chip design can be discovered in a timely manner, and the reliability and performance of the chip can be optimized. Ultimately, this helps to improve the chip's stability and adaptability, ensuring its performance meets the expected requirements in actual applications.

[0077] Furthermore, generating the first analysis result according to the multiple curve evaluation results includes: obtaining all - quantity environmental combination data according to the test ranges of multiple environmental parameters; calculating the first environmental weight according to the occurrence frequency of the first environmental parameter condition in the all - quantity environmental combination data, and adding it to the multiple environmental weights; performing a weighted calculation on the multiple environmental weights and the multiple curve evaluation results to obtain the first analysis result.

[0078] Specifically, all - quantity environmental combination data refers to all environmental combination data generated based on the test ranges of multiple environmental parameters (such as temperature, humidity, electromagnetic interference, etc.). It includes all environmental condition combinations and is used to comprehensively evaluate the chip's performance under different conditions. Environmental weight refers to the weight value corresponding to the occurrence frequency of a specific environmental condition or combination in the all - quantity environmental combination data. An environmental condition with a high weight represents that this condition appears more frequently during the test and has a greater influence.

[0079] The weighted calculation of the curve evaluation result means combining the curve evaluation results under multiple environmental conditions with the corresponding environmental weights and calculating a comprehensive evaluation result through weighting. This helps to more accurately evaluate the overall performance of the chip under different environmental conditions.

[0080] First, it is necessary to obtain the full set of environmental combination data. This means that for the test range of each environmental parameter (such as temperature range, humidity range, electromagnetic interference range), all possible combination data are generated. The full set of environmental combination data generated in this way is: the cross combination of different temperatures, humidities, and electromagnetic interferences.

[0081] Next, calculate the environmental weights. The environmental weights are determined by calculating the frequency of each environmental condition appearing in the full set of combination data. The weight reflects the importance of this condition to the test results. Then, perform a weighted calculation on the curve evaluation results. After obtaining the curve evaluation results corresponding to each environmental combination, it is necessary to combine the weight of each environmental condition with the corresponding curve evaluation result. For example, assume that under a certain environmental condition, the curve evaluation result shows a large deviation in the chip leakage current, while under another environmental condition, the curve evaluation result is more ideal. By weighting these evaluation results, a more accurate analysis result can be obtained, reflecting the influence of more important environmental conditions on the leakage current performance.

[0082] Finally, generate the first analysis result. Through the weighted calculation, a comprehensive analysis result is finally obtained. This result can reflect the performance of the chip under all environmental conditions and help developers identify the most critical environmental factors, thus providing a basis for subsequent chip optimization.

[0083] Through this method of weighted calculation, the influence of various environmental parameters on the leakage current characteristics can be more accurately considered comprehensively, so as to obtain a more comprehensive and reliable chip performance analysis result. This can not only identify the most influential environmental conditions but also provide a strong basis for chip optimization and adjustment. Ultimately, the performance of the chip in real applications can be significantly improved, reducing potential problems in the design.

[0084] Furthermore, based on the first analysis result and the second analysis result, perform a correlation evaluation on the target low-power chip to obtain the leakage current characteristic evaluation result of the target low-power chip, including: based on the application scenario of the target low-power chip, obtain the voltage change situation and the environmental change situation, where the voltage change situation characterizes the fluctuation degree of the voltage in the application scenario, and the environmental change situation characterizes the fluctuation degree of the environment in the application scenario; determine the first weight coefficient according to the voltage change situation, and determine the second weight coefficient according to the environmental change situation; perform a weighted calculation on the first analysis result and the first weight coefficient to obtain the voltage dimension evaluation score; perform a weighted calculation on the second analysis result and the second weight coefficient to obtain the environmental dimension evaluation score; generate the leakage current characteristic evaluation result of the target low-power chip according to the voltage dimension evaluation score and the environmental dimension evaluation score.

[0085] Specifically, the voltage change refers to the fluctuation range and frequency of the voltage in the actual application scenario of the target low-power chip. The environmental change refers to the degree of fluctuation of environmental factors when the chip is in the application scenario. In different scenarios, the amplitude changes of temperature, humidity, and electromagnetic interference are different, which affect the stability and leakage current performance of the chip. The weight coefficient is a data ratio used to measure and adjust the importance of different influencing factors. The first weight coefficient is used to represent the degree of influence of voltage change, and the second weight coefficient represents the degree of influence of environmental change. The voltage dimension evaluation score and the environmental dimension evaluation score are the weighted calculation results based on the first analysis result and the voltage change, and the second analysis result and the environmental change respectively, indicating the leakage current performance of the chip under specific conditions of voltage or environment.

[0086] First, we obtain the weight coefficients according to the voltage change and environmental change in the application scenario, and then perform a weighted calculation of the analysis results and the weights to generate the final evaluation result.

[0087] Specifically, first, analyze the actual application scenario of the target chip. For example, in industrial control applications, there are large voltage fluctuations (high voltage change), and the environmental temperature and humidity also fluctuate at any time (high environmental change); in consumer electronics applications, the changes in voltage and environment are relatively stable.

[0088] Determine the weight coefficients of voltage and environment according to the change situation of the application scenario. For example, for a scenario with large voltage changes, a higher first weight coefficient (such as 0.7) can be set, while for a scenario with relatively stable environmental changes, a lower second weight coefficient (such as 0.3) can be set. These weight coefficients can be obtained through historical data analysis or scenario evaluation tools (such as statistical analysis libraries in MATLAB or Python).

[0089] Multiply the first analysis result (voltage - leakage current characteristic) by the first weight coefficient to obtain the voltage dimension evaluation score. For example, if the first analysis result is 80 and the first weight coefficient is 0.7, then the voltage dimension evaluation score is 80×0.7 = 56. Multiply the second analysis result (environment - leakage current characteristic) by the second weight coefficient to obtain the environmental dimension evaluation score. For example, if the second analysis result is 70 and the second weight coefficient is 0.3, then the environmental dimension evaluation score is 70×0.3 = 21.

[0090] Based on the voltage dimension and environmental dimension evaluation scores, comprehensively obtain the evaluation result of the leakage current characteristic of the target chip. A weighted average method can be used to obtain a comprehensive score, indicating the overall leakage current performance of the chip in this application scenario.

[0091] Through this method, the leakage current characteristics of the chip can be more accurately evaluated under different application scenarios, and the stability and reliability of the chip under specific conditions can be identified. The final evaluation results can help optimize the chip design, improve the performance of the chip in complex application environments, and provide a basis for users to select suitable chips.

[0092] In summary, the leakage current test and analysis method for a low-power chip provided by the embodiments of the present application has the following technical effects:

[0093] 1. By generating an adaptive test scheme and optimizing the environmental and voltage test sequences, the leakage current performance of the low-power chip under different environmental and voltage conditions can be accurately tested, improving the comprehensiveness and accuracy of the test. This method can provide a more scientific basis for the reliability evaluation of low-power chips and ensure the stability of the chips in variable environments.

[0094] 2. By constructing retrieval constraints and centralized interval analysis, the environmental data and voltage data of similar chips can be effectively obtained from the chip operation database, so as to determine a suitable test range. This analysis method ensures the rationality of the test range, avoids overly broad or narrow test conditions, and improves the effectiveness and pertinence of the test.

[0095] 3. By combining the environmental and voltage test sequences to generate an adaptive test scheme, the test conditions can be flexibly adjusted according to the characteristics and actual needs of the chip. This scheme can more comprehensively cover the performance of the chip under different working states, ensure that the test results are more reliable and comprehensive, and contribute to the performance optimization of the chip.

[0096] Embodiment 2, based on the same inventive concept as the leakage current test and analysis method for a low-power chip in the foregoing embodiment, as Figure 2 shown, the embodiments of the present application provide a leakage current test and analysis platform for a low-power chip, and the platform includes:

[0097] Chip feature data acquisition module 11: used to collect the chip feature data of the target low-power chip, and determine multiple environmental parameter test ranges and working voltage test ranges of the target low-power chip according to the chip feature data, wherein the multiple environmental parameter test ranges include temperature test ranges, humidity test ranges, and electromagnetic interference test ranges.

[0098] Environmental test sequence generation module 12: used to generate an environmental test sequence according to the multiple environmental parameter test ranges, generate a voltage test sequence according to the working voltage test range, and combine the environmental test sequence and the voltage test sequence to generate an adaptive test scheme.

[0099] Leakage current test data acquisition module 13: configured to set environmental parameters and apply a working voltage based on the adaptive test scheme, acquire leakage current test data of the target low-power chip through a current sensor, and construct a leakage current data matrix from the leakage current test data.

[0100] First analysis result acquisition module 14: configured to sequentially extract row vector data of the leakage current data matrix, analyze the voltage-leakage current characteristics under the same environmental parameter conditions, and obtain a first analysis result.

[0101] Second analysis result acquisition module 15: configured to sequentially extract column vector data of the leakage current data matrix, analyze the environment-leakage current characteristics under the same working voltage conditions, and obtain a second analysis result.

[0102] Correlation evaluation module 16: configured to perform a correlation evaluation on the target low-power chip based on the first analysis result and the second analysis result, and obtain a leakage current characteristic evaluation result of the target low-power chip.

[0103] Further, the chip feature data acquisition module 11 is further configured to perform the following steps: construct a retrieval constraint based on the chip feature data, perform data retrieval in the chip operation database based on the retrieval constraint, and obtain a set of similar chip operation samples, including multiple similar chip operation samples, where each similar chip operation sample has corresponding chip operation environment data and chip working voltage data; perform a centralized interval analysis on multiple environmental parameters in the chip operation environment data of multiple similar chip operation samples, obtain a centralized interval of multiple environmental parameters, and form an environmental parameter test range, where the multiple environmental parameters at least include temperature, humidity, and electromagnetic interference; perform a centralized interval analysis on the chip working voltage data of multiple similar chip operation samples, and obtain a working voltage test range.

[0104] Further, the chip feature data acquisition module 11 is further configured to perform the following steps: sort the chip working voltage data of multiple similar chip operation samples from largest to smallest, obtain a voltage data sorting result, and determine a voltage median according to the voltage data sorting result; extract the maximum voltage value from the voltage data sorting result, and obtain the median between the voltage median and the maximum voltage value as the test voltage upper limit value; extract the minimum voltage value from the voltage data sorting result, and obtain the median between the minimum voltage value and the voltage median as the test voltage lower limit value; generate a working voltage test range according to the test voltage upper limit value and the test voltage lower limit value.

[0105] Further, the environmental test sequence generation module 12 is further configured to perform the following steps: dividing the temperature test range into multiple temperature test points according to a temperature step size, dividing the humidity test range into multiple humidity test points according to a humidity step size, and dividing the electromagnetic interference test range into multiple electromagnetic interference test points according to an electromagnetic interference step size; performing permutation and combination on the multiple temperature test points, multiple humidity test points, and multiple electromagnetic interference test points to generate an environmental parameter combination set; screening the environmental parameter combination set based on a preset environmental parameter combination constraint to obtain an effective environmental parameter combination set, and generating the environmental test sequence, where the environmental parameter combination constraint is a combination limit condition set based on physical laws, actual application scenarios, and chip characteristic data; dividing the operating voltage test range into multiple voltage test points according to a voltage step size, and generating the voltage test sequence in ascending order; combining the environmental test sequence and the voltage test sequence in a matrix form to generate the adaptive test scheme.

[0106] Further, the first analysis result acquisition module 14 is further configured to perform the following steps: obtaining the expected voltage-leakage current characteristics under different environmental parameter conditions to generate multiple expected voltage-leakage current curves; extracting the first expected voltage-leakage current curve under the first environmental parameter condition; according to the leakage current data matrix, extracting the row vector data under the first environmental parameter condition to obtain the corresponding actual voltage-leakage current characteristics, and generating the first actual voltage-leakage current curve; performing deviation evaluation on the actual voltage-leakage current curve based on the expected voltage-leakage current curve to obtain a first curve evaluation result, and adding it to the multiple curve evaluation results; generating the first analysis result according to the multiple curve evaluation results.

[0107] Further, the first analysis result acquisition module 14 is further configured to perform the following steps: obtaining full-scale environmental combination data according to multiple environmental parameter test ranges; calculating a first environmental weight according to the occurrence frequency of the first environmental parameter condition in the full-scale environmental combination data, and adding it to the multiple environmental weights; performing weighted calculation on the multiple environmental weights and the multiple curve evaluation results to obtain the first analysis result.

[0108] Further, the association evaluation module 16 is further configured to perform the following steps: obtaining the voltage change condition and the environment change condition based on the application scenario of the target low-power chip, where the voltage change condition characterizes the fluctuation degree of the voltage in the application scenario, and the environment change condition characterizes the fluctuation degree of the environment in the application scenario; determining a first weight coefficient according to the voltage change condition, and determining a second weight coefficient according to the environment change condition; performing weighted calculation on the first analysis result and the first weight coefficient to obtain a voltage dimension evaluation score; performing weighted calculation on the second analysis result and the second weight coefficient to obtain an environment dimension evaluation score; generating an evaluation result of the leakage current characteristic of the target low-power chip according to the voltage dimension evaluation score and the environment dimension evaluation score.

[0109] Any step of the above-described method can be stored as computer instructions or programs in a computer memory without limitation and can be called and recognized by a computer processor without limitation to implement any method in the embodiments of the present application, and no redundant limitation is made here.

[0110] Further, the first or second mentioned above does not only represent an order relationship, but also represents a specific concept, and / or means that multiple elements can be selected individually or in whole. Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the present application and its equivalent technologies, the present application is intended to include these modifications and variations.

Claims

1. A leakage current test and analysis method for a low-power chip, characterized in that: include: Collect chip feature data of the target low-power chip, and determine multiple environmental parameter test ranges and operating voltage test ranges of the target low-power chip according to the chip feature data, wherein the multiple environmental parameter test ranges include a temperature test range, a humidity test range, and an electromagnetic interference test range; Generate an environmental test sequence according to the multiple environmental parameter test ranges, generate a voltage test sequence according to the working voltage test range, combine the environmental test sequence and the voltage test sequence to generate an adaptive test scheme; Based on the adaptive test scheme, environmental parameters are set and working voltage is applied, leakage current test data of the target low-power chip is obtained through a current sensor, and a leakage current data matrix is ​​constructed with the leakage current test data; Sequentially extracting row vector data of the leakage current data matrix, analyzing the voltage-leakage current characteristics under the same environmental parameter conditions, and obtaining a first analysis result; Sequentially extracting column vector data of the leakage current data matrix, analyzing the environment-leakage current characteristics under the same working voltage condition, and obtaining a second analysis result; Performing an associated evaluation on the target low-power chip based on the first analysis result and the second analysis result to obtain a leakage current characteristic evaluation result of the target low-power chip; Among them, generating an environmental test sequence according to the multiple environmental parameter test ranges, generating a voltage test sequence according to the working voltage test range, combining the environmental test sequence and the voltage test sequence to generate an adaptive test scheme, including: Dividing the temperature test range into a plurality of temperature test points according to the temperature step length, dividing the humidity test range into a plurality of humidity test points according to the humidity step length, and dividing the electromagnetic interference test range into a plurality of electromagnetic interference test points according to the electromagnetic interference step length; Arrange and combine multiple temperature test points, multiple humidity test points and multiple electromagnetic interference test points to generate an environmental parameter combination set; The environmental parameter combination set is screened based on preset environmental parameter combination constraints to obtain a valid environmental parameter combination set, and the environmental test sequence is generated, wherein the environmental parameter combination constraint is a combination restriction condition set based on physical laws, actual application scenarios and chip feature data; Dividing the working voltage test range into a plurality of voltage test points according to the voltage step length, and generating the voltage test sequence in order from small to large; Combining the environmental test sequence and the voltage test sequence in a matrix form to generate the adaptive test scheme; The step of performing an associated evaluation on the target low-power chip based on the first analysis result and the second analysis result to obtain a leakage current characteristic evaluation result of the target low-power chip includes: Based on the application scenario of the target low-power chip, the voltage change and the environment change are obtained, wherein the voltage change represents the degree of voltage fluctuation in the application scenario, and the environment change represents the degree of environment fluctuation in the application scenario; Determine a first weight coefficient according to the voltage change, and determine a second weight coefficient according to the environment change; Performing weighted calculation on the first analysis result and the first weight coefficient to obtain a voltage dimension evaluation score; Performing weighted calculation on the second analysis result and the second weight coefficient to obtain an environmental dimension evaluation score; A leakage current characteristic evaluation result of the target low-power chip is generated according to the voltage dimension evaluation score and the environment dimension evaluation score.

2. The method for testing and analyzing leakage current of a low-power chip according to claim 1, characterized in that: Determine multiple environmental parameter test ranges and operating voltage test ranges of the target low-power chip according to the chip characteristic data, wherein the multiple environmental parameter test ranges include a temperature test range, a humidity test range, and an electromagnetic interference test range, including: Constructing a retrieval constraint according to the chip feature data, performing data retrieval in a chip operation database based on the retrieval constraint, and acquiring a similar chip operation sample set, including a plurality of similar chip operation samples, wherein each similar chip operation sample has corresponding chip operation environment data and chip operating voltage data; Performing concentrated interval analysis on multiple environmental parameters in chip operating environment data of multiple similar chip operating samples, obtaining concentrated intervals of multiple environmental parameters, and forming an environmental parameter test range, wherein the multiple environmental parameters include at least temperature, humidity, and electromagnetic interference; Perform centralized interval analysis on the chip operating voltage data of multiple similar chip running samples to obtain the operating voltage test range.

3. The method for testing and analyzing leakage current of a low-power chip according to claim 2, characterized in that: Perform centralized interval analysis on the chip operating voltage data of multiple similar chip running samples to obtain the operating voltage test range, including: Sorting chip operating voltage data of a plurality of similar chip operation samples from large to small according to numerical values, obtaining a voltage data sorting result, and determining a voltage median according to the voltage data sorting result; Extracting the maximum voltage value in the voltage data sorting result, and obtaining the median between the voltage median and the maximum voltage value as the test voltage upper limit value; Extracting the minimum voltage value in the voltage data sorting result, and obtaining the median between the minimum voltage value and the voltage median as the test voltage lower limit value; An operating voltage test range is generated according to the test voltage upper limit value and the test voltage lower limit value.

4. The method for testing and analyzing leakage current of a low-power chip according to claim 1, characterized in that: Extracting row vector data of the leakage current data matrix in sequence, analyzing the voltage-leakage current characteristics under the same environmental parameter conditions, and obtaining a first analysis result, including: Obtain the expected voltage-leakage current characteristics under different environmental parameter conditions and generate multiple expected voltage-leakage current curves; Extracting a first expected voltage-leakage current curve under a first environmental parameter condition; Extracting row vector data of the first environmental parameter condition according to the leakage current data matrix, obtaining the corresponding actual voltage-leakage current characteristic, and generating a first actual voltage-leakage current curve; Performing deviation evaluation on the actual voltage-leakage current curve based on the expected voltage-leakage current curve, obtaining a first curve evaluation result, and adding the result to the plurality of curve evaluation results; The first analysis result is generated according to the plurality of curve evaluation results.

5. The method for testing and analyzing leakage current of a low-power chip according to claim 4, characterized in that: Generating the first analysis result according to the plurality of curve evaluation results includes: Obtain full environmental combination data based on multiple environmental parameter test ranges; Calculate a first environmental weight according to the frequency of occurrence of the first environmental parameter condition in the full amount of environmental combination data, and add it to the multiple environmental weights; The multiple environmental weights and the multiple curve evaluation results are weighted and calculated to obtain a first analysis result.

6. A leakage current test and analysis platform for low-power chips, characterized in that: For executing the method according to any one of claims 1 to 5, the platform comprises: Chip feature data acquisition module: used to collect chip feature data of the target low-power chip, and determine multiple environmental parameter test ranges and operating voltage test ranges of the target low-power chip according to the chip feature data, wherein the multiple environmental parameter test ranges include temperature test range, humidity test range and electromagnetic interference test range; An environmental test sequence generation module: used to generate an environmental test sequence according to the multiple environmental parameter test ranges, and to generate a voltage test sequence according to the working voltage test range, and to combine the environmental test sequence and the voltage test sequence to generate an adaptive test scheme; A leakage current test data acquisition module is used to set environmental parameters and apply working voltage based on the adaptive test scheme, acquire leakage current test data of the target low-power chip through a current sensor, and construct a leakage current data matrix with the leakage current test data; A first analysis result acquisition module: used to sequentially extract row vector data of the leakage current data matrix, analyze the voltage-leakage current characteristics under the same environmental parameter conditions, and acquire a first analysis result; A second analysis result acquisition module: used to sequentially extract column vector data of the leakage current data matrix, analyze the environment-leakage current characteristics under the same working voltage conditions, and obtain a second analysis result; An associated evaluation module is used to perform an associated evaluation on the target low-power chip based on the first analysis result and the second analysis result, and obtain a leakage current characteristic evaluation result of the target low-power chip.

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