Continuous write-in method of memory and memory applied to continuous write-in method

Abstract

The invention relates to the technical field of memories, and provides a memory continuous writing method and a memory applied to the same. The method comprises the following steps: writing data of a plurality of bytes into a memory, wherein the plurality of bytes comprise one or more non-writing bytes; and sending a write protection bit during the period of the non-write byte, so that the non-write byte is not written into the storage unit and the address is increased progressively. According to the invention, writing of any number of bytes can be realized in a page writing mode, and whether data is written into the address can be selected, so that the efficiency of writing operation of the memory can be greatly improved.

Description

Technical Field

[0001] The present invention generally relates to the field of memory technology. Specifically, the present invention relates to a memory continuous writing method and a memory to which the method is applied. Background Art

[0002] The I2C (Inter-Integrated Circuit) protocol is a serial communication protocol used for onboard communication and is widely used in various types of memory. Figure 1A -B shows a schematic diagram of a memory writing method based on the I2C protocol in the prior art. Figure 1A As shown in Figure 2-B, in a traditional memory (such as an electronically erasable programmable read-only memory (EEPRAM)), the memory writing methods based on the I2C protocol include a byte write mode (Byte Write) and a page write mode (PageWrite).

[0003] like Figure 1A As shown, in the byte write mode, one byte is written at a time. The master memory (Master) first sends a write command, further sends the address to be written, and then sends the data to be written. After receiving the data, the transmission ends and the data is written in the memory. However, the byte write mode has the problem that only one byte of data can be written at a time.

[0004] like Figure 1B As shown, in page write mode, one page (e.g., 128 bytes) is written at a time. This mode is similar to byte write mode, except that it will continue to receive new data after receiving data, and the transmission ends when the memory receives all 128 bytes of data, and 128 bytes are written to the storage unit at the same time in one write operation. However, the page write mode has the problem of fixed data capacity and lack of flexibility. Summary of the invention

[0005] In order to at least partially solve the above problems in the prior art, the present invention provides a memory continuous writing method, comprising: writing a plurality of bytes of data to a memory, wherein the plurality of bytes includes one or more non-write bytes; and A write protection bit is sent during the non-write byte so that the non-write byte is not written to the memory cell and the address is incremented.

[0006] In one embodiment of the present invention, writing a plurality of bytes of data into a memory includes: Multiple bytes of data are transferred from main memory; and The last bit of each byte, or the rising edge of the clock corresponding to the acknowledge bit triggers internal operations so that the data is written into the storage unit after each byte of data is received from the memory.

[0007] In one embodiment of the present invention, it is provided that sending a write protection bit during the non-write byte includes: sending a write protection bit during the last bit of said non-write byte; or The write protection bit is sent at the rising edge or falling edge of the last bit of the non-write byte.

[0008] In one embodiment of the present invention, the memory continuous writing method further includes: The address information transmitted by the data line is stored by the address register and counting unit; The address is incremented by controlling the address register and counting unit through the rising signal; Determine the serial clock line clock corresponding to the address transmission by the clock signal; and The memory is reset by the reset signal.

[0009] In one embodiment of the present invention, it is provided that sending a write protection bit during the non-write byte includes: Make the XEN signal and / or the YEN signal become a high pulse to latch the operation signal, wherein the memory starts to perform a write operation through the XEN control; and The XEN signal passes through the delay unit and pulls up the rising signal to increase the address in the address register and counting unit.

[0010] In one embodiment of the present invention, it is stipulated that the clock signal that increments the address in the address storage and counting unit includes a high pulse after the delay unit detects a signal delay, a high pulse generated by the falling edge of the last bit of data, or a high pulse generated by the rising or falling edge of the clock corresponding to the response bit of the data.

[0011] In one embodiment of the present invention, an X address is latched by an X signal, and a Y address is latched by a Y signal, wherein the memory starts to perform a read operation after obtaining the X address, and selects an output byte by the Y address.

[0012] In one embodiment of the present invention, it is provided that the execution of the write operation is controlled by a delay chain inside the memory, which includes: The XEN signal starts the delay chain and pulls the operation window signal high. After the write operation is completed, the delay chain generates an end pulse signal to pull the operation window signal low; and The reset signal is pulled high when power is turned on to reset each module of the memory, and the reset signal is pulled low after power is turned on.

[0013] In one embodiment of the present invention, it is provided that the position in the address storage and counting unit is used as the operation address, wherein the operation window signal is detected by the delay unit to determine whether the internal operation is in progress, when the operation is in progress, the rising signal selects the first pulse signal as the path for address increment, and when there is no operation, the rising signal selects the second pulse signal as the path for address increment, the first pulse signal includes a high pulse generated by the falling edge of the operation window signal or a delay of the pulse, and the second pulse signal includes a high pulse after the delay of the delay unit detection signal, a high pulse generated by the falling edge of the last bit of the data, or a high pulse generated by the rising edge or falling edge of the clock corresponding to the response bit of the data.

[0014] The present invention also provides a memory, which uses the memory continuous writing method to write data.

[0015] The present invention has at least the following beneficial effects: The present invention proposes a method for continuous writing to a memory based on the IIC protocol, which can realize the writing of any number of bytes in the page write mode, and can select whether to write data in the address. The present invention can greatly improve the efficiency of the write operation. Taking the example of continuously writing 64 bytes at an even address starting from address 00, the traditional writing method needs to write 64 times through the byte write mode, that is, it is necessary to send 64 write commands (1 byte), 64 addresses (each address is usually 2 to 3 bytes) and 64 bytes of data. However, the use of this method only requires 1 write command, 1 address and 128 bytes of data (including 64 bytes of virtual data). The efficiency of the write operation is 2 to 2.5 times that of the traditional writing method, and the larger the capacity of the memory, the more obvious the improvement in write efficiency will be. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] To further illustrate the advantages and features of various embodiments of the present invention, a more detailed description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that these drawings only depict typical embodiments of the present invention and are therefore not to be considered as limiting the scope thereof. In the accompanying drawings, for clarity, identical or corresponding parts will be represented by identical or similar reference numerals.

[0017] Figure 1A -B is a schematic diagram showing a memory writing method based on the I2C protocol in the prior art.

[0018] Figure 2 A schematic flow chart of a memory continuous writing method in an embodiment of the present invention is shown.

[0019] Figure 3 A schematic diagram of a writing process of writing any number of bytes into a page in one embodiment of the present invention is shown.

[0020] Figure 4 A circuit diagram of flexible writing of a page in one embodiment of the present invention is shown.

[0021] Figure 5 A circuit diagram of flexible writing of a page in another embodiment of the present invention is shown. DETAILED DESCRIPTION

[0022] It should be noted that the components in the figures may be shown exaggeratedly for the sake of illustration and are not necessarily true to scale. In the figures, identical or functionally identical components are provided with the same reference numerals.

[0023] In the present invention, unless otherwise specified, "arranged on...", "arranged above..." and "arranged above..." do not exclude the existence of an intermediate between the two. In addition, "arranged on or above..." merely indicates the relative positional relationship between two components, and in certain cases, such as after reversing the product direction, it can also be converted into "arranged below or below...", and vice versa.

[0024] In the present invention, each embodiment is only intended to illustrate the aspects of the present invention and should not be construed as limiting.

[0025] In the present invention, unless otherwise specified, the quantifiers "a", "an" and "an" do not exclude the presence of a plurality of elements.

[0026] It should also be noted that in the embodiments of the present invention, for the sake of clarity and simplicity, only a portion of the parts or components may be shown, but those of ordinary skill in the art will understand that under the teachings of the present invention, the required parts or components may be added according to the needs of the specific scenario. In addition, unless otherwise specified, the features in different embodiments of the present invention may be combined with each other. For example, a feature in the second embodiment may be used to replace a corresponding or functionally identical or similar feature in the first embodiment, and the resulting embodiment also falls within the disclosure scope or recorded scope of the present application.

[0027] It should also be noted that within the scope of the present invention, the terms "same", "equal", "equal to" and the like do not mean that the values ​​of the two are absolutely equal, but allow a certain reasonable error, that is, the terms also cover "substantially the same", "substantially equal", "substantially equal to". By analogy, in the present invention, the terms "perpendicular to", "parallel to" and the like indicating directions also cover the meanings of "substantially perpendicular to" and "substantially parallel to".

[0028] In addition, the numbering of the steps of the methods of the present invention does not limit the execution order of the method steps. Unless otherwise specified, the method steps can be executed in different orders.

[0029] The present invention will be further described below in conjunction with specific embodiments with reference to the accompanying drawings.

[0030] Figure 2 FIG. 2 shows a flow chart of a method for continuously writing to a memory in one embodiment of the present invention. Figure 2 As shown, the method comprises the following steps: Step 201: Write a plurality of bytes of data into a memory, wherein the plurality of bytes include one or more non-write bytes.

[0031] Step 202: Send a write protection bit during the non-write byte period so that the non-write byte is not written into the storage unit and the address is incremented.

[0032] Based on step 201 of the method, any number of bytes can be written into the page, and based on step 202 of the method, flexible page writing can be achieved (that is, data at any address in the page can be retained or written). The steps of the method are described in detail below.

[0033] Figure 3 FIG. 2 shows a schematic diagram of a writing process of writing any number of bytes into a page in one embodiment of the present invention. Figure 3 As shown, compared with the conventional EEEPROM and other conventional memories with fixed page write capacity (e.g., 128 Byte) in the prior art, the present invention can realize the writing of any number of bytes for memories with fast writing speed such as ferroelectric random access memory (FeRAM), magnetoresistive random access memory (MRAM), variable resistance random access memory (ReRAM), phase change memory (PCM), etc. Specifically, as Figure 3 As shown, the main memory transmits N bytes of data, where the internal operation is triggered at the last bit (Bit) of the data or at the rising edge of the clock corresponding to the acknowledgement bit (ACK), that is, the slave memory (Slave) writes the data into the storage unit after receiving each byte of data.

[0034] In the prior art, although it is possible to write any number of bytes when writing a page in a memory with a fast writing speed such as FeRAM, it can only write to continuous addresses. For example, when the address of the page write is 001, the data sent by the main memory will be written to 001 first, then the second byte will be written to 002, and the third byte will be written to 003. If the write protection bit (wp=high) is sent during the fourth byte, then the fourth byte will not be written to the storage unit, and the fifth byte will be written to 004. Or when the write protection bit is sent, the page write operation is directly terminated from the memory, and no response is given to the subsequent data. Based on this method, in a similar scenario, during the fourth byte, or during the last bit of the fourth byte, or at the rising edge or falling edge of the last bit of the fourth byte, the write protection bit (wp=high) is sent. At this time, the fourth byte is not written to the storage unit, and the data corresponding to the address 004 does not change, but the address +1, so the fifth byte will be written to 005. This method can achieve the retention or writing of data at any address in the page.

[0035] Figure 4 A circuit diagram of flexible writing of a page in one embodiment of the present invention is shown. Figure 4 The connection mode of N-bit address is shown, in which the address register and counting logic unit (Reg&Cnt) are used to store the address information transmitted by the data line (SDA), and the address can be controlled by the rising signal (INC) to increase by 1. The clock signal (CLK) represents the serial clock line (SCL) clock corresponding to the address transmission, and the reset signal (RST) is reset valid at power-on and invalid after power-on.

[0036] Although the memory is written one byte at a time, the amount of data in a read or write operation to the memory array is usually greater than 1 byte, and can be 4 bytes, 8 bytes, or 128 bytes (for example, in EEPRAM), which is determined by the memory structure. Figure 4 Medium ADD <n:0>Indicates the address of the memory read and write operation. If the memory operates 4 bytes at the same time, M=2; if it operates 8 bytes at the same time, M=3, and so on.

[0037] The internal write operation is triggered at the last bit of data or the rising edge of the clock corresponding to ACK. At this time, the XEN / YEN signal becomes a high pulse, latches the operation address, and the XEN signal controls the start of the memory write operation. After the XEN signal passes through the delay unit (delay), it pulls up the rising signal (INC) to make the Reg&Cnt address +1. The clock signal of the address +1 here can be a high pulse after the XEN delay unit detects the signal delay, or a high pulse generated by the falling edge of the 8th bit of data, or a high pulse generated by the rising or falling edge of the clock corresponding to the data ACK.

[0038] The X / Y addresses are latched separately, so that the memory can start to perform internal read operations after obtaining the X address, and the Y address is used to select 1 byte among 4 bytes or 8 bytes to output.

[0039] Each step of the write operation is controlled by the delay chain inside the memory. The XEN signal starts the delay chain and pulls the operation window signal (OP_WIN) high. After the write operation is completed, the delay chain generates an end pulse signal (DC_DONE_PLS) to pull the operation window signal (OP_WIN) low. The reset signal (RST) is pulled high at power-on to enable each module (BLOCK), and the reset signal is pulled low after power-on is completed.

[0040] Figure 5 FIG. 2 shows a circuit diagram of a flexible writing of a page in another embodiment of the present invention. Figure 4 In the embodiment shown, the address is latched before the write operation and will not be released until the next operation, so changes in the address in Reg&Cnt will not affect the operation address. Figure 5 In the embodiment shown, the address in Reg&Cnt is directly used as the operation address. Among them, the XEN delay unit detects whether the internal operation is in progress after a period of time (by detecting whether the operation window signal OP_WIN is in a high position or a low position). If the operation is in progress, the rising signal (INC) selects the first pulse signal (PLS1) as the path of address + 1, and if there is no operation, the second pulse signal (PLS2) is selected. PLS1 can be a high pulse generated by the falling edge of the operation window signal or a delay of the pulse. PLS2 can make the XEN delay unit detect the high pulse after the signal is delayed, or the high pulse generated by the falling edge of the 8th bit of the data, or the high pulse generated by the rising edge or falling edge of the clock corresponding to the ACK of the data.

[0041] It should be noted that Figure 4 and Figure 5 The address+1 logic in the illustrated embodiments is used for write operations, and the address+1 logic for read operations is different therefrom. The write operation address+1 logic or the read operation address+1 logic can be selected according to the read and write commands.

[0042] In one embodiment of the present invention, a memory is further provided, which uses the memory continuous writing method to write data.

[0043] Although various embodiments of the present invention are described above, it should be understood that they are presented as examples only and not as limitations. It is obvious to those skilled in the relevant art that various combinations, modifications and changes can be made thereto without departing from the spirit and scope of the present invention. Therefore, the breadth and scope of the present invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should only be defined according to the attached claims and their equivalents.

Claims

1. A method for continuous writing into a memory, characterized in that: include: Writing a plurality of bytes of data into a memory, wherein the plurality of bytes includes one or more non-write bytes; as well as A write protection bit is sent during the non-write byte so that the non-write byte is not written to the memory cell and the address is incremented.

2. The memory continuous writing method according to claim 1, characterized in that: Writing multiple bytes of data to memory involves: Multiple bytes of data are transferred from main memory; and The last bit of each byte, or the rising edge of the clock corresponding to the acknowledge bit triggers internal operations so that the data is written into the storage unit after each byte of data is received from the memory.

3. The memory continuous writing method according to claim 1, characterized in that: Sending a write protection bit during the non-write byte comprises: sending a write protection bit during the last bit of said non-write byte; or The write protection bit is sent at the rising edge or falling edge of the last bit of the non-write byte.

4. The memory continuous writing method according to claim 3, characterized in that: Also includes: The address information transmitted by the data line is stored by the address register and counting unit; The address is incremented by controlling the address register and counting unit through the rising signal; Determine the serial clock line clock corresponding to the address transmission by the clock signal; and The memory is reset by the reset signal.

5. The memory continuous writing method according to claim 4, characterized in that: Sending a write protection bit during the non-write byte comprises: Make the XEN signal and / or the YEN signal become a high pulse to latch the operation signal, wherein the memory starts to perform a write operation through the XEN control; and The XEN signal passes through the delay unit and pulls up the rising signal to increase the address in the address register and counting unit.

6. The memory continuous writing method according to claim 5, characterized in that: The clock signal that increments the address in the address storage and counting unit includes a high pulse after the delay unit detects a signal delay, a high pulse generated by the falling edge of the last bit of data, or a high pulse generated by the rising or falling edge of the clock corresponding to the response bit of the data.

7. The memory continuous writing method according to claim 6, characterized in that: The X address is latched by the X signal, and the Y address is latched by the Y signal, wherein the memory starts to perform a read operation after obtaining the X address, and selects an output byte by the Y address.

8. The memory continuous writing method according to claim 7, characterized in that: The execution of the write operation is controlled by a delay chain inside the memory, which includes: The XEN signal starts the delay chain and pulls the operation window signal high. After the write operation is completed, the delay chain generates an end pulse signal to pull the operation window signal low; and The reset signal is pulled high when power is turned on to reset each module of the memory, and the reset signal is pulled low after power is turned on.

9. The memory continuous writing method according to claim 4, characterized in that: The position in the address storage and counting unit is used as the operation address, wherein the operation window signal is detected by the delay unit to determine whether the internal operation is in progress. When the operation is in progress, the rising signal selects the first pulse signal as the path for address increment. When there is no operation, the rising signal selects the second pulse signal as the path for address increment. The first pulse signal includes a high pulse generated by the falling edge of the operation window signal or a delay of the pulse. The second pulse signal includes a high pulse after the delay of the delay unit detection signal, a high pulse generated by the falling edge of the last bit of the data, or a high pulse generated by the rising edge or falling edge of the clock corresponding to the response bit of the data.

10. A memory, characterized in that: Data is written using the memory continuous writing method described in any one of claims 1-9.

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