A random address accessible first-in-first-out memory and data processing method

Abstract

The application relates to the computer technical field, and discloses a FIFO memory with random address access and a data processing method to solve the problem that data written in a FIFO memory cannot be modified in a current circuit, the FIFO memory comprising a random access memory, a plurality of fixed-size memory blocks, each memory block being used for storing an Ethernet frame, write control logic and read control logic, the write control logic and the read control logic being used for reading and writing the current memory block in a FIFO order through a first external interface signal, and being used for reading and rewriting data in a specified address of the current memory block through the first external interface signal and a second external interface signal, the second external interface signal comprising an intra-block write enable signal, an intra-block write address signal, an intra-block read enable signal, an intra-block read address signal, a block write end signal and a block read end signal. The FIFO memory with random address access can modify data in the FIFO memory in the current circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the computer technical field, more particularly, to a random address accessible first-in first-out memory and a data processing method. BACKGROUND

[0002] In a network data processing system, due to the different data processing performance of each circuit in the system, the data input speed and output speed do not match in the interface part of the system. In order to avoid the loss of transmitted data, a first-in first-out (FIFO) memory is generally used to store data frames, and the empty / full indication of the FIFO memory is used to control the data processing speed of the front and rear two circuits, so as to realize the speed matching of the data processing system.

[0003] In a computer network, the FIFO memory usually stores Ethernet data frames, and according to the working characteristics of the network data processing system, it is often necessary to modify part of the fields of the data frames. Due to the first-in first-out characteristic of the FIFO memory, the data already written into the FIFO memory cannot be modified in the current circuit, and can only be modified after being read out from the current FIFO in the next circuit, which increases the complexity of the network data processing system. SUMMARY

[0004] In order to solve the above problems, the present application provides a random address accessible first-in first-out memory and a data processing method, which can modify the data already written into the FIFO memory in the current circuit, effectively reducing the complexity of the network data processing system.

[0005] To achieve the above object, according to the first aspect of the present application, a random address accessible first-in first-out memory is provided, comprising a random access memory, a write control logic, and a read control logic.

[0006] The random access memory comprises a plurality of fixed-size memory blocks, each memory block being used to store an Ethernet frame, and the size of the memory block is not less than the frame length of the Ethernet frame.

[0007] The write control logic and the read control logic are used to access the current memory block in a first-in first-out order through a first external interface signal; the first external interface signal comprises a write enable signal, a write data signal, a read enable signal, and a read data signal.

[0008] The write control logic and the read control logic are also used to specify the address of the current storage block for data read / write through the first pair of external interface signals and the second pair of external interface signals; the second pair of external interface signals includes a block write enable signal, a block write address signal, a block read enable signal, a block read address signal, a block write end signal and a block read end signal; the write control logic and the read control logic are also used to determine whether to jump out of the current storage block and access the next storage block through the block write end signal and the block read end signal.

[0009] Further, the write control logic and the read control logic are also used to perform read / write access to the address of the current storage block through the block write enable signal, the block write address signal, the block read enable signal and the block read address signal.

[0010] Further, the first pair of external interface signals also includes a status signal, which includes a full flag signal, a nearly full signal, an empty flag signal and a nearly empty signal, and is used to identify the empty / full state of the FIFO memory which can be accessed at random addresses; the write control logic and the read control logic are also used to count the block write end signal and the block read end signal to generate the full flag signal, the nearly full signal, the empty flag signal or the nearly empty signal.

[0011] According to a second aspect of the present application, a data processing method is also provided, which is applied to the FIFO memory which can be accessed at random addresses, and the data to be processed is in the form of Ethernet frames, and the method comprises the following steps:

[0012] storing the Ethernet frames in the storage blocks in sequence according to the sequence of the received Ethernet frames;

[0013] writing the Ethernet frame in the current storage block from the start position to the end position of the frame by operating the write enable signal and the write data signal;

[0014] directly jumping to the position of the data to be modified to modify the data by operating the block write enable signal and the block write address signal;

[0015] controlling the jump to the start position of the next frame in the next storage block to start processing the next frame of data by operating the block write end signal.

[0016] Further, the data processing method also comprises the following steps: storing the Ethernet frames in the storage blocks in sequence according to the sequence of the received Ethernet frames; reading the Ethernet frame in the current storage block from the start position to the end position of the frame by operating the read enable signal and the read data signal; directly jumping to the position of the data to be read to read the data by operating the block read enable signal and the block read address signal; and controlling the jump to the start position of the next frame in the next storage block to start processing the next frame of data by operating the block read end signal.

[0017] Further, the data processing method further comprises reading and writing access to the specified address of the current memory block according to the block write address signal and the block read address signal when the block write enable signal and the block read enable signal are valid.

[0018] Further, the data processing method further comprises counting the block write end signal and the block read end signal to generate a full flag signal, a nearly full signal, an empty flag signal or a nearly empty signal for identifying the empty / full state of the FIFO memory with random address access.

[0019] According to a third aspect of the present application, a computer device is provided, which comprises a memory, a processor and a computer program stored in the memory, the processor executing the computer program to implement the steps of any of the above data processing methods.

[0020] According to a fourth aspect of the present application, a computer readable storage medium is provided, which stores a computer program, the computer program being executed by a processor to implement the steps of any of the above data processing methods.

[0021] According to a fifth aspect of the present application, a computer program product is provided, which comprises a computer program, the computer program being executed by a processor to implement the steps of any of the above data processing methods.

[0022] Overall, the above technical solutions conceived by the present application can achieve the following beneficial effects compared with the prior art:

[0023] The FIFO memory with random address access provided by the present application realizes the random address access of the Ethernet data frame stored in the FIFO memory by changing the storage structure of the RAM buffer of the FIFO memory and adding a set of external interface signals, which has both the FIFO characteristics of the ordinary FIFO memory and the function of supporting the specified address data reading and writing, and can achieve the purpose of modifying the data written into the FIFO memory in the current circuit, effectively reducing the complexity of the network data processing system. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0025] Figure 1 A structure schematic diagram of a conventional FIFO memory provided by the embodiments of the present application is shown in the following figure.

[0026] Figure 2 A format diagram of an Ethernet frame provided for an embodiment of the present application is shown in FIG. 1.

[0027] Figure 3 A network data processing system based on a conventional FIFO isolation multi-stage circuit provided for an embodiment of the present application is shown in FIG. 2.

[0028] Figure 4 Another network data processing system based on a conventional FIFO isolation multi-stage circuit provided for an embodiment of the present application is shown in FIG. 3.

[0029] Figure 5 A structure diagram of a random address accessible FIFO memory provided for an embodiment of the present application is shown in FIG. 4.

[0030] Figure 6 A flow diagram of data processing based on a random address accessible FIFO memory provided for an embodiment of the present application is shown in FIG. 5.

[0031] Figure 7 A network data processing system based on a random address accessible FIFO memory provided for an embodiment of the present application is shown in FIG. 6.

[0032] Figure 8 A structure diagram of a computer device provided for an embodiment of the present application is shown in FIG. 7. DETAILED DESCRIPTION

[0033] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application. In addition, the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0034] The terms "first", "second", "third", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish different objects, and are not used to describe a specific order. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but can optionally include steps or units not listed or can optionally include other steps or units inherent to the process, method, product or device.

[0035] The present embodiment provides a random address accessible first-in-first-out (FIFO) memory, as shown in FIG. 4. Figure 1As shown, like a conventional FIFO memory, it contains RAM (Random Access Memory), write control logic, read control logic, and external interface signals including a first pair of external interface signals, i.e. write data, write enable, read data, read enable and status signals, the status signals including full flag, almost full, empty flag, almost empty, for identifying the empty / full status of the random address accessible first-in-first-out memory.

[0036] As shown, in the network data processing system, the data processed is usually an Ethernet frame, and the composition of the Ethernet frame includes the following data segments in sequence: destination MAC address, source MAC address, Ethernet type, IP header, payload, padding, FCS (Frame Check Sequence) check code. Figure 2 Since the FIFO memory has the first-in-first-out feature, i.e. the writing order of the Ethernet frame is from the destination MAC address to the FCS check code, and the reading order is also from the destination MAC address to the FCS check code, each stage of circuit of the network data processing system writes or reads the data segments of the Ethernet frame in sequence from left to right to or from the FIFO memory by controlling the external interface signals of the FIFO memory.

[0037] As shown, the network data processing system is composed of multiple stages of circuits, and the stages of circuits are isolated by FIFO memories, i.e. the network data processing system is composed of a previous stage of circuit, a current stage of circuit and a next stage of circuit, the previous stage of circuit and the current stage of circuit are isolated by a FIFO memory (i.e. ordinary fifo1), and the current stage of circuit and the next stage of circuit are also isolated by a FIFO memory (i.e. ordinary fifo2). Thus, the stages of circuits can be implemented to process in parallel in a pipeline manner and the processing speed can be matched, and each stage of circuit reads the data segments of the Ethernet frame from the FIFO memory of the previous stage and performs corresponding processing, and then writes the processed data segments to the FIFO memory of the next stage for buffering. Taking the current stage of circuit as an example, the current stage of circuit reads the data segments of the Ethernet frame from ordinary fifo1 and performs processing, and writes the processed data to ordinary fifo2 for buffering.

[0038] Figure 3 As shown, the circuit of a certain stage reads all data segments of the Ethernet frame from the FIFO memory of the previous stage (such as

[0039] As shown, the circuit of a certain stage reads all data segments of the Ethernet frame from the FIFO memory of the previous stage (such as Figure 4 Figure 2 ​​After all the data from the destination MAC address to the FCS check code is written into the FIFO memory, it is often necessary to modify some data segments, such as the IP length information of the IP header data segment and the IP header check, according to all the read data. Due to the first-in first-out characteristic of the ordinary fifo 1, after the sequence from the destination MAC address to the FCS check code is written and the IP header field is modified, the sequence read from the ordinary fifo 2 by the subsequent circuit is no longer from the destination MAC address to the FCS check code. Therefore, as shown in the figure, a circuit 2 and an ordinary fifo 3 are added, and the function of modifying the IP header field is placed in the circuit 2 to simply realize the function of modifying the IP header field. In this way, the function of modifying the IP header is realized, and the sequence of the Ethernet frame content is ensured to be correct. However, this way increases the complexity of the network data processing system. Figure 4

[0040] In order to solve the problem that the data already written into the FIFO memory cannot be modified in the current circuit without increasing the complexity of the network data processing system, the embodiment provides a FIFO memory with random address access, the RAM of which is divided into a plurality of fixed-size storage blocks, and an Ethernet frame can be sequentially stored in each storage block. The external interface signals further include second external interface signals, i.e. block-in writing enable, block-in writing address, block-in reading enable, block-in reading address, block writing end, and block reading end.

[0041] Like the conventional FIFO, the FIFO memory with random address access performs read and write access on the current storage block in the order of first-in first-out through the external interface signals such as writing enable, writing data, reading enable, and reading data. The performance matching between the front-end circuit and the rear-end circuit is realized through the state signals such as full flag, almost full, empty flag, and almost empty. Generally, the front-end circuit controls the writing enable signal according to the full flag and the almost full, and the rear-end circuit controls the reading enable signal according to the empty flag and the almost empty.

[0042] Taking the RAM depth of the ordinary fifo 1 as 64k for example, the read address is incremented by 1 every time the read enable is valid, and the write address is incremented by 1 every time the write enable is valid. Only sequential reading or writing can be performed, and the previous address cannot be accessed by back reading or back writing. That is, the address is cyclically written from 0 to 64k-1, and the address is cyclically read from 0 to 64k-1. At the same time, the full flag, the almost full, the empty flag, and the almost empty are generated through the difference between the write address and the read address.

[0043] ​Unlike conventional FIFOs, the random address access FIFO uses memory blocks as the basic data processing unit. By counting block write end and block read end signals, it generates full, almost full, empty, and almost empty status signals for the random address access FIFO. It performs read and write access to a specified address in the current memory block through block write enable, block write address, block read enable, and block read address signals. It determines whether to jump out of the current memory block and access the next memory block through block write end and block read end signals. It performs data readback / rewrite at a specified address in the current memory block through the first and second external interface signals.

[0044] In this embodiment, a FIFO memory with random address access is used to enable data readback / rewriting at a specified address of the current storage block, allowing modification of data already written to the FIFO memory within the current circuit level.

[0045] In one embodiment, such as Figure 5 As shown, the FIFO memory with random address access divides the RAM into N storage blocks of equal size. In network data processing systems, considering that the frame length of the stored Ethernet frames does not exceed 1518 bytes, and the size of the storage block is not less than the frame length of the Ethernet frame, the storage block size is usually set to 2K bytes. Each storage block stores one Ethernet frame, and the received Ethernet frames are sequentially stored in storage blocks 1 to N. By controlling the write enable, write data, read enable, and read data signals, the current storage block is accessed in a first-in-first-out order for reading and writing. When the block write enable and block read enable signals are valid, the specified address is read or written according to the block write address and block read address indications. Before the block write end and block read end signals are received, data is always read and written within the current storage block, and only after the block write end and block read end signals are received will the system jump to the starting address of the next storage block.

[0046] In one embodiment, for a write operation, such as Figure 6 As shown, a data processing method based on a FIFO memory with random address access is provided, including the following steps: controlling the write enable and write data signals of the FIFO memory with random address access to transfer Ethernet frames from... Figure 6 The process starts from the "frame start position" and ends at the "frame end position". Then, through the block write enable and block write address signals, it jumps directly to the "data to be modified position" to rewrite the data. Finally, through the block write end signal, it controls the jump to the "next frame start position" of the next storage block to start processing the next frame of data.

[0047] For read operation, the operation process is similar to that of write operation, including the following steps: storing each Ethernet frame in the storage block in sequence according to the received Ethernet frame order; operating the read enable signal and the read data signal to read the Ethernet frame in the current storage block from the frame start position to the frame end position; operating the in-block read enable signal and the in-block read address signal to directly jump to the to-be-read data position for data read-back; and operating the block read end signal to control jumping to the next frame start position of the next storage block to start processing the next frame data.

[0048] In one embodiment, as shown in Figure 7 the network data processing system based on the random address accessible FIFO memory directly completes the Ethernet frame data storage and the read-back or modification operation of some field data in the current circuit.

[0049] The random address accessible FIFO memory provided in the embodiment realizes the random address access of the Ethernet data frame stored in the FIFO memory by changing the storage structure of the RAM buffer of the FIFO memory and adding a set of external interface signals, has the first-in first-out feature of the ordinary FIFO memory and can support the specified address data read-write function, can achieve the purpose of modifying the data written in the FIFO memory in the current circuit, effectively reduces the complexity of the network data processing system, is strong in universality and has certain practical value.

[0050] The application further provides a computer device, which can be a computer device, and an internal structure diagram of the computer device can be as shown in Figure 8As shown in the figure. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit and an input device. Among them, the processor, the memory and the input / output interface are connected through the system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capability. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The input / output interface of the computer device is used to exchange information between the processor and the external device. The communication interface of the computer device is used to communicate with the external terminal in a wired or wireless manner. The wireless manner can be realized through WIFI, mobile cellular network, NFC (near field communication) or other technologies. The computer program is executed by the processor to realize the above-mentioned data processing method. The display unit of the computer device is used to form a visually visible picture, which can be a display screen, a projection device or a virtual reality imaging device. The input device of the computer device can be a touch layer overlaid on the display screen, or a key, trackball or touchpad arranged on the shell of the computer device, or an external keyboard, touchpad or mouse, etc.

[0051] Those skilled in the art can understand that, Figure 8 The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different component arrangement.

[0052] As Figure 8 The present application also provides a computer device, which includes a memory, a processor and a computer program stored on the memory, and the processor executes the computer program to realize the steps in each method embodiment.

[0053] The present application also provides a computer readable storage medium having a computer program stored thereon, and the computer program is executed by the processor to realize the steps in each data processing method embodiment. Among them, the computer readable storage medium can include but not limited to any type of disk, including floppy disk, optical disk, DVD, CD-ROM, micro drive and magneto-optical disk, ROM, RAM, EPROM, EEPROM, DRAM, VRAM, flash memory device, magnetic or optical card, nanosystem (including molecular memory IC), or any type of medium or device suitable for storing instructions and / or data.

[0054] The application further provides a computer program product comprising a computer program which, when executed by a processor, implements the steps of any of the above method embodiments.

[0055] It should be noted that, for the above-mentioned method embodiments, in order to simply describe, they are all expressed as a series of action combinations, but those skilled in the art should know that the application is not limited by the action order described, because according to the application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions and modules involved are not necessarily necessary for the application.

[0056] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0057] The above is only exemplary embodiments of the present disclosure, which cannot limit the scope of the present disclosure. That is, any equivalent changes and modifications made according to the teachings of the present disclosure are still within the scope of the present disclosure. Those skilled in the art will easily think of the embodiments of the present disclosure after considering the specification and practicing the disclosure herein. The present application is intended to cover any variations, uses, or adaptive changes of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or conventional technical means in the art not described in the present disclosure. The specification and examples are only considered as exemplary, and the scope and spirit of the present disclosure are defined by the claims.

[0058] The technical features of the above embodiments can be combined in any way. In order to make the description simple, not all possible combinations of the technical features in the above embodiments are described, but as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present disclosure.

[0059] Those skilled in the art readily understand that the above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A first-in-first-out (FIFO) memory with random address access, characterized in that, This includes random access memory, write control logic, and read control logic; The random access memory includes multiple fixed-size storage blocks, each of which is used to store one Ethernet frame, and the size of the storage block is not less than the frame length of the Ethernet frame; The write control logic and the read control logic are used to perform data readback / rewrite at a specified address of the current storage block using the storage block as the basic data processing unit, through a first external interface signal and a second external interface signal. The first external interface signal includes a write enable signal, a write data signal, a read enable signal, and a read data signal. The second external interface signal includes an intra-block write enable signal, an intra-block write address signal, an intra-block read enable signal, an intra-block read address signal, a block write end signal, and a block read end signal. The step of reading back / rewriting data at a specified address in the current storage block via the first external interface signal and the second external interface signal includes: By counting the block write end signal and the block read end signal, a status signal is generated. The status signal is used to identify the empty / full status of the random address-accessible first-in-first-out memory, including a full marker signal, an almost full signal, an empty marker signal, and an almost empty signal. The current storage block is read and written in a first-in-first-out order through the first external interface signal; When the intra-block write enable signal and the intra-block read enable signal are valid, the specified address read and write access is performed according to the intra-block write address signal and the intra-block read address signal. Before the block write end signal or block read end signal is received, data is always read and written within the current memory block until the block write end signal or block read end signal is received, at which point the program jumps to the starting address of the next memory block.

2. A data processing method, applied to a first-in-first-out memory with random address access as described in claim 1, characterized in that, The data to be processed is in the form of Ethernet frames, and the method includes: According to the order of the received Ethernet frames, each Ethernet frame is stored sequentially into its respective storage block; The write enable signal and write data signal are used to write the Ethernet frame in the current storage block from the start position of the frame to the end position of the frame. The operation block write enable signal and block write address signal will directly jump to the location of the data to be modified and rewrite the data. The operation block write end signal controls the jump to the next frame start position of the next storage block to start processing the next frame of data.

3. The data processing method as described in claim 2, characterized in that, The method further includes: The received Ethernet frames are stored sequentially into the respective storage blocks according to their order. The operation read enable signal and read data signal are used to read the Ethernet frames in the current storage block from the start position of the frame to the end position of the frame. The operation block read enable signal and block read address signal directly jump to the data to be read back and read back the data; The operation block read end signal controls the jump to the next frame start position of the next storage block to start processing the next frame of data.

4. The data processing method as described in claim 2 or 3, characterized in that, The method further includes: The block write end signal and block read end signal are counted to generate a full mark signal, a nearly full signal, an empty mark signal, or a nearly empty signal, which are used to identify the empty / full state of the first-in-first-out memory that can be accessed by random addresses.

5. A computer device, characterized in that, The method includes a memory, a processor, and a computer program stored in the memory, characterized in that the processor executes the computer program to implement the steps of the method according to any one of claims 2-4.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 2-4.

7. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 2-4.

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