OTP programming logic circuit and programming method

Abstract

The invention discloses an OTP programming logic circuit and a programming method in the technical field of integrated circuits. Comprising a coding signal input control logic module, a first test mode judgment module, a second test mode judgment module, a test mode output signal selection logic module, a pre-programming logic module, a programming logic module, a programming module and a fuse reading pulse signal generation module. The coded signal input control logic module is used for receiving a first external clock signal and outputting a first coded signal to the first test mode judgment module, and the coded signal input control logic module is provided with a first external clock signal input port and a first coded signal output port. According to the circuit parameter pre-programming method and device, middle test programming can be achieved, programming can also be conducted during finished test, programming flexibility is greatly improved, circuit parameters are pre-programmed in a specific mode, programming precision and accuracy are guaranteed, the parameter drift phenomenon is reduced, and the performance of an integrated circuit is improved.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, in particular to an OTP programming logic circuit and a programming method. Background Art

[0002] Due to the fluctuation and unevenness of the process for manufacturing integrated circuit chip wafers, coupled with factors such as packaging stress, the chip parameters will drift and discrete. Therefore, it is necessary to adjust the key parameters of the chip to ensure that each chip can meet the established index requirements. The electrical parameters of the chip can be adjusted during the wafer testing stage, that is, during the intermediate test, or they can be adjusted on the packaged circuit, that is, during the final test. The types of fuses for adjusting electrical parameters include metal fuses, polysilicon fuses, and floating gate fuses. Among them, metal fuses and polysilicon fuses can only be burned during the intermediate test. A large current is generated by applying a voltage across the fuse, and the high temperature generated by the large current burns the fuse. In addition, lasers can be used to blow metal fuses. Floating gate fuses can be burned during both the intermediate test and the final test, and do not require a large current.

[0003] The traditional method of burning fuses in the test is often done by burning PAD or laser. The disadvantage of burning PAD is that there must be PADs that can apply voltage at both ends of each fuse. Once the number of fuses reaches more than 16 bits, the PAD used for burning will occupy too much area, causing a sharp increase in chip costs. Although laser burning can improve the burning efficiency of fuses with more bits, it is necessary to calculate the number of bits to be burned in advance, and once the burning is completed, it cannot be modified. However, the parameter fluctuations of the chip will cause the predetermined fuse bit adjustment step to change, reducing the accuracy of laser burning. On the other hand, in some circuit structures, one parameter needs to be adjusted to the right position before another parameter can be adjusted. It is impossible to complete all the burning through one adjustment, and multiple adjustments have to be used for burning. The multiple adjustment burning method greatly increases the test cost and time consumption. Summary of the invention

[0004] The purpose of the present invention is to provide an OTP burning logic circuit and a burning method, which can save a large number of burning PADs, adjust the burning fuse bits and re-burn to ensure chip accuracy, and can also burn and adjust the chip during testing, further optimize the parameter drift caused by packaging, reduce the burning PAD and improve the burning accuracy.

[0005] To achieve the above object, the present invention provides the following technical solutions: In a first aspect, a method is provided that includes a coding signal input control logic module, a first test mode determination module, a second test mode determination module, a test mode output signal selection logic module, a pre-writing logic module, a writing logic module, a writing module, and a fuse read pulse signal generation module; The coding signal input control logic module is used to receive a first external clock signal and output a first coding signal to the first test mode determination module. The coding signal input control logic module has a first external clock signal input port and a first coding signal output port. The first coding signal can be output to the first test mode determination module only within a specific cycle of the first external clock signal input, thereby preventing the oscillation of the external port signal and avoiding inputting an erroneous signal into the internal burning logic circuit. The pre-burning logic module and the burning logic module constitute an internal burning logic circuit, so that the first test mode determination module enters the first test mode to generate a first output code, a first pre-burning and a first burning signal.

[0006] The first coded signal received by the first test mode determination module is triggered by a first external clock signal. When the first test mode determination module enters the first test mode, the first test mode determination module will maintain the on state of the first test mode under the triggering action of the clock signal.

[0007] When the coding signal input control logic module receives the second external clock signal, it outputs the second coding signal to the second test mode determination module, and the second test mode determination module outputs the second coding signal and enters the second test mode to generate a second output code, a second pre-writing signal and a second writing signal. The second output code is the test mode output code, the second pre-writing signal is the pre-writing setting code, and the second writing signal is the writing setting code and the writing trigger coding signal.

[0008] The test mode output signal selection logic module is used to output a channel control signal to turn on the test mode output gating circuit and transmit the corresponding internal signal to the external port for testing; The pre-writing logic module is used to receive the writing fuse setting code and the pre-writing code signal input through the clock signal, and output the writing setting bit signal and the pre-writing signal to the writing module for pre-writing; The burning module is used to receive the burning coding signal and generate a burning trigger signal to burn the burning module; The fuse reading pulse signal generating module is used to generate a high level pulse signal and set the output of the programming module to a preset value when powered on. The output of the module that has not been programmed is 0, and the output of the module that has been programmed is 1.

[0009] As a further solution of the present invention: the first test mode determination module outputs a locking signal after entering the first test mode, and the locking signal locks the first test mode determination module into the test process of the first test mode to maintain the first test mode of the first test mode determination module.

[0010] As a further solution of the present invention: the first test mode determination module is a burning mode entry logic module. When the first test mode determination module enters the first test mode, the first test mode determination module locks the encoding output channel. During the process of the first test mode determination module entering the first test mode, there is no need to input a control logic signal to the burning mode entry logic module, and the encoding signal can be directly transmitted to the second test mode determination module.

[0011] As a further solution of the present invention: the second test mode determination module is a burning mode coding logic module, the second test mode exits after a limited clock signal cycle, and inputting the second coding signal to the second test mode determination module again will re-enter the second test mode, the output end of the second test mode determination module is respectively connected to the test mode output signal selection logic module, the pre-burning logic module and the burning logic module, the output ends of the pre-burning logic module and the burning logic module are electrically connected to the burning module, and the input end of the burning module is electrically connected to the fuse reading pulse signal generating module, after entering the first test mode, the second coding signal is triggered by the second clock signal to be transmitted to the burning mode coding logic module, the burning mode coding logic module needs to enter the second test mode first, and input the coding signal to generate the test mode output code, the burning setting code, the pre-burning setting code and the burning trigger coding signal.

[0012] The second test mode determination module can only output one set of test mode output codes, or one set of fuse setting codes, or one set of pre-burn codes, or one set of burn codes. For example, when 16 internal signals need to be output, 16 sets of test mode output codes are required, so it is necessary to enter the second test mode 16 times. The 64-bit burn module has 60-bit burn fuse bits, and the pre-burn logic module has 8 bits as a group, requiring 8 sets of fuse setting codes and 8 sets of pre-burn codes, that is, a total of 16 times need to enter the second test mode.

[0013] When programming is performed in groups of 16 bits, 4 groups of programming trigger coding signals are required. At this time, the second test mode needs to be entered 4 times. When the second test mode determination module outputs the coding to the test mode output signal selection logic module, the reference voltage or current to be tested can be output to the external port, so as to directly measure the internal parameters. The programming setting coding is output to the pre-programming logic, and the fuse bits to be programmed are set through the pre-programming logic module; the pre-programming setting coding is output to the pre-programming logic module, and the pre-programming logic module outputs the corresponding pre-programming setting coding. The programming signal is used to pre-program the 64-bit programming module; the programming trigger coding signal is output to the programming logic module, and the programming logic module outputs the programming signal to program the 64-bit programming module. By setting the fuse reading pulse signal generation module, different programming signals can be output, and the auxiliary power supply port is used for power supply. When the floating gate fuse is read, the chip can be programmed after packaging, and there is no need to supply power from the auxiliary power supply port. Instead, a multiplexed external port is used, which is compatible with mid-test programming and final test programming, greatly improving the convenience of program programming.

[0014] As a further solution of the present invention: the burning module is a 64-bit burning module, which is used to realize 60-bit fuse pre-burning and burning. After pre-burning, the internal state is locked. Each internal module can be burned through the burning trigger bit. The default bit of each module output is 0, and the output bit becomes 1 after burning.

[0015] As a further solution of the present invention: the burning module includes four input ports and one output port, and the four input ports are respectively a burning setting port, a pre-burning signal input port, a burning signal input port and a data initialization port. When the burning setting port is at a high level, it indicates that the burning unit needs to be burned. When the port of the pre-burning signal input port is at a high level, pre-burning is performed; when the port of the burning signal input port is at a high level, burning is performed; the data initialization port is triggered by a pulse voltage, and the internal fuse state can be output to the output port of the module at the initial stage of power-on of the entire chip.

[0016] As a further solution of the present invention: the test mode output selection circuit includes a primary switch and several secondary switches, the primary switch is used to control the on-off of the connection path between the several secondary switches and the test mode output signal selection logic module, and one end of the primary switch is connected to the test mode output port TM_OUT.

[0017] As a further solution of the present invention: the coded signal input control logic module is connected to the first test mode determination module via a coded data input port, a clock input port and a test mode lock port; The coding signal input control logic module is connected to the second test mode determination module via a coding data input port, a clock input port and a test mode drive port; the coding data input port, the clock input port and the test mode lock port are all multiplexed ports, wherein the coding data input port is used for the coding signal input control logic module to receive an external signal, the clock input port is used for the coding signal input control logic module to receive a clock signal, and the test mode lock port is used to output a test mode drive signal to the first test mode determination module; the coding data input port, the clock input port and the test mode lock port can all reuse other ports of the modules to which they are connected; by allowing multiple modules to share the same port, the overhead of frequently opening and closing ports can be avoided, the efficiency of resource utilization can be improved, the complexity of ports can be simplified, and the ease of use and maintainability of the system can be improved; especially under high load conditions, by setting a multiplexed port, the overall performance and efficiency of the system can be improved.

[0018] In a second aspect, the present invention further provides an OTP burning method, which is applied to the OTP burning logic circuit as described in the above scheme, and the OTP burning method comprises: The chip is powered on, and a specific code is input into the first test mode determination module within a specific time to enter the first test mode; the way to enter the first test mode is to input a clock signal from the input clock signal port within a specific time, and at the same time, input a specific coding signal from the coding signal input port, and synchronously input the input coding signal into the burning mode entry logic module through the coding signal input port to enter the first test mode. Once entering the first test mode, the coding signal can be directly output from the coding signal input port and passed to the subsequent burning mode coding logic module.

[0019] If the first test mode is not entered, repeat the above steps, otherwise proceed to the next step; Input the second test mode code and clock signal to the second test mode determination module to enter the second test mode; after entering the first test mode, input the code signal for entering the second test mode again to enter the second test mode. Only after entering the second test mode can the burn mode code logic have an output signal; When the output signal does not reach the preset value for the first time, the second test mode is entered for the second time for pre-programming. After pre-programming, the second test mode is entered for the third time and the output signal is measured. When the output signal does not reach the preset value for the second time, the second test mode code and clock signal are input, the second test mode is entered for the fourth time and pre-programming is performed. Enter the second test mode again, input the fuse setting position and pre-burning code. Fuse setting and pre-burning are in a set of coded signals. From the time point of view, pre-burning can be performed directly after setting the fuse position. Pre-burning also requires entering the second test mode multiple times and burning multiple times; Repeat the process of measuring internal parameters. If the parameters reach the preset values, fuse burning can be performed. If they do not reach the preset values, the fuse positions need to be adjusted and pre-burned again. Pre-burning can be repeated multiple times. When programming the fuse, you need to enter the second test mode first, enter the fuse programming code, and program all fuses multiple times. After the fuse programming is completed, a fuse bit output will be left in each group of fuses to lock the logic of the fuse programming code, making the module unable to be programmed again. Therefore, if a 64-bit fuse bit needs to be programmed 4 times, then 4 bits of fuse will be used to lock the programming code logic; When the second output signal reaches the preset value, the second test mode is entered and programming is performed. After programming is completed, programming is terminated and the chip is powered off. When the power is turned on again, the first test coding logic needs to be re-entered to enter the first test mode again.

[0020] As a further solution of the present invention: when the output signal reaches a preset value for the first time, the programming is terminated and the chip is powered off.

[0021] Compared with the prior art, the present invention has the following beneficial effects: 1. The present invention can realize mid-test programming by adopting different types of fuses, and can also perform programming during final testing, which greatly improves the flexibility of programming. It can also pre-program circuit parameters in a specific way to ensure the precision and accuracy of programming, reduce process fluctuations and parameter drift caused by production processes, and is beneficial to improving the performance of integrated circuits.

[0022] 2. The present invention can read the pulse signal generation module through the fuse after power-on, and output the burned state from the burning module, and can cooperate with the auxiliary power supply port for power supply. When the burned floating gate fuse is read, the chip can be burned after packaging, and there is no need to supply power from the auxiliary power supply port. Instead, a multiplexed external port is used, so that it is compatible with mid-test burning and final test burning, which greatly improves the convenience of program burning and saves burning cost and burning time.

[0023] 3. Compared with the method of using a burning PAD to burn fuses, the present invention can save a large number of burning PADs. Compared with laser burning, the internal coding logic can also effectively prevent false triggering. By pre-burning and pre-testing the results after burning, the burning fuse position can be adjusted and re-burned, which is beneficial to ensure chip accuracy. When the wafer manufacturing process used supports floating gate fuses, the chip can be burned and adjusted during testing, and the parameter drift caused by packaging can be further optimized. Therefore, the fuse burning method of the present invention can reduce the burning PAD and improve the burning accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 The programming logic circuit diagram of the present invention; Figure 2 It is a programming module diagram of the present invention; Figure 3 It is a symbol diagram of the programming unit of the programming module of the present invention; Figure 4 It is the working flow chart of the programming circuit of the present invention.

[0025] The figure includes: a coding signal input control logic module; a test mode output signal selection logic; a burning module; a first test mode determination module; a second test mode determination module; and a fuse reading pulse signal generation module. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] Example:

[0028] See also Figure 1-Figure 3 , an OTP burning logic circuit is provided, including a first aspect, providing a coding signal input control logic module 1, a first test mode determination module 2, a second test mode determination module 3, a test mode output signal selection logic module 4, a pre-burning logic module 5, a burning logic module 6, a burning module 7 and a fuse reading pulse signal generating module 8; The coding signal input control logic module 1 is used to receive the first external clock signal and output the first coding signal to the first test mode determination module 2. The coding signal input control logic module 1 has a first external clock signal input port and a first coding signal output port. Only within a specific period of the first external clock signal input can the first coding signal be output to the first test mode determination module 2, thereby preventing the oscillation of the external port signal and avoiding inputting erroneous signals into the internal burning logic circuit. Among them, the pre-burning logic module 5 and the burning logic module 6 constitute an internal burning logic circuit, so that the first test mode determination module 2 enters the first test mode to generate a first output code, a first pre-burning and a first burning signal.

[0029] The first coding signal received by the first test mode determination module 2 is triggered by the first external clock signal. When the first test mode determination module 2 enters the first test mode, the first test mode determination module 2 will maintain the on state of the first test mode under the triggering action of the clock signal.

[0030] When the coding signal input control logic module 1 receives the second external clock signal, it outputs the second coding signal to the second test mode determination module 3, the second test mode determination module 3 outputs the second coding signal and enters the second test mode to generate a second output code, a second pre-writing signal and a second writing signal, the second output code is the test mode output code, the second pre-writing signal is the pre-writing setting code, the second writing signal is the writing setting code and the writing trigger coding signal.

[0031] The test mode output signal selection logic module 4 is used to output a channel control signal to turn on the test mode output gating circuit and transmit the corresponding internal signal to the external port for testing; The pre-writing logic module 5 is used to receive the writing fuse setting code and the pre-writing code signal input through the clock signal, and output the writing setting bit signal and the pre-writing signal to the writing module 7 for pre-writing; The burning module 7 is used to receive the burning coding signal and generate a burning trigger signal to burn the burning module 7; The fuse reading pulse signal generating module 8 is used to generate a high level pulse signal and set the output of the programming module 7 to a preset value when powered on. The output of the module that has not been programmed is 0, and the output of the module that has been programmed is 1.

[0032] Preferably, the first test mode determination module 2 outputs a locking signal after entering the first test mode, and the locking signal locks the first test mode determination module 2 into the test process of the first test mode to maintain the first test mode of the first test mode determination module 2 .

[0033] Preferably, the first test mode determination module 2 is a burning mode entry logic module. When the first test mode determination module 2 enters the first test mode, the first test mode determination module 2 locks the encoding output channel. During the process of the first test mode determination module 2 entering the first test mode, there is no need to input a control logic signal to the burning mode entry logic module, and the encoding signal can be directly transmitted to the second test mode determination module 3.

[0034] Preferably, the second test mode determination module 3 is a burning mode coding logic module. The second test mode is exited after a limited clock signal cycle. Inputting the second coding signal to the second test mode determination module 3 again will re-enter the second test mode. After entering the first test mode, the second coding signal is triggered by the second clock signal to be transmitted to the burning mode coding logic module. The burning mode coding logic module needs to enter the second test mode first and input the coding signal to generate the test mode output code, burning setting code, pre-burning setting code and burning trigger coding signal.

[0035] The second test mode determination module 3 can only output one set of test mode output codes, or one set of fuse setting codes, or one set of pre-burning codes, or one set of burning codes. For example, when 16 internal signals need to be output, 16 sets of test mode output codes are required, so it is necessary to enter the second test mode 16 times. The 64-bit burning module has 60-bit burning fuse bits, and the pre-burning logic module 5 has 8 bits as a group, which requires 8 sets of fuse setting codes and 8 sets of pre-burning codes, that is, a total of 16 times need to enter the second test mode.

[0036] When programming is performed in groups of 16 bits, 4 groups of programming trigger coding signals are required. At this time, the second test mode needs to be entered 4 times. When the second test mode determination module 3 outputs the coding to the test mode output signal selection logic module 4, the reference voltage or current to be tested can be output to the external port, so as to directly measure the internal parameters. The programming setting coding is output to the pre-programming logic, and the fuse position to be programmed is set through the pre-programming logic module 5; the pre-programming setting coding is output to the pre-programming logic module 5, and the pre-programming logic module 5 outputs the corresponding pre-programming setting coding. The burning signal is used to pre-burn the 64-bit burning module; the burning trigger coding signal is output to the burning logic module 6, and the burning logic module 6 outputs the burning signal to burn the 64-bit burning module. By setting the fuse reading pulse signal generating module 8, different burning signals can be output, and the auxiliary power supply port is used for power supply. When the floating gate fuse is read, the chip can be burned after packaging, and there is no need to supply power from the auxiliary power supply port. Instead, a multiplexed external port is used, so that it is compatible with mid-test burning and final test burning, which greatly improves the convenience of program burning.

[0037] Preferably, the burning module 7 is a 64-bit burning module, which is used to realize 60-bit fuse pre-burning and burning. After pre-burning, the internal state is locked. Each internal module can be burned through the burning trigger bit. The default output bit of each module is 0, and the output bit becomes 1 after burning.

[0038] Preferably, the burning module 7 includes four input ports and one output port, and the four input ports are respectively a burning setting port, a pre-burning signal input port, a burning signal input port and a data initialization port. When the burning setting port is at a high level, it indicates that the burning unit needs to be burned. When the port of the pre-burning signal input port is at a high level, pre-burning is performed; when the port of the burning signal input port is at a high level, burning is performed; the data initialization port is triggered by a pulse voltage, and the internal fuse state can be output to the output port of the module at the initial stage of power-on of the entire chip.

[0039] Preferably, the test mode output selection circuit includes a primary switch and several secondary switches, the primary switch is used to control the on-off of the connection path between the several secondary switches and the test mode output signal selection logic module 4, and one end of the primary switch is connected to the test mode output port TM_OUT.

[0040] Preferably, the coded signal input control logic module 1 is connected to the first test mode determination module 2 via a coded data input port, a clock input port and a test mode locking port; The coding signal input control logic module 1 is connected to the second test mode determination module 3 through a coding data input port, a clock input port and a test mode drive port. The coding data input port, the clock input port and the test mode lock port are all multiplexed ports, wherein the coding data input port is used for the coding signal input control logic module 1 to receive an external signal, the clock input port is used for the coding signal input control logic module 1 to receive a clock signal, and the test mode lock port is used to output a test mode drive signal to the first test mode determination module 4. The coding data input port, the clock input port and the test mode lock port can all reuse other ports of the modules to which they are connected. By allowing multiple modules to share the same port, the overhead of frequently opening and closing the ports can be avoided, the resource utilization efficiency can be improved, the complexity of the ports can be simplified, and it is beneficial to improve the usability and maintainability of the system. Especially under high load conditions, by setting a multiplexed port, the overall performance and efficiency of the system can be improved.

[0041] like Figure 4 As shown, the present invention also provides an OTP burning method, which is applied to the OTP burning logic circuit of the above scheme, and the OTP burning method includes: S1: Power on the chip, input a specific code to the first test mode determination module 2 within a specific time, and enter the first test mode; The way to enter the first test mode is to input a clock signal from the input clock signal port within a specific time, and at the same time, input a specific coding signal from the coding signal input port, and synchronously input the input coding signal into the burning mode entry logic module through the coding signal input port to enter the first test mode. Once entering the first test mode, the coding signal can be directly output from the coding signal input port and passed to the subsequent burning mode coding logic module.

[0042] S2: If the first test mode is not entered, repeat the above steps, otherwise proceed to the next step; S3: input the second test mode code and the clock signal to the second test mode determination module 3 to enter the second test mode; After entering the first test mode, input the coding signal for entering the second test mode again to enter the second test mode. Only after entering the second test mode can the programming mode coding logic have an output signal. According to the input DATA coding signal, the test mode output code CODE_TM_OUT, fuse setting code CODE_TRIM_SET, pre-programming code CODE_PRE_TRIM and programming trigger signal code CODE_TRIM_TRIG will be generated respectively. These codes are independent of each other. One input code can only generate one output signal. Measure whether the output signal reaches the preset value; after entering the second test mode for the first time, input the test mode output port parameter coding logic, measure the internal parameters, and exit the second test mode after a limited clock cycle, such as 16 clock cycles. At this time, it is necessary to input the second clock cycle coding signal again to enter the second test mode, and then input the test mode output port parameter coding logic to measure the second internal parameter. Repeat this cycle. After all parameter measurements are completed, calculate the fuse that needs to be burned based on the deviation between the measured value and the preset value.

[0043] S4: When the first output signal does not reach the preset value, enter the second test mode for the second time and perform pre-writing, enter the second test mode for the third time after pre-writing and measure the output signal, when the second output signal does not reach the preset value, input the second test mode code and clock signal, enter the fourth second test mode and perform pre-writing; Enter the second test mode again, input the fuse setting position and pre-burning code. Fuse setting and pre-burning are in a set of coded signals. From the time point of view, pre-burning can be performed directly after setting the fuse position. Pre-burning also requires entering the second test mode multiple times and burning multiple times; Repeat the process of measuring internal parameters. If the parameters reach the preset values, fuse burning can be performed. If they do not reach the preset values, the fuse positions need to be adjusted and pre-burned again. Pre-burning can be repeated multiple times. When programming the fuse, you need to enter the second test mode first, enter the fuse programming code, and program all fuses multiple times. After the fuse programming is completed, a fuse bit output will be left in each group of fuses to lock the logic of the fuse programming code, making the module unable to be programmed again. Therefore, if the 64-bit fuse bit needs to be programmed 4 times, then there are 4 fuse bits used to lock the programming code logic.

[0044] S5: When the second output signal reaches the preset value, the second test mode is entered and programming is performed. When programming is completed, programming is terminated and the chip is powered off; When the power is turned on again, the first test coding logic needs to be re-entered to enter the first test mode again.

[0045] Preferably, when the output signal reaches a preset value for the first time, the programming is terminated and the chip is powered off.

[0046] The above are only preferred specific implementation modes of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical solutions and inventive concepts of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. An OTP programming logic circuit, characterized in that: It includes a coding signal input control logic module, a first test mode determination module, a second test mode determination module, a test mode output signal selection logic module, a pre-burning logic module, a burning logic module, a burning module and a fuse reading pulse signal generation module; The coding signal input control logic module is used to receive a first external clock signal and output a first coding signal to the first test mode determination module, so that the first test mode determination module enters a first test mode to generate a first output code, a first pre-programming signal and a first programming signal; The test mode output signal selection logic module is used to output a channel control signal to turn on the test mode output gating circuit and transmit the corresponding internal signal to the external port for testing; The pre-writing logic module is used to receive the writing fuse setting code and the pre-writing code signal input through the clock signal, and output the writing setting bit signal and the pre-writing signal to the writing module for pre-writing; The burning module is used to receive the burning coding signal and generate a burning trigger signal to burn the burning module; The fuse reading pulse signal generating module is used to generate a high level pulse signal and set the output of the programming module to a preset value when powered on.

2. The OTP programming logic circuit according to claim 1, characterized in that: The first test mode determination module outputs a locking signal after entering the first test mode, and the locking signal locks the first test mode determination module into the test process of the first test mode.

3. The OTP programming logic circuit according to claim 2, characterized in that: The first test mode determination module is a programming mode entry logic module. When the first test mode determination module enters the first test mode, the first test mode determination module locks the encoding output channel.

4. The OTP programming logic circuit according to claim 1, characterized in that: The second test mode determination module is a burning mode encoding logic module. The second test mode is exited after a limited clock signal cycle. Inputting the second encoding signal to the second test mode determination module again will re-enter the second test mode. The output end of the second test mode determination module is respectively connected to the test mode output signal selection logic module, the pre-burning logic module and the burning logic module. The output ends of the pre-burning logic module and the burning logic module are electrically connected to the burning module, and the input end of the burning module is electrically connected to the fuse reading pulse signal generation module.

5. The OTP programming logic circuit according to claim 1, characterized in that: The burning module is a 64-bit burning module, which is used to realize 60-bit fuse pre-burning and burning, and the internal state is locked after pre-burning.

6. The OTP programming logic circuit according to claim 1, characterized in that: The burning module comprises four input ports and one output port, wherein the four input ports are respectively a burning setting port, a pre-burning signal input port, a burning signal input port and a data initialization port.

7. The OTP programming logic circuit according to claim 1, characterized in that: The test mode output selection circuit includes a primary switch and several secondary switches. The primary switch is used to control the on-off of the connection path between the several secondary switches and the test mode output signal selection logic module. One end of the primary switch is connected to the test mode output port TM_OUT.

8. The OTP programming logic circuit according to claim 1, characterized in that: The coded signal input control logic module is connected to the first test mode determination module via a coded data input port, a clock input port and a test mode lock port; The coded signal input control logic module is connected to the second test mode determination module via a coded data input port, a clock input port and a test mode driving port.

9. An OTP programming method, characterized in that: Applied to the OTP programming logic circuit according to any one of claims 1 to 8, the OTP programming method comprises: The chip is powered on, and a specific code is input into the first test mode determination module within a specific time to enter the first test mode; If the first test mode is not entered, repeat the above steps, otherwise proceed to the next step; Inputting a second test mode code and a clock signal into the second test mode determination module to enter the second test mode; When the output signal does not reach the preset value for the first time, the second test mode is entered for the second time for pre-programming. After pre-programming, the second test mode is entered for the third time and the output signal is measured. When the output signal does not reach the preset value for the second time, the second test mode code and clock signal are input, the second test mode is entered for the fourth time and pre-programming is performed. When the second output signal reaches the preset value, the second test mode is entered and programming is performed. After programming is completed, the programming is terminated and the chip is powered off.

10. The OTP programming method according to claim 9, characterized in that: When the first output signal reaches the preset value, the programming is completed and the chip is powered off.

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