Chip startup method, device, computer-readable storage medium, computer program product, chip, and computing device

Abstract

Provided are a chip startup method, device, computer-readable storage medium, computer program product, chip, and computing device, the method comprising: loading and running a chip initialization program when a chip triggers a startup condition; loading and running a chip hierarchical startup program when the chip initialization is completed based on the initialization program; wherein the hierarchical startup program is configured to optimize chip startup in stages and adapt to an external memory based on the specification information of the external memory. By optimizing the chip startup program in stages, the chip startup time is shortened and the chip startup efficiency is improved; by adaptively generating a startup program adapted to an external memory according to the specification information of different external memories, the compatibility with external memories of different manufacturers and the flexibility of applying different startup schemes are improved.

Description

Technical Field

[0001] The present disclosure relates to the field of chip technology, and in particular to a chip startup method, device, computer-readable storage medium, computer program product, chip, and computing device. Background Art

[0002] After the hardware design of the chip is completed, the corresponding firmware software needs to be designed to achieve the combination of chip hardware and software, realize the loading and running of chip firmware code, and finally achieve the purpose of normal operation of chip functions. Traditional chip startup methods often require a long hardware initialization and system loading process, resulting in a long startup time and affecting the efficiency of equipment use. Therefore, how to achieve fast startup of the chip has become a problem that needs to be solved urgently.

[0003] NOR Flash is a non-volatile flash memory and one of the important external memories that supports chip startup and determines chip startup efficiency. In order to achieve the purpose of fast chip startup, various memory manufacturers have designed different startup solutions based on different chips, but these solutions do not take into account the compatibility of the same chip with memories from different manufacturers, resulting in low application flexibility of the startup solutions provided by different manufacturers. Summary of the invention

[0004] It would be advantageous to provide a mechanism that mitigates, alleviates or eliminates at least one of the problems discussed above.

[0005] In a first aspect, a chip startup method is provided, comprising:

[0006] When the chip triggers the startup condition, the chip initialization program is loaded and run;

[0007] When the chip initialization is completed based on the initialization program, loading and running the hierarchical startup program of the chip;

[0008] The hierarchical startup program is configured to optimize chip startup in stages and adapt to the external memory based on specification information of the external memory.

[0009] In a second aspect, a chip startup device is provided, comprising:

[0010] An initialization unit, used to load and run the chip initialization program when the chip triggers the start condition;

[0011] A startup unit is used to load and run a hierarchical startup program of the chip when the chip initialization is completed based on the initialization program; wherein the hierarchical startup program is configured to optimize chip startup in stages and adapt to the external memory based on the specification information of the external memory.

[0012] In a third aspect, a computer-readable storage medium is provided, on which instructions are stored. When the instructions are executed individually or collectively by at least one processor of a computing device, the computing device is caused to perform the method according to any one of the above items.

[0013] In a fourth aspect, a computer program product is provided, comprising instructions, which, when executed individually or collectively by at least one processor of a computing device, cause the computing device to perform a method according to any one of the above.

[0014] In a fifth aspect, a chip is provided, wherein the chip is configured to execute any of the methods described above.

[0015] In a sixth aspect, a computing device is provided, comprising the above chip.

[0016] According to an exemplary embodiment of the present disclosure, during the startup process of a chip, on the one hand, by loading and running a hierarchical startup program of the chip and optimizing the chip startup program in stages, compared with the traditional method of loading a complete code, the chip startup time can be shortened and the chip startup efficiency can be improved; on the other hand, by adaptively generating a startup program compatible with an external memory according to the specification information of different external memories provided by different manufacturers, the purpose of making the same chip compatible with external memories of different manufacturers is achieved, thereby improving the flexibility of applying startup solutions provided by different manufacturers.

[0017] It should be understood that the invention summary is not intended to identify the key or essential features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects, features and advantages of the present disclosure will become more apparent through a more detailed description of some embodiments of the present disclosure in the accompanying drawings, in which:

[0019] Figure 1 A schematic diagram of a chip startup method in an embodiment of the present disclosure is shown;

[0020] Figure 2 A schematic diagram showing a flow chart of another chip startup method in an embodiment of the present disclosure is shown;

[0021] Figure 3 A schematic diagram showing the structure of a chip startup device in an embodiment of the present disclosure is shown; and

[0022] Figure 4 A structural block diagram of a computing device in an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0023] The principle of the present disclosure will now be described with reference to some embodiments. It should be understood that the description of these embodiments is only for illustrative purposes, and helps those skilled in the art to understand and implement the present disclosure, without any limitation to the scope of the present disclosure. The disclosure described herein can be implemented in a manner different from that described below.

[0024] In the following description and claims, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.

[0025] References in this disclosure to "one embodiment," "an embodiment," "an exemplary embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an exemplary embodiment, whether or not explicitly described, those skilled in the art will recognize that such feature, structure, or characteristic affects incorporation into other embodiments.

[0026] It should be understood that although the terms "first" and "second" etc. may be used to describe various elements herein, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the exemplary embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. The term "and / or" as used herein includes any and all combinations of one or more of the listed terms.

[0027] The terms used herein are only for describing specific embodiments, rather than for limiting exemplary embodiments. The singular forms "one", "an", and "the" used herein also include plural forms, unless the context clearly indicates otherwise. "A group of elements" or "element set" used herein is intended to include one or more elements. It should also be understood that the terms "include", "comprise", "have", "have", "include" and / or "include", when used herein, specify the presence of the features, elements and / or parts, etc., but do not exclude the presence or addition of one or more other features, elements, parts and / or combinations thereof.

[0028] As used in this disclosure, the term "computing device" refers to any computing device capable of wireless communication. As an example and not a limitation, a computing device may also be referred to as a communication device, a user equipment (UE), a user station (SS), a portable user station, a mobile station (MS), or an access terminal (AT). The computing device may include, but is not limited to, a mobile phone, a cellular phone, a smart phone, a voice over IP (VoIP) phone, a wireless local loop phone, a tablet computer, a wearable terminal device, a personal digital assistant (PDA), a portable computer, a desktop computer, an image capture computing device such as a digital camera, a game terminal device, a music storage and playback device, a vehicle-mounted wireless computing device, a wireless endpoint, a mobile station, a notebook embedded device (LEE), a laptop computer installation device (LME), a USB dongle, a smart device, a wireless user equipment (CPE), an Internet of Things (Lot) device, a watch or other wearable device, a head-mounted display (HMD), a vehicle, a drone, medical equipment and applications (e.g., remote surgery), industrial equipment and applications (e.g., robots and / or other wireless devices operating in the context of an industrial and / or automated processing chain), consumer electronic devices, relay nodes, devices operating on commercial and / or industrial wireless networks, etc. The mobile terminal (MT) portion of the IAB node may perform the functions of a "computing device" and may therefore operate as a computing device. In the following description, the terms "computing device", "communication device", "terminal", "user equipment" and "UE" may be used interchangeably.

[0029] Although the functions described herein may be performed in fixed and / or wireless network nodes in various exemplary embodiments, in other exemplary embodiments, the functions may be implemented in a user equipment device (such as a cellular phone, or a tablet computer, or a laptop computer, or a desktop computer, or a mobile Internet of Things device, or a fixed Internet of Things device). For example, the user equipment device may appropriately have the corresponding capabilities described in relation to fixed and / or wireless network nodes. The user equipment device may be a user device and / or a control device, such as a chipset or a processor, which is configured to control the user device when the user device is installed therein. Examples of these functions include boot server functions and / or home user servers, which may be implemented in a user equipment device by providing the user equipment device with software configured to cause the user equipment device to execute from the perspective of these functions / nodes.

[0030] The main technical terms involved in this disclosure are as follows:

[0031] NOR Flash: Also known as NOR flash memory, it is a non-volatile memory.

[0032] BootROM: It is a read-only memory (ROM) in the chip. When the chip is powered on or restarted, it executes the initial startup code to prepare for subsequent boot loading and operating system startup.

[0033] BootLoader: It is the first code executed by the embedded system after power-on. After it completes the initialization of the CPU and related hardware, it loads the operating system image or solidified embedded application into the memory and then jumps to the space where the operating system is located to start the operating system.

[0034] RAM (Random Access Memory): Random access memory is a type of memory used to temporarily store programs and data that a computer is running.

[0035] SRAM (Static Random-Access Memory): Static random access memory is a type of random access memory. The so-called "static" means that as long as the memory remains powered, the data stored in it can be kept constant.

[0036] ROM (Read-Only Memory): Read-only memory is a memory that can only read data but not write data.

[0037] ILM (Instruction Local Memory): instruction local memory.

[0038] DLM (Data Local Memory): Data local memory.

[0039] DDR (Double Data Rate Synchronous Dynamic Random Access Memory): Double Data Rate Synchronous Dynamic Random Access Memory is a dynamic random access memory with a double data transfer rate. Its data transfer speed is twice the system clock frequency.

[0040] PLL (Phase Locked Loop): Phase-locked loop.

[0041] QSPI (Queued SPI): Queued Serial Peripheral Interface, an interface for communicating with NOR Flash.

[0042] CACHE: Cache memory.

[0043] MMU (Memory Management Unit): memory management unit.

[0044] Generally speaking, the modules involved in the process of chip booting firmware are mainly divided into BootROM module, BootLoader module and application module. First, the BootROM module executes and moves the BootLoader in the power-off non-volatile storage to the executable storage for execution. Then the BootLoader performs its task and moves the application module code to the executable storage for execution.

[0045] However, traditional chip startup methods often require a long hardware initialization and system loading process, resulting in a long startup time and affecting the efficiency of device use. Therefore, how to achieve fast startup of multi-core chips has become an urgent problem to be solved.

[0046] The time for chip startup is mainly determined by the performance of the system and storage devices, and the software design. Different design schemes achieve different results. In order to achieve the purpose of fast startup of chips, different manufacturers have designed different startup schemes based on different chips. For example, a manufacturer provides a technology to solve the poor reusability of chip startup schemes and the long startup-related design cycle. First, after the chip is powered on, the first-layer main core in the chip runs the startup program to load the boot loader through the operation of the startup program; the first-layer main core runs the loaded boot loader to load the application programs of each layer in the chip into their respective address spaces through the operation of the boot loader and make the program counter pointer of the first-layer main core jump to the first address of the first-layer application program; wherein, the startup of each layer of main core in the chip except the first layer is controlled by the main core of the previous layer in hardware, and when startup is required, the startup is controlled by the operation of the boot loader.

[0047] However, although the above startup method can realize the startup of the chip and has improved the reusability of the solution compared to the traditional startup method, the complete loading code and its loading method have no obvious advantage in shortening the startup time of the entire system, and this solution has no specific implementation in terms of compatibility with external memory.

[0048] Therefore, in view of the problems of long startup time and poor compatibility of external memory in chip startup scenarios, the disclosed embodiment proposes a solution for chip startup, which will be referred to below. Figure 1 The principles and implementations of the present disclosure are described in detail.

[0049] The disclosed embodiments provide a chip startup method, apparatus, storage device, program product, chip, and computing device. Figure 1 As shown, a schematic flow chart of a chip startup method 100 in an embodiment of the present disclosure is provided. The chip startup method 100 at least includes the following steps S110 to S120.

[0050] Step S110, when the chip triggers the start-up condition, the chip initialization program is loaded and executed.

[0051] Combination Figure 2 The flowchart of another chip startup method in the embodiment of the present disclosure is shown. Before the chip is started, it is necessary to detect the startup conditions of the chip, mainly to detect whether the system is powered on or the reset signal is triggered. If the system is powered on or the reset signal is triggered, the chip automatically enters the reset state. The chip reset signal can be the pressing of the hardware reset button, the system power-on, the software reset instruction, etc.

[0052] After the chip is automatically reset, the initialization code of BootROM is loaded from the preset storage location of the chip. The initialization code of BootROM is the code fixed on the chip. BootROM can be regarded as the lowest and most basic link in the startup chain of the chip. It is usually stored in the read-only memory of the chip, that is, the ROM area, and cannot be modified. The initialization code in BootROM is run in the ROM area to start the preliminary initialization of the hardware and software environment, so as to prepare for the subsequent loading and execution of the startup program.

[0053] In one example, initialization work may include:

[0054] 1) Configure the processor core, such as setting the clock frequency, instruction set, etc.

[0055] 2) Configure the memory management unit (MMU), such as setting memory protection, virtual address mapping, etc.

[0056] 3) Initialize peripherals such as serial ports, timers, interrupt controllers, etc., and configure their operating modes and parameters.

[0057] In addition, it may also include initializing the system clock and timer to ensure the accuracy of the system time base, initializing the system memory, such as allocating memory space for the operating system or application, etc. The specific initialization operations can be flexibly set by those skilled in the art according to actual needs, and are not specifically limited here.

[0058] Step S120, when the chip initialization is completed based on the initialization program, load and run the hierarchical startup program of the chip; wherein the hierarchical startup program is configured to optimize chip startup in stages and adapt to the external memory based on the specification information of the external memory.

[0059] After completing the chip initialization operation, it is necessary to further load the chip's hierarchical startup program. It should be emphasized that the hierarchical startup program is different from the original startup program provided by the external memory manufacturer. It can be understood as a startup program obtained through a series of optimizations and adjustments based on the original startup programs provided by different manufacturers.

[0060] On the one hand, the hierarchical boot program is a boot program that divides the chip boot process into multiple stages and optimizes them in stages. Compared with the complete loading code and its loading method, it has more obvious advantages in shortening the startup time of the entire system. It can significantly shorten the startup time of the chip and make the chip have better response efficiency.

[0061] On the other hand, considering the compatibility of the same chip with memories provided by different manufacturers, the original boot program is further adaptively adjusted, that is, based on the original boot program provided by the external memory, combined with the specification information of the external memory such as the model and capacity of the NOR Flash, the boot program adapted to the external memory is adaptively adjusted. By adaptively adjusting the boot program, the same chip is compatible with external memories of different manufacturers, thereby improving the flexibility of the application of boot solutions provided by different manufacturers.

[0062] It should be noted that the external memory may include but is not limited to NOR Flash, and those skilled in the art may flexibly expand the solution of the present disclosure to compatible scenarios with other types of Flash according to actual needs.

[0063] In some embodiments, the hierarchical startup program includes an original first-level startup program and an original second-level startup program, and the loading and running of the hierarchical startup program of the chip includes: loading the original first-level startup program from the external memory to the first local memory of the chip; optimizing the original first-level startup program to obtain the optimized first-level startup program and running it; when the optimized first-level startup program is completed, loading the original second-level startup program from the external memory to the first local memory of the chip; adaptively adjusting the original second-level startup program based on the specification information of the external memory and running it.

[0064] Continue to refer Figure 2 Generally, the chip startup program is implemented by BootLoader, and Figure 2 In the example, the loading and running of the hierarchical boot program is divided into two stages: BootLoader0 and BootLoader1.

[0065] The main task of the BootLoader0 stage is to run the first-level boot program. The first-level boot program mainly completes the basic initialization of the hardware, maximizes the hardware capabilities, and prepares for the next stage of loading and running. In the BootLoader0 stage, the chip will first load the original first-level boot program chip in the external memory into the local designated area, that is, the first local memory. Then a series of optimization measures are taken to optimize the original first-level boot program in the NOR Flash to obtain the optimized first-level boot program, and finally run the optimized first-level boot program, thereby shortening the task time of BootLoader0 and the loading time of BootLoader1.

[0066] After BootLoader0 runs the optimized first-level boot program, it enters the BootLoader1 stage. The main task of the BootLoader1 stage is to run the second-level boot program to implement more complex boot logic and configuration options, including further configuration of the chip's peripherals and operating system. In the BootLoader1 stage, the chip will first load the original second-level boot program from the external memory, and then adaptively adjust the original second-level boot program according to the specification information of the external memory, such as the model, capacity, interface type, etc. of the NOR Flash, and then run it, so that the chip can correctly communicate with NOR Flash of different specifications and perform interactive operations such as data reading and writing.

[0067] By adopting a hierarchical boot program, loading, optimizing and running different levels of boot programs in stages, the chip initialization and configuration work is gradually completed, which shortens the chip startup time and improves the chip startup efficiency. In addition, by adaptively adjusting the boot program to adapt to the specifications and performance of different external memories, the compatibility with external memories of different manufacturers and the flexibility of the application of different manufacturers' boot solutions are improved.

[0068] In some embodiments, the optimizing the original first-level boot program to obtain and run the optimized first-level boot program includes at least one of the following optimization processes: deleting the running code of non-essential modules in the original first-level boot program; optimizing the code structure in the original first-level boot program; adjusting the running parameters of the chip, wherein the running parameters include at least one of the CPU running speed and the bus running speed; and running the optimized first-level boot program in the first local memory of the chip, wherein the first local memory is an instruction local memory or a data local memory.

[0069] A series of optimization measures may be designed for the optimization of the first-level startup program. In some embodiments, the optimization measures may include:

[0070] Delete the running code of unnecessary modules in the original first-level boot program: Since the BootLoader0 stage is mainly for the initial configuration of hardware capabilities, the original first-level boot program may contain some modules or functions that are irrelevant to the hardware configuration or unnecessary. By streamlining the boot code, removing unnecessary functions and module codes, and minimizing the boot code, the code complexity and running time can be reduced.

[0071] Optimize the code structure in the original first-level boot program: In one example, the core code in the original first-level boot program can be rewritten in assembly code, and the logical order of the code can be adjusted to ensure the fast loading and execution of key functions, thereby improving the running efficiency of the code and making the boot process smoother.

[0072] Adjust the operating parameters of the chip: In one example, the chip's CPU operating speed, bus operating speed and other parameters can be adjusted because the chip is generally configured to run at a lower operating speed when it leaves the factory. By increasing the CPU operating speed, the execution speed of instructions can be increased, and by increasing the bus operating speed, the data transmission efficiency can be improved, thereby improving the overall operating capability of the chip.

[0073] Running the optimized first-level boot program in the LM area of ​​the chip: Running the optimized first-level boot program in the ILM area or the DLM area can greatly improve the execution efficiency of the code.

[0074] Through the above series of measures to optimize the startup time, the task execution time of BootLoader0 and the loading time of BootLoader1 can be significantly shortened, thereby improving the startup efficiency of the chip.

[0075] Of course, it should be noted that the specific optimization strategies to be adopted in actual applications can be flexibly selected and set by those skilled in the art according to actual needs, and no specific limitation is made here.

[0076] In some embodiments, the adaptively adjusting and running the original secondary boot program based on the specification information of the external memory includes: reading the specification information of the external memory from the first local memory of the chip, the specification information of the external memory is read from the external memory to the first local memory of the chip during the initialization phase of the chip, and the specification information of the external memory includes at least one of the model, capacity and interface standard of the external memory; adaptively adjusting and running the original secondary boot program according to the specification information of the external memory, and the adaptive adjustment includes modifying at least one of the boot parameters, configuring registers and setting the data transmission mode.

[0077] During the BootROM initialization phase, the NOR Flash specification information will be read into the first local memory of the chip. The NOR Flash specification information of different manufacturers is different, for example, it may include information such as the NOR Flash model, capacity, interface standard, etc. This information will be used to adjust the chip's boot program to adapt to the specific NOR Flash.

[0078] Since the specification information of the NOR Flash mentioned above has been read into the local storage of the chip during the BootROM initialization phase, the specification information of the NOR Flash can be directly read from the local storage of the chip during the BootLoader1 phase. Then, based on the specification information of the NOR Flash, the secondary startup program can be adaptively adjusted, including modifying startup parameters, configuring registers, and setting data transmission protocols, so that the chip can correctly communicate and perform interactive operations such as data reading and writing with NOR Flash chips of different specifications.

[0079] As an example, different models of NOR Flash may support or be configured with different data transmission modes, so the supported data transmission mode can be determined based on the read NOR Flash model. The data transmission modes supported by NOR Flash are generally divided into single-line mode and four-line mode. The single-line mode means that one line is mainly used to send or receive commands and data during the data transmission process. The four-line mode means that four lines are used to send or receive commands and data during the data transmission process. Compared with the single-line mode, it has more efficient data transmission capabilities. The chip is configured to single-line mode by default. If the current NOR Flash supports four-line mode, it will adaptively switch from single-line mode to four-line mode to quickly start the chip.

[0080] In some embodiments, after adaptively adjusting and running the original secondary boot program, the method further includes: reconfiguring the chip environment; wherein the reconfiguration includes reconfiguring at least one of the phase-locked loop PLL, the queue serial peripheral interface QSPI, the cache memory CACHE, and the memory management unit MMU.

[0081] In the BootLoader1 stage, the main core also needs to reconfigure the entire chip environment, which mainly includes adjusting the chip hardware capabilities and the interaction capabilities between the chip and NOR Flash. The adjustment of the chip hardware capabilities can exemplarily include adjusting PLL and QSPI, etc., so as to improve the hardware capabilities of the chip.

[0082] The adjustment of the interaction capability between the chip and NOR Flash mainly includes adjusting CACHE and MMU, etc., which includes the supplement of the chip functional integrity. For example, in the aforementioned embodiment, the running code of some non-essential modules is deleted in the BootLoader0 stage. At this stage, the deleted function or module code needs to be supplemented or restored.

[0083] Through the reconfiguration of the above two aspects, the processing power of the entire chip and the interaction ability between the chip and NORFlash can be improved, and the loading and running time of subsequent multi-core firmware can be significantly shortened.

[0084] In some embodiments, after loading and running the hierarchical startup program of the chip, the method also includes: loading multiple core firmwares in parallel from the external memory to the second local memory of the chip by running the hierarchical startup program, the second local memory being a random access memory or a double rate synchronous dynamic random access memory; setting an environment for multiple core firmwares to complete the loading of multiple core firmwares; running multiple core firmwares in the second local memory of the chip to complete the startup of the chip.

[0085] Continue to refer Figure 2 In addition to the BootLoader0 and BootLoader1 firmwares, the external memory also stores multiple core firmwares. After completing the main startup procedures of the BootLoader0 and BootLoader1 stages in the aforementioned embodiment, BootLoader1 can further load multiple core firmwares from the external memory. In one example, multiple modules can be started simultaneously through parallel processing technology, thereby shortening the startup time.

[0086] Bootloader1 can load the firmware of multiple cores into the second local memory respectively. The second local memory can be RAM, SRAM or DDR memory. These types of memory have high-speed reading and writing capabilities and are suitable for storing data and programs that need to be frequently accessed in a short time.

[0087] After the loading of multiple core firmwares is completed, the related environments of the multiple core firmwares are set, which may include configuring the necessary hardware resources (such as CPU, memory, bus, etc.) and software environment (such as operating system, driver, etc.). The process of setting the environment may involve configuring the internal registers of the chip, dividing the memory area, and loading the software resources. After the environment configuration is completed, the main core releases the completion start signal.

[0088] After the core firmware is loaded, the chip can start running the core firmware system. In one example, the core firmware system can run in the RAM, SRAM or DDR area of ​​the chip. By running multiple core firmwares, the multi-core processing capability of the chip can be fully utilized to improve the overall performance and response speed of the system.

[0089] When all necessary core firmware runs successfully, the chip boot process is complete and the chip can be considered ready to execute user tasks or applications.

[0090] By loading multiple core firmware in parallel, the startup time of the chip is significantly shortened. During the startup process and operation stage, the multi-core processing capability of the chip can be fully utilized to improve the overall performance of the system. In addition, it can flexibly adapt to different numbers and types of core firmware, which facilitates future expansion and upgrades.

[0091] In some embodiments, the chip has key chip parameters preset in it for reading when running at least one of the initialization program and the hierarchical startup program, and the key chip parameters include at least one of software configuration parameters and hardware configuration parameters.

[0092] The aforementioned embodiments involve reading and using various chip parameters during execution. For example, in the BootROM initialization phase, the chip's processor core, memory management unit, and other peripheral hardware parameters need to be read. In the BootLoader0 startup phase, the chip's CPU operating speed, bus operating speed, and other parameters need to be read. Therefore, key chip-related parameters, including various key software configuration parameters and hardware configuration parameters, can be set in advance in the chip's local memory for use in subsequent program execution.

[0093] By presetting key parameters, the parameters required for each stage can be quickly read and used in subsequent chip initialization and startup stages, avoiding tedious parameter calculation and configuration operations during the overall startup process, thereby improving the startup efficiency of the chip.

[0094] The disclosed embodiment also provides a chip startup device 300, such as Figure 3 FIG. 1 is a schematic diagram showing the structure of a chip startup device in an embodiment of the present disclosure. The chip startup device 300 at least includes: an initialization unit 310 and a startup unit 320, wherein:

[0095] The initialization unit 310 is used to load and run the initialization program of the chip when the chip triggers the startup condition;

[0096] The startup unit 320 is used to load and run the hierarchical startup program of the chip when the chip initialization is completed based on the initialization program; wherein the hierarchical startup program is configured to optimize the chip startup in stages and adapt to the external memory based on the specification information of the external memory.

[0097] The chip startup device described above can implement the various steps of the chip startup method provided in the aforementioned embodiments. The relevant explanations on the chip startup method are applicable to the chip startup device and will not be repeated here.

[0098] Although specific functions are discussed above with reference to specific units, it should be noted that the functions of the various units discussed herein can be divided into multiple units, and / or at least some functions of multiple units can be combined into a single unit. The specific unit discussed herein performs an action including the specific unit itself performing the action, or alternatively the specific unit calls or otherwise accesses another component or unit that performs the action (or performs the action in conjunction with the specific unit). Therefore, the specific unit that performs an action can include the specific unit itself that performs the action and / or another unit that the specific unit calls or otherwise accesses and performs the action.

[0099] It should also be understood that various techniques may be described herein in the general context of software hardware elements or program units. Figure 3 The various units described may be implemented in hardware or in hardware in combination with software and / or firmware. For example, these units may be implemented as computer program code / instructions configured to be executed in one or more processors and stored in a computer-readable storage medium. Alternatively, these units may be implemented as hardware logic / circuits.

[0100] An embodiment of the present disclosure also provides a computer-readable storage medium on which instructions are stored. When the instructions are executed individually or collectively by at least one processor of a computing device, the computing device executes the method of the first aspect.

[0101] The embodiment of the present disclosure also provides a computer program product, including instructions, which, when executed individually or collectively by at least one processor of a computing device, enable the computing device to execute the above-mentioned chip startup method.

[0102] An embodiment of the present disclosure further provides a chip, which is configured to execute the above chip startup method.

[0103] An embodiment of the present disclosure also provides a computing device, comprising the above-mentioned chip.

[0104] Figure 44 is a block diagram of a computing device 400 suitable for implementing the embodiments of the present disclosure. As shown in the figure, the computing device 400 includes one or more processors 410, one or more memories 420 coupled to the processors 410, and one or more communication modules 440 coupled to the processors 410.

[0105] The communication module 440 is used for two-way communication. The communication module 440 has at least one antenna to facilitate communication. The communication interface may represent any interface necessary for communicating with other network elements.

[0106] Processor 410 may be of any type suitable for the local technology network, and may include, as non-limiting examples, one or more of: a general purpose computer, a special purpose computer, a microprocessor, a digital signal processor (DSP), and a processor based on a multi-core processor architecture. Computing device 400 may have multiple processors, such as application specific integrated circuit chips, which are driven in time to a clock that synchronizes a master processor.

[0107] The memory 420 may include one or more non-volatile memories and one or more volatile memories. Examples of non-volatile memories include, but are not limited to, read-only memory (ROM) 424, electrically programmable read-only memory (EPROM), flash memory, hard disk, compact disk (CD), digital video disk (DVD), and other magnetic and / or optical memories. Examples of volatile memories include, but are not limited to, random access memory (RAM) 422 and other volatile memories that do not persist during the duration of a power outage.

[0108] Computer program 430 includes computer executable instructions that are executed by associated processor 410. Program 430 may be stored in ROM 424. Processor 410 may perform any appropriate actions and processes by loading program 430 into RAM 422.

[0109] The embodiments of the present disclosure may be implemented by a program 430, so that the computing device 400 may execute the reference Figure 1 Any process of the disclosure discussed. The embodiments of the present disclosure may also be implemented by hardware or by a combination of software and hardware.

[0110] In some embodiments, program 430 may be tangibly embodied in a computer-readable medium, which may be contained in computing device 400 (e.g., memory 420) or other storage devices accessible to computing device 400. Computing device 400 may load program 430 from the computer-readable medium to RAM 422 for execution. The computer-readable medium may include any type of tangible non-volatile memory, such as ROM, EPROM, flash memory, hard disk, CD, DVD, etc. The computer-readable medium has program 430 stored thereon.

[0111] It should be noted that computing devices include but are not limited to terminal devices, base station devices (for example, ground base stations or satellite network devices), and devices that can implement the above-mentioned chip startup method all fall within the scope of protection of this disclosure.

[0112] Generally, various embodiments of the present disclosure may be implemented in hardware or dedicated circuits, software, logic, or any combination thereof. Certain aspects may be implemented in hardware, while other aspects may be implemented in firmware or software, which may be executed by a controller, microprocessor, or other computing device. Although various aspects of the embodiments of the present disclosure are shown and described as block diagrams, flow charts, or using some other graphical representations, it should be understood that, as non-limiting examples, the blocks, devices, systems, techniques, or methods described herein may be implemented in hardware, software, firmware, dedicated circuits or logic, general hardware or controllers or other computing devices, or some combination thereof.

[0113] The present disclosure also provides at least one computer program product tangibly stored on a non-transient computer-readable storage medium. The computer program product includes computer executable instructions, such as instructions included in program modules, which are executed in a device on a target real or virtual processor. Typically, program modules include routines, programs, libraries, objects, classes, components, data structures, etc. that perform specific tasks or implement specific abstract data types. In various embodiments, the functions of program modules can be combined or separated between program modules as needed. Machine executable instructions for program modules can be executed in local or distributed devices. In distributed devices, program modules can be located in local and remote storage media.

[0114] The program code for executing the disclosed method can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer or other programmable data processing equipment so that when the program code is executed by the processor or controller, the function / operation specified in the flow chart and / or block diagram is realized. The program code can be executed completely on the machine as an independent software package, partially on the machine, partially on the machine, partially on a remote machine, partially on a remote machine, or all on a remote machine or server.

[0115] In the context of the present disclosure, computer program codes or related data may be carried by any appropriate carrier to enable a device, apparatus or processor to perform various processes and operations as described above. Examples of carriers include signals, computer readable media, etc.

[0116] The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared or semiconductor systems, devices or apparatuses, or any suitable combination of the foregoing. More specific examples of computer readable storage media include an electrical connection having one or more conductors, a portable computer floppy disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0117] In addition, although the operations are described in a specific order, this should not be understood as requiring the specific order or sequence shown to be performed, or performing all the operations shown, to obtain the desired result. In some cases, multitasking and parallel processing may be advantageous. Similarly, although several specific implementation details are included in the above discussion, these details should not be interpreted as limitations on the scope of the present disclosure, but can be interpreted as descriptions of features specific to a particular embodiment. Certain features described in the context of a separate embodiment may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination.

[0118] Although the disclosure has been described in language specific to structural features and / or methodological acts, it should be understood that the disclosure defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

[0119] It should be fully understood that the use of personally identifiable information should be subject to privacy policies and practices generally recognized as meeting or exceeding industry or government requirements for maintaining user privacy. In particular, personally identifiable information data should be managed and processed to minimize the risk of inadvertent or unauthorized access or use, and the nature of authorized use should be clearly indicated to users.

Claims

1. A chip startup method, the method comprising: When the chip triggers the startup condition, the chip initialization program is loaded and run; In the case where the chip initialization is completed based on the initialization program, a hierarchical startup program of the chip is loaded and run, the hierarchical startup program includes an original first-level startup program and an original second-level startup program, and the loading and running of the hierarchical startup program of the chip includes: adaptively adjusting the original second-level startup program based on the specification information of the external memory and running it, the specification information of the external memory is read from the external memory to the first local memory of the chip during the initialization phase of the chip, and the adaptive adjustment includes at least one of modifying the startup parameters, configuring the registers, and setting the data transmission mode; The hierarchical startup program is configured to optimize chip startup in stages and adapt to the external memory based on specification information of the external memory.

2. The method of claim 1, wherein: The hierarchical startup program includes an original primary startup program and an original secondary startup program, and the step of loading the hierarchical startup program of the chip and running the program includes: Loading the original first-level boot program from the external memory into the first local memory of the chip; Optimizing the original first-level startup program to obtain an optimized first-level startup program and running it; When the optimized first-level boot program is completed, loading the original second-level boot program from the external memory into the first local memory of the chip; The original secondary startup program is adaptively adjusted and executed based on the specification information of the external memory.

3. The method of claim 2, wherein: The optimizing the original first-level startup program to obtain and run the optimized first-level startup program includes at least one of the following optimization processes: Delete the running codes of non-essential modules in the original first-level startup program; Optimize the code structure in the original first-level startup program; Adjusting the operating parameters of the chip, wherein the operating parameters include at least one of a CPU operating speed and a bus operating speed; The optimized first-level boot program is run in a first local memory of the chip, where the first local memory is an instruction local memory or a data local memory.

4. The method of claim 2, wherein: The adaptively adjusting and running the original secondary startup program based on the specification information of the external memory includes: Reading specification information of the external memory from the first local memory of the chip, wherein the specification information of the external memory includes at least one of a model, a capacity, and an interface standard of the external memory; The original secondary startup program is adaptively adjusted and executed according to the specification information of the external memory.

5. The method of claim 2, wherein: After adaptively adjusting and running the original secondary startup program, the method further includes: Reconfigure the chip's environment; The reconfiguration includes reconfiguring at least one of a phase-locked loop PLL, a queue serial peripheral interface QSPI, a cache memory CACHE, and a memory management unit MMU.

6. The method of claim 1, wherein: After loading and running the hierarchical startup program of the chip, the method further includes: By running the hierarchical startup program, multiple core firmwares are loaded in parallel from the external memory into the second local memory of the chip, where the second local memory is a random access memory or a double rate synchronous dynamic random access memory; Setting up multiple core firmware environments to complete the loading of multiple core firmwares; A plurality of core firmwares are run in the second local memory of the chip to complete the startup of the chip.

7. The method according to any one of claims 1 to 6, wherein: The chip is pre-installed with chip key parameters for reading when at least one of the initialization program and the hierarchical startup program is run. The chip key parameters include at least one of software configuration parameters and hardware configuration parameters.

8. A chip startup device, comprising: An initialization unit, used to load and run the chip initialization program when the chip triggers the start condition; A startup unit is used to load and run a hierarchical startup program of the chip when the chip initialization is completed based on the initialization program, the hierarchical startup program includes an original first-level startup program and an original second-level startup program, and the startup unit is specifically used to: adaptively adjust and run the original second-level startup program based on specification information of an external memory, the specification information of the external memory is read from the external memory to the first local memory of the chip during the initialization phase of the chip, and the adaptive adjustment includes modifying startup parameters, configuring registers, and setting data transmission modes; wherein the hierarchical startup program is configured to optimize chip startup in stages, and adapt to the external memory based on the specification information of the external memory.

9. A computer-readable storage medium storing instructions, characterized in that: When the instructions are executed individually or collectively by at least one processor of a computing device, the computing device is caused to perform the method according to any one of claims 1 to 7.

10. A computer program product comprising instructions, characterized in that When the instructions are executed individually or collectively by at least one processor of a computing device, the computing device is caused to perform the method according to any one of claims 1 to 7.

11. A chip, characterized in that: The chip is configured to perform the method according to any one of claims 1 to 7.

12. A computing device, characterized in that: Comprising the chip according to claim 11.

Images