Flash memory access scheduling

Abstract

Embodiments of the invention relate to flash memory access scheduling. Various examples disclosed herein relate to trimming of system elements to prepare elements for execution of boot code and application code. In an example embodiment, a system is provided. The system (100) includes memory access circuitry (112) and processing circuitry (114) coupled to the memory access circuitry (112). The memory access circuitry (112) is configured to receive a read request (XIP code (122)) corresponding to an instruction set stored in the non-volatile memory (120) for execution by the processing circuitry (114), the method further includes receiving a set of instructions from the non-volatile memory (120), determining whether to preempt a current access to the non-volatile memory (120) corresponding to one or more access requests to support the read request based on a priority of the read request relative to the one or more access requests, obtaining the set of instructions from the non-volatile memory (120), and providing the set of instructions to processing circuitry (114). Processing circuitry (114) executes the set of instructions.

Description

Technical Field

[0001] This document generally relates to prioritizing requests from one or more processors to access memory. Background Art

[0002] A microcontroller unit (MCU) is designed to run a software program and perform functions enabled by running the software program. To this end, the MCU may include a processing core configured to execute the software and a memory coupled to the processing core, the memory storing the instructions and data of the software. For example, the MCU may have one or more central processing units (CPUs) that communicate with a random access memory (RAM) to execute such a software program. If the software program is too large to be executed from the RAM, the MCU may additionally utilize a non-volatile memory, such as a flash memory, which has a larger capacity to store instructions and data related to the software. The MCU typically executes the software program from the RAM at a higher speed and lower latency, however, the increase in the complexity and size of the program may require the MCU to execute from the RAM and / or flash memory to perform the task.

[0003] Executing program instructions directly from flash memory may also be referred to as operations in place ("XIP"). In order to utilize flash memory, a traditional solution may include multiple flash memory instances in the system architecture. One flash memory may be used to execute a write request from an on-chip memory to, for example, a flash memory, while another flash memory may be used to execute a read request from the flash memory to the on-chip memory. However, such a solution is expensive due to the need for multiple flash memories. Other solutions may utilize a single flash memory. In this case, a priority sorting mechanism is required to determine which read and write requests may take precedence over other read and write requests. Although multiple requests from a single processing core may be interleaved, this solution does not address the inefficiency when prioritizing one request over another. Summary of the invention

[0004] Improvements to memory access prioritization and preemption are disclosed herein. Access requests may include read requests, write requests, and / or execution requests. In an environment including multiple processing cores, each processing core may attempt to access non-volatile memory while executing program code, and various access requests may be prioritized to reduce latency and increase processing throughput. In an example embodiment, a system is provided. The system includes a memory access circuit system and a processing circuit system coupled to the memory access circuit system. The memory access circuit system is configured to receive a read request corresponding to an instruction set stored in a non-volatile memory for execution by a processing circuit system, determine whether to preempt a current access to the non-volatile memory corresponding to the one or more access requests to support the read request based on the priority of the read request relative to one or more access requests, obtain the instruction set from the non-volatile memory, and provide the instruction set to the processing circuit system. The processing circuit system executes the instruction set.

[0005] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. It should be understood that this Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 An example operating environment for scheduling accesses to memory is shown according to an embodiment.

[0007] Figure 2 A series of steps in an implementation scheme for preempting access to memory in favor of another access request is shown.

[0008] Figure 3 An example sequence diagram showing access between system elements according to an embodiment is shown.

[0009] Figure 4 An example operating environment is shown that may be configured to perform memory access prioritization in an embodiment.

[0010] Figure 5 An example operating environment is shown that may be configured to perform memory access prioritization and scheduling in an embodiment.

[0011] Figure 6 Computing devices that may be used in accordance with some examples of the present technology are shown.

[0012] The drawings are not necessarily drawn to scale. In the drawings, the same reference numerals indicate corresponding parts throughout the several views. In some examples, components or operations may be separated into different blocks or may be combined into a single block. DETAILED DESCRIPTION

[0013] This article discusses enhancement components, techniques and systems related to prioritization and preemption of access to memory by one or more processors. A processor may be responsible for executing software to implement the functions of an application, device or system. However, under design constraints, cost and other considerations, a processor may lack the ability to execute all the code and data of the software from an internal (e.g., volatile) memory. Therefore, a non-volatile memory such as a flash memory may be included in a system external to the processor. In such a system, some code and data may be stored in an internal memory (e.g., RAM) at runtime, while other code and data may be stored in an external non-volatile memory (e.g., flash memory) at runtime. The processor may attempt to access both the internal memory and the external memory during the execution of the software. In various examples, the processor may have multiple processing cores that execute code and perform reads and writes simultaneously using an external flash memory. The problem is that previous solutions cannot provide a prioritization technique for requests between multiple processors. In addition, such a prioritization technique cannot weigh factors between various flash memory access requests, such as whether the request is for real-time execution, interruption or critical request, or whether one or more requests corresponding to one of the processors are executed at a threshold rate.

[0014] The system discussed herein can monitor the status of multiple processors of the system, the addresses that multiple processors attempt to access, and the rates at which multiple processors read from or write to flash memory to determine the priority of requests to access flash memory. Advantageously, such logic can increase the overall processing power of each of the multiple processors and allow ongoing access requests for other high-priority access requests to be preempted without using multiple flash memories.

[0015] In an example embodiment, a system is provided. The system includes a memory access circuit system and a processing circuit system coupled to the memory access circuit system. The memory access circuit system is configured to receive a read request corresponding to an instruction set stored in a non-volatile memory for execution by the processing circuit system, determine whether to preempt a current access to the non-volatile memory corresponding to the one or more access requests to support the read request based on a priority of the read request relative to one or more access requests, obtain the instruction set from the non-volatile memory, and provide the instruction set to the processing circuit system. The processing circuit system executes the instruction set.

[0016] In another example, a memory access circuit system is provided. The memory access circuit system includes an interface circuit system and an access circuit system coupled to the interface circuit system. The interface circuit system is configured to receive a read request corresponding to an instruction set stored in a non-volatile memory that can be executed by a processing circuit system, and provide an indication of the read request to the access circuit system. The access circuit system is configured to determine whether to preempt a current access to the non-volatile memory corresponding to the one or more access requests to support the read request based on a priority of the read request relative to one or more access requests, obtain an instruction set from the non-volatile memory, and provide the instruction set to the processing circuit system.

[0017] In yet another embodiment, a method is provided. The method includes receiving a read request corresponding to a set of instructions stored in a non-volatile memory executable by a processing circuit system, determining whether to preempt a current access to the non-volatile memory corresponding to the one or more access requests in support of the read request based on a priority of the read request relative to one or more access requests, obtaining the set of instructions from the non-volatile memory, and providing the set of instructions to the processing circuit system.

[0018] Figure 1 An example environment for scheduling accesses to memory is shown, according to an embodiment. Figure 1 An operating environment 100 is shown that includes a system 110, a non-volatile memory 120, and a random access memory (RAM) 130. The system 110 includes a memory access circuitry 112, a processing circuitry 114, and a memory 116. The non-volatile memory 120 includes XIP code 122, read-only data 124, and loadable instructions 126. The memory access circuitry 112 may provide access to the non-volatile memory 120 and the RAM 130 to the processing circuitry 114. To provide such access, the memory access circuitry 112 may be configured to perform access procedures, such as Figure 2 process 200.

[0019] System 110 represents a processing system, such as a microcontroller unit (MCU), which includes various hardware elements configured to execute access processes, software and / or firmware to implement functions based thereon. System 110 includes memory access circuitry 112, processing circuitry 114, and memory 116 storing code 117 and data 118. System 110 may be coupled to non-volatile memory 120 and RAM 130, which system 110 may use to execute application code (e.g., code 117). System 110 may also be coupled to one or more peripheral devices (not shown), which may obtain results and data from the execution of the application code to implement the functions of the one or more peripheral devices.

[0020] Memory access circuitry 112 represents one or more hardware components configured to provide processing circuitry 114 with access to memory 116, non-volatile memory 120, and RAM 130 for executing application code. For example, memory access circuitry 112 may be a hardware accelerator (HWA) that includes hardware elements that are coupled to receive access requests (e.g., read, write) from processing circuitry 114 and are coupled to provide access to memory 116, non-volatile memory 120, and RAM 130 based on the access requests and their scheduling or priority ordering queues. Memory access circuitry 112 may further include one or more interfaces for communicating with memory 116, non-volatile memory 120, and RAM 130. For example, memory access circuitry 112 may include one or more serial peripheral interfaces (SPI), extended serial peripheral interfaces (xSPI), or octal serial peripheral interfaces (OSPI).

[0021] Processing circuit system 114 represents one or more processors or processing cores capable of executing software and firmware (e.g., code 117 and / or XIP code 122). Such processors may include microcontrollers, DSPs, general-purpose central processing units, special-purpose processors or circuits (e.g., ASICs), and logic devices (e.g., FPGAs), as well as any other type of processing device, combination, or variation thereof. Code 117 may be initially stored in non-volatile memory 120 and copied to memory 116 for execution by processing circuit system 114, while XIP code 122 is configured to be executed directly from non-volatile memory without first being copied to memory 116. When executing code 117 or XIP code 122, processing circuit system 114 may attempt to access memory 116 or non-volatile memory 120, respectively. An access attempt may refer to a read request in which processing circuit system 114 reads instructions or data 118 from one or more addresses of memory 116 or non-volatile memory 120 to perform processing or calculations using instructions or data 118, or an access attempt may refer to a write request in which processing circuit system 114 writes data 118 to one or more addresses of memory 116 or non-volatile memory 120.

[0022] Memory 116 represents a computer-readable storage medium located on system 110. For example, memory 116 may represent a level 1 (L1) RAM, a tightly coupled memory (TCM), or another type of memory. Although only one block is shown in operating environment 100, memory 116 may be implemented as multiple memories working in an integrated or separate manner. Memory 116 may store code 117 and data 118. Code 117 may include application code, such as instructions that enable functions when executed by processing circuit system 114. Data 118 may include results and / or other information related to code 117, XIP code 122, loadable instructions 126, etc. Processing circuit system 114 may access memory 116 via memory access circuit system 112 to execute code 117 thereon.

[0023] The non-volatile memory 120 represents a non-volatile computer-readable storage medium that is external to the system 110. For example, the non-volatile memory 120 may represent a flash memory. The non-volatile memory 120 may be included to provide additional capacity for storing instructions and data. The non-volatile memory 120 stores XIP code 122, read-only data 124, and loadable instructions 126.

[0024] XIP code 122 includes different program instructions relative to the program instructions of code 117. As an example, code 117 may include a first instruction set executable by processing circuitry 114, while XIP code 122 may include a second instruction set, different from the first instruction set, executable by processing circuitry 114 directly from non-volatile memory 120. Thus, XIP code 122 may represent instructions that may be executed from non-volatile memory 120 without first loading XIP code 122 onto memory 116 or RAM 130.

[0025] Read-only data 124 includes data stored on nonvolatile memory 120 that is different from data 118 stored in memory 116. For example, read-only data 124 may include a result corresponding to execution of XIP code 122, initialization information related to nonvolatile memory 120, and the like.

[0026] Loadable instructions 126 include initialization information and data related to the startup of RAM 130. For example, when system 110 starts (i.e., processing circuit system 114 executes startup code from read-only memory (ROM) (not shown)), system 110 can obtain loadable instructions 126 from non-volatile memory 120 to configure RAM 130 and execute code from RAM 130.

[0027] RAM 130 represents a volatile computer-readable storage medium. RAM 130 may include static RAM (SRAM), dynamic RAM (DRAM), or other types of memory, such as double data rate (DDR). System 110 may be coupled to RAM 130 and execute code 117 from RAM 130. In some examples, code 117 and other information and data may be moved to RAM 130 before processing circuitry 114 executes instructions from RAM 130.

[0028] In operation, the system 110 may receive a processing request to execute a program instruction from a peripheral device (not shown). The program instruction may include operations and addresses associated with the non-volatile memory 120 (e.g., XIP code 122) and different operations and addresses associated with the RAM 130 (e.g., code 117). In response to receiving the request, the processing circuit system 114 may be configured to execute one or more requests to access the non-volatile memory 120 and / or the RAM 130 based on the operations and addresses in the program instructions.

[0029] As an example, the first portion of the program instructions may include a first access request to read data from RAM 130. Therefore, processing circuitry 114 may attempt to read the corresponding data from RAM 130 via memory access circuitry 112. In response to the attempt to read from RAM 130, memory access circuitry 112 may allow the read request from RAM 130, and processing circuitry 114 may read the corresponding data from RAM 130.

[0030] As another example, the second portion of the program instructions may include a second access request to read read-only data 124 from non-volatile memory 120. Therefore, processing circuitry 114 may attempt to read the corresponding read-only data 124 from non-volatile memory 120 via memory access circuitry 112. Memory access circuitry 112 may determine whether there are other ongoing requests for access to non-volatile memory 120, and in response to determining that there are no other ongoing requests, allow processing circuitry 114 to read read-only data 124 from RAM 130.

[0031] Following the previous example, the third portion of the program instructions may include a third access request to execute the XIP code 122 from the non-volatile memory 120. At the time this third access request is received, a second access request related to reading the read-only data 124 from the non-volatile memory 120 may be ongoing, or in other words, the processing circuitry 114 may still be reading the read-only data 124 from the non-volatile memory 120 at this time. The memory access circuitry 112 may identify the second access request and the third access request, and identify a priority of the third access request relative to the second access request.

[0032] In some examples, the memory access circuit system 112 may determine the priority of the request based on the state of the processing circuit system 114. This may require determining the type of request (e.g., read, write, or execute), the mode of the processing circuit system 114 at the time of the request (e.g., operating mode, exception mode, secure mode, privileged mode, or whether the processing circuit system 114 makes the request in response to receiving an interrupt from a peripheral device), and other factors, such as whether a user-defined signal indicating a high priority has been provided to the memory access circuit system 112. In other examples, the memory access circuit system 112 may determine the priority of the request based on the address sought to be written or read in the two access requests. In some other examples, the memory access circuit system 112 may determine the priority based on the two methods described. Alternatively, the memory access circuit system 112 may recognize that the third request corresponds to the execution of the XIP code 122, so the memory access circuit system 112 may gradually upgrade the third access request regardless of other ongoing accesses.

[0033] Still referring to this example, the memory access circuitry 112 may determine that the priority of the third access request associated with the execution of the XIP code 122 has a higher priority relative to the second access request associated with the reading of the read-only data 124. Therefore, the memory access circuitry 112 may preempt the ongoing read request and allow the processing circuitry 114 to execute the XIP code 122 before the read request is completed. After executing the XIP code 122 from the non-volatile memory 120, the memory access circuitry 112 may resume the second access request, whereby the processing circuitry 114 may continue to read the data 124 from the non-volatile memory 120. For example, in this case, the memory access circuitry 112 may store the context associated with the preempted access request and restore the context after the execution of the XIP code 122 when resuming the initial access request.

[0034] These examples discuss only a few cases and a few types of access requests, however, any combination or variation of access requests to different types of memory can be considered. Regardless of the request type, the memory access circuit system 112 can prioritize access to the non-volatile memory 120 to ensure that the requests are executed in an order that at least improves the processing efficiency of the processing circuit system 114 by following the priority sorting scheme. In various examples, the processing circuit system 114 can include multiple processing circuit systems or cores. Each processing circuit system can attempt to access the non-volatile memory 120 at the same time. Therefore, the memory access circuit system 112 can prioritize access between each processing circuit.

[0035] Figure 2 A series of steps in an implementation scheme for preempting access to memory in favor of another access request is shown. Figure 2 The process 200 described below includes the process 200 described below. Figure 1 Process 200 may be implemented in software, firmware, and / or fixed-purpose hardware, or any combination or variation thereof. For example, a memory access circuit system, such as Figure 1 The memory access circuit system 112 may perform the process 200.

[0036] In operation 205, memory access circuitry 112 receives a read request corresponding to XIP code 122 of non-volatile memory 120. Processing circuitry 114, representing one or more processors or processing cores capable of executing software and firmware, may provide a read request when assigned to execute program instructions according to commands from a peripheral device to attempt to read XIP code 122 from non-volatile memory 120. When executing such program instructions, processing circuitry 114 may attempt to access non-volatile memory 120 or RAM 130 to execute XIP code 122 or code 117, respectively. In this example, a first processing core of processing circuitry 114 may attempt to read one or more blocks of information of XIP code 122 for execution.

[0037] In operation 210, the memory access circuit system 112 preempts current access to the non-volatile memory 120 corresponding to the one or more access requests to the non-volatile memory 120 in support of the read request based on the priority of the read request relative to the one or more access requests to the non-volatile memory 120. The current access may refer to concurrent or simultaneous access to the non-volatile memory 120, whereby a processing core of the processing circuit system 114 attempts to read from or write to the non-volatile memory 120 at the same time or during overlapping time frames as a different processing core of the processing circuit system 114. For example, when the first processing core attempts to read one or more information blocks of the XIP code 122, one or more processing cores of the processing circuit system 114 may access the non-volatile memory 120. Therefore, the memory access circuit system 112 may be configured to determine the priority of the read request from the first processing core to determine whether to preempt the current access to the non-volatile memory 120.

[0038] In order to determine the priority of read requests corresponding to the execution of XIP code 122 and other access requests, the memory access circuit system 112 can follow a prioritization scheme. The prioritization scheme can generally identify the real-time execution of XIP code 122 as the highest priority relative to other access requests, such as large read requests, write requests, and best-effort (i.e., non-real-time) execution of XIP code 122. In the prioritization scheme, write requests can be considered to be the lowest priority. However, in various examples, the memory access circuit system 112 can preempt large read requests and best-effort requests in favor of write requests. Other scenarios regarding prioritization and preemption can be envisioned. As an example, in operation 211, the memory access circuit system 112 can identify the state of the processing core accessing the non-volatile memory 120 and / or identify the address set corresponding to the read request. Determining the state of the processing core may require identifying the type of request, such as read, write, or execute; the mode of the processing core at the time of the request, such as operating mode, exception mode, secure mode, privileged mode; or whether the processing core has treated the request as an interrupt event; and other factors, such as whether a user-defined signal indicating a high priority has been provided to the memory access circuit system 112. The memory access circuit system 112 may alternatively or additionally determine the priority of the read request based on the address that the first processing core seeks to access. For example, the memory access circuit system 112 may mark a specified address as a higher or lower priority than other addresses. In some other examples, the memory access circuit system 112 may determine both the state and the address.

[0039] In operation 212, the memory access circuit system 112 may determine a relative access rate corresponding to one or more access requests relative to a threshold access rate to determine a priority. The access rate may refer to a write speed or a progress rate at which a processing core writes to the non-volatile memory 120 relative to a clock signal. The threshold access rate may be a user-defined, pre-configured value. The memory access circuit system 112 may compare the access rate of an ongoing access request with the threshold access rate to determine whether the ongoing access request is below, meets, or exceeds the threshold access rate. In various examples, operation 212 may be used to determine whether to gradually upgrade the priority of a write request among other access requests. Therefore, operation 212 may be optional because the memory access circuit system 112 is determining whether to gradually upgrade access requests associated with the execution of the XIP code 122. However, operation 212 may also be used to determine whether to gradually upgrade other types of access requests.

[0040] In operation 213, the memory access circuit system 112 determines the priority based on the state, address set and / or relative access rate. As an example, the memory access circuit system 112 can determine that the first processing core providing the read request is functioning in the operating mode, and therefore the read request involves a real-time XIP request. Therefore, the memory access circuit system 112 can determine that the read request has a higher priority than other ongoing access requests. As another example, the memory access circuit system 112 can determine that the first processing core is trying to execute a portion of the XIP code 122 at a high priority address set. Therefore, the portion of the XIP code 122 can be a critical portion of a program instruction. Therefore, the memory access circuit system 112 can determine that the read request has a higher priority than other ongoing access requests. As another example, the memory access circuit system 112 can determine that other processing cores are writing to the non-volatile memory 120 at a rate greater than a threshold access request. In this case, the memory access circuitry 112 may determine that the read request has a higher priority than other ongoing access requests, particularly because the other access requests are accessing the non-volatile memory 120 at a rate sufficient not to cause delays elsewhere in the processing system. Any combination or variation of prioritization methods may be used, and the memory access circuitry 112 may weight the results from each method in a manner that improves code execution performance.

[0041] After the memory access circuitry 112 determines that the read request from the first processing core has a higher priority than another ongoing access request, the memory access circuitry 112 may preempt access to the non-volatile memory 120 in favor of the read request. This may require preventing or stopping access to the non-volatile memory 120 with respect to other processing cores and corresponding access requests. Although access may be temporarily stopped, the memory access circuitry 112 may store the context (e.g., address, data, instruction) of the stopped access so that the memory access circuitry 112 may resume access from the same point at a later time after resuming access.

[0042] Next, in operation 215, memory access circuitry 112 obtains XIP code 122 from non-volatile memory 120. Memory access circuitry 112 may identify the address set corresponding to the read request and interface with non-volatile memory 120 to obtain XIP code 122 or a block thereof.

[0043] In operation 220, memory access circuitry 112 provides XIP code 122 to processing circuitry 114, or more specifically in this example, to a first processing core of processing circuitry 114. In various examples, processing circuitry 114 may read and execute blocks of XIP code 122 directly on non-volatile memory 120. As a result of executing XIP code 122, processing circuitry 114 may output one or more results related to execution of XIP code 122 for downstream use, such as use by one or more peripheral devices.

[0044] In some cases, process 200 may not apply to access requests directed to executing XIP code 122. In fact, such access requests may be automatically stepped up to the highest priority and immediately acted upon by memory access circuitry 112 and processing circuitry 114 based on a prioritization scheme. In such cases, process 200 may apply to access requests other than access requests associated with executing XIP code 122 (i.e., large read, write, best-effort XIP requests for read-only data 124). However, in other cases, process 200 may apply to any access request from any number of processors.

[0045] Figure 3 An example sequence diagram showing access between system elements according to an embodiment is shown. Figure 3An operating environment 300 is included, which includes non-volatile memory 305, access scheduler 310, processing circuitry 315, and memory 320. The elements of operating environment 300 may represent elements of operating environment 100, such as non-volatile memory 120, memory access circuitry 112, processing circuitry 114, and memory 116 and RAM 130, respectively.

[0046] At a first time, a peripheral device coupled to a processing system including elements of operating environment 300 may initiate execution of program code. Processing circuitry 315, representing one or more processing cores, may obtain program code from memory 320. The program code may include instructions and addresses corresponding to instructions in memory 320 and / or non-volatile memory 305. In some examples, memory 320 may be on-chip memory, such as a level 1 (L1) RAM, a tightly coupled memory, or other type of memory (e.g., Figure 1 In other examples, memory 320 may be a level 2 (L2) RAM (e.g., Figure 1 The processing circuit system 315 may execute the program code or information blocks thereof, which may cause the processing circuit system 315 to provide access requests to the access scheduler 310 to access (eg, read or write) the non-volatile memory 305.

[0047] The access scheduler 310 represents one or more hardware components configured to provide access to one or more memories (e.g., memory 320 and non-volatile memory 305) in the system to the processing circuit system 315 for executing program code and XIP code. For example, the access scheduler 310 can be a hardware accelerator (HWA) that includes a hardware element coupled to receive access requests (e.g., read, write) from the processing circuit system 315 and coupled to provide access to the memory 320 and non-volatile memory 305 based on the access request and its scheduling or queue. The access scheduler 310 may further include one or more interfaces (e.g., SPI, OSPI, xSPI) for communicating with the memory 320 and non-volatile memory 305.

[0048] The access scheduler 310 may allow the processing circuitry 315 to access the non-volatile memory 305 for a period of time, such as until the processing circuitry 315 has completed executing program code, or until an interrupt, address jump, or higher priority intervening event occurs. Figure 3In the example shown, the processing circuit system 315 can provide a further access request to the access scheduler 310 while executing the program code. This access request can include a read request corresponding to the XIP code stored in the non-volatile memory 305. As shown, this access request can occur when the processing circuit system 315 accesses the non-volatile memory 305 via a previous access request. When the access scheduler 310 receives the read request, the access scheduler 310 can determine that the priority of the read request is higher than the priority of the previously ongoing access request, so the access scheduler 310 can preempt the access request and suspend access to the non-volatile memory 305 relative to the first access request. Once the access scheduler 310 suspends the first access request, the access scheduler 310 can allow the processing circuit system 315 to read the XIP code from the non-volatile memory 305. The processing circuit system 315 can execute the XIP code from the non-volatile memory 305.

[0049] After completing execution of the XIP code from the non-volatile memory 305 , the access scheduler 310 may resume access to the non-volatile memory 305 corresponding to the previously suspended first access request.

[0050] Figure 4 An example operating environment is shown that may be configured to perform memory access prioritization in an embodiment. Figure 4 An operating environment 400 is included, which includes processors 410 , 411 , and 412 , a processor state prioritization engine 415 , a region prioritization engine 420 , a priority selector 425 , and a request queue map 430 .

[0051] Processors 410, 411, and 412 represent any type of processor or processing core of a system (e.g., a microcontroller unit) capable of executing software and firmware. Examples of such processors may include general-purpose central processing units, special-purpose processors or circuits (e.g., ASICs), and logic devices (e.g., FPGAs), as well as any other type of processing device, combination, or variation thereof. For example, processors 410, 411, and 412 may embody Figure 1 The processing circuit system 114 or Figure 3 The processing circuitry 315 may include multiple processing cores. Although three processors are shown in the operating environment 400, any number of processors may be used in the system.

[0052] In various examples, processors 410, 411, and 412 may each be configured to execute different information blocks of application code to implement the functionality of the system. Processor 410 may be configured to execute a first instruction set corresponding to the application code, processor 411 may be configured to execute a second instruction set corresponding to the application code, and processor 412 may be configured to execute a third instruction set corresponding to the application code. Thus, each of processors 410, 411, and 412 may attempt to access one or more memories (e.g., non-volatile memory and / or volatile storage) while executing application code. When processors 410, 411, and 412 attempt to access non-volatile memory (e.g., Figure 1 When accessing the non-volatile memory 120 ), the processors 410 , 411 , and 412 may provide access requests to the processor state prioritization engine 415 and / or the region prioritization engine 420 .

[0053] The processor state prioritization engine 415 and the regional prioritization engine 420 represent one or more hardware components configured to identify attempts by processors 410, 411, and 412 to access non-volatile memory and other types of memory. Both the processor state prioritization engine 415 and the regional prioritization engine 420 can identify attempts and prioritize the attempts according to different criteria. In some cases, only one of the processor state prioritization engine 415 and the regional prioritization engine 420 can be used in the system, but in other cases, both can be used to determine the priority among several access requests. In the case where both are used, the overall priority can be determined based on the higher priority of the priorities output by the processor state prioritization engine 415 and the regional prioritization engine 420. Alternatively, the choice of using either or both of the processor state prioritization engine 415 and the regional prioritization engine 420 can be statically selected for any access request or dynamically selected on a per-request basis.

[0054] The processor state prioritization engine 415 can prioritize access requests based on the states of the processors 410, 411, and 412. The states of the processors 410, 411, and 412 can include an operating state, an abnormal state, a secure state, and a privileged state. The state can be determined based on the access type requested (e.g., read, write, execute), the mode of the processor, and / or any other user-defined signal accompanying the access request when the access is requested. Therefore, the processor state prioritization engine 415 can identify the corresponding states of the processors 410, 411, and 412, and classify or sort the access requests based on the states. The regional prioritization engine 420 can prioritize access requests based on the addresses that the processors 410, 411, and 412 are trying to access. The regional prioritization engine 420 can be pre-configured with a mapping or list of addresses and corresponding priorities. For example, some address sets can be marked as having a higher priority than other address sets. The regional prioritization engine 420 can identify the addresses associated with the access requests and prioritize the access requests accordingly.

[0055] Priority selector 425 represents one or more hardware components configured to receive access requests and corresponding priorities from processor state prioritization engine 415 and region prioritization engine 420, and classify access requests into two or more categories (e.g., request queue map 430) based on the priorities. In various examples, priority selector 425 can be configured with pre-configured, user-defined rules and thresholds for classifying access requests. Priority selector 425 can create request map queues 430 and classify access requests into real-time XIP queues 431, best-effort XIP queues 432, large read queues 433, and write queues 434.

[0056] The request mapping queue 430 represents a classified mapping of access requests, corresponding addresses, and corresponding priorities from processors 410, 411, and 412. The real-time XIP queue 431 may contain access requests related to real-time execution of XIP code in non-volatile memory. Real-time execution of XIP code refers to the execution of a program instruction set that can be executed directly from non-volatile memory (i.e., not from RAM) by processors 410, 411, and / or 412 as part of a real-time processing loop in application code that may need to be completed within a time interval. The best-effort XIP queue 432 may contain access requests related to non-real-time execution of XIP code in non-volatile memory. For example, best-effort XIP execution may refer to the execution of a program instruction set from non-volatile memory that produces results that may not be immediately available downstream or by processors 410, 411, or 412 in other executions of application code. In other words, best-effort XIP requests may be more tolerant of delays in accessing non-volatile memory. Large read queue 433 may contain access requests for reading blocks of data information in non-volatile memory that exceed a threshold amount. The threshold amount may be a user-defined, pre-configured amount that priority selector 425 may compare. Write queue 434 may contain access requests for writing data in non-volatile memory.

[0057] Each queue may be assigned an overall priority relative to the other queues, and each request in the queue may have a priority relative to the other requests in the corresponding queue. For example, the real-time XIP queue 431 may have the highest priority among the queues in the request mapping queue 430. The best-effort XIP queue 432 may have the second highest priority. The large read queue 433 may have the third highest priority. The write queue 434 may have the lowest priority. However, in some cases, if the rate at which the processor writes data to the non-volatile memory is lower than a threshold rate, the write queue 434 may have the second highest priority. In this case, the access scheduler (e.g., the access scheduler 310, the memory access circuit system 112) may determine that the write rate is too slow relative to the threshold rate and increase the priority of the write request among the other requests. Any combination, variation or ordering of priorities may be envisioned.

[0058] Figure 5 An example operating environment is shown that may be configured to perform memory access prioritization and scheduling in an embodiment. Figure 5 An operating environment 500 is included, which includes Figure 4 The request queue map 430, event monitoring engine 510, logic gate 515 and access scheduler 520 are provided.

[0059] In operation, access requests from one or more processors (e.g., processors 410, 411, and 412) may be classified and prioritized in request queue map 430. Based on the type of classification within request queue map 430 (real-time XIP queue 431, best-effort XIP queue 432, large read queue 433, write queue 434), the access requests of request queue map 430 may be fed to logic gate 515 and / or access scheduler 520. For example, real-time XIP access requests classified in real-time XIP queue 431 may flow directly to access scheduler 520. However, other requests classified in best-effort XIP queue 432, large read queue 433, and write queue 434 may flow through logic gate 515 before flowing to access scheduler 520.

[0060] Logic gate 515 represents one or more circuits, logic devices, switches, etc., which can be controlled by event monitoring engine 510 to be "closed" to allow access requests from best-effort XIP queue 432, large read queue 433 and write queue 434 to flow to access scheduler 520 or "opened" and prevent access scheduler 520 from receiving such access requests.

[0061] The access scheduler 520 represents one or more hardware components configured to provide access to the processor (e.g. Figure 4 processors 410, 411 and 412, Figure 1 The processing circuit system 114 provides for non-volatile memory (e.g. Figure 1 The access scheduler 520 may be a hardware accelerator (HWA) including a hardware element coupled to receive access requests classified into the request queue map 430 from the processor and coupled to provide access 525 to the non-volatile memory. The access scheduler 520 may include a preemption engine 521 and other components and elements, such as an interface for communicating with a memory (not shown).

[0062] The preemption engine 521 can be configured to preempt or resume access 525 to the non-volatile memory based on the access request and the corresponding priority in the access request. For example, the access scheduler 520 can allow the processor to access the non-volatile memory according to the request queue map 430 at a first time. However, at a second time, the access scheduler 520 can identify an access request of a higher priority (relative to the access at the first time). Therefore, the preemption engine 521 can suspend the ongoing access from the first time, allow the access associated with the higher priority access request at the second time, and then resume the access from the first time and using the same context after the access is completed from the second time. Advantageously, the preemption engine 521 can manage the scheduling of access requests so that not only the critical execution is performed on time, but also the writing and reading of data can be performed at a sufficient rate or within certain time frames so as not to cause delays in the performance of the system.

[0063] The event monitoring engine 510 represents one or more components of the system that are configured to recognize event types 505 and critical section alarms 506 and control logic gates 515 based on the event types 505 and critical section alarms 506. In fact, the event monitoring engine 510 can allow and / or block certain accesses to the non-volatile memory based on the event types 505 and critical section alarms 506.

[0064] The event type 505 may refer to an interrupt event, such as an interrupt event from a peripheral device, a jump event, or any other high-interest and priority event, and therefore is related to access requests categorized within the request queue map 430. For each event identified by the event monitoring engine 510, the event monitoring engine 510 may implement a guard interval, which may include opening or closing a logic gate 515 for a predetermined duration according to the event monitoring lookup table 507. For example, for a high-priority interrupt event corresponding to real-time XIP execution, the event monitoring engine 510 may instruct the logic gate 515 to open for a time interval (e.g., 50 microseconds) to prevent access requests within the best-effort XIP queue 432, the large read queue 433, and the write queue 434 from flowing to the access scheduler 520. The event monitoring engine 510 may then close the logic gate so that other access requests can resume flowing to the access scheduler 520. To do so, the event monitoring engine 510 may include logic that, when executed by the event monitoring engine 510, instructs the event monitoring engine 510 to open or close the logic gate 515 for a certain amount of time according to the event monitoring lookup table 507. As an example, for a first event (e.g., event 1) of event type 505, the event monitoring engine 510 may identify the event type 505, identify a time interval corresponding to the event type 505, and close the logic gate 515 for the amount of time identified in the event monitoring lookup table 507. Although only "event" is shown in the event monitoring lookup table 507, the event monitoring lookup table 507 may alternatively or additionally include an interval time corresponding to the critical section alarm 506. Advantageously, this may allow the access scheduler 520 to read only the real-time XIP access requests from the real-time XIP queue 431 associated with the interrupt event, and allow one or more processors to access 525 the non-volatile memory to execute the XIP code.

[0065] The critical section alarm 506 may include a signal that an access request associated with the execution of the XIP code and therefore associated with the access request classified within the request queue map 430 is associated with a high priority address or a high importance operation implemented by executing the XIP code. For example, the event monitoring engine 510 may include a binary memory mapped register (MMR) that identifies the critical information block of the XIP code. If the processor attempts to execute any identified critical information block, the event monitoring engine 510 may open the logic gate 515 so that the access scheduler 520 only receives access requests corresponding to the critical information block of the XIP code and thus allows access 525 based on the access request.

[0066] In various examples, event monitoring engine 510 may perform such activities via hardware, software, firmware, or any combination or variation thereof.

[0067] Although some of the examples provided herein are described in the context of systems on a chip, processors, microcontroller units, circuit systems, environments, etc., it should be understood that the memory access methods, techniques, and systems described herein are not limited to such examples and can be applied to various other processes, systems, applications, devices, etc. Aspects of the present invention may be embodied as systems, methods, computer program products, and other configurable systems. Therefore, aspects of the present invention may take the form of a complete hardware embodiment, a complete software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects (all of which may be collectively referred to as "circuits", "modules", or "systems" herein). In addition, aspects of the present invention may take the form of a computer program product implemented in one or more computer-readable media, the computer-readable media having computer-readable program code implemented thereon.

[0068] Unless the context clearly requires otherwise, throughout the specification and claims, the words "comprise", "comprising", etc. should be interpreted in an inclusive sense, rather than in an exclusive or exhaustive sense, that is, in the sense of "including but not limited to". As used herein, the terms "connect", "couple" or any variation thereof mean any connection or coupling, direct or indirect, between two or more elements; the coupling or connection between elements can be physical, logical or a combination thereof. In addition, the words "herein", "above", "below" and words of similar meaning, when used in this application, should refer to the application as a whole, rather than to any particular part of the application. Where the context permits, the words used in the singular or plural in the above specific embodiments may also include the plural or singular, respectively. The word "or", when referring to a list of two or more items, covers all the following interpretations of the word: any item in the list, all items in the list, and any combination of items in the list.

[0069] The phrases "in some examples," "according to some examples," "in the examples shown," "in other examples," etc. generally mean that the particular feature, structure, or characteristic following the phrase is included in at least one embodiment of the present technology, and may be included in more than one embodiment. Additionally, such phrases are not necessarily referring to the same example or different examples.

[0070] The above specific implementation of the example of technology is not intended to be exhaustive or to limit the technology to the exact form disclosed above. Although the specific examples of technology are described above for illustrative purposes, as those skilled in the relevant art will recognize, various equivalent modifications can be made within the scope of technology. For example, although processes or blocks are presented in a given order, alternative embodiments can perform routines with steps in different orders or adopt systems with blocks, and some processes or blocks can be deleted, moved, added, subdivided, combined and / or modified to provide alternatives or sub-combinations. Each of these processes or blocks can be implemented in various different ways. And, although processes or blocks are sometimes shown as serial execution, these processes or blocks can be executed or implemented in parallel instead, or can be executed at different times. In addition, any specific numbers mentioned herein are only examples; alternative embodiments can adopt different values ​​or ranges.

[0071] The teachings of the technology provided herein can be applied to other systems, not necessarily the systems described above. The elements and actions of the various examples described above can be combined to provide further embodiments of the technology. Some alternative embodiments of the technology can include not only the additional elements of those implementations mentioned above, but also fewer elements.

[0072] According to the above specific embodiments, these and other changes can be made to the technology. Although the above description describes certain examples of the technology and describes the expected best mode, no matter how detailed the above content appears in this article, the technology can be practiced in many ways. The details of the system can vary considerably in its specific implementation, while still being covered by the technology disclosed herein. As mentioned above, the specific terms used when describing certain features or aspects of the technology should not be understood to imply that the term is redefined herein as any specific characteristic, feature or aspect of the technology associated with the term. In general, unless such terms are clearly defined in the above specific implementation section, the terms used in the attached claims should not be interpreted as limiting the technology to the specific examples disclosed in the specification. Therefore, the actual scope of the present technology not only covers the disclosed examples, but also includes all equivalent ways of practicing or realizing the present technology under the claims.

[0073] In order to reduce the number of claims, certain aspects of the technology are presented below in certain claim forms, but applicants consider various aspects of the technology in any number of claim forms. For example, although only one aspect of the technology is described as a computer-readable media claim, other aspects may also be embodied as a computer-readable media claim, or in other forms, such as means-plus-function claims. It is expected that any claim processed under 35 U.S.C. §112(f) will begin with "members for," but the use of the term "for" in any other context is not intended to invoke processing under 35 U.S.C. §112(f). Therefore, applicants reserve the right to seek additional claims after filing this application to seek such additional claim forms in this application or a continuation application.

Claims

1. A system comprising: A memory access circuit system configured to: receiving a read request corresponding to a set of instructions stored in a non-volatile memory for execution by the processing circuitry; determining whether to preempt a current access to the non-volatile memory corresponding to the one or more access requests in support of the read request based on a priority of the read request relative to one or more access requests; obtaining the instruction set from the non-volatile memory; and providing the instruction set to the processing circuitry; as well as The processing circuitry is coupled to the memory access circuitry and is configured to execute the set of instructions.

2. The system of claim 1 , wherein, in order to preempt current access to the non-volatile memory, the memory access circuit system is further configured to determine the priority based on a state of the processing circuit system, wherein the state of the processing circuit system includes one or more of an operating state, an abnormal state, a privileged state, and a secure state. 3 . The system of claim 2 , wherein the priority is further based on a user-defined signal accompanying the read request.

4. The system of claim 1 , wherein, to preempt current access to the non-volatile memory, the memory access circuit system is further configured to determine the priority based on a first address set corresponding to the instruction set and a second address set corresponding to the one or more access requests.

5. The system of claim 1, wherein the one or more access requests include large read requests, write requests, and non-real-time read requests corresponding to the instruction set.

6. The system of claim 1 , wherein the memory access circuit system is further configured to prioritize the current access to the non-volatile memory based on a prioritization scheme, wherein the prioritization scheme defines a read request corresponding to an instruction set for execution by the processing circuit system as a highest priority, a non-real-time read request corresponding to an instruction set for execution by the processing circuit system as a second highest priority, a large read request for data as a third highest priority, and a write request as a fourth highest priority.

7. The system of claim 6, wherein the memory access circuitry is configured to resume the current access to the non-volatile memory after the processing circuitry executes the set of instructions according to the prioritization scheme.

8. The system of claim 6, wherein the memory access circuitry is further configured to escalate the priority of the write request above the non-real-time read request and the large read request based on determining that a write progress rate drops below a write progress threshold rate.

9. The system of claim 1, further comprising event monitoring circuitry coupled to the memory access circuitry and configured to provide the one or more access requests to the memory access circuitry.

10. The system of claim 1 , wherein the event monitoring circuitry is further configured to provide the one or more access request delay intervals to the memory access circuitry in response to identifying that the one or more access requests correspond to a non-critical portion of an instruction for execution by the processing circuitry.

11. A memory access circuit system, comprising: interface circuitry; and access circuitry coupled to the interface circuitry; wherein the interface circuit system is configured to: receiving a read request corresponding to a set of instructions stored in the non-volatile memory that are executable by the processing circuitry; and providing an indication of the read request to the access circuitry; and wherein the access circuitry is configured to: determining whether to preempt a current access to the non-volatile memory corresponding to the one or more access requests in support of the read request based on a priority of the read request relative to one or more access requests; obtaining the instruction set from the non-volatile memory; and The set of instructions is provided to the processing circuitry.

12. The memory access circuitry of claim 11, wherein to preempt current access to the non-volatile memory, the access circuitry is further configured to determine the priority based on a state of the processing circuitry.

13. The memory access circuitry of claim 12, wherein the state of the processing circuitry comprises one or more of an operational state, an exception state, a privileged state, and a secure state.

14. The memory access circuitry of claim 12, wherein the priority is further based on a user defined signal accompanying the read request.

15. The memory access circuit system of claim 11, wherein in order to preempt current access to the non-volatile memory, the access circuit system is further configured to determine the priority based on a first address set corresponding to the instruction set and a second address set corresponding to the one or more access requests for data.

16. The memory access circuitry of claim 11, wherein preempting a current access to the non-volatile memory is further based on a write progress rate of a write request of the one or more access requests relative to a threshold write progress rate.

17. A method of operating a memory controller, comprising: receiving a read request corresponding to a set of instructions stored in a non-volatile memory that are executable by the processing circuitry; determining whether to preempt a current access to the nonvolatile memory corresponding to one or more access requests to the data in support of the read request based on a priority of the instruction set relative to the data; obtaining the instruction set from the non-volatile memory; as well as The set of instructions is provided to the processing circuitry.

18. The method of claim 17, wherein preempting current access to the non-volatile memory comprises determining the priority based on a state of the processing circuitry.

19. The method of claim 18, wherein the state of the processing circuitry comprises one or more of an operational state, an exception state, a privileged state, and a secure state.

20. The method of claim 17, wherein preempting current access to the non-volatile memory comprises determining the priority based on a first set of addresses corresponding to the instruction set and a second set of addresses corresponding to the one or more access requests.

Images