Memory module, electronic equipment and signal transmission method

Abstract

The embodiment of the invention discloses a memory module, electronic equipment and a signal transmission method. The memory module is a dual-in-line memory module, a fool-proof bayonet and a locking bayonet are arranged on a circuit board of the memory module, and a plurality of memory chips are respectively arranged on two side board surfaces of the circuit board; wherein the plurality of memory chips are connected with the processing chip through a parallel bus, and the processing chip is connected with the golden finger interface through a serial bus. Through the arrangement, the memory module can realize a serial interconnection relation through the connector, the data transmission rate can be reliably improved, crosstalk and synchronous switch noise generated by high-speed transmission based on a parallel bus are avoided, and the SI is effectively improved; the actual occupied area is small, and high-density layout is facilitated. On the whole, technical guarantee is provided for high-density layout and high-performance operation of the architecture. In addition, the physical space occupied by the memory module is roughly the same as that occupied by a traditional memory bank, and structural standardization design of a mainboard is facilitated.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer hardware, and in particular to a memory module, an electronic device, and a signal transmission method. Background Art

[0002] The dual in-line memory module (DIMM) connector is used in the double data rate (DDR) parallel bus system. The DIMM connector is used to install and connect the memory stick to achieve the connection between the central processing unit (CPU) and the synchronous dynamic random access memory (SDRAM) particles configured on the internal stick. Through this connection, an efficient and low-cost memory system is formed between the CPU and the storage medium, achieving fast read and write access operations.

[0003] With the development of data-intensive applications such as high-performance computing and artificial intelligence, the demand for memory system bandwidth and capacity continues to increase, which has promoted the continuous improvement of DDR parallel bus speed and SDRAM particle capacity on memory sticks. At present, the DDR parallel bus has gradually transitioned from the 4th generation DDR (DDR4) to the 5th generation DDR (DDR5), and the single-line rate has also increased from 2.133Gbps to 3.2Gbps to 4.8Gbps to 8.4Gbps. Due to problems such as crosstalk and simultaneous switching noise (SSN), further increasing the single-line rate will affect signal integrity (SI).

[0004] In order to solve the problem of memory system bandwidth and capacity, the industry has proposed a serial memory solution to achieve memory expansion. Among them, different connection methods can be used between the memory expansion module and the motherboard. A typical method is to use the GENZ (Generation Z, a high-speed protocol) connector for vertical plug-in connection. The height of the GENZ connector is relatively high, and due to the limitation of the internal space of the device, the board width of the memory expansion module cannot meet the layout requirements of larger-sized expansion chips; another typical method is to use the GENZ splint connector for flat plug-in connection. The memory expansion module is arranged parallel to the motherboard, which occupies a large space on the motherboard surface, which is not conducive to the high-density implementation of the architecture. Summary of the invention

[0005] The embodiments of the present application provide a memory module and an electronic device, which, on the basis of effectively improving the signal transmission rate, provide technical support for improving SI and taking into account the design requirements of high-density architecture layout.

[0006] The first aspect of the embodiment of the present application provides a memory module, which includes a circuit board, a processing chip and a plurality of memory chips arranged on the circuit board, and a gold finger interface located at the edge of the circuit board; wherein, the circuit board is provided with an anti-fool card slot and a locking card slot, and a plurality of memory chips are arranged on the two side panels of the circuit board respectively; wherein, a plurality of memory chips are connected to the processing chip through a parallel bus, and the processing chip is connected to the gold finger interface through a serial bus. With such a configuration, the memory module can realize a serial interconnection relationship through a connector. On the one hand, the serial bus can reliably improve the data transmission rate, and can avoid the crosstalk and synchronous switching noise generated by high-speed transmission based on the parallel bus to a certain extent, meet the reliability and stability requirements of signal transmission, and effectively improve SI. On the other hand, based on the relatively small height size of the DIMM connector, for the same assembly space, the circuit board provided by this scheme has a relatively large board width, which can realize the layout of larger devices; and the memory module is a vertical plug-in connection method, and the actual board area is small. On the whole, it provides technical guarantee for the high-density layout and high-performance operation of the architecture.

[0007] In addition, the physical space occupied by the memory module in the electronic device is roughly the same as the physical space occupied by the traditional memory stick, which is conducive to the structural standardization design of the electronic device motherboard and can further improve the structural compatibility of the memory module and the motherboard.

[0008] Exemplarily, the memory module may be a memory expansion card, and the processing chip may be a memory expansion chip for managing and controlling a plurality of memory chips to ensure compatibility and coordination with the computer system. For example, the computer system may determine the data storage location according to the access frequency, for example, data with a high access frequency may be stored in the storage space provided by the system memory bar, and data with a relatively low access frequency may be stored in the storage space provided by the memory chip of the memory expansion card, thereby improving the performance and processing capability of the computer system.

[0009] Based on the first aspect, the embodiment of the present application also provides a first implementation of the first aspect: the gold finger interface includes a second power pin area, a management control signal pin area and a serial bus pin area, which are respectively arranged on both sides of the circuit board; wherein the first power pin area is used to provide a first voltage power supply, and the second power pin area is used to provide a second voltage power supply, and the voltage of the second voltage power supply is lower than the voltage of the first voltage power supply; both sides of the circuit board include two serial bus pin areas, in the arrangement direction of the gold finger interface, the first power pin area is located at one end of the circuit board, one serial bus pin area is arranged adjacent to the first power pin area, wherein the other serial bus pin area is located at the other end of the circuit board, and the management control signal pin area and the second power pin area are located between the two serial bus pin areas. In this way, the electromagnetic crosstalk that may be generated by the first power pin area with a higher output voltage to other pin areas can be reduced. In addition, for the management control signal pin area and the second power pin area, they can be flexibly arranged between the two serial bus pin areas as needed to provide part of the power supply and control signal channels for the devices on the circuit board. It has good adaptability.

[0010] Exemplarily, the power provided by the first power pin area is 5V, 6V or 12V, which is converted into a low-voltage power supply (such as 1.2V or 1V, etc.) through the secondary power supply on the circuit board to power devices such as processing chips and memory chips on the circuit board.

[0011] In practical applications, for application scenarios where there are many devices arranged on the circuit board and the overall load is large, the second power pin area can provide partial power supply according to the actual operating status.

[0012] Based on the first implementation of the first aspect, the embodiment of the present application also provides a second implementation of the first aspect: an empty pin is arranged between the first power pin area and the adjacent serial bus pin area, where the "empty pin" refers to a pin on which no signal is defined; based on the setting of the empty pin, the noise of the first power pin area can be effectively prevented from interfering with the differential signal.

[0013] Exemplarily, the number of the empty pins can also be one, or multiple of other numbers. In practical applications, reasonable configuration can be performed while effectively preventing the possible influence of 12V noise.

[0014] Based on the first implementation of the first aspect, or the second implementation of the first aspect, the embodiment of the present application also provides a third implementation of the first aspect: the gold finger interface also includes a differential clock pin to ensure data synchronization in high-speed serial transmission, and the differential clock pin is located between the empty pin and the serial bus pin area arranged adjacent to the first power pin area.

[0015] Based on the first implementation of the first aspect, or the second implementation of the first aspect, or the third implementation of the first aspect, the embodiment of the present application also provides a fourth implementation of the first aspect: wherein the portion of the gold finger interface located on one side of the circuit board is the first-side gold finger, and the portion of the gold finger interface located on the other side of the circuit board is the second-side gold finger; the serial bus pin area includes differential pair pins arranged at intervals, the differential pair pins include two differential signal pins for transmitting differential signals, and a ground pin is arranged between two adjacent pairs of differential pair pins. In this way, crosstalk that may be generated between adjacent differential pairs can be avoided.

[0016] Based on the fourth implementation of the first aspect, the embodiment of the present application further provides a fifth implementation of the first aspect: the serial bus pin area includes eight pairs of differential pair pins arranged at intervals, and the differential pair pins of the first-side gold fingers are arranged alternately with the differential pair pins of the second-side gold fingers. In other words, the first-side gold fingers and the second-side gold fingers are each provided with two eight pairs of serial signal pins, based on which a high-speed transmission bandwidth of X16 can be provided.

[0017] Based on the fourth implementation of the first aspect, or the fifth implementation of the first aspect, the embodiment of the present application also provides a sixth implementation of the first aspect: four ground pins are set between adjacent differential pair pins, and along the arrangement direction of the gold finger interface, the four ground pins on one of the first-side gold fingers and the second-side gold fingers are arranged continuously with a pair of differential pair pins on the other as the center. Based on the four GND pins set at intervals, when the single-line rate further evolves and improves, it has good anti-interference ability; at the same time, on the basis of reducing the signal crosstalk between the two adjacent pairs of differential pair pins on the same surface, it can further reasonably control the signal crosstalk between the differential pin pairs on the two sides.

[0018] Based on the sixth implementation of the first aspect, the embodiment of the present application also provides a seventh implementation of the first aspect: the four ground pins on one side of the first-side gold finger are connected through the first conductor sheet, and the four ground pins on one side of the second-side gold finger are connected through the second conductor sheet; the first conductor sheet is electrically connected to the four third pads, and the second conductor sheet is electrically connected to the four fourth pads, wherein the third pads on one side of the first-side gold finger correspond one-to-one to the fourth pads on one side of the second-side gold finger, and the corresponding third pads and fourth pads on both sides are formed through a via. In this way, based on the setting of the first conductor sheet and the second conductor sheet, and the POFV process to realize the via formation, the pins of each place can be connected to the same ground, which helps to maintain the consistency and stability of high-speed signal transmission, and can further effectively suppress noise and interference.

[0019] Based on the fourth implementation of the first aspect, or the fifth implementation of the first aspect, the embodiment of the present application further provides an eighth implementation of the first aspect: two ground pins are set between adjacent differential pair pins, the differential pair pins on one side of the first side gold finger are arranged correspondingly to the two ground pins on one side of the second side gold finger, and the differential pair pins on one side of the second side gold finger are arranged correspondingly to the two ground pins on one side of the first side gold finger. In this way, the differential signal definition of the serial bus pin area is relatively compact, and the number of pins used to define the management control signal pin area and the second power supply (low-voltage power supply) pin area is relatively large.

[0020] In practical applications, the two ground pins on one side of the first-side gold finger are connected through the first conductor sheet, and the two ground pins on one side of the second-side gold finger are connected through the second conductor sheet; the first conductor sheet is electrically connected to the three third pads, and the second conductor sheet is electrically connected to the three fourth pads, wherein the two third pads on both sides electrically connected to the first conductor sheet correspond to the fourth pads on both sides electrically connected to the second conductor sheet, and the corresponding third pads and fourth pads on both sides are formed through a via. Similarly, the ground pins on both sides of the first-side gold finger and the second-side gold finger are connected to the same ground, which helps to maintain the consistency and stability of high-speed signal transmission, and can further effectively suppress noise and interference.

[0021] Based on the fourth implementation of the first aspect, or the fifth implementation of the first aspect, the embodiment of the present application further provides a ninth implementation of the first aspect: a ground pin is set between adjacent differential pair pins.

[0022] In practical applications, the ground pin on one side of the first-side gold finger is connected to the first conductor sheet, and the first conductor sheet is electrically connected to the two third pads; the ground pin on one side of the second-side gold finger is connected to the second conductor sheet, and the second conductor sheet is electrically connected to the two fourth pads; wherein the third pad on one side of the first-side gold finger corresponds to the fourth pad on one side of the second-side gold finger, and the corresponding third pad and fourth pad on both sides are formed by a via. In this way, the ground pins on both sides of the first-side gold finger and the second-side gold finger can be connected to the same ground, which helps to maintain the consistency and stability of high-speed signal transmission, and can further effectively suppress noise and interference.

[0023] A second aspect of an embodiment of the present application provides an electronic device, which includes a housing and a mainboard and a memory module arranged in the housing; a DIMM connector is arranged on the mainboard; the memory module is plugged into the DIMM connector on the mainboard, and the memory module is the memory module described above.

[0024] In practical applications, the electronic device may be a server, a computer or a high performance computing cluster. In addition, the electronic device may also be a switch or a router.

[0025] The third aspect of the embodiment of the present application provides a signal transmission method, which is applied to a memory module. Specifically, the memory module is a dual in-line memory module, including a circuit board, a processing chip and multiple memory chips arranged on the circuit board, and a gold finger interface located at the edge of the circuit board, and the circuit board is provided with an anti-foolproofing slot and a locking slot; wherein the multiple memory chips are connected to the processing chip through a parallel bus, and the processing chip is connected to the gold finger interface through a serial bus; the signal transmission method comprises the following steps: transmitting data signals, control signals and power signals through the gold finger interface of the memory module.

[0026] Based on the third aspect, the embodiment of the present application also provides a first implementation method of the third aspect: the gold finger interface includes a first power pin area, a second power pin area, a serial bus pin area and a management control signal pin area, and are respectively arranged on both side surfaces of the circuit board; the first power pin area is used to provide a first voltage power supply, and the second power pin area is used to provide a second voltage power supply, and the voltage of the second voltage power supply is lower than the voltage of the first voltage power supply; both side surfaces of the circuit board include two serial bus pin areas, in the arrangement direction of the gold finger interface, the first power pin area is located at one end of the circuit board, one serial bus pin area is arranged adjacent to the first power pin area, and the other serial bus pin area is located at the other end of the circuit board, and the management control signal pin area and the second power pin area are located between the two serial bus pin areas; at the same time, data signals, control signals and power signals are transmitted through the gold finger interface, including: transmitting data signals through the serial bus pin area, transmitting control signals through the management control signal pin area, transmitting the first power signal in the power signal through the first power pin area, and transmitting the second power signal in the power signal through the second power pin area. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0028] Figure 2 A schematic diagram of a memory module structure provided in an embodiment of the present application;

[0029] Figure 3 A schematic diagram of the arrangement of the gold finger interface of a memory module provided in an embodiment of the present application;

[0030] Figure 4 for Figure 3 A partial enlarged schematic diagram of the serial bus pin area of ​​the gold finger interface shown in FIG.

[0031] Figure 5 They are shown respectively Figure 3 Schematic diagram of the relationship between the pins and pad positions on both sides of the serial bus pin area shown in FIG;

[0032] Figure 6 A schematic diagram of the arrangement of the gold finger interface of another memory module provided in an embodiment of the present application;

[0033] Figure 7 for Figure 6 A partial enlarged schematic diagram of the serial bus pin area of ​​the gold finger interface shown in FIG.

[0034] Figure 8 They are shown respectively Figure 6 Schematic diagram of the relationship between the pins and pad positions on both sides of the serial bus pin area shown in FIG;

[0035] Fig. 9 A schematic diagram of the arrangement of the gold finger interface of another memory module provided in an embodiment of the present application;

[0036] Fig.10 for Fig. 9 A partial enlarged schematic diagram of the serial bus pin area of ​​the gold finger interface shown in FIG.

[0037] Fig.11 They are shown respectively Fig. 9 The schematic diagram of the relationship between the pins and pad positions on both sides of the serial bus pin area is shown in the figure. DETAILED DESCRIPTION

[0038] The embodiment of the present application provides a memory module that can provide technical support for improving the high-density layout of the architecture on the basis of obtaining a higher data transmission rate.

[0039] For ease of description, the terms involved in this application are first explained as follows.

[0040] DIMM connector: refers to the connector used to install and connect memory modules, using parallel high-speed transmission technology to provide the memory capacity and performance required by the system. DIMM connectors can support different standard protocols, such as but not limited to, 288 pin connectors that can support DDR4 SDRAM (4th generation double data rate synchronous dynamic random access memory) or DDR5 SDRAM (5th generation double data rate synchronous dynamic random access memory) standard protocols.

[0041] Memory Expansion Module: A hardware device used to increase the memory capacity of a computer system. Memory expansion modules are usually plug-in board modules that can provide additional physical memory to expand the available memory capacity of the system.

[0042] Memory Expansion Chip: An integrated circuit processing chip used to expand the memory capacity of a computer system. A memory expansion chip is usually a chip integrated into a memory expansion module or other expansion device, responsible for managing and controlling additional physical memory to ensure its compatibility and collaboration with the computer system. Among them, a memory expansion chip that implements memory expansion based on a serial memory solution transmits data and control signals through a serial bus, which can achieve a higher data transmission rate.

[0043] For the connection between the memory expansion board and the motherboard, a typical method is to use the GENZ connector for vertical connection. The height of the GENZ connector is relatively high, and due to the limitation of the internal space of the device, the board width of the memory expansion module cannot meet the layout requirements of the larger expansion chip; another typical method is to use the GENZ splint connector for flat connection. The memory expansion module is arranged parallel to the motherboard, which occupies a large space on the motherboard surface and is not conducive to the high-density implementation of the architecture.

[0044] Based on this, an embodiment of the present application provides a memory module, which includes a circuit board and a processing chip and multiple memory chips arranged on the circuit board; the edge of the circuit board has a gold finger interface adapted to the DIMM connector, wherein the circuit board is provided with an anti-fool-proofing latch and a locking latch, and multiple memory chips are arranged on the two side surfaces of the circuit board respectively; wherein the multiple memory chips are connected to the processing chip through a parallel bus, and the processing chip is connected to the gold finger interface through a serial bus. The "gold finger layout" here refers to the ability to achieve electrical connection between the gold finger and the pins on the side of the DIMM connector, which may include the position and spacing of the gold finger, and may also include the size and number of the gold finger, etc.

[0045] With such a configuration, the memory module can realize serial interconnection through the connector. On the one hand, the serial bus can reliably increase the data transmission rate, and can avoid the crosstalk and synchronous switching noise caused by high-speed transmission based on the parallel bus to a certain extent, which can meet the reliability and stability requirements of signal transmission and effectively improve SI. On the other hand, based on the relatively small height size of the DIMM connector, for the same assembly space, the circuit board provided by this solution has a relatively large board width, which can realize the layout of larger and more devices; and the memory module is a vertical plug-in connection method, and the actual board area is small. On the whole, it provides technical support for the high-density layout and high-performance operation of the architecture.

[0046] In addition, the physical space occupied by the memory module in the electronic device is roughly the same as the physical space occupied by the traditional memory stick, which is conducive to the structural standardization design of the electronic device motherboard and can further improve the structural compatibility of the memory module and the motherboard.

[0047] See also Figure 1 , which is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application, the memory module 300 can be applied to Figure 1 The electronic device shown. In a specific implementation, the electronic device may be a server, a computer or a high-performance computing cluster. For high-power, high-integration, and ultra-large-scale data center servers, the above technical advantages are particularly significant; in addition, the electronic device may also be a switch or a router, etc., which is not limited in the embodiments of the present application.

[0048] like Figure 1 As shown, the electronic device includes a housing 100 and a mainboard 200 and a memory module 300 arranged in the housing 100, the mainboard 200 is provided with a CPU 210, and the mainboard 200 is provided with a DIMM connector 220; the circuit board of the memory module 300 is provided with a processing chip 310, and the gold finger interface (not shown in the figure) at the bottom edge of the circuit board is plugged into the DIMM connector 220 on the mainboard 200, that is, the memory module 300 is vertically plugged in relative to the board surface of the mainboard 200, so that the memory module 300 is electrically connected to the mainboard 200 to realize signal transmission.

[0049] Please also see Figure 2 , which is a schematic diagram of a memory module structure provided by an embodiment of the present application. Among them, the processing chip 310 and the gold finger interface 320 on the circuit board of the memory module 300, and the gold finger interface 320 and the DIMM connector 220 are all connected through a serial protocol standard.

[0050] The plate-shaped body of the memory module 300 may be provided with a foolproofing bayonet 301 and a locking bayonet 302 adapted to the DIMM connector 220, making full use of the foolproofing structure and the locking buckle structure (not shown in the figure) on the side of the DIMM connector 220 to realize the assembly and fixation of the memory module 300. In other words, the assembly structure based on the DIMM connector 220 can meet the reliability and stability requirements of the assembly of the memory module 300, provide technical guarantee for the serial high-speed transmission performance, and do not need to increase the design implementation cost.

[0051] In a specific implementation, the memory module 300 may be a memory expansion card, the processing chip 310 may be a memory expansion chip, and each memory chip 330 is connected to the processing chip 310 via a parallel bus, and thus managed and controlled by the processing chip 310. Here, Figure 2 Six memory chips 330 are used as an example, and the specific number of memory chips 330 can be determined according to the overall design of the memory expansion card.

[0052] In other specific implementations, the memory module 300 may also be an artificial intelligence training card, an artificial intelligence reasoning card, or a graphics processing card, or any memory module that needs to be configured with a high-speed transmission interface. This embodiment of the present application is not limited thereto.

[0053] It is understandable that, for the gold finger interface 320 of the memory module 300, the size and configuration spacing of the gold fingers are set corresponding to the slot pins of the DIMM connector 220. Here, the number of gold fingers set at the bottom edge of the memory module 300 can be determined according to the performance requirements of the actual memory module. Taking the DIMM connector 220 with 288 PINs as an example, 288 gold fingers can be set on the circuit board and all of them can be enabled; 288 gold fingers can also be set on the circuit board and partially enabled according to performance requirements.

[0054] Of course, the number of golden fingers can also be set according to actual activation needs, such as but not limited to setting 210 golden fingers or setting 260 golden fingers, etc., as long as serial interconnection can be established by setting corresponding golden fingers. This embodiment of the application is not limited.

[0055] like Figure 2 As shown, the gold finger interface 320 at the bottom edge of the circuit board of the memory module 300 includes a serial bus pin area 321, a first power pin area 322, a management control signal pin area 323 and a second power pin area 324, and they are respectively arranged on the two sides of the edge of the circuit board. For the convenience of description, the part of the gold finger interface 320 located on one side of the circuit board is defined as the first side gold finger, and the part of the gold finger interface 320 located on the other side of the circuit board is defined as the second side gold finger.

[0056] The serial bus pin area 321 is used to transmit high-speed interconnection signals, such as but not limited to transmitting data signals, to achieve data storage and reading; in a specific implementation, the serial bus pin area 321 can transmit multiple groups of high-speed interconnection signals. The management control signal pin area 323 is used to transmit low-speed signals, such as but not limited to transmitting I2C signals, enable signals or GPIO signals.

[0057] The first power pin area 322 provides a first voltage power supply for transmitting a first power signal, such as but not limited to 12V voltage, and after being converted into a low voltage power supply (such as 1.2V or 1V, etc.) by the secondary power supply on the memory module 300, supplies power to the memory expansion chip and memory chip and other devices on the memory module 300. The second power pin area 324 provides a second voltage power supply for transmitting a second power signal, such as but not limited to 1.2V, 3.3V or 5V, etc., for supplying power to the memory expansion chip and memory chip and other devices on the memory module 300.

[0058] It is understandable that, in the case where there are many devices arranged on the memory module 300, the overall load is large, and the power supply capacity of the first power pin area 322 cannot meet the working needs of all devices, the second power pin area 324 can provide partial power supply according to the actual operating status; in the specific implementation, power management and control can be performed through the power circuit of the memory expansion chip and the memory module, which will not be repeated here.

[0059] Here, the power supply capacity of the first power pin area 322 meets the working requirements of various components on the memory module 300; the second power pin area 324 can be used as power redundancy to ensure that the memory module operates reliably and stably.

[0060] like Figure 2 As shown, in the arrangement direction X of the gold finger interface 320, the first power pin area 322 is located at one end of the circuit board, that is, the 12V pin is set at the side position of the circuit board. In this way, the electromagnetic crosstalk that may be generated by the first power pin area 322 that outputs a higher voltage to other pin areas can be reduced.

[0061] In this embodiment, the gold finger interface 320 includes two serial bus pin areas 321. In the arrangement direction X of the gold finger interface 320, one of the serial bus pin areas 321 is arranged adjacent to the first power pin area 322, and the other serial bus pin area 321 is located at the other end of the circuit board. The management control signal pin area 323 and the second power pin area 324 are centrally arranged between the two serial bus pin areas 321 to avoid crosstalk to the pins of the serial bus pin area 321. Corresponding to the slot pin shape of the DIMM connector 220, the management control signal pin area 323 and the second power pin area 324 are roughly located in the long PIN area of ​​the circuit board, and the first power pin area 322 and the serial bus pin area 321 are correspondingly located in the short PIN area.

[0062] In other specific implementations, the number of serial bus pin areas 321 can be determined according to the high-speed transmission performance requirements of the memory module.

[0063] On the basis of reasonably controlling the crosstalk between pins, the regional layout of each pin area mentioned above also needs to take into account the device layout relationship on the memory module 300 board. For example, for a memory expansion card, when the memory expansion chip is arranged in the middle of the circuit board and each memory chip is arranged on both sides of the memory expansion chip, the management control signal pin area 323 and the second power pin area 324 can be arranged between the two serial bus pin areas 321 to optimize the internal circuit of the circuit board. Furthermore, the gold finger interface 320 also includes a differential clock pin, which can be arranged adjacent to one of the two serial bus pin areas 321.

[0064] For the management control signal pin area 323 and the second power pin area 324, two management control signal pin areas 323 may be included, such as Figure 2 As shown, the two management control signal pin areas 323 are respectively arranged on both sides of the second power pin area 324. In other specific implementations, multiple second power pin areas 324 may be included, and each second power pin area 324 is respectively configured with a different power supply voltage; and in the arrangement direction of the gold finger interface, the two management control signal pin areas 323 may be staggered between each second power pin area 324.

[0065] It is understandable that for the management control signal pin area 323 and the second power pin area 324 set between the two serial bus pin areas 321, the corresponding second power pin area 324 and the management control signal pin area 323 can be defined according to the low-voltage power supply voltage and the number of low-speed signals to provide partial power to the devices on the circuit board and the control signal channel of the memory module respectively. The specific arrangement can be flexibly arranged according to the overall design of the product, and the embodiment of the present application is not limited.

[0066] In order to better understand the technical solution and technical effects of the present application, without losing generality, the specific embodiments will be described in detail below in conjunction with the accompanying drawings. Figure 3 , which is a schematic diagram of the arrangement of a gold finger interface 320a of a memory module provided in an embodiment of the present application. As shown in the figure, the 144 pins of the first-side gold finger 320A and the 144 pins of the second-side gold finger 320B are arranged in sequence on the board surface of the side circuit board, and the pins of the T surface and the B surface are arranged one by one.

[0067] In this embodiment, the first side gold finger 320A and the second side gold finger 320B both include a first power pin area 322 with a power supply voltage of 12V, two serial bus pin areas 321a, two management control signal pin areas 323a and three second power pin areas 324a.

[0068] Among them, the pins on the left end of the surface are defined as the first power pin area 322 of 12V power supply, which is the same as the PIN position of the 12V power supply of the standard DDR5 memory stick. The pin area adjacent to the first power pin area 322 is defined as a serial bus pin area 321a, that is, the serial bus pin area 321a is arranged adjacent to the first power pin area 322, and the pin area on the right end of the surface is defined as another serial bus pin area 321a. The pin areas between the two serial bus pin areas 321a are defined as two management control signal pin areas 323a and three second power pin areas 324a, and are the first second power pin area 324a, the first management control signal pin area 323a, the second second power pin area 324a, the third second power pin area 324a and the second management control signal pin area 323a.

[0069] In a specific implementation, the three second power pin areas 324a can provide different power supply voltages, such as but not limited to providing 1.2V, 3.3V or 5V power supply voltages respectively, to meet the functional requirements of different devices on the memory module.

[0070] The first side gold finger 320A and the second side gold finger 320B are both provided with two eight pairs (lane) of serial signal pins, which can provide X16 high-speed transmission bandwidth. The serial bus pin area 321a includes eight pairs of differential pair pins, two differential signal pins constitute differential pair pins for transmitting differential signals, and four ground pins (GND) are defined between adjacent differential pair pins. Please refer to Figure 4 , the figure shows Figure 3 The arrangement relationship of the serial bus pin area 321a of the gold finger interface 320a is shown in FIG. The serial bus pin area 321a shown in FIG. is located at Figure 3 The serial bus pin area on the left side is partially enlarged to clearly illustrate the pin arrangement relationship. It can be understood that the pin arrangement of the two serial bus pin areas 321a is the same, so Figure 3 The serial bus pin area on the right is no longer enlarged.

[0071] In this embodiment, the serial bus pin area 321a of the first side gold finger 320A and the second side gold finger 320B has four GND pins 3212 arranged at intervals between two adjacent pairs of differential pair pins 3211 to reduce crosstalk between signals during high-speed serial transmission. The four GND pins arranged at intervals have good anti-interference capability when the single pair rate is further evolved and improved.

[0072] Combination Figure 4As shown, the differential pair pins 3211 of the first-side gold finger 320A are arranged alternately with the differential pair pins 3211 of the second-side gold finger 320B. Specifically, along the arrangement direction of the gold finger interface, the four GND pins 3212 on one of the first-side gold finger 320A and the second-side gold finger 320B are arranged continuously with a pair of differential pair pins 3211 on the other side as the center; in other words, the two pins of the differential pair pins 3211 on one side of the board are arranged corresponding to the middle two of the four GND pins 3212 arranged continuously on the other side of the board. In this way, on the basis of reducing the signal crosstalk between the two adjacent pairs of differential pair pins 3211 on the same side, the signal crosstalk between the differential pin pairs on the two sides can be further reasonably controlled.

[0073] In other specific implementations, for the serial bus pin area 321a of the first-side gold finger 320A and the second-side gold finger 320B, the four GND pins 3212 on one are not limited to being arranged continuously with a pair of differential pair pins 3211 on the other as the center. For example, but not limited to, two pins of the differential pair pins 3211 on one side of the board are arranged corresponding to two GND pins located on the side (left or right) of the four GND pins 3212 on the other side of the board, which can also reduce the signal crosstalk between the differential pin pairs on the two sides.

[0074] For example Figure 3 and Figure 4 As shown, the gold finger interface 320a of the memory module described in this embodiment includes a pair of differential clock pins 325, and the differential clock pins 325 are located between the serial bus pin area 321a on the left side of the first gold finger 320A and the 12V first power pin area 322. Of course, the differential clock pin 325 can also be configured at adjacent positions of other serial bus pin areas 321a, including adjacent positions of any serial bus pin area 321a in the second gold finger 320B. This embodiment of the application is not limited.

[0075] Optionally, in order to further reduce the noise interference of the first power pin area 322, two empty pins 326 are arranged between the first power pin area 322 of the first side gold finger 320A and the differential clock pin 325, where "empty pin" refers to a pin that does not define any signal; two empty pins 326 are also arranged between the first power pin area 322 of the second side gold finger 320B and the serial bus pin area 321a. Based on the setting of the empty pins, the interference of 12V noise on the differential signal can be effectively prevented.

[0076] In other specific implementations, the number of the above-mentioned empty pins 326 can also be one, or multiple of other numbers. It should be understood that too many empty pins will affect the available number of defined pins. In comparison, setting two empty pins between the 12V power pin and the differential signal can effectively prevent the possible impact of 12V noise while reasonably configuring the number of available pins.

[0077] Optionally, in order to support the signal transmission rate under the serial standard protocol, in the specific implementation, the electrical connection between each pin of the gold finger interface and the corresponding conductor layer in the circuit board can be realized through the POFV (plated over filled via) process. The POFV process is a special plugging process for VIP (Vias In Pad). It uses resin and other materials to plug the through hole, and then copper is electroplated to form a pad, which can improve the PCB layout density and electrical performance. Please refer to Figure 5 , the figure shows Figure 3 The schematic diagram of the relationship between the pins and pads on both sides of the serial bus pin area is shown in FIG. Figure 5 Figure (a) shows the relationship between the pins and pads of the first side gold finger 320A. Figure 5 The middle figure (b) shows the position relationship between the pins and pads of the second side gold finger 320B.

[0078] In the arrangement direction of the gold finger interface, the first pad 3211A electrically connected to the differential pair pin 3211 on one side of the first-side gold finger 320A, and the second pad 3211B electrically connected to the differential pair pin 3211 on one side of the second-side gold finger 320B are arranged at intervals, and corresponding electrical connections are respectively achieved through conductors in the circuit board (not shown in the figure); and in the extension direction of the gold finger, the first pad 3211A and the second pad 3211B of each differential pair pin 3211 are staggered with the pad of the GND pin 3212. Specifically, relative to the pad electrically connected to the GND pin 3212, the first pad 3211A and the second pad 3211B are arranged on the circuit board away from the gold finger.

[0079] like Figure 5 As shown in FIG. 1 (a), four GND pins 3212 between two pairs of differential pair pins 3211 on one side of the first side gold finger 320A are connected through a first conductor sheet 3213A to obtain the same ground level; Figure 5 As shown in FIG. (b), four GND pins 3212 between two pairs of differential pair pins 3211 on one side of the second side gold finger 320B are connected through a second conductor sheet 3213B to obtain the same ground level. In this way, the common ground connection of the pins in each region can help maintain the consistency and stability of high-speed signal transmission, and can further effectively suppress noise and interference.

[0080] Further, the first conductor sheet 3213A on one side of the first-side gold finger 320A is electrically connected to the four third pads 3212A, and the second conductor sheet 3213B on one side of the second-side gold finger 320B is electrically connected to the four fourth pads 3212B; each third pad 3212A and the fourth pad 3212B are arranged at intervals in the arrangement direction of the gold finger interface, and as shown in FIG. Figure 5 The dotted line indicates the corresponding relationship of the pads. The third pad 3212A on the first side of the gold finger 320A corresponds to the fourth pad 3212B on the second side of the gold finger 320B. The corresponding third pad 3212A and fourth pad 3212B on both sides are formed by a via. At the same time, the GND pins on both sides of the board have the same ground level.

[0081] The foregoing Figure 3 In the described implementation, four ground pins are defined between two adjacent differential pairs of pins in the serial bus pin area. In other specific implementations, other numbers of ground pins may be defined according to overall design requirements, for example but not limited to, two ground pins may be defined between two adjacent differential pairs of pins, or one ground pin may be defined.

[0082] See also Figure 6 and Figure 7 ,in, Figure 6 A schematic diagram of another arrangement of gold finger interfaces of a memory module provided in an embodiment of the present application, Figure 7 for Figure 6 The enlarged schematic diagram of the serial bus pin area of ​​the gold finger interface is shown in FIG. Figure 3 The differences and connections between the described arrangements of the gold finger interfaces, and the components or structures with the same functions are indicated by the same marks in the figures.

[0083] The gold finger interface 320b provided in this embodiment, the first gold finger 320A and the second gold finger 320B each include a first power pin area 322 with a power supply voltage of 12V, two serial bus pin areas 321b, two management control signal pin areas 323b and three second power pin areas 324b. In terms of overall layout, Figure 6 As shown, two management control signal pin areas 323b and three second power pin areas 324b are also defined between two serial bus pin areas 321b, and are sequentially the first management control signal pin area 323b, the first second power pin area 324b, the second second power pin area 324b, the third second power pin area 324b and the second management control signal pin area 323b. One of the serial bus pin areas 321b is defined in the pin area adjacent to the first power pin area 322, and the other serial bus pin area 321b is defined in the pin area at the right end.

[0084] Two ground pins (GND) are defined between adjacent differential pair pins of the serial bus pin area 321b. Figure 7 , there are two consecutively arranged GND pins 3212 between the two adjacent pairs of differential pair pins 3211 of the first-side gold finger 320A and the second-side gold finger 320B; and the differential pair pins 3211 of the first-side gold finger 320A are arranged alternately with the differential pair pins 3211 of the second-side gold finger 320B. In other words, the pins on the second-side gold finger 320B corresponding to the differential pair pins 3211 on the first-side gold finger 320A side are defined as GND pins 3212, and the pins on the second-side gold finger 320B side corresponding to the GND pins 3212 on the first-side gold finger 320A side are defined as differential pair pins 3211, which can reduce signal crosstalk between the differential pin pairs on the two sides. Compared with Figure 3 In the described implementation scheme, the differential signal definition of the serial bus pin area 321b in this implementation scheme is relatively compact, and the number of pins used to define the management control signal pin area 323b and the second power supply (low voltage power supply) pin area 324b is relatively large.

[0085] See also Figure 8 , the figure shows Figure 6 The schematic diagram of the relationship between the pins and pads on both sides of the serial bus pin area is shown in FIG. Figure 8 Figure (a) shows the relationship between the pins and pads of the first side gold finger 320A. Figure 8 The middle figure (b) shows the position relationship between the pins and pads of the second side gold finger 320B.

[0086] In the board surface of the circuit board, the first pad 3211A electrically connected to the differential pair pin 3211 on the first side gold finger 320A side and the second pad 3211B electrically connected to the differential pair pin 3211 on the second side gold finger 320B side are arranged in a staggered manner, and are respectively electrically connected through conductors in the circuit board (not shown in the figure). Similarly, the first pad 3211A and the second pad 3211B of each differential pair pin 3211 are arranged in a staggered manner with the pad of the GND pin 3212.

[0087] like Figure 8 As shown in FIG. 1 (a), two GND pins 3212 between two pairs of differential pair pins 3211 on one side of the first side gold finger 320A are connected through a first conductor sheet 3213A1 to obtain the same ground level; Figure 8 As shown in FIG. 5( b ), two GND pins 3212 between two pairs of differential pair pins 3211 on one side of the second-side gold finger 320B are connected via a second conductor sheet 3213B1 to obtain the same ground level.

[0088] Furthermore, the first conductor sheet 3213A1 on one side of the first-side gold finger 320A is electrically connected to the three third pads 3212A, and the second conductor sheet 3213B1 on one side of the second-side gold finger 320B is electrically connected to the three fourth pads 3212B, and each third pad 3212A and fourth pad 3212B is arranged at intervals in the arrangement direction of the gold finger interface. Figure 8 The pad correspondence relationship indicated by the dotted line in the middle, the two third pads 3212A on both sides electrically connected to the first conductor sheet 3213A1, and the two fourth pads 3212B1 on both sides electrically connected to the second conductor sheet 3213B1 correspond one to one, and the corresponding third pads 3212A and fourth pads 3212B on both sides are formed by a via. At the same time, the GND pins on both sides of the board have the same ground level, which helps to maintain consistency and stability of high-speed signal transmission, and effectively suppress noise and interference.

[0089] See also Fig. 9 and Fig.10 ,in, Fig. 9 A schematic diagram of the arrangement of the gold finger interface of another memory module provided in an embodiment of the present application is shown in FIG. Fig.10 for Fig. 9 The enlarged schematic diagram of the serial bus pin area of ​​the gold finger interface is shown in FIG. Figure 3 and Figure 6 The differences and connections between the described arrangements of the gold finger interfaces, and the components or structures with the same functions are indicated by the same marks in the figures.

[0090] The gold finger interface 320c provided in this embodiment, the first gold finger 320A and the second gold finger 320B each include a first power pin area 322 with a power supply voltage of 12V, two serial bus pin areas 321c, two management control signal pin areas 323c and three second power pin areas 324c. In terms of overall layout, Fig. 9 As shown, two management control signal pin areas 323c and three second power pin areas 324c are defined between two serial bus pin areas 321c, and are sequentially the first management control signal pin area 323c, the first second power pin area 324c, the second second power pin area 324c, the third second power pin area 324c and the second management control signal pin area 323c. One of the serial bus pin areas 321c is defined in the pin area adjacent to the first power pin area 322, and the other serial bus pin area 321c is defined in the pin area at the right end.

[0091] A ground pin (GND) is defined between adjacent differential pair pins in the serial bus pin area 321c. Fig.10, there is a GND pin 3212 between the two adjacent pairs of differential pair pins 3211 of the first-side gold finger 320A and the second-side gold finger 320B; and the differential pair pins 3211 of the first-side gold finger 320A are arranged alternately with the differential pair pins 3211 of the second-side gold finger 320B. In other words, the pin on the second-side gold finger 320B corresponding to the differential pair pin 3211 on the first-side gold finger 320A side is defined as one of the GND pin 3212 and the differential pair pin 3211, and the pin on the second-side gold finger 320B side corresponding to the GND pin 3212 on the first-side gold finger 320A side is defined as the other of the differential pair pins 3211. Compared to Figure 3 and Figure 6 In the described implementation scheme, the differential signal definition of the serial bus pin area 321b in this implementation scheme is the most compact, and the number of pins used to define low-voltage power supply and low-speed signals is richer, which facilitates the implementation of corresponding layout according to the needs of different application scenarios.

[0092] See also Fig.11 , the figure shows Fig. 9 The schematic diagram of the relationship between the pins and pads on both sides of the serial bus pin area is shown in FIG. Fig. 9 Figure (a) shows the relationship between the pins and pads of the first side gold finger 320A. Fig. 9 The middle figure (b) shows the position relationship between the pins and pads of the second side gold finger 320B.

[0093] In the board surface of the circuit board, the first pad 3211A electrically connected to the differential pair pin 3211 on the first side gold finger 320A side and the second pad 3211B electrically connected to the differential pair pin 3211 on the second side gold finger 320B side are arranged in a staggered manner, and are respectively electrically connected through conductors in the circuit board (not shown in the figure). Similarly, the first pad 3211A and the second pad 3211B of each differential pair pin 3211 are arranged in a staggered manner with the pad of the GND pin 3212.

[0094] like Fig.11 As shown in FIG. 1 (a), the GND pin 3212 on one side of the first gold finger 320A is connected to the first conductor sheet 3213A1, and the first conductor sheet 3213A2 is electrically connected to the two third pads 3212A; Fig.11 As shown in FIG. (b), the GND pin 3212 on one side of the second side gold finger 320B is connected to the second conductor sheet 3213B1, and the second conductor sheet 3213B2 is electrically connected to the two fourth pads 3212B. The third pads 3212A and the fourth pads 3212B are arranged at intervals in the arrangement direction of the gold finger interface. Fig.11The pad correspondence indicated by the dotted line in the middle indicates that the two third pads 3212A electrically connected to the first conductor sheet 3213A2 and the two fourth pads 3212B1 electrically connected to the second conductor sheet 3213B1 correspond to each other, and the corresponding third pads 3212A and fourth pads 3212B on both sides are formed by a via hole, so that the GND pins on both sides of the board have the same ground level. That is, the ground connection of the ground pins helps to maintain consistency and stability of high-speed signal transmission, and effectively suppress noise and interference.

[0095] Based on the gold finger interface definition method described in the above embodiment, it can be selected according to the actual needs of different application scenarios. For example, when the serial transmission rate needs to be increased to above 16GBPS, you can select Figure 3 The memory module with the gold finger interface definition described above meets the functional requirements of single-pair rate improvement based on good anti-crosstalk capability. For another example, when the motherboard needs to provide more low-speed signals and low-voltage power supply channels, you can choose Fig. 9 The memory module with the gold finger interface definition method described above realizes corresponding layout based on the number of pins of richer low-voltage power supply and low-speed signal.

[0096] In a specific implementation, taking a memory expansion card as an example, the memory expansion card is installed on the DIMM connector on the motherboard, and the system can recognize and utilize the additional memory provided by the memory chip on the memory expansion card, thereby providing more available memory capacity for the operating system and application programs. The application of the memory expansion card provided by the embodiment of the present application can effectively improve the performance and processing power of the computer system. For example, the computer system can determine the data storage location according to the access frequency. For example, data with a higher access frequency can be stored in the storage space provided by the system memory bar, and data with a relatively low access frequency can be stored in the storage space provided by the memory chip of the memory expansion card. In particular, when it is necessary to process large data sets, run memory-intensive applications, or perform complex computing tasks, the technical advantages are particularly significant.

[0097] It should be noted that the aforementioned memory module is physically connected and electrically connected at high speed via a DIMM connector, and can also be used in other scenarios where serial signal transmission based on a DIMM connector is required, such as but not limited to existing computing or storage products, and also includes future computing or storage products. This application embodiment is not limited thereto.

[0098] Based on the aforementioned memory module, an embodiment of the present application further provides a signal transmission method, which comprises the following steps:

[0099] Data signals, control signals and power signals are transmitted through the gold finger interface.

[0100] Optionally, the transmission of data signals, control signals and power signals through the gold finger interface includes: transmitting data signals through a serial bus pin area, transmitting control signals through a management control signal pin area, and transmitting a first power signal in the power signal through a first power pin area.

[0101] Further optionally, the transmitting of the data signal, the control signal and the power signal through the gold finger interface includes: transmitting the second power signal in the power signal through the second power pin area.

[0102] It should be noted that the directional words "bottom", "left end" and "right end" used in this article are defined based on the state of the memory module shown in the figure. The memory module assembled and applied in the actual scene is not limited to the state shown in the figure. For example, in the use state, the motherboard of the electronic device extends vertically, or the extension direction of the motherboard of the electronic device forms a certain angle with the vertical. It should be understood that the use of the above directional words does not constitute a substantial limitation on the memory module described in this application.

[0103] In addition, the ordinal numbers "first", "second", "third" and "fourth" used in this document are only used to describe the same functional components or structures in the technical solution. It is understood that the use of the above ordinal numbers does not constitute an understanding of the technical solution for which protection is sought in this application.

[0104] The above are only preferred embodiments of the present invention. It should be pointed out that, for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A memory module, characterized in that: The memory module is a dual in-line memory module, comprising: A circuit board, wherein the circuit board is provided with an anti-foolproofing bayonet and a locking bayonet; A processing chip and a plurality of memory chips disposed on the circuit board; A gold finger interface located at the edge of the circuit board; The plurality of memory chips are connected to the processing chip via a parallel bus, and the processing chip is connected to the gold finger interface via a serial bus.

2. The memory module according to claim 1, characterized in that: The gold finger interface includes a first power pin area, a second power pin area, a management control signal pin area and a serial bus pin area, and is respectively arranged on two side surfaces of the circuit board; the first power pin area is used to provide a first voltage power supply, and the second power pin area is used to provide a second voltage power supply, and the voltage of the second voltage power supply is lower than the voltage of the first voltage power supply; Both side surfaces of the circuit board include two serial bus pin areas. In the arrangement direction of the gold finger interface, the first power pin area is located at one end of the circuit board, one of the two serial bus pin areas is arranged adjacent to the first power pin area, and the other of the two serial bus pin areas is located at the other end of the circuit board, and the management control signal pin area and the second power pin area are located between the two serial bus pin areas.

3. The memory module according to claim 2, wherein: Empty pins are arranged between the first power pin area and the adjacent serial bus pin area.

4. The memory module according to claim 3, characterized in that: The gold finger interface further includes a differential clock pin, and the differential clock pin is located between the empty pin and the serial bus pin area arranged adjacent to the first power pin area.

5. The memory module according to any one of claims 2 to 4, characterized in that: The serial bus pin area includes differential pair pins arranged at intervals, the differential pair pins include two differential signal pins for transmitting differential signals, and a ground pin is arranged between two adjacent pairs of the differential pair pins; the portion of the gold finger interface located on one side of the circuit board is the first side gold finger, and the portion of the gold finger interface located on the other side of the circuit board is the second side gold finger.

6. The memory module according to claim 5, characterized in that: The serial bus pin area includes eight pairs of differential pair pins arranged at intervals, and the differential pair pins of the first-side gold fingers and the differential pair pins of the second-side gold fingers are arranged in an alternating manner.

7. The memory module according to claim 6, wherein: Four ground pins are arranged between adjacent differential pair pins. Along the arrangement direction of the gold finger interface, the four ground pins on one of the first gold finger and the second gold finger are arranged continuously with a pair of differential pair pins on the other as the center.

8. The memory module according to claim 7, characterized in that: The four ground pins on one side of the first-side gold finger are connected through a first conductor sheet, and the four ground pins on one side of the second-side gold finger are connected through a second conductor sheet; the first conductor sheet is electrically connected to four third pads, and the second conductor sheet is electrically connected to four fourth pads, wherein the third pads on one side of the first-side gold finger correspond one to one with the fourth pads on one side of the second-side gold finger, and the corresponding third pads and fourth pads on both sides are formed by a via.

9. The memory module according to claim 6, wherein: Two ground pins are arranged between adjacent differential pair pins, the differential pair pins on one side of the first-side gold finger are arranged correspondingly to the two ground pins on one side of the second-side gold finger, and the differential pair pins on one side of the second-side gold finger are arranged correspondingly to the two ground pins on one side of the first-side gold finger.

10. The memory module according to claim 9, characterized in that: The two ground pins on one side of the first-side gold finger are connected through a first conductor sheet, and the two ground pins on one side of the second-side gold finger are connected through a second conductor sheet; the first conductor sheet is electrically connected to three third pads, and the second conductor sheet is electrically connected to three fourth pads, wherein the two third pads on both sides electrically connected to the first conductor sheet and the fourth pads on both sides electrically connected to the second conductor sheet correspond one to one, and the corresponding third pads and fourth pads on both sides are formed by a via.

11. The memory module according to claim 6, wherein: A ground pin is arranged between adjacent differential pair pins.

12. The memory module according to claim 11, wherein: The ground pin on one side of the first-side gold finger is connected to the first conductor sheet, and the first conductor sheet is electrically connected to two third pads; the ground pin on one side of the second-side gold finger is connected to the second conductor sheet, and the second conductor sheet is electrically connected to two fourth pads; wherein the third pad on one side of the first-side gold finger corresponds one to the fourth pad on one side of the second-side gold finger, and the corresponding third pad and fourth pad on both sides are formed by a via.

13. The memory module according to any one of claims 1 to 12, characterized in that: The memory module is a memory expansion card, and a plurality of memory chips are arranged on the circuit board. The processing chip is a memory expansion chip used for managing and controlling the plurality of memory chips.

14. An electronic device, characterized in that: It comprises a shell and a mainboard and a memory module arranged in the shell; a DIMM connector is arranged on the mainboard; the memory module is plugged into the DIMM connector on the mainboard, and the memory module is the memory module described in any one of claims 1 to 13.

15. A signal transmission method, characterized in that: The signal transmission method is applied to a memory module, which is a dual in-line memory module. The memory module includes a circuit board, a processing chip, a plurality of memory chips and a gold finger interface. The circuit board is provided with an anti-foolproofing bayonet and a locking bayonet. The processing chip and the plurality of memory chips are arranged on the circuit board, and the gold finger interface is located at the edge of the circuit board; wherein the plurality of memory chips are connected to the processing chip via a parallel bus, and the processing chip is connected to the gold finger interface via a serial bus; the method includes the following steps: Data signals, control signals and power signals are transmitted through the gold finger interface.

16. The signal transmission method according to claim 15, characterized in that: The gold finger interface includes a first power pin area, a second power pin area, a serial bus pin area and a management control signal pin area, and they are respectively arranged on both sides of the circuit board; the first power pin area is used to provide a first voltage power supply, and the second power pin area is used to provide a second voltage power supply, and the voltage of the second voltage power supply is lower than the voltage of the first voltage power supply; both sides of the circuit board include two serial bus pin areas, in the arrangement direction of the gold finger interface, the first power pin area is located at one end of the circuit board, one of the two serial bus pin areas is arranged adjacent to the first power pin area, and the other of the two serial bus pin areas is located at the other end of the circuit board, and the management control signal pin area and the second power pin area are located between the two serial bus pin areas; The transmitting of data signals, control signals and power signals through the gold finger interface includes: The data signal is transmitted through the serial bus pin area, the control signal is transmitted through the management control signal pin area, the first power signal among the power signals is transmitted through the first power pin area, and the second power signal among the power signals is transmitted through the second power pin area.

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