Method for establishing high-frequency full-circuit model of common-mode choke

Abstract

The invention discloses a method for establishing a high-frequency full-circuit model of a common-mode choke, and belongs to the field of high-frequency modeling of passive devices in filters, and the method comprises the steps: determining a common-mode circuit topology and a differential-mode circuit topology according to the characteristics of a common-mode impedance characteristic curve and a differential-mode impedance characteristic curve; calculating an initial value of each device in the common-mode circuit topology and the differential-mode circuit topology, and determining a value range of each device according to the initial value of each device in the common-mode circuit topology and the differential-mode circuit topology; respectively fitting a common-mode impedance characteristic curve and a differential-mode impedance characteristic curve by utilizing a genetic algorithm according to the value range of each device, determining accurate values of each device in the common-mode circuit topology and the differential-mode circuit topology, and obtaining a common-mode high-frequency circuit model and a differential-mode high-frequency circuit model; and converting the common-mode high-frequency circuit model and the differential-mode high-frequency circuit model into a full-circuit model by utilizing a circuit equivalence principle according to the parasitic capacitance. The method solves the problem that an existing modeling method cannot give consideration to both precision and efficiency.

Description

Technical Field

[0001] The invention belongs to the field of high-frequency modeling of passive devices in filters, and in particular relates to a method for establishing a high-frequency full-circuit model of a common-mode choke. Background Art

[0002] With the widespread application of third-generation semiconductor materials represented by silicon carbide (SiC) and gallium nitride (GaN) in the field of power electronics, the performance of power electronic switching devices has been significantly improved, especially the switching frequency is getting higher and higher. These new semiconductor materials have a higher bandgap and better thermal stability, allowing the devices to work stably at higher frequencies and temperatures. However, with the increase in switching speed, the electromagnetic interference (EMI) generated by the device during operation is also becoming increasingly serious, posing new challenges to the stability and reliability of the circuit system.

[0003] In order to effectively suppress electromagnetic interference noise, filters have been widely used in power electronic systems. Among them, common mode chokes, as a key component of filters, can significantly reduce common mode interference and improve the electromagnetic compatibility of the system. Common mode chokes suppress the propagation of common mode current by increasing impedance on the common mode path, thereby reducing interference to other electronic devices.

[0004] Accurately and quickly building a circuit model of a common-mode choke is essential for the optimal design of the filter. This not only helps to accurately predict the performance parameters of the filter, such as insertion loss and stopband width, but also shortens the design cycle and improves design efficiency. However, in practical applications, due to the frequency characteristics of the magnetic permeability of the common-mode choke core material, as well as the influence of non-ideal factors such as parasitic capacitance and winding leakage inductance, its actual frequency response is significantly different from the ideal model. Summary of the invention

[0005] In view of the above-mentioned deficiencies in the prior art, a method for establishing a high-frequency full-circuit model of a common-mode choke provided by the present invention solves the problem that the existing modeling methods cannot take into account both accuracy and efficiency.

[0006] In order to achieve the above-mentioned invention object, the technical solution adopted by the present invention is: a method for establishing a high-frequency full-circuit model of a common-mode choke, comprising:

[0007] Use an impedance analyzer to perform impedance testing on the common mode choke to obtain common mode impedance characteristic curve, differential mode impedance characteristic curve and parasitic capacitance;

[0008] Determine the common mode circuit topology and the differential mode circuit topology according to the characteristics of the common mode impedance characteristic curve and the differential mode impedance characteristic curve respectively;

[0009] Calculating initial values ​​of each device in the common-mode circuit topology and the differential-mode circuit topology according to the characteristics of the common-mode impedance characteristic curve and the differential-mode impedance characteristic curve, and determining the value range of each device according to the initial values ​​of each device in the common-mode circuit topology and the differential-mode circuit topology;

[0010] According to the value range of each device, the common mode impedance characteristic curve and the differential mode impedance characteristic curve are fitted by using genetic algorithm, the precise value of each device in the common mode circuit topology and the differential mode circuit topology is determined, and the common mode high frequency circuit model and the differential mode high frequency circuit model are obtained;

[0011] According to the parasitic capacitance, the common-mode high-frequency circuit model and the differential-mode high-frequency circuit model are converted into a full circuit model using the principle of circuit equivalence.

[0012] The beneficial effects of the present invention are as follows: the circuit topology established by the method of the present invention combined with the initial parameters obtained by calculation can basically characterize the characteristics of the impedance curve, and the genetic algorithm is used for correction, which reduces the dependence on complex algorithms and speeds up the modeling speed. The established full circuit model has high accuracy and can accurately characterize the high-frequency characteristics of the common-mode choke within a wide frequency band.

[0013] Furthermore, the impedance analyzer is used to perform impedance testing on the common-mode choke to obtain the common-mode impedance characteristic curve, the differential-mode impedance characteristic curve and the parasitic capacitance. Specifically, the common-mode choke is tested in common mode, differential mode and open circuit respectively using the impedance analyzer to obtain the common-mode impedance characteristic curve, the differential-mode impedance characteristic curve and the parasitic capacitance.

[0014] The beneficial effect of the above further solution is that the impedance curve data can be directly obtained through the impedance analyzer, and the data can be directly used to calculate the initial value of the circuit device without conversion.

[0015] Furthermore, the calculation formula of the value of the parasitic capacitance is:

[0016]

[0017] Wherein, Z is the impedance of any point on the straight line segment before the resonance point in the open circuit impedance characteristic curve; π is the circumference of a circle; and f is the frequency of the point corresponding to Z.

[0018] The beneficial effect of the above further solution is that the capacitance is the parasitic capacitance between the common-mode choke coils, and the accuracy of the full circuit model can be improved through the calculation in the above steps.

[0019] Further, the determining of the common mode circuit topology and the differential mode circuit topology is specifically:

[0020] Obtain the number n of resonance points of the impedance characteristic curve, and number the resonance points in sequence from left to right according to the horizontal axis;

[0021] When the number of resonance points n is an even number, the first n-1 resonance points are topologically transformed based on the RLC parallel circuit to obtain the unit topology of each resonance point, and the unit topologies are connected in series according to the order of the resonance point numbers, and the circuit topology obtained after the series connection is connected in series with an inductor to obtain the corresponding circuit topology;

[0022] When the number of resonance points n is an odd number, each resonance point is topologically improved based on the RLC parallel circuit to obtain the unit topology of each resonance point, and each unit topology is connected in series according to the resonance point numbering sequence to obtain the corresponding circuit topology;

[0023] When the impedance characteristic curve is a common-mode impedance characteristic curve, the corresponding circuit topology obtained is a common-mode circuit topology; when the impedance characteristic curve is a differential-mode impedance characteristic curve, the corresponding circuit topology obtained is a differential-mode circuit topology.

[0024] The beneficial effects of the above further solution are: being able to match the number of circuit units with the characteristics of the impedance curve, reducing the reliance on the algorithm in the subsequent process, and shortening the time for finding accurate parameters.

[0025] Furthermore, the topology transformation based on the RLC parallel circuit is performed to obtain the unit topology of each resonance point, which is specifically:

[0026] The impedance curve from the third zone of the resonance point i-1 to the resonance point i is taken as the first zone, the resonance point i is taken as the second zone, and the impedance curve from the resonance point i to the first zone of the resonance point i+1 is taken as the third zone. The impedance curves of the first zone and the third zone are analyzed respectively, and the topology of the RLC parallel circuit is transformed based on the analysis results to obtain the unit topology of the resonance point.

[0027] For the impedance curve of the first zone:

[0028] If the analysis result is: the impedance curve is a straight line with a slope greater than zero, then the inductance branch of the RLC parallel circuit remains unchanged;

[0029] If the analysis result is: the slope of the impedance curve tends to zero at first and then increases to a constant value, then a resistor is connected in series with the inductor branch of the RLC parallel circuit;

[0030] If the analysis result is: the impedance curve is first a straight line with a slope greater than zero, and then the slope decreases but is still greater than zero, then add a branch of resistance and inductance in series to the RLC parallel circuit;

[0031] For the impedance curve of the third zone:

[0032] If the analysis result is: there is no third zone, delete the capacitor branch in the RLC parallel circuit;

[0033] If the analysis result is: the impedance curve is a straight line with a slope less than c, then the capacitive branch of the RLC parallel circuit remains unchanged; c is a negative number;

[0034] If the analysis result is that the impedance curve is a straight line with a slope less than zero and greater than c, a resistor is connected in series with the capacitor branch of the RLC parallel circuit.

[0035] The beneficial effects of the above further solution are as follows: the advantage is that the circuit topology that matches the detailed characteristics of the impedance curve can be quickly determined, greatly reducing the difficulty of subsequent parameter search.

[0036] Furthermore, the calculation formula for calculating the initial value of each device in the common mode circuit topology and the differential mode circuit topology is:

[0037]

[0038] R i,old =Z i,2

[0039]

[0040] R i,new.L =Z i,1 '

[0041] R i,new.L-R =Z i,1 ”

[0042]

[0043]

[0044] Among them, L i,old is the initial value of the inductance of the RLC parallel circuit in the unit topology at the i-th resonance point; Z i,1 is the impedance of any point in the straight line portion of the impedance curve of the first zone of the i-th resonance point. If the impedance curve of the first zone is first a straight line with a slope greater than zero, and then the slope decreases but is still greater than zero, then it is the impedance of any point in the straight line portion before the turning point; f i,1 Z i,1 The frequency of the corresponding point; R i,old is the initial value of the resistance of the RLC parallel circuit in the unit topology at the i-th resonance point; Z i,2 is the impedance of the i-th resonance point; π is the circumference of a circle; C i,old is the initial value of the capacitance of the RLC parallel circuit in the unit topology at the i-th resonance point; Z i,3 is the impedance of any point in the straight line portion of the impedance curve of the third region of the i-th resonance point; f i,3 Z i,3 The frequency of the corresponding point; R i,new.Lis the initial value of the resistance added to the inductor branch of the RLC parallel circuit in the unit topology at the i-th resonance point; Z i,1 ' is the impedance of any point in the part where the slope tends to zero in the first zone impedance curve of the i-th resonance point; R i,new.L-R is the initial value of the resistance of the newly added inductor-resistor branch in the RLC parallel circuit in the unit topology at the i-th resonance point; Z i,1 " is the impedance of the turning point where the slope of the impedance curve of the first zone of the i-th resonance point changes; L i,new.L-R is the initial value of the inductance of the newly added inductor-resistor branch in the RLC parallel circuit in the unit topology at the i-th resonance point; Z i,1 ”' is the impedance of any point in the straight line portion after the turning point where the slope of the impedance curve of the first zone of the i-th resonance point changes; f i,1 ”' for Z i,1 ”'The frequency of the corresponding point; R i,new.C is the initial value of the resistance of the capacitor branch in the RLC parallel circuit in the unit topology at the i-th resonance point.

[0045] The beneficial effects of the above further scheme are as follows: the advantage of determining the initial parameters is that, first, it can help determine whether the circuit topology of the previous step is accurate. If the impedance curve of the initial parameters does not correspond to the basic characteristics of the test results, it proves that the circuit topology needs further adjustment; secondly, the initial parameters can provide assistance for subsequent algorithms. The value range of the device is given according to the initial parameters, which can greatly help the genetic algorithm to solve the problem and ensure the rationality of the solution (for example, the resistance value is a positive number).

[0046] Furthermore, the value range of each device is specifically as follows:

[0047] L i ×10 -1 ≤L i ≤L i ×10

[0048] R i ×10 -1 ≤R i ≤R i ×10

[0049] C i ×10 -1 ≤C i ≤C i ×10

[0050] L i ∈[L i,old ,L i,new.L-R ]

[0051] R i ∈[R i,old,R i,new.L ,R i,new.L-R ,R i,new.C ]

[0052] C i ∈[C i,old ]

[0053] Among them, L i is the initial value of the inductance in the unit topology at the i-th resonance point; R i is the initial value of the resistance in the unit topology at the i-th resonance point; C i is the initial value of the capacitance in the unit topology at the i-th resonance point.

[0054] The beneficial effect of the above further solution is that the device parameter value range is determined according to the initial parameters, which can reduce the range of the algorithm to find the parameters, speed up the algorithm, and also maintain the rationality of the results.

[0055] Furthermore, the fitness function of the genetic algorithm is:

[0056] d=∑|Z CA -Z test | 2

[0057] Among them, d is the fitness function of the genetic algorithm; Z CA is the impedance of the circuit topology; Z test is the corresponding impedance test data; |·| is the absolute value.

[0058] The beneficial effect of the above further solution is that the fitness function can evaluate whether the impedance characteristics of the device parameters to be found are close to the impedance characteristics of the test.

[0059] Furthermore, according to the parasitic capacitance, the common-mode high-frequency circuit model and the differential-mode high-frequency circuit model are converted into a full circuit model using the principle of circuit equivalence, specifically:

[0060] Splitting the common-mode high-frequency circuit model into a first common-mode high-frequency sub-circuit model and a second common-mode high-frequency sub-circuit model; the circuit topologies of the first common-mode high-frequency sub-circuit model and the second common-mode high-frequency sub-circuit model are the same as the common-mode high-frequency circuit model;

[0061] Splitting the differential-mode high-frequency circuit model into a first differential-mode high-frequency sub-circuit model and a second differential-mode high-frequency sub-circuit model; the circuit topologies of the first differential-mode high-frequency sub-circuit model and the second differential-mode high-frequency sub-circuit model are the same as those of the differential-mode high-frequency circuit model;

[0062] The first common-mode high-frequency sub-circuit model is connected in series with the first differential-mode high-frequency sub-circuit model; the second common-mode high-frequency sub-circuit model is connected in series with the second differential-mode high-frequency sub-circuit model; the output end of the first common-mode high-frequency sub-circuit model and the output end of the second common-mode high-frequency sub-circuit model are connected in parallel with parasitic capacitance; the output end of the first differential-mode high-frequency sub-circuit model and the output end of the second differential-mode high-frequency sub-circuit model are connected in parallel with parasitic capacitance.

[0063] The beneficial effect of the above further solution is that the split model can convert the two-port circuit model into a four-port circuit model, which corresponds to the actual structure of the choke and is convenient for simulation.

[0064] Furthermore, the device parameter values ​​in the first common-mode high-frequency sub-circuit model and the second common-mode high-frequency sub-circuit model are the same; the device parameter values ​​in the first differential-mode high-frequency sub-circuit model and the second differential-mode high-frequency sub-circuit model are the same:

[0065] r CM =2R CM

[0066]

[0067] c CM =0.5C CM

[0068] r DM =0.5R DM

[0069]

[0070] c DM =2(C DM -C op )

[0071] Among them, r CM is the resistance value in the first common-mode high-frequency sub-circuit model or the second common-mode high-frequency sub-circuit model; R CM is the resistance value at the corresponding position in the common-mode high-frequency circuit model; l CM is the inductance value in the first common-mode high-frequency sub-circuit model or the second common-mode high-frequency sub-circuit model; L CM is the inductance value of the corresponding position in the common-mode high-frequency circuit model; K CM is the coupling coefficient of the inductor after the common-mode high-frequency circuit model is disassembled; c CM is the capacitance value in the first common-mode high-frequency sub-circuit model or the second common-mode high-frequency sub-circuit model; C CM is the capacitance value at the corresponding position in the common-mode high-frequency circuit model; r DM is the resistance value in the first differential mode high frequency sub-circuit model or the second differential mode high frequency sub-circuit model; R DMis the resistance value of the corresponding position in the differential mode high frequency circuit model; l DM is the inductance value in the first differential mode high frequency sub-circuit model or the second differential mode high frequency sub-circuit model; L DM is the inductance value of the corresponding position in the differential mode high frequency circuit model; K DM is the coupling coefficient of the inductance after the differential mode high frequency circuit is disassembled; c DM is the capacitance value in the first differential mode high frequency sub-circuit model or the second differential mode high frequency sub-circuit model; C DM is the capacitance value at the corresponding position in the differential mode high frequency circuit model; C op is the parasitic capacitance.

[0072] The beneficial effect of the above further solution is: by determining the parameters of the split model and utilizing the circuit equivalent principle, the impedance characteristics before and after the split can be kept unchanged. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] Figure 1 The figure is a flow chart of the method of the present invention.

[0074] Figure 2 This is a schematic diagram of the impedance test in an embodiment of the present invention.

[0075] Figure 3 Schematic diagram of impedance test results in an embodiment of the present invention.

[0076] Figure 4 Schematic diagram of impedance curve analysis in an embodiment of the present invention.

[0077] Figure 5 Schematic diagram of a high-frequency circuit model in an embodiment of the present invention.

[0078] Figure 6 Schematic diagram of comparison between initial parameter simulation results and tests in an embodiment of the present invention.

[0079] Figure 7 4 is a flow chart of a genetic algorithm in an embodiment of the present invention.

[0080] Figure 8 Schematic diagram of comparison between genetic algorithm optimization results and test results in an embodiment of the present invention.

[0081] Fig. 9 Schematic diagram of a full circuit model of an equivalent circuit in an embodiment of the present invention.

[0082] Fig.10 It is a schematic diagram of the comparison of the simulation test of the full circuit model after the circuit is equivalent in the embodiment of the present invention. DETAILED DESCRIPTION

[0083] The specific implementation modes of the present invention are described below so that those skilled in the art can understand the present invention. However, it should be clear that the present invention is not limited to the scope of the specific implementation modes. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations utilizing the concept of the present invention are protected.

[0084] like Figure 1 As shown, in one embodiment of the present invention, a method for establishing a high-frequency full-circuit model of a common-mode choke includes:

[0085] Use an impedance analyzer to perform impedance testing on the common mode choke to obtain common mode impedance characteristic curve, differential mode impedance characteristic curve and parasitic capacitance;

[0086] Determine the common mode circuit topology and the differential mode circuit topology according to the characteristics of the common mode impedance characteristic curve and the differential mode impedance characteristic curve respectively;

[0087] Calculating initial values ​​of each device in the common-mode circuit topology and the differential-mode circuit topology according to the characteristics of the common-mode impedance characteristic curve and the differential-mode impedance characteristic curve, and determining the value range of each device according to the initial values ​​of each device in the common-mode circuit topology and the differential-mode circuit topology;

[0088] According to the value range of each device, the common mode impedance characteristic curve and the differential mode impedance characteristic curve are fitted by using genetic algorithm, the precise value of each device in the common mode circuit topology and the differential mode circuit topology is determined, and the common mode high frequency circuit model and the differential mode high frequency circuit model are obtained;

[0089] According to the parasitic capacitance, the common-mode high-frequency circuit model and the differential-mode high-frequency circuit model are converted into a full circuit model using the principle of circuit equivalence.

[0090] The method of using an impedance analyzer to perform an impedance test on the common-mode choke to obtain a common-mode impedance characteristic curve, a differential-mode impedance characteristic curve and a parasitic capacitance is specifically as follows: using an impedance analyzer to perform a common-mode test, a differential-mode test and an open-circuit test on the common-mode choke to obtain a common-mode impedance characteristic curve, a differential-mode impedance characteristic curve and a parasitic capacitance.

[0091] The calculation formula of the value of the parasitic capacitance is:

[0092]

[0093] Wherein, Z is the impedance of any point on the straight line segment before the resonance point in the open circuit impedance characteristic curve; π is the circumference of a circle; and f is the frequency of the point corresponding to Z.

[0094] The determining of the common mode circuit topology and the differential mode circuit topology is specifically:

[0095] Obtain the number n of resonance points of the impedance characteristic curve, and number the resonance points in sequence from left to right according to the horizontal axis;

[0096] When the number of resonance points n is an even number, the first n-1 resonance points are topologically transformed based on the RLC parallel circuit to obtain the unit topology of each resonance point, and the unit topologies are connected in series according to the order of the resonance point numbers, and the circuit topology obtained after the series connection is connected in series with an inductor to obtain the corresponding circuit topology;

[0097] When the number of resonance points n is an odd number, each resonance point is topologically improved based on the RLC parallel circuit to obtain the unit topology of each resonance point, and each unit topology is connected in series according to the resonance point numbering sequence to obtain the corresponding circuit topology;

[0098] When the impedance characteristic curve is a common-mode impedance characteristic curve, the corresponding circuit topology obtained is a common-mode circuit topology; when the impedance characteristic curve is a differential-mode impedance characteristic curve, the corresponding circuit topology obtained is a differential-mode circuit topology.

[0099] The topology transformation based on the RLC parallel circuit is performed to obtain the unit topology of each resonance point, which is specifically:

[0100] The impedance curve from the third zone of the resonance point i-1 to the resonance point i is taken as the first zone, the resonance point i is taken as the second zone, and the impedance curve from the resonance point i to the first zone of the resonance point i+1 is taken as the third zone. The impedance curves of the first zone and the third zone are analyzed respectively, and the topology of the RLC parallel circuit is transformed based on the analysis results to obtain the unit topology of the resonance point.

[0101] For the impedance curve of the first zone:

[0102] If the analysis result is: the impedance curve is a straight line with a slope greater than zero, then the inductance branch of the RLC parallel circuit remains unchanged;

[0103] If the analysis result is: the slope of the impedance curve tends to zero at first and then increases to a constant value, then a resistor is connected in series with the inductor branch of the RLC parallel circuit;

[0104] If the analysis result is: the impedance curve is first a straight line with a slope greater than zero, and then the slope decreases but is still greater than zero, then add a branch of resistance and inductance in series to the RLC parallel circuit;

[0105] For the impedance curve of the third zone:

[0106] If the analysis result is: there is no third zone, delete the capacitor branch in the RLC parallel circuit;

[0107] If the analysis result is: the impedance curve is a straight line with a slope less than c, then the capacitive branch of the RLC parallel circuit remains unchanged; c is a negative number;

[0108] If the analysis result is that the impedance curve is a straight line with a slope less than zero and greater than c, a resistor is connected in series with the capacitor branch of the RLC parallel circuit.

[0109] In this embodiment, the impedance test needs to be performed three times, namely, common mode test, differential mode test and open circuit test. The common mode and differential mode tests are to obtain the common mode and differential mode characteristics of the common mode choke at high frequency, while the open circuit test is to obtain the parasitic capacitance between the two sets of coils. The abscissa and ordinate of the common mode and differential mode impedance characteristic curves of the common mode choke are both logarithmic coordinates.

[0110] Step 1: The entire impedance curve can be preliminarily partitioned according to the resonance point. When there are multiple resonance points, the first resonance point is selected for partitioning. The area before the resonance point is called the "first area", the resonance point is called the "second area", and the area after the resonance point is called the third area. Since the method described in the present invention is based on the RLC parallel model, the first area usually corresponds to the inductor L branch in the circuit topology, the second area corresponds to the resistor R branch, and the third area corresponds to the capacitor C branch.

[0111] The order of curve characteristics analysis is from left to right on the horizontal axis, that is, the first area to the third area.

[0112] When the impedance curve is in the first zone, it is divided into the following situations:

[0113] (1) If the impedance curve is a straight line, that is, the slope of the curve is constant and greater than zero, then the circuit topology does not change in the inductor branch;

[0114] (2) If the impedance curve is approximately parallel to the horizontal axis at the beginning, and then the slope increases to a constant value, the impedance curve rises linearly; at this time, a resistor needs to be connected in series with the inductor branch based on the RLC parallel circuit;

[0115] (3) If the impedance curve is a straight line at the beginning and then a turning point appears, the slope of the impedance curve changes before and after the turning point, and the slope decreases but is still greater than zero. At this time, the circuit topology needs to add a branch on the basis of the RLC parallel circuit, and the devices on this added branch are resistors and inductors in series;

[0116] When the impedance curve is in the second zone:

[0117] The second area defined by the present invention is the resonance point. The impedance characteristics before and after the resonance point change from inductance to capacitance, and the resonance point shows resistance characteristics. The resonance point is the basis for dividing the analysis area in the present invention, but it does not change the circuit topology;

[0118] When the impedance curve is in the third zone, it is divided into the following situations:

[0119] (1) There is no third zone in the measured frequency range curve, and the capacitor branch needs to be deleted;

[0120] (2) After the resonance point, the slope of the impedance curve is less than zero and the value remains unchanged, and the overall trend is relatively steep. At this time, the capacitor branch in the circuit topology does not change; c can be used as a threshold to determine whether the slope is steep;

[0121] (3) After the resonance point, the slope of the impedance curve is less than zero and the value remains unchanged, but the downward trend is relatively gentle. At this time, a resistor needs to be connected in series with the capacitor branch.

[0122] The above analysis is applicable to the case where there is no resonance point or only one resonance point. In practical applications, the above situations are flexibly combined according to the characteristics of the impedance curve. For example, situation (2) appears in the first zone and situation (3) appears in the third zone. Then the circuit topology is (resistance-inductance / / resistance / / resistance-capacitance).

[0123] Step 2: The above content has completely analyzed the situation with one resonance point. The overall trend of the curve is "convex". Since the impedance characteristics will change before and after the resonance point, if the impedance curve has a second resonance point, then the curve will be "concave". When the third resonance point appears, the curve will be "convex". If there are more resonance points, it will go back and forth like this. The situation with multiple resonance points will be explained in the next step.

[0124] When there are multiple resonance points, the resonance point is in the third zone, then the analysis of the first zone and the second zone still follows the content of step 1, so step 2 is analyzed immediately after step 1, and the analysis order is still from left to right. The circuit topology established in step 1 is called the "first unit" in the present invention. The first unit has completely characterized the characteristics of the first resonance point, and the first unit as a whole exhibits the characteristics of capacitance at the current position. Then when the next resonance point appears, the circuit topology will be established in the following cases:

[0125] (1) The second resonance point appears but the third resonance point does not appear, and the impedance curve changes from "convex" to "concave". At this time, the circuit topology needs to connect the "first unit" in series with an inductor, and the topology structure of the "first unit" remains unchanged.

[0126] (2) The third resonance point appears, and the impedance curve is "convex", "concave", and "convex" as a whole. At this time, the circuit topology is the "first unit" connected in series with the RLC parallel circuit. This RLC parallel circuit can be called the "second unit". At this time, if the curve shape has similar characteristics to the situation described in step 1, the RLC circuit topology in the second unit can also be analyzed according to the process in step 1.

[0127] (3) When more resonant points appear, the analysis can be done according to the first two cases, with inductors connected in series or more "units" connected in series.

[0128] At this point, the characteristics analysis of the impedance curve has been completed and the corresponding circuit topology has been established.

[0129] The calculation formula for calculating the initial value of each device in the common mode circuit topology and the differential mode circuit topology is:

[0130]

[0131] R i,old =Z i,2

[0132]

[0133] R i,new.L =Z i,1 '

[0134] R i,new.L-R =Z i,1 ”

[0135]

[0136]

[0137] Among them, L i,old is the initial value of the inductance of the RLC parallel circuit in the unit topology at the i-th resonance point; Z i,1 is the impedance of any point in the straight line portion of the impedance curve of the first zone of the i-th resonance point. If the impedance curve of the first zone is first a straight line with a slope greater than zero, and then the slope decreases but is still greater than zero, then it is the impedance of any point in the straight line portion before the turning point; f i,1 Z i,1 The frequency of the corresponding point; R i,old is the initial value of the resistance of the RLC parallel circuit in the unit topology at the i-th resonance point; Z i,2 is the impedance of the i-th resonance point; π is the circumference of a circle; C i,old is the initial value of the capacitance of the RLC parallel circuit in the unit topology at the i-th resonance point; Z i,3 is the impedance of any point in the straight line portion of the impedance curve of the third region of the i-th resonance point; f i,3 Z i,3 The frequency of the corresponding point; R i,new.L is the initial value of the resistance added to the inductor branch of the RLC parallel circuit in the unit topology at the i-th resonance point; Z i,1 ' is the impedance of any point in the part where the slope tends to zero in the first zone impedance curve of the i-th resonance point; R i,new.L-Ris the initial value of the resistance of the newly added inductor-resistor branch in the RLC parallel circuit in the unit topology at the i-th resonance point; Z i,1 " is the impedance of the turning point where the slope of the impedance curve of the first zone of the i-th resonance point changes; L i,new.L-R is the initial value of the inductance of the newly added inductor-resistor branch in the RLC parallel circuit in the unit topology at the i-th resonance point; Z i,1 ”' is the impedance of any point in the straight line portion after the turning point where the slope of the impedance curve of the first zone of the i-th resonance point changes; f i,1 ”' for Z i,1 ”'The frequency of the corresponding point; R i,new.C is the initial value of the resistance of the capacitor branch in the RLC parallel circuit in the unit topology at the i-th resonance point.

[0138] In this embodiment, Figure 1 As shown, the modeling method of the common mode choke high frequency full circuit model of the present invention is as follows:

[0139] (1) Use an impedance analyzer to measure the common mode, differential mode and open circuit impedance characteristic curves of the common mode choke. The frequency range is 100Hz-120MHz. The measurement method is as follows: Figure 2 As shown in the figure, different impedance curves are measured by different wiring methods. Figure 2 In the figure, P1 and P2 are one set of coils, and N1 and N2 are another set of coils. When performing common mode testing, P1 and N1 are short-circuited, P2 and N2 are short-circuited, and then connected to the impedance analyzer according to the wiring method shown in the figure to perform impedance testing. For differential mode testing, only P2 and N2 need to be short-circuited, and the impedance analyzer is connected to ports P1 and N1. For open circuit testing, short-circuiting is not required, and ports P1 and N1 are tested with an impedance analyzer.

[0140] (2) The test results of the impedance analyzer are as follows Figure 3 As shown. The open circuit test is to test the parasitic capacitance C between the coils. op The test results will be used when the full circuit model is established later. At this time, the main focus is on the common mode and differential mode impedance curves. The high-frequency circuit model of ordinary inductors is usually an RLC parallel model. The impedance curve of the RLC parallel model is similar to the impedance curve of the common mode choke. Therefore, the present invention is mainly based on the optimization of the traditional RLC parallel model. By adding or reducing the components in the circuit, a high-frequency circuit topology is established. The impedance curve of the RLC parallel model is as follows: Figure 4 As shown in (a), there is a resonance point in the curve. Before the resonance point, the curve shows inductance characteristics, and after the resonance point, it shows capacitance characteristics. The entire impedance curve shows inductance characteristics, resistance characteristics, and capacitance characteristics from left to right. Then the circuit model optimized based on the RLC parallel model should also have similar characteristics.

[0141] Then further analysis Figure 4 (b) shows the common-mode impedance curve of the common-mode choke. Initially, the curve shows an inductance characteristic. After passing the "turning point" R1, the rising trend of the curve slows down, but it still shows an inductance characteristic. It can be seen that there should be two inductance branches in the common-mode high-frequency circuit model, and the inductance values ​​of the two inductance branches are different (L1 and L2). In addition, since L2 shows the characteristic of "slowing rising trend", it is necessary to connect a resistor R1 in series with its branch L2; then the curve reaches the resonance point R2, so there is a resistance branch; after passing the resonance point, it shows a "conventional" capacitance characteristic, so the capacitance branch does not need to be optimized. So far, the following is established. Figure 5 (a) Circuit topology. In the same way, the differential mode characteristics Figure 4 (c) Analysis shows that compared with the traditional RLC parallel model, the differential mode impedance curve shows a short resistance characteristic at low frequency, and then shows inductance characteristics. Therefore, a resistor needs to be added to the inductor branch, and the other branches remain unchanged. The differential mode high frequency circuit topology is as follows: Figure 5 As shown in (b), the common-mode and differential-mode high-frequency circuit models have been established. The initial parameters of the inductor and capacitor can be calculated by taking points according to the corresponding formulas.

[0142] The points for calculating the initial value of each device are as follows:

[0143] The calculation of inductance is to select the first zone before the resonance point, and select a point on the part where the impedance curve is a straight line, and use the impedance value and frequency of this point to calculate; the calculation of capacitance is the third zone after the resonance point, and select a point on the part where the impedance curve is a straight line, and use the impedance value and frequency of this point to calculate. Here are the devices in the RLC parallel circuit that are calculated, not the initial values ​​of the newly added devices.

[0144] The calculation formula for the initial value of the newly added device in the topology is the same as the calculation formula for the initial value of the device in the RLC parallel circuit, except that the selection points are different. The following is an explanation for each case:

[0145] For the impedance curve of the first zone:

[0146] If the analysis result shows that the impedance curve is a straight line with a slope greater than zero, the inductance branch of the RLC parallel circuit remains unchanged (the topology is not changed)

[0147] If the analysis result shows that the slope of the impedance curve tends to zero at first and then increases to a constant value, a resistor is connected in series with the inductor branch of the RLC parallel circuit; (the point where the slope of the impedance curve tends to zero is selected, and the impedance value of this point is taken as the resistance value)

[0148] If the analysis result shows that the impedance curve is first a straight line with a slope greater than zero, and then the slope decreases and is still greater than zero, then add a branch of resistance and inductance in series to the RLC parallel circuit; (In this case, the slope of the impedance curve will change, and the impedance curve will have a turning point. The impedance value at the turning point is the resistance value of the newly added branch; the initial value of the newly added inductance is after the turning point and before the resonance point, and the point is taken and substituted into the above formula for calculation. The "original" initial value of the inductance in the RLC parallel circuit is calculated by taking a point in the area before the turning point of the impedance curve.)

[0149] For the impedance curve of the third zone:

[0150] If the analysis result shows that there is no third zone, delete the capacitor branch in the RLC parallel circuit;

[0151] If the analysis result shows that the impedance curve is a straight line with a slope less than c, the capacitive branch of the RLC parallel circuit remains unchanged; c is a negative number;

[0152] If the analysis result shows that the impedance curve is a straight line with a slope less than zero and greater than c, then a resistor is connected in series with the capacitor branch of the RLC parallel circuit (the initial value of the new resistor is 0.5*R i,old ).

[0153] In this embodiment, after the initial parameters are calculated, the initial parameters are brought into the established high-frequency circuit topology for simulation. The simulation comparison results are as follows: Figure 6 As shown, the simulation results are consistent with the test results, which proves that the circuit topology determination method of the present invention is effective. Next, a more accurate model can be obtained by optimizing the initial parameters using a genetic algorithm.

[0154] The value ranges of the components are specifically as follows:

[0155] L i ×10 -1 ≤L i ≤L i ×10

[0156] R i ×10 -1 ≤R i ≤R i ×10

[0157] C i ×10 -1 ≤C i ≤C i ×10

[0158] L i ∈[L i,old ,L i,new.L-R ]

[0159] R i ∈[R i,old ,R i,new.L ,R i,new.L-R ,R i,new.C ]

[0160] C i ∈[C i,old ]

[0161] Among them, L i is the initial value of the inductance in the unit topology at the i-th resonance point; R i is the initial value of the resistance in the unit topology at the i-th resonance point; C i is the initial value of the capacitance in the unit topology at the i-th resonance point.

[0162] The fitness function of the genetic algorithm is:

[0163] d=∑|Z CA -Z test | 2

[0164] Among them, d is the fitness function of the genetic algorithm; Z CA is the impedance of the circuit topology; Z test is the corresponding impedance test data; |·| is the absolute value.

[0165] In this embodiment, a genetic algorithm is used to search for parameters based on the initial parameter values ​​to further optimize the impedance characteristics of the model. The genetic algorithm process is as follows: Figure 7 As shown, the initial population parameters are the initial parameters. Taking the common-mode high-frequency circuit model as an example, the initial population parameters are set to L1, L2, R1, R2, and C. After the initial population parameters are set, the value range needs to be set. The value range is as follows:

[0166] L1×10 -1 ≤L1≤L1×10 1

[0167] L2×10 -1 ≤L2≤L2×10 1

[0168] R1×10 -1 ≤R1≤R1×10 1

[0169] R2×10 -1 ≤R2≤R2×10 1

[0170] C×10 -1 ≤C≤C×10 1

[0171] The value range is usually from 10 times smaller than the initial parameter to 10 times larger than the initial parameter.

[0172] Next, we need to define the fitness function. In the fitness function, Z CA The impedance expression of the established circuit topology is as follows. The circuit topology in the present invention is determined based on the characteristics of the impedance curve, so different common mode chokes will have different Z CA Expression; Z test The corresponding impedance test data, the minimum fitness function represents a good fitting effect. Finally, because the method of the present invention is less dependent on the algorithm, the setting of genetic algorithm parameters (population size, number of iterations, crossover rate, etc.) can use the default settings without being too harsh, which can save computer resources. The results of genetic algorithm optimization are brought into the circuit simulation software, and the simulation results are compared. Figure 8 As shown, compared to Figure 6 In terms of the initial parameter simulation results, the results after genetic algorithm optimization are more accurate, which effectively improves the accuracy of the model. So far, the basic high-frequency circuit model has been built, but the number of ports in the circuit model does not match the actual number of ports. The next step is to convert the number of ports through equivalent transformation to facilitate circuit simulation.

[0173] According to the parasitic capacitance, the common-mode high-frequency circuit model and the differential-mode high-frequency circuit model are converted into a full circuit model using the principle of circuit equivalence, specifically:

[0174] Splitting the common-mode high-frequency circuit model into a first common-mode high-frequency sub-circuit model and a second common-mode high-frequency sub-circuit model; the circuit topologies of the first common-mode high-frequency sub-circuit model and the second common-mode high-frequency sub-circuit model are the same as the common-mode high-frequency circuit model;

[0175] Splitting the differential-mode high-frequency circuit model into a first differential-mode high-frequency sub-circuit model and a second differential-mode high-frequency sub-circuit model; the circuit topologies of the first differential-mode high-frequency sub-circuit model and the second differential-mode high-frequency sub-circuit model are the same as those of the differential-mode high-frequency circuit model;

[0176] The first common-mode high-frequency sub-circuit model is connected in series with the first differential-mode high-frequency sub-circuit model; the second common-mode high-frequency sub-circuit model is connected in series with the second differential-mode high-frequency sub-circuit model; the output end of the first common-mode high-frequency sub-circuit model and the output end of the second common-mode high-frequency sub-circuit model are connected in parallel with parasitic capacitance; the output end of the first differential-mode high-frequency sub-circuit model and the output end of the second differential-mode high-frequency sub-circuit model are connected in parallel with parasitic capacitance.

[0177] The device parameter values ​​in the first common-mode high-frequency sub-circuit model and the second common-mode high-frequency sub-circuit model are the same; the device parameter values ​​in the first differential-mode high-frequency sub-circuit model and the second differential-mode high-frequency sub-circuit model are the same:

[0178] r CM =2R CM

[0179]

[0180] c CM =0.5C CM

[0181] r DM =0.5R DM

[0182]

[0183] c DM =2(C DM -C op )

[0184] Among them, r CM is the resistance value in the first common-mode high-frequency sub-circuit model or the second common-mode high-frequency sub-circuit model; R CM is the resistance value at the corresponding position in the common-mode high-frequency circuit model; l CM is the inductance value in the first common-mode high-frequency sub-circuit model or the second common-mode high-frequency sub-circuit model; L CM is the inductance value of the corresponding position in the common-mode high-frequency circuit model; K CM is the coupling coefficient of the inductor after the common-mode high-frequency circuit model is disassembled; c CM is the capacitance value in the first common-mode high-frequency sub-circuit model or the second common-mode high-frequency sub-circuit model; C CM is the capacitance value at the corresponding position in the common-mode high-frequency circuit model; r DM is the resistance value in the first differential mode high frequency sub-circuit model or the second differential mode high frequency sub-circuit model; R DM is the resistance value of the corresponding position in the differential mode high frequency circuit model; l DM is the inductance value in the first differential mode high frequency sub-circuit model or the second differential mode high frequency sub-circuit model; L DM is the inductance value of the corresponding position in the differential mode high frequency circuit model; K DM is the coupling coefficient of the inductance after the differential mode high frequency circuit is disassembled; c DM is the capacitance value in the first differential mode high frequency sub-circuit model or the second differential mode high frequency sub-circuit model; C DM is the capacitance value at the corresponding position in the differential mode high frequency circuit model; C op is the parasitic capacitance.

[0185] In this embodiment, the common-mode high-frequency circuit model and the differential-mode high-frequency circuit model have been successfully established, and both have good accuracy in a wide frequency range (100Hz-120MHz). At this time, it is necessary to use the circuit equivalent conversion principle to merge the two circuit models into a four-port circuit model. Therefore, both the common-mode circuit model and the differential-mode circuit model need to be "split into two" for disassembly, and the two-port circuit model is replaced with a four-port full circuit model. The complete common-mode choke high-frequency full circuit model is as follows Fig. 9 As shown, the equivalent conversion formula between common mode and differential mode parameters is as follows:

[0186]

[0187]

[0188] In order to make the full circuit model only show common mode (differential mode) characteristics under common mode (differential mode) conditions, K is introduced in the formula CM1 , K CM2 and K DM1 . K CM1 and K CM2 is the coupling coefficient of the corresponding inductance after the common mode circuit model is disassembled, and the value is equal to 1, K DM1 It is the coupling coefficient of the inductance corresponding to the differential mode circuit model after disassembly, and its value is equal to -1.

[0189] In this embodiment, the circuit can be equivalent to two C op The impedance curve formed by a parallel circuit.

[0190] So far, the establishment of the high-frequency full circuit model of the common-mode choke has been completed. The comparison between the simulation and test results is as follows: Fig.10 As shown, the high-frequency model established by the method of the present invention has high accuracy and can accurately characterize the high-frequency characteristics of the common-mode choke within a wide frequency range.

[0191] The core of the modeling method of the present invention is to determine the circuit topology according to the characteristics of the impedance curve. Therefore, the method of the present invention is not only applicable to common-mode chokes, but also to any situation where a model is established through an impedance curve. For example, it is also applicable to high-frequency circuit models of magnetic rings established through impedance curves. It should be noted that the circuit topology established by the method of the present invention is combined with the initial parameters obtained by simple calculations, which can basically characterize the characteristics of the impedance curve. Therefore, it is only necessary to simply use a genetic algorithm (or other suitable algorithms) for correction, which reduces the dependence on complex algorithms and speeds up the modeling speed. In addition, the impedance curve characteristics of different chokes may be different, so the circuit topology established by the method of the present invention will also change. Therefore, the circuit topology described in this embodiment is only an example, and in actual applications, the circuit topology needs to be flexibly adjusted according to the characteristics of the specific impedance curve.

Claims

1. A method for establishing a high-frequency full-circuit model of a common-mode choke, characterized in that: include: Use an impedance analyzer to perform impedance testing on the common mode choke to obtain common mode impedance characteristic curve, differential mode impedance characteristic curve and parasitic capacitance; Determine the common mode circuit topology and the differential mode circuit topology according to the characteristics of the common mode impedance characteristic curve and the differential mode impedance characteristic curve respectively; Calculating initial values ​​of each device in the common-mode circuit topology and the differential-mode circuit topology according to the characteristics of the common-mode impedance characteristic curve and the differential-mode impedance characteristic curve, and determining the value range of each device according to the initial values ​​of each device in the common-mode circuit topology and the differential-mode circuit topology; According to the value range of each device, the common mode impedance characteristic curve and the differential mode impedance characteristic curve are fitted by using genetic algorithm, the precise value of each device in the common mode circuit topology and the differential mode circuit topology is determined, and the common mode high frequency circuit model and the differential mode high frequency circuit model are obtained; According to the parasitic capacitance, the common-mode high-frequency circuit model and the differential-mode high-frequency circuit model are converted into a full circuit model using the principle of circuit equivalence.

2. The method for establishing a high-frequency full-circuit model of a common-mode choke according to claim 1, characterized in that: The method of using an impedance analyzer to perform an impedance test on the common-mode choke to obtain a common-mode impedance characteristic curve, a differential-mode impedance characteristic curve and a parasitic capacitance is specifically as follows: using an impedance analyzer to perform a common-mode test, a differential-mode test and an open-circuit test on the common-mode choke to obtain a common-mode impedance characteristic curve, a differential-mode impedance characteristic curve and a parasitic capacitance.

3. The method for establishing a high-frequency full-circuit model of a common-mode choke coil according to claim 2, characterized in that: The calculation formula of the value of the parasitic capacitance is: Wherein, Z is the impedance of any point on the straight line segment before the resonance point in the open circuit impedance characteristic curve; π is the circumference of a circle; and f is the frequency of the point corresponding to Z.

4. The method for establishing a high-frequency full-circuit model of a common-mode choke coil according to claim 1, characterized in that: The determining of the common mode circuit topology and the differential mode circuit topology is specifically: Obtain the number n of resonance points of the impedance characteristic curve, and number the resonance points in sequence from left to right according to the horizontal axis; When the number of resonance points n is an even number, the first n-1 resonance points are topologically transformed based on the RLC parallel circuit to obtain the unit topology of each resonance point, and the unit topologies are connected in series according to the order of the resonance point numbers, and the circuit topology obtained after the series connection is connected in series with an inductor to obtain the corresponding circuit topology; When the number of resonance points n is an odd number, each resonance point is topologically improved based on the RLC parallel circuit to obtain the unit topology of each resonance point, and each unit topology is connected in series according to the resonance point numbering sequence to obtain the corresponding circuit topology; When the impedance characteristic curve is a common-mode impedance characteristic curve, the corresponding circuit topology obtained is a common-mode circuit topology; when the impedance characteristic curve is a differential-mode impedance characteristic curve, the corresponding circuit topology obtained is a differential-mode circuit topology.

5. The method for establishing a high-frequency full-circuit model of a common-mode choke coil according to claim 4, characterized in that: The topology transformation based on the RLC parallel circuit is performed to obtain the unit topology of each resonance point, which is specifically: The impedance curve from the third zone of the resonance point i-1 to the resonance point i is taken as the first zone, the resonance point i is taken as the second zone, and the impedance curve from the resonance point i to the first zone of the resonance point i+1 is taken as the third zone. The impedance curves of the first zone and the third zone are analyzed respectively, and the topology of the RLC parallel circuit is transformed based on the analysis results to obtain the unit topology of the resonance point. For the impedance curve of the first zone: If the analysis result is: the impedance curve is a straight line with a slope greater than zero, then the inductance branch of the RLC parallel circuit remains unchanged; If the analysis result is: the slope of the impedance curve tends to zero at first and then increases to a constant value, then a resistor is connected in series with the inductor branch of the RLC parallel circuit; If the analysis result is: the impedance curve is first a straight line with a slope greater than zero, and then the slope decreases but is still greater than zero, then add a branch of resistance and inductance in series to the RLC parallel circuit; For the impedance curve of the third zone: If the analysis result is: there is no third zone, delete the capacitor branch in the RLC parallel circuit; If the analysis result is: the impedance curve is a straight line with a slope less than c, then the capacitive branch of the RLC parallel circuit remains unchanged; c is a negative number; If the analysis result is that the impedance curve is a straight line with a slope less than zero and greater than c, a resistor is connected in series with the capacitor branch of the RLC parallel circuit.

6. The method for establishing a high-frequency full-circuit model of a common-mode choke according to claim 1, characterized in that: The calculation formula for calculating the initial value of each device in the common mode circuit topology and the differential mode circuit topology is: R i,old =Z i,2 R i,new.L =Z i,1 ' R i,new.L-R =Z i,1 ” Among them, L i,old is the initial value of the inductance of the RLC parallel circuit in the unit topology at the i-th resonance point; Z i,1 is the impedance of any point in the straight line portion of the impedance curve of the first zone of the i-th resonance point. If the impedance curve of the first zone is first a straight line with a slope greater than zero, and then the slope decreases but is still greater than zero, then it is the impedance of any point in the straight line portion before the turning point; f i,1 Z i,1 The frequency of the corresponding point; R i,old is the initial value of the resistance of the RLC parallel circuit in the unit topology at the i-th resonance point; Z i,2 is the impedance of the i-th resonance point; π is the circumference of a circle; C i,old is the initial value of the capacitance of the RLC parallel circuit in the unit topology at the i-th resonance point; Z i,3 is the impedance of any point in the straight line portion of the impedance curve of the third region of the i-th resonance point; f i,3 Z i,3 The frequency of the corresponding point; R i,new.L is the initial value of the resistance added to the inductor branch of the RLC parallel circuit in the unit topology at the i-th resonance point; Z i,1 ' is the impedance of any point in the part where the slope tends to zero in the first zone impedance curve of the i-th resonance point; R i,new.L-R is the initial value of the resistance of the newly added inductor-resistor branch in the RLC parallel circuit in the unit topology at the i-th resonance point; Z i,1 ” is the impedance of the turning point where the slope of the impedance curve of the first zone of the i-th resonance point changes; L i,new.L-R is the initial value of the inductance of the newly added inductor-resistor branch in the RLC parallel circuit in the unit topology at the i-th resonance point; Z i,1 ”' is the impedance of any point in the straight line portion after the turning point where the slope of the impedance curve of the first zone of the i-th resonance point changes; f i,1 ”' for Z i,1 ”'The frequency of the corresponding point; R i,new.C is the initial value of the resistance of the capacitor branch in the RLC parallel circuit in the unit topology at the i-th resonance point.

7. The method for establishing a high-frequency full-circuit model of a common-mode choke coil according to claim 6, characterized in that: The value ranges of the components are specifically as follows: L i ×10 -1 ≤L i ≤L i ×10 R i ×10 -1 ≤R i ≤R i ×10 C i ×10 -1 ≤C i ≤C i ×10 L i ∈[L i,old ,L i,new.L-R ] R i ∈[R i,old ,R i,new.L ,R i,new.L-R ,R i,new.C ] C i ∈[C i,old ] Among them, L i is the initial value of the inductance in the unit topology at the i-th resonance point; R i is the initial value of the resistance in the unit topology at the i-th resonance point; C i is the initial value of the capacitance in the unit topology at the i-th resonance point.

8. The method for establishing a high-frequency full-circuit model of a common-mode choke coil according to claim 1, characterized in that: The fitness function of the genetic algorithm is: d=Σ|Z CA -WITH test | 2 Among them, d is the fitness function of the genetic algorithm; Z CA is the impedance of the circuit topology; Z test is the corresponding impedance test data; |·| is the absolute value.

9. The method for establishing a high-frequency full-circuit model of a common-mode choke coil according to claim 1, characterized in that: According to the parasitic capacitance, the common-mode high-frequency circuit model and the differential-mode high-frequency circuit model are converted into a full circuit model using the principle of circuit equivalence, specifically: Splitting the common-mode high-frequency circuit model into a first common-mode high-frequency sub-circuit model and a second common-mode high-frequency sub-circuit model; the circuit topologies of the first common-mode high-frequency sub-circuit model and the second common-mode high-frequency sub-circuit model are the same as the common-mode high-frequency circuit model; Splitting the differential-mode high-frequency circuit model into a first differential-mode high-frequency sub-circuit model and a second differential-mode high-frequency sub-circuit model; the circuit topologies of the first differential-mode high-frequency sub-circuit model and the second differential-mode high-frequency sub-circuit model are the same as those of the differential-mode high-frequency circuit model; The first common-mode high-frequency sub-circuit model is connected in series with the first differential-mode high-frequency sub-circuit model; the second common-mode high-frequency sub-circuit model is connected in series with the second differential-mode high-frequency sub-circuit model; the output end of the first common-mode high-frequency sub-circuit model and the output end of the second common-mode high-frequency sub-circuit model are connected in parallel with parasitic capacitance; the output end of the first differential-mode high-frequency sub-circuit model and the output end of the second differential-mode high-frequency sub-circuit model are connected in parallel with parasitic capacitance.

10. The method for establishing a high-frequency full-circuit model of a common-mode choke coil according to claim 9, characterized in that: The device parameter values ​​in the first common-mode high-frequency sub-circuit model and the second common-mode high-frequency sub-circuit model are the same; the device parameter values ​​in the first differential-mode high-frequency sub-circuit model and the second differential-mode high-frequency sub-circuit model are the same: r CM ＝2R CM c CM =0.5C CM r DM ＝0.5R DM c DM =2(C DM -C op ) Among them, r CM is the resistance value in the first common-mode high-frequency sub-circuit model or the second common-mode high-frequency sub-circuit model; R CM is the resistance value at the corresponding position in the common-mode high-frequency circuit model; l CM is the inductance value in the first common-mode high-frequency sub-circuit model or the second common-mode high-frequency sub-circuit model; L CM is the inductance value of the corresponding position in the common-mode high-frequency circuit model; K CM is the coupling coefficient of the inductor after the common-mode high-frequency circuit model is disassembled; c CM is the capacitance value in the first common-mode high-frequency sub-circuit model or the second common-mode high-frequency sub-circuit model; C CM is the capacitance value at the corresponding position in the common-mode high-frequency circuit model; r DM is the resistance value in the first differential mode high frequency sub-circuit model or the second differential mode high frequency sub-circuit model; R DM is the resistance value of the corresponding position in the differential mode high frequency circuit model; l DM is the inductance value in the first differential mode high frequency sub-circuit model or the second differential mode high frequency sub-circuit model; L DM is the inductance value of the corresponding position in the differential mode high frequency circuit model; K DM is the coupling coefficient of the inductance after the differential mode high frequency circuit is disassembled; c DM is the capacitance value in the first differential mode high frequency sub-circuit model or the second differential mode high frequency sub-circuit model; C DM is the capacitance value at the corresponding position in the differential mode high frequency circuit model; C op is the parasitic capacitance.

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