Distributed reasoning techniques

Abstract

The invention discloses distributed reasoning techniques, and particularly discloses devices, systems, and techniques for executing neural networks. In at least one embodiment, a processor causes information to be distributed to a processing core. In at least one embodiment, the processor is configured to distribute inference of two or more contiguous portions of information only between two or more corresponding processing cores.

Description

Technical Field

[0001] At least one embodiment relates to computing resources for training and operating neural networks. For example, at least one embodiment relates to distributing input data to processors for training and operating neural networks. Background Art

[0002] Performing computational operations can consume significant amounts of memory, time, or resources. Computer programs can be organized so that multiple computer systems can be used to execute various components in different ways and in different orders. While advances in computer hardware have accelerated or otherwise aided the performance of various components of computer programs, these advances generally fail to take into account the various ways in which computer programs can be constructed and the various ways in which elements of a computer program can be distributed across computer systems. The amount of memory, time, and / or computational resources used to perform computational operations can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 is a block diagram illustrating a computer system in which a neural network is trained using partitioned training data and activations according to at least one embodiment;

[0004] Figure 2 is a block diagram illustrating a computer system in which data and activation are partitioned according to a partitioning standard, according to at least one embodiment;

[0005] Figure 3 is a block diagram illustrating a process for partitioning neural network training data and activations according to at least one embodiment;

[0006] Figure 4 is a block diagram illustrating forward and backward propagation in a neural network according to at least one embodiment;

[0007] Figure 5 is a block diagram illustrating a first portion of a computing system in which a neural network is trained using partitioned neural network training data and activations in accordance with at least one embodiment;

[0008] Figure 6 is a block diagram illustrating a second portion of a computing system in which a neural network is trained using partitioned neural network training data and activations in accordance with at least one embodiment;

[0009] Figure 7 is a block diagram illustrating training a neural network using partitioned neural network training data and activations in accordance with at least one embodiment;

[0010] Figure 8 is a block diagram illustrating a processor and modules according to at least one embodiment;

[0011] Figure 9A illustrates logic according to at least one embodiment;

[0012] Figure 9B illustrates logic according to at least one embodiment;

[0013] Figure 10 illustrates the training and deployment of a neural network according to at least one embodiment;

[0014] Figure 11 An example data center system is shown in accordance with at least one embodiment;

[0015] Figure 12A An example of an autonomous vehicle according to at least one embodiment is shown;

[0016] Figure 12B According to at least one embodiment, Figure 12A Examples of camera positions and fields of view for autonomous vehicles;

[0017] Figure 12C According to at least one embodiment Figure 12A A block diagram of an example system architecture for an autonomous vehicle;

[0018] Figure 12D is a diagram illustrating a method for one or more cloud-based servers and Figure 12A A diagram of a system for communicating between autonomous vehicles;

[0019] Figure 13 is a block diagram illustrating a computer system according to at least one embodiment;

[0020] Figure 14 is a block diagram illustrating a computer system according to at least one embodiment;

[0021] Figure 15 A computer system according to at least one embodiment is shown;

[0022] Figure 16 A computer system according to at least one embodiment is shown;

[0023] Figure 17A A computer system according to at least one embodiment is shown;

[0024] Figure 17B A computer system according to at least one embodiment is shown;

[0025] Figure 17C A computer system according to at least one embodiment is shown;

[0026] Figure 17D A computer system according to at least one embodiment is shown;

[0027] Figure 17E and Figure 17F illustrates a shared programming model in accordance with at least one embodiment;

[0028] Figure 18 An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0029] Figure 19A and Figure 19B An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0030] Figure 20A and Figure 20B Additional exemplary graphics processor logic is shown in accordance with at least one embodiment;

[0031] Figure 21 A computer system according to at least one embodiment is shown;

[0032] Figure 22A A parallel processor according to at least one embodiment is shown;

[0033] Figure 22B shows a partition unit according to at least one embodiment;

[0034] Figure 22C illustrates a processing cluster according to at least one embodiment;

[0035] Figure 22D A graphics multiprocessor is shown in accordance with at least one embodiment;

[0036] Figure 23 A multi-graphics processing unit (GPU) system is shown in accordance with at least one embodiment;

[0037] Figure 24 A graphics processor according to at least one embodiment is shown;

[0038] Figure 25 is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment;

[0039] Figure 26 A deep learning application processor according to at least one embodiment is shown;

[0040] Figure 27 is a block diagram illustrating an example neuromorphic processor in accordance with at least one embodiment;

[0041] Figure 28 illustrates at least a portion of a graphics processor according to at least one embodiment;

[0042] Figure 29 illustrates at least a portion of a graphics processor according to at least one embodiment;

[0043] Figure 30 illustrates at least a portion of a graphics processor according to at least one embodiment;

[0044] Figure 31 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment;

[0045] Figure 32 is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0046] Figure 33A and Figure 33B Thread execution logic including an array of processing elements of a graphics processor core is shown in accordance with at least one embodiment;

[0047] Figure 34 illustrates a parallel processing unit ("PPU") in accordance with at least one embodiment;

[0048] Figure 35 illustrates a general processing cluster ("GPC") in accordance with at least one embodiment;

[0049] Figure 36 illustrates a memory partitioning unit of a parallel processing unit ("PPU") according to at least one embodiment;

[0050] Figure 37 A streaming multiprocessor is shown in accordance with at least one embodiment;

[0051] Figure 38 is an example data flow diagram of a high-level computing pipeline according to at least one embodiment;

[0052] Figure 39 is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline in accordance with at least one embodiment;

[0053] Figure 40 includes an example diagram of a high-level computational pipeline 3910A for processing imaging data in accordance with at least one embodiment;

[0054] Figure 41A including an example data flow diagram of a virtual instrument supporting an ultrasound device according to at least one embodiment;

[0055] Figure 41B An example data flow diagram including a virtual instrument supporting a CT scanner according to at least one embodiment;

[0056] Figure 42A A data flow diagram illustrating a process for training a machine learning model according to at least one embodiment;

[0057] Figure 42B is an example illustration of a client-server architecture for enhancing an annotation tool using a pre-trained annotation model in accordance with at least one embodiment; and

[0058] Figure 43 Components of a system for accessing a large language model are shown in accordance with at least one embodiment. DETAILED DESCRIPTION

[0059] In the following description, numerous specific details are set forth to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one skilled in the art that the inventive concept may be practiced without one or more of these specific details.

[0060] In at least one embodiment, a neural network is trained using one or more operations and techniques described herein. In at least one embodiment, a neural network is trained in parallel using a distributed system having multiple processors on a multi-processor system. In at least one embodiment, input data to the neural network is partitioned and distributed to multiple processors, thereby enabling the processors to perform one or more operations using the partitioned input data to train the neural network in parallel. In at least one embodiment, activations of the partitioned input data are also partitioned and distributed to multiple processors based at least in part on partitioning the input data. In at least one embodiment, communications between processors are performed concurrently, such as causing a first processor to perform a first computation on a first partition of the input data and concurrently indicating, sending, or otherwise providing a result of the first computation to a second processor while the first processor is performing a second computation. In at least one embodiment, a processor comprising one or more circuits is used to cause reasoning about two or more connected portions of information to be distributed only between two or more corresponding processing cores, or otherwise performed in a manner consistent with Figures 1 to 8 Related operations described below.

[0061] Figure 1is a block diagram 100 illustrating a computer system for training a neural network using partitioned training data and activations according to at least one embodiment. In at least one embodiment, a processor 122 of a client computing system 108 includes one or more circuits for training a neural network 110. In at least one embodiment, the processor 122 of the client computing system 108 includes one or more circuits for partitioning neural network training data and activations using one or more operations such as those described herein. In at least one embodiment, the client computing system 108 includes one or more client devices such as those described herein. Figure 1 In at least one embodiment not shown in the drawings, the client computing system 108 includes one or more devices that are clients of a cloud computing environment such as those described herein. In at least one embodiment, the processor 122 is a processor such as those described below. In at least one embodiment, the processor 122 is a central processing unit (CPU), a graphics processing unit (GPU), a parallel processing unit (PPU), a general purpose graphics processing unit (GPGPU), a computing cluster, and / or a combination of these and / or other such processors. In at least one embodiment, the processor 122 is part of a computer system such as those described herein.

[0062] In at least one embodiment, one or more circuits of processor 122 are configured to perform one or more operations to train neural network 110. In at least one embodiment, one or more circuits of processor 122 are configured to use a method such as at least one of the methods described herein. Figure 10 The systems and methods described above perform one or more operations to train the neural network 110. Figure 1 In at least one embodiment not shown in FIG, one or more circuits of processor 122 are configured to perform one or more operations to train neural network 110 by causing execution of one or more application programming interfaces (APIs).

[0063] In at least one embodiment, the neural network trained using training neural network 110 is a neural network such as that described herein at least in conjunction with Figures 9A to 43 In at least one embodiment, the neural network trained using training neural network 110 is a portion of a neural network such as those described herein. In at least one embodiment, the neural network trained using training neural network 110 is a large language model such as large language model 4312, which is described herein at least in conjunction with Figure 43 In at least one embodiment, the neural network trained using training neural network 110 is a diffusion model (e.g., an image generation model that uses one or more neural networks to generate images based on an understanding of the underlying structure of a dataset, such as an image dataset).

[0064] In at least one embodiment, one or more operations for training neural network 110 are directed, sent, or otherwise provided to computing system 102. Figure 1 In at least one embodiment not shown in FIG, one or more operations for training neural network 110 are instructed, sent, or otherwise provided to computing system 102 using one or more APIs.

[0065] In at least one embodiment, computing system 102 is a high performance computing system. In at least one embodiment, computing system 102 is a distributed computing system. In at least one embodiment, computing system 102 is a deep learning computing system. In at least one embodiment, the operations of training neural network 110 are performed by computing system 102 using the systems, methods, operations, and / or techniques described herein. In at least one embodiment, computing system 102 is a cloud computing environment such as those described herein. In at least one embodiment, computing system 102 includes one or more processors 104. In at least one embodiment, Figure 1 ), computing system 102 includes one or more graphics processors. In at least one embodiment, processor 104 includes one or more processors such as those described herein. In at least one embodiment, the graphics processor of computing system 102 includes one or more graphics processors such as those described herein. In at least one embodiment, processor 104 of computing system 102 includes one or more central processing units (CPUs), graphics processing units (GPUs), parallel processing units (PPUs), general purpose graphics processing units (GPGPUs), computing clusters, and / or combinations of these and / or other such processors as described herein. In at least one embodiment ( Figure 1 ), one or more processors 104 of computing system 102 include multiple processors such as those described herein (eg, processor 104A includes multiple processors, processor 104B includes multiple processors, etc.).

[0066] In at least one embodiment ( Figure 1 ), one or more processors of processor 104 are connected together using systems and methods such as those described herein. For example, in at least one embodiment, at least some of processors 104 are implemented as processors such as those described herein. Figure 20B One or more computing clusters (or GPU clusters) of those described above are connected together.

[0067] In at least one embodiment, one or more circuits of processor 122 are configured to perform one or more operations for partitioning training data 112. In at least one embodiment, training data 106 is directed, sent, or otherwise provided to processor 122 of client computing system 108. In at least one embodiment, training data 106 includes data such as documents, images, videos, and / or other such data that can be used by processor 122 to train neural network 110, as described herein. In at least one embodiment, training data 106 is data used by training framework 1004 to generate training dataset 1002 for trained neural network 1008, as described herein. Figure 10 Related description.

[0068] In at least one embodiment, the one or more operations for partitioning the training data 112 include one or more operations for generating one or more subsets of the training data 106. For example, in at least one embodiment, if the training data 106 includes documents, the one or more operations for partitioning the training data 112 generate training data subsets, where each training data subset includes one or more pages of the documents. For example, in at least one embodiment, if the training data 106 includes documents, the one or more operations for partitioning the training data 112 generate training data subsets, where each subset of the training data includes one or more portions of a page of the document (e.g., half a page, a paragraph, a sentence, a word, etc.). For example, in at least one embodiment, if the training data 106 includes a plurality of images (e.g., a collection of images and / or a video stream of images), the one or more operations for partitioning the training data 112 generate training data subsets, where each subset of the training data includes one or more images. For example, in at least one embodiment, if the training data 106 includes one or more images, the one or more operations for partitioning the training data 112 generate subsets of training data, where each subset of the training data includes one or more portions of an image (e.g., portions of an image, sets of pixels, etc.).

[0069] In at least one embodiment, the one or more operations for partitioning the training data 112 generate one or more training data subsets and corresponding activations (e.g., activations of a neural network layer associated with the one or more training data subsets. In at least one embodiment, the one or more operations for partitioning the training data 112 generate one or more training data subsets and activations, such as training data subsets and activations 114, training data subsets and activations 116, training data subsets and activations 118, and / or training data subsets and activations 120. In at least one embodiment, training data subsets and activations 114 include a training data subset and one or more activations corresponding to the training data subset. In at least one embodiment, training data subsets and activations 116 include a training data subset and one or more activations corresponding to the training data subset. In at least one embodiment, training data subsets and activations 118 include a training data subset and one or more activations corresponding to the training data subset. In at least one embodiment, training data subsets and activations 120 include a training data subset and one or more activations corresponding to the training data subset.

[0070] In at least one embodiment, training data subset and activations 114 are indicated, sent, or otherwise provided to computing system 102 by processor 122. In at least one embodiment, one or more processors 104 of computing system 102 use training data subset and activations 114 to train neural network 110, as described herein. In at least one embodiment, training data subset and activations 116 are indicated, sent, or otherwise provided to computing system 102 by processor 122. In at least one embodiment, one or more processors 104 of computing system 102 use training data subset and activations 116 to train neural network 110, as described herein. In at least one embodiment, training data subset and activations 118 are indicated, sent, or otherwise provided to computing system 102 by processor 122. In at least one embodiment, one or more processors 104 of computing system 102 use training data subset and activations 118 to train neural network 110, as described herein. In at least one embodiment, training data subset and activations 120 are indicated, sent, or otherwise provided to computing system 102 by processor 122. In at least one embodiment, one or more processors 104 of computing system 102 train neural network 110 using the training data subset and activations 120 as described herein.

[0071] In at least one embodiment, processor 104A trains neural network 110 using a portion of training data subset and activations 114 and a portion of training data subset and activations 116. In at least one embodiment, processor 104B trains neural network 110 using a portion of training data subset and activations 114 and a portion of training data subset and activations 116. In at least one embodiment, the portion of training data subset and activations 114 that processor 104A uses to train neural network 110 includes at least a portion of training data 106 that is not included in the portion of training data subset and activations 114 that processor 104B uses to train neural network 110. In at least one embodiment, the portion of training data subset and activations 116 that processor 104A uses to train neural network 110 includes at least a portion of training data 106 that is not included in the portion of training data subset and activations 116 that processor 104B uses to train neural network 110.

[0072] In at least one embodiment, a first portion of the training data subset and activations 114 used by processor 104A to train neural network 110 is contiguous with a second portion of the training data subset and activations 114 used by processor 104B to train neural network 110 (e.g., the first portion and the second portion occupy contiguous physical or virtual spaces in the computer system memory of client computing system 108). In at least one embodiment, a first portion of the training data subset and activations 116 used by processor 104A to train neural network 110 is contiguous with a second portion of the training data subset and activations 116 used by processor 104B to train neural network 110 (e.g., the first portion and the second portion occupy contiguous physical or virtual spaces in the computer system memory of client computing system 108).

[0073] In at least one embodiment (not in Figure 1), one or more processors 104 include two or more processing cores. In at least one embodiment, a processor, such as one or more processors 104 including two or more processors, includes one or more circuits configured to distribute inference of two or more connected portions of information only between the two or more respective processing cores, such that a first of the two or more connected portions of information is distributed to a first processing core of the two or more respective processing cores, and a second of the two or more connected portions of information is distributed to a second processing core of the two or more respective processing cores. In at least one embodiment, one or more circuits of a processor in processor 104 (e.g., processor 104A) configure to distribute inference of a first portion of training data subsets and activations (e.g., training data subsets and activations 114) connected to a second portion of training data subsets and activations (e.g., training data subsets and activations 114) only between the two or more respective processing cores of the processor in processor 104. In at least one embodiment, one or more circuits of the processor in the processor 104 are configured to distribute inference of a first portion of training data subsets and activations (e.g., training data subsets and activations 116) connected to a second portion of training data subsets and activations (e.g., training data subsets and activations 116) only among the two or more respective processing cores of the processor in the processor 104.

[0074] In at least one embodiment, a first portion of the training data subset and activations 114 used by processor 104A to train neural network 110 is not contiguous with a second portion of the training data subset and activations 114 used by processor 104B to train neural network 110 (e.g., the first portion and the second portion do not occupy contiguous physical or virtual space in computer system memory of client computing system 108). In at least one embodiment, a first portion of the training data subset and activations 114 used by processor 104A to train neural network 110 is not contiguous with a second portion of the training data subset and activations 114 used by processor 104B to train neural network 110, and one or more portions between the first portion and the second portion (e.g., portions in physical or virtual memory between the first portion and the second portion) are not used to train neural network 110.

[0075] In at least one embodiment, a first portion of the training data subset and activations 116 used by processor 104A to train neural network 110 is not contiguous with a second portion of the training data subset and activations 116 used by processor 104B to train neural network 110 (e.g., the first portion and the second portion do not occupy contiguous physical or virtual space in computer system memory of client computing system 108). In at least one embodiment, where a first portion of the training data subset and activations 116 used by processor 104A to train neural network 110 is not contiguous with a second portion of the training data subset and activations 116 used by processor 104B to train neural network 110, one or more portions between the first portion and the second portion (e.g., portions in physical or virtual memory between the first portion and the second portion) are not used to train neural network 110.

[0076] In at least one embodiment, processor 104C trains neural network 110 using portion 118 of training data subset and activations and portion 120 of training data subset and activations. In at least one embodiment, processor 104D trains neural network 110 using portion 118 of training data subset and activations and portion 120 of training data subset and activations. In at least one embodiment, the portion of training data subset and activations 118 that processor 104C uses to train neural network 110 includes at least a portion of training data 106 that is not included in the portion of training data subset and activations 118 that processor 104D uses to train neural network 110. In at least one embodiment, the portion of training data subset and activations 120 that processor 104C uses to train neural network 110 includes at least a portion of training data 106 that is not included in the portion of training data subset and activations 120 that processor 104D uses to train neural network 110.

[0077] In at least one embodiment, a first portion of the training data subset and activations 118 used by processor 104C for training neural network 110 is coupled to a second portion of the training data subset and activations 118 used by processor 104D for training neural network 110 (e.g., the first portion and the second portion occupy coupled physical or virtual space in a computer system memory of client computing system 108). In at least one embodiment, a first portion of the training data subset and activations 120 used by processor 104C for training neural network 110 is coupled to a second portion of the training data subset and activations 120 used by processor 104D for training neural network 110 (e.g., the first portion and the second portion occupy coupled physical or virtual space in a computer system memory of client computing system 108).

[0078] In at least one embodiment, a first portion of the training data subset and activations 118 used by processor 104C to train neural network 110 is not contiguous with a second portion of the training data subset and activations 118 used by processor 104D to train neural network 110 (e.g., the first portion and the second portion do not occupy contiguous physical or virtual space in computer system memory of client computing system 108). In at least one embodiment, where the first portion of the training data subset and activations 118 used by processor 104C to train neural network 110 is not contiguous with the second portion of the training data subset and activations 118 used by processor 104D to train neural network 110, one or more portions between the first portion and the second portion (e.g., portions in physical or virtual memory between the first portion and the second portion) are not used to train neural network 110.

[0079] In at least one embodiment, a first portion of the training data subset and activations 120 used by processor 104C for training neural network 110 is not contiguous with a second portion of the training data subset and activations 120 used by processor 104D for training neural network 110 (e.g., the first portion and the second portion do not occupy contiguous physical or virtual space in computer system memory of client computing system 108). In at least one embodiment, a first portion of the training data subset and activations 120 used by processor 104C for training neural network 110 is not contiguous with a second portion of the training data subset and activations 120 used by processor 104D for training neural network 110, and one or more portions between the first portion and the second portion (e.g., portions in physical or virtual memory between the first portion and the second portion) are not used to train neural network 110.

[0080] In at least one embodiment, processor 104A has training data 106 including a portion of training data subsets and activations 114 and a portion of training data subsets and activations 116. In at least one embodiment, processor 104B has training data 106 including a portion of training data subsets and activations 114 and a portion of training data subsets and activations 116. In at least one embodiment, processor 104A and processor 104B communicate 124 intermediate results (e.g., forward propagation, backpropagation, etc.) of performing neural network training to train neural network 110, as described herein.

[0081] In at least one embodiment, processor 104A transmits 124 one or more intermediate results of training, such as those described herein, to processor 104B using systems and methods such as those described herein. In at least one embodiment, processor 104A transmits 124 one or more intermediate results of reasoning, such as those described herein, to processor 104B using systems and methods such as those described herein. In at least one embodiment, processor 104B transmits 124 one or more intermediate results of training, such as those described herein, to processor 104A using systems and methods such as those described herein. In at least one embodiment, processor 104B transmits 124 one or more intermediate results of reasoning, such as those described herein, to processor 104A using systems and methods such as those described herein. In at least one embodiment, processor 104B transmits 124 one or more intermediate results of reasoning, such as those described herein, to processor 104A using systems and methods such as those described herein. Figure 1 ), processor 104A and / or processor 104B transmits 124 one or more intermediate results of training and / or inference to one or more other processors of computing system 102 .

[0082] In at least one embodiment, processor 104C has training data 106 including a portion of training data subsets and activations 118 and a portion of training data subsets and activations 120. In at least one embodiment, processor 104D has training data 106 including a portion of training data subsets and activations 118 and a portion of training data subsets and activations 120. In at least one embodiment, processor 104C and processor 104D communicate 126 intermediate results (e.g., forward propagation, backpropagation, etc.) of performing neural network training to train neural network 110, as described herein.

[0083] In at least one embodiment, processor 104C communicates 126 one or more intermediate results of training, such as those described herein, to processor 104D using systems and methods such as those described herein. In at least one embodiment, processor 104C communicates 126 one or more intermediate results of reasoning, such as those described herein, to processor 104D using systems and methods such as those described herein. In at least one embodiment, processor 104D communicates 126 one or more intermediate results of training, such as those described herein, to processor 104C using systems and methods such as those described herein. In at least one embodiment, processor 104D communicates 126 one or more intermediate results of reasoning, such as those described herein, to processor 104C using systems and methods such as those described herein. In at least one embodiment, processor 104D communicates 126 one or more intermediate results of reasoning, such as those described herein, to processor 104C using systems and methods such as those described herein. Figure 1 ), processor 104C and / or processor 104D transmits 126 one or more intermediate results of training and / or inference to one or more other processors of computing system 102 .

[0084] In at least one embodiment, one or more layers of a neural network, such as those described herein, compute outputs. In at least one embodiment, the outputs are stored in locations addressable by one or more processors, such as processor 104. In at least one embodiment, the outputs are provided to the one or more processors, which use the outputs to compute outputs using one or more layers (e.g., the next layer, the previous layer, or the same layer) of the neural network. In at least one embodiment, partitioning the training data and activations (e.g., as described herein) reduces the demand on the processors to provide data to the processors by executing a portion of the neural network on the processors. In at least one embodiment, partitioning the training data and activations (e.g., as described herein) reduces bottlenecks that may occur when some processors have activations (e.g., outputs from a layer) that are more important than other processors and the other processors need the more important activations. In at least one embodiment, the bottlenecks can cause memory issues when a processor needs to recompute activations that are not stored on it. In at least one embodiment, large training data sequences have a large number of activations that cannot all be stored on a single processor. In at least one embodiment, the processor may receive repeated requests (e.g., from other processors) to provide activations that are not stored on it, requiring frequent recomputation.

[0085] In at least one embodiment, one or more processors (e.g., processor 122, one or more of processors 104, and / or other processors such as those described herein) include one or more circuits for performing the operations or instructions described herein, such as one or more circuits for distributing reasoning about two or more connected portions of information only between two or more corresponding processing cores. In at least one embodiment, one or more processors include one or more circuits for distributing reasoning about two or more connected portions of information only between two or more corresponding processing cores to train a neural network such as those described herein. In at least one embodiment, one or more processors include one or more circuits for distributing reasoning about two or more connected portions of information only between two or more corresponding processing cores to execute a neural network such as those described herein. In at least one embodiment, one or more processors include one or more circuits for distributing reasoning about two or more connected portions of information only between two or more corresponding processing cores to train and / or execute a large language model (LLM) such as those described herein. In at least one embodiment, one or more processors include one or more circuits for distributing inference on two or more connected portions of information only between two or more respective processing cores to train and / or execute diffusion models such as those described herein. In at least one embodiment, one or more processors include one or more circuits for performing operations or instructions such as those described herein, such as one or more circuits for causing two or more other processors to each perform one or more operations of one or more neural networks based at least in part on two or more non-connected portions of an input sequence. In at least one embodiment, one or more processors include one or more circuits for performing operations or instructions such as those described herein, such as one or more circuits for causing inference on two or more connected portions of information only between two or more respective processing cores to cause two or more other processors to each perform one or more operations of one or more neural networks based at least in part on two or more non-connected portions of an input sequence. In at least one embodiment ( Figure 1 ), a non-transitory machine-readable medium storing thereon a set of instructions that, if executed by one or more processors, will perform at least the Figures 1 to 8 Related described operations, such as causing reasoning about two or more connected portions of information to be distributed only between two or more corresponding processing cores.

[0086] Figure 2is a block diagram 200 illustrating a computer system in which data and activations are partitioned according to a partitioning criterion in accordance with at least one embodiment. In at least one embodiment, a processor 222 of a computing system 208 executes instructions to partition training data 212 as described herein. In at least one embodiment, processor 222 is a processor as described herein at least in conjunction with Figure 1 In at least one embodiment, the computing system 208 is a processor such as the processor 122 described in conjunction with the present invention. Figure 1 In at least one embodiment, the one or more instructions for partitioning the training data 212 include at least one of the instructions described herein. Figure 1 Instructions such as instructions for partitioning the training data 112 are described in conjunction.

[0087] In at least one embodiment, the instructions executed by processor 222 for partitioning training data 212 generate subsets of training data from training data 206, as described herein. In at least one embodiment, training data 206 is at least as described herein. Figure 1 In conjunction with the training data described above, such as training data 106. In at least one embodiment, the instructions for partitioning the training data 212 executed by the processor 222 generate training data subsets 216A through 216N (e.g., for a total of "N" training data subsets). For example, in at least one embodiment, if the training data 206 includes ten pages of documents, the instructions for partitioning the training data 212 executed by the processor 222 generate ten training data subsets (e.g., "N" equals 10), each of which includes one page. For example, in at least one embodiment, if the training data 206 includes ten pages of documents, the instructions for partitioning the training data 212 executed by the processor 222 generate twenty training data subsets (e.g., "N" equals 20), each of which includes half of a page. For example, in at least one embodiment, if training data 206 includes a ten-page document, the instructions for partitioning training data 212 executed by processor 222 generate five training data subsets (e.g., "N" equals 5), each of which includes two pages. In at least one embodiment, other values ​​of "N" (e.g., other values ​​for several training data subsets) can be generated by the instructions for partitioning training data 212 executed by processor 222.

[0088] In at least one embodiment, the instructions for partitioning the training data 212 executed by the processor 222 generate one or more activations based at least in part on the training data subsets 216A through 216N. In at least one embodiment, the instructions for partitioning the training data 212 executed by the processor 222 generate one activation corresponding to each training data subset (e.g., training data subsets 216A through 216N). For example, in at least one embodiment, the instructions for partitioning the training data 212 executed by the processor 222 generate activations 218A (e.g., comprising a single activation) corresponding to the training data subset 216A, activations 218N (e.g., comprising a single activation) corresponding to the training data subset 216N, and activations 218A (e.g., comprising a single activation) corresponding to the training data subset 216N, and activations 218N (e.g., comprising a single activation) corresponding to each other training data subset ( Figure 2 Not shown) corresponding to the activation ( Figure 2 (not shown in the figure).

[0089] In at least one embodiment ( Figure 2 216N), the instructions for partitioning the training data 212 executed by the processor 222 generate a plurality of activations corresponding to each training data subset (e.g., training data subset 216A through training data subset 216N). For example, in at least one embodiment, the instructions for partitioning the training data 212 executed by the processor 222 generate a plurality of activations 218A corresponding to the training data subset 216A, a plurality of activations 218N corresponding to the training data subset 216N, and a plurality of activations 218A corresponding to the training data subset 216N, and a plurality of activations 218N corresponding to the other training data subsets ( Figure 2 ) corresponding to multiple activations ( Figure 2 ). In at least one embodiment, the instructions executed by processor 222 to partition training data 212 generate both a single activation and multiple activations for the training data set.

[0090] In at least one embodiment, instructions executed by processor 222 to partition training data 212 are executed based at least in part on processor resources 214. In at least one embodiment, processor resources 214 are indicative of resources of processor 204 of high performance computing system 202. In at least one embodiment, processor 204 is at least as described herein. Figure 1 In at least one embodiment, the high performance computing system 202 is a processor such as the processor 104 described in conjunction with the present invention. Figure 1 A high performance computing system such as computing system 102 is described in conjunction with.

[0091] In at least one embodiment, processor resources 214 include an indication of resources of high-performance computing system 202 for training a neural network using partitioned training data and activations 210. In at least one embodiment, processor 222 uses the information indicated by processor resources 214 to determine how to partition training data 212 to generate training data subsets (e.g., training data subset 216A through training data subset 216N) and to determine activations (e.g., activations 218A through 218N). In at least one embodiment, processor resources 214 include an indication of the number of processors 204 available for training a neural network using partitioned training data and activations 210. In at least one embodiment, processor resources 214 include an indication of one or more specifications of processors 204 available for training a neural network using partitioned training data and activations 210 (e.g., the type of processor, the memory capacity of the processor, other processes executed on the processor, etc.). In at least one embodiment, processor resources 214 include an indication of the memory bandwidth between processors available for training a neural network using partitioned training data and activations 210. In at least one embodiment, processor resources 214 include an indication of one or more architectures of high performance computing system 202 (e.g., an indication of relationships between processors 204 of high performance computing system 202) that can be used to train a neural network using partitioned training data and activations 210. In at least one embodiment, at least a portion of processor resources 214 is stored in high performance computing system 202. In at least one embodiment, Figure 2 ), at least a portion of processor resources 214 are stored in computing system 208. In at least one embodiment, processor resources 214 are directed, sent, or otherwise provided to processor 222 using one or more application programming interfaces (APIs) such as those described herein.

[0092] In at least one embodiment, the instructions executed by processor 222 for partitioning training data 212 are executed based at least in part on partitioning criteria 220. In at least one embodiment, partitioning criteria 220 includes an indication of a number of partitions of training data 206 for training a neural network using the partitioned training data and activations 210. In at least one embodiment, partitioning criteria 220 includes an indication of a size of partitions of training data 206 for training a neural network using the partitioned training data and activations 210. In at least one embodiment, the indication in partitioning criteria 220 is based at least in part on one or more characteristics of training data 206 (e.g., size of the data, type of the data, location of the data, etc.). In at least one embodiment, partitioning criteria 220 is indicated, sent, or otherwise provided to processor 222 using one or more application programming interfaces (APIs) such as those described herein.

[0093] In at least one embodiment, processor 222 uses the training data subsets (e.g., training data subsets 216A through 216N) and activations (e.g., activations 218A through 218N) to cause processor 204 of high-performance computing system 202 to train a neural network using partitioned training data and activations 210, as described herein. In at least one embodiment, processor 222 uses the training data subsets (e.g., training data subsets 216A through 216N) and activations (e.g., activations 218A through 218N) to cause processor 204 of high-performance computing system 202 to train a neural network using partitioned training data and activations 210, such that inference of two or more connected portions of information is distributed only between two or more corresponding processing cores and / or otherwise to perform other operations such as those described herein.

[0094] Figure 3 is a block diagram 300 illustrating a process for partitioning neural network training data and activations according to at least one embodiment. In at least one embodiment, one or more of processors 122 and / or processor 104 (as described herein at least in conjunction with Figure 1 A processor (described in connection with the present invention) performs one or more steps in the process for partitioning neural network training data and activations shown in block diagram 300 (or any other process described herein, or variations and / or combinations thereof). In at least one embodiment, some or all of the process for partitioning neural network training data and activations shown in block diagram 300 (or any other process described herein, or variations and / or combinations thereof) is performed on a processor such as a computer system. Figures 9A to 43 The computer program is executed under the control of one or more computer systems described in the , one or more computer systems are configured by computer executable instructions and implemented as code (e.g., computer executable instructions, one or more computer programs, or one or more application programs) that is jointly executed on one or more processors through hardware, software, or a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program that includes multiple computer-readable instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium.

[0095] In at least one embodiment, at step 302 of the process for partitioning neural network training data and activations shown in block diagram 300, the processor executes instructions for receiving training data. In at least one embodiment, in step 302, the received training data is training data such as training data 106, which is at least related to Figure 1In at least one embodiment, in step 302, the received training data is received by a processor such as processor 122, and this document is at least related to Figure 1 In at least one embodiment, in step 302, the received training data is directed, sent, or otherwise provided using one or more operations such as those described herein. In at least one embodiment, after step 302, the process for partitioning the neural network training data and activations shown in block diagram 300 continues in step 304.

[0096] In at least one embodiment, at step 304 of the process for partitioning neural network training data and activations shown in block diagram 300, the processor executes instructions for receiving processor resources. In at least one embodiment, in step 304, the received processor resources are processor resources such as processor resources 214, which are described herein at least in conjunction with Figure 2 In at least one embodiment, in step 304, the received processor resources are received by a processor such as processor 122, and this document is at least related to Figure 1 In at least one embodiment, in step 304, a processor resource is indicated, sent, or otherwise provided by a high performance computing system such as computing system 102, as described herein at least with reference to Figure 1 In at least one embodiment, after step 304 , the process for partitioning neural network training data and activations shown in block diagram 300 is continued in step 306 .

[0097] In at least one embodiment, at step 306 of the process for partitioning neural network training data and activations shown in block diagram 300, the processor executes instructions for receiving a partitioning criterion. In at least one embodiment, the partitioning criterion received at step 306 is a partitioning criterion such as partitioning criterion 220, which is described herein at least in conjunction with Figure 2 In at least one embodiment, at step 306, the received partition criteria is received by a processor such as processor 122, and at least one embodiment of the present invention is described in detail in detail in the following manner. Figure 1 In at least one embodiment, at step 306, the received partitioning criteria are indicated, sent, or otherwise provided using one or more operations such as those described herein. In at least one embodiment, after step 306, the process for partitioning neural network training data and activations shown in block diagram 300 continues at step 308.

[0098] In at least one embodiment, at step 308 of the process for partitioning neural network training data and activations shown in block diagram 300, the processor executes instructions for determining a data subset size. In at least one embodiment, at step 308, the data subset size is the size of the training data subset (e.g., training data subsets 216A through 216N, as described herein at least in relation to the training data subsets 216A through 216N). Figure 2 In at least one embodiment, at step 308, the data subset size is determined based at least in part on the training data received in step 302, as described herein. In at least one embodiment, at step 308, the data subset size is determined based at least in part on the processor resources received in step 304, as described herein. In at least one embodiment, at step 308, the data subset size is determined based at least in part on the partitioning criteria received in step 306, as described herein. In at least one embodiment, after step 308, the process for partitioning neural network training data and activations continues at step 310 as shown in block diagram 300.

[0099] In at least one embodiment, at step 310 of the process for partitioning neural network training data and activations shown in block diagram 300, a processor executes instructions for selecting a first partition. In at least one embodiment, at step 310, a partition is selected from the training data received in step 302. In at least one embodiment, at step 310, the partition is selected based at least in part on the data subset size determined in step 308. In at least one embodiment, the first partition is selected from the training data received in step 302 based on a starting position or a starting location of the training data received in step 302. In at least one embodiment, the next partition is selected from the training data received in step 302 based on a location of a previously selected partition from the training data received in step 302. In at least one embodiment, a partition is randomly selected from the training data received in step 302. In at least one embodiment, a partition is selected from the training data received in step 302 based on one or more other criteria (e.g., criteria specified in the partitioning criteria received in step 306). In at least one embodiment, after step 310, the process for partitioning neural network training data and activations shown in block diagram 300 continues in step 312.

[0100] In at least one embodiment, at step 312 of the process for partitioning neural network training data and activations shown in block diagram 300, the processor executes instructions for partitioning the training data to generate training data subsets, as described herein. In at least one embodiment, at step 312, the instructions for partitioning the training data to generate training data subsets are based at least in part on the data subset size determined at step 308. In at least one embodiment, after step 302, the process for partitioning neural network training data and activations shown in block diagram 300 continues at step 314.

[0101] In at least one embodiment, at step 314 of the process for partitioning neural network training data and activations shown in block diagram 300, the processor executes instructions for determining one or more activations for a subset of the training data, as described herein at least in connection with Figure 1 In at least one embodiment, at step 314, the instructions for determining one or more activations for the subset of training data include instructions for determining one or more activations for the subset of training data partitioned at step 312. In at least one embodiment, after step 314, the process for partitioning neural network training data and activations shown in block diagram 300 continues at step 316.

[0102] In at least one embodiment, at step 316 of the process for partitioning neural network training data and activations shown in block diagram 300, the processor executes instructions for determining whether to select a next partition. In at least one embodiment, at step 316, the determination of whether to select a next partition is based at least in part on the training data received from step 302, the processor resources received from step 304, and / or the partitioning criteria received from step 306, as described herein. In at least one embodiment, the determination of whether to select a next partition is based at least in part on the data subset size determined in step 308. In at least one embodiment, the determination of whether to select a next partition is based at least in part on one or more previously selected partitions (e.g., at step 310) at step 316. In at least one embodiment, if it is determined at step 316 that a next partition is to be selected ("YES" branch), the process for partitioning neural network training data and activations shown in block diagram 300 continues at step 310 to select the next partition. In at least one embodiment, if, at step 316 , it is determined not to select a next partition (“NO” branch), the process for partitioning neural network training data and activations shown in block diagram 300 continues at step 318 .

[0103] In at least one embodiment, at step 318 of the process for partitioning neural network training data and activations shown in block diagram 300, the processor executes instructions for training the neural network using the partitioned training data and activations. In at least one embodiment, at step 318, the instructions for training the neural network using the partitioned training data and activations include instructions such as instructions for training the neural network using the partitioned training data and activations 210, which are described herein at least in conjunction with Figure 2 In at least one embodiment, after step 318, the process for partitioning neural network training data and activations shown in block diagram 300 is terminated. In at least one embodiment ( Figure 3 (not shown), after step 318, the process for partitioning neural network training data and activations shown in block diagram 300 continues at step 302 to receive new training data. In at least one embodiment ( Figure 3 (not shown), after step 318, the process for partitioning the neural network training data and activations shown in block diagram 300 continues in step 304 to receive new processor resources. In at least one embodiment ( Figure 3 (not shown), after step 318, the process for partitioning neural network training data and activations shown in block diagram 300 continues at step 306 to receive a new partitioning criterion. In at least one embodiment ( Figure 3 ), after step 318, the process for partitioning the neural network training data and activations shown in block diagram 300 continues at step 308 to determine a new data subset size.

[0104] In at least one embodiment, different from Figure 3 The operations of the process for partitioning neural network training data and activations shown in block diagram 300 are performed in the order shown. In at least one embodiment, the operations of the process for partitioning neural network training data and activations shown in block diagram 300 are performed simultaneously or in parallel. In at least one embodiment, the operations of the process for partitioning neural network training data and activations shown in block diagram 300 that are not dependent on each other (e.g., independent of order) are performed simultaneously or in parallel. In at least one embodiment, the operations of the process for partitioning neural network training data and activations shown in block diagram 300 are performed by multiple threads executing on a processor such as those described herein.

[0105] Figure 4is a block diagram 400 illustrating forward and backward propagation in a neural network according to at least one embodiment. In at least one embodiment, forward propagation 402 is used to calculate output values ​​414 of the neural network. In at least one embodiment, forward propagation 402 is the process of feeding input data (e.g., from input layer 404) through one or more layers (e.g., hidden layer 406) of the neural network to produce an output (e.g., output layer 408). In at least one embodiment, a processor such as those described herein includes code and / or data storage (e.g., code and / or data storage 905, which is at least partially described herein). Figure 9A and Figure 9B 915) to store forward and / or output weights and / or input / output data, and / or other parameters to configure the neurons or layers of the neural network trained and / or used when performing inference in aspects of one or more embodiments. In at least one embodiment, logic 915 includes and / or is coupled to code and / or data storage 905 to store graphics code or other software to control the timing and / or sequence in which weights and / or other parameter information will be loaded to configure logic 915, at least in accordance with the present invention. Figure 9A and Figure 9B (described in detail below). In at least one embodiment, code (e.g., graphics code) loads weights or other parameter information into a processor based on the architecture of the neural network to which such code corresponds. In at least one embodiment, code and / or data storage 905 stores weight parameters and / or input / output data layers of a neural network trained or used in conjunction with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments.

[0106] In at least one embodiment, forward propagation 402 is performed by one or more processors, such as processor 104, as described herein at least in conjunction with Figure 1 In at least one embodiment, forward propagation 402 is a step in training a neural network (e.g., training neural network 110, which is at least related to Figure 1 In at least one embodiment, computing output values ​​414 of a neural network is applying biases and weights to nodes (or neurons) of the neural network and applying one or more activations (or activation functions) to generate one or more output values, as described herein.

[0107] In at least one embodiment, forward propagation 402 is performed using one or more neural network layers such as those described herein. In at least one embodiment, the neural network layers are an input layer such as input layer 404, a hidden layer such as one of hidden layers 406, and / or an output layer such as output layer 408. Figure 4), the neural network layer is a combination of these and / or other such neural network layers.

[0108] In at least one embodiment, the neural network layer used to perform forward propagation 402 includes an input layer 404. In at least one embodiment, the input layer 404 is the neural network layer that includes input data to the neural network. Figure 4 ), the neural network layers for performing forward propagation 402 include multiple input layers such as input layer 404.

[0109] In at least one embodiment, the neural network layers used to perform the forward propagation 402 include one or more hidden layers 406. In at least one embodiment, the hidden layers 406 are inner layers of the neural network used to calculate the output values ​​414. Figure 4 ), hidden layer 406 is empty (e.g., does not include any activations, thresholds, weights, etc.). In at least one embodiment, data from input layer 404 is directed, sent, or otherwise provided to one or more layers of hidden layer 406, as described herein. In at least one embodiment, data from one or more layers of hidden layer 406 is directed, sent, or otherwise provided to one or more other layers of hidden layer 406, as described herein.

[0110] In at least one embodiment, the neural network layer used to perform forward propagation 402 includes an output layer 408. In at least one embodiment, the output layer 408 is a neural network layer that includes output data from the neural network. Figure 4 4 ), the neural network layers used to perform the forward propagation 402 include multiple output layers such as the output layer 408. In at least one embodiment, data from one or more layers of the hidden layer 406 is directed, sent, or otherwise provided to the output layer 408, as described herein.

[0111] In at least one embodiment, data from the output layer 408 is evaluated to determine the accuracy of one or more parameters and / or hyperparameters of the neural network. In at least one embodiment, the data from the output layer 408 is compared to one or more expected values ​​410. In at least one embodiment, the expected values ​​410 are values ​​that the neural network is expected to generate based at least in part on the input layer 404. For example, in at least one embodiment, if the neural network is trained to recognize dogs in images and an input image that includes one or more dogs is received, the expected values ​​410 include an indication that a dog is present in the input image.

[0112] In at least one embodiment, data from the output layer 408 and the expected values ​​410 are used to determine one or more loss values ​​412. In at least one embodiment, the loss value 412 is the difference between the value in the output layer 408 and the expected value 410. For example, in at least one embodiment, if a neural network is being trained to recognize dogs in images, an input image including one or more dogs is received, and the expected values ​​410 do not include an indication that a dog is present in the input image, then the loss value 412 includes an indication that a dog was not found but was expected to be found. In at least one embodiment, the loss value 412 is indicated, sent, or otherwise provided to a backpropagation 416 (also referred to herein as "backward propagation").

[0113] In at least one embodiment, backpropagation 416 (or backward propagation) is used to update the biases and weights 426 of the neural network. In at least one embodiment, backpropagation 416 (or backward propagation) is backpropagating the loss (e.g., loss value 412) through the neural network to determine how much of the loss each node (or neuron) is responsible for and updating the weights and biases of the neural network to minimize the loss. In at least one embodiment, a processor such as those described herein includes code and / or data storage (e.g., code and / or data storage 905, at least as described herein). Figure 9A and Figure 9B 915) to store backward and / or output weights and / or input / output data corresponding to neurons or layers of a neural network that is trained and / or used for reasoning in aspects of one or more embodiments such as those described herein. In at least one embodiment, logic 915 includes and / or is coupled to code and / or data storage 905 to store graphics code or other software to control the timing and / or sequence in which weights and / or other parameter information will be loaded to configure logic 915, as described herein at least in connection with Figure 9A and Figure 9B (described in connection therewith). In at least one embodiment, code (e.g., graphics code) loads weight or other parameter information into a processor based on the architecture of the neural network to which such code corresponds. In at least one embodiment, the code and / or data storage stores weight parameters and / or input / output data for layers of a neural network trained or used in conjunction with one or more embodiments during backpropagation of input / output data and / or weight parameters during training and / or inference using one or more embodiments.

[0114] In at least one embodiment, backpropagation 416 (or backward propagation) is performed by one or more processors, such as processor 104, as described herein at least in conjunction with Figure 1 In at least one embodiment, back propagation 416 is a step in training a neural network (e.g., training neural network 110, which is at least related to Figure 1 ). In at least one embodiment, updating the biases and weights 426 of the neural network is a process of adjusting the weights and biases of the neural network using backpropagation to minimize loss, as described herein. In at least one embodiment, loss value 418 is used to update the biases and weights 426 of the neural network. In at least one embodiment, loss value 418 is the same as loss value 412. In at least one embodiment, loss value 418 is a modified version of loss value 412 (e.g., loss value 418 is generated by applying one or more transformations to loss value 412).

[0115] In at least one embodiment, backpropagation 416 is performed using one or more layers of a neural network, such as those described herein. In at least one embodiment, backpropagation 416 uses loss value 418 to update one or more weights and biases of output layer 420, as described herein. In at least one embodiment, output layer 420 is the same as output layer 408 before backpropagation 416 updates one or more weights and biases of output layer 420 using loss value 418. In at least one embodiment, output layer 420 is modified (e.g., has changed weights and biases) after backpropagation 416 updates one or more weights and biases of output layer 420 using loss value 418. In at least one embodiment, output layer 420 is not modified (e.g., has unchanged weights and biases) after backpropagation 416 updates one or more weights and biases of output layer 420 using loss value 418.

[0116] In at least one embodiment, the updated weights and biases of the output layer 420 are indicated, sent, or otherwise provided to one or more hidden layers 422. In at least one embodiment, backpropagation 416 uses loss value 418 to update one or more weights and biases of the hidden layer 422, as described herein. In at least one embodiment, the hidden layer 422 is the same as the hidden layer 406 before backpropagation 416 uses loss value 418 to update the one or more weights and biases of the hidden layer 422. In at least one embodiment, the one or more hidden layers 422 are modified (e.g., have changed weights and biases) after backpropagation 416 uses loss value 418 to update the one or more weights and biases of the hidden layer 422. In at least one embodiment, the hidden layer 422 is not modified (e.g., has unchanged weights and biases) after backpropagation 416 uses loss value 418 to update the one or more weights and biases of the hidden layer 422.

[0117] In at least one embodiment, the updated weights and biases of hidden layer 422 are indicated, sent, or otherwise provided to input layer 424. In at least one embodiment, backpropagation 416 uses loss value 418 to update one or more weights and biases of input layer 424, as described herein. In at least one embodiment, input layer 424 is the same as input layer 404 before backpropagation 416 updates one or more weights and biases of input layer 424 using loss value 418. In at least one embodiment, input layer 424 is modified (e.g., has changed weights and biases) after backpropagation 416 updates one or more weights and biases of input layer 424 using loss value 418. In at least one embodiment, input layer 424 is not modified (e.g., has unchanged weights and biases) after backpropagation 416 updates one or more weights and biases of input layer 424 using loss value 418.

[0118] In at least one embodiment ( Figure 4 ), using systems, methods, techniques, and operations such as those described herein to train a neural network (e.g., train neural network 110, which is described herein at least with reference to Figure 1 ) includes multiple forward propagations such as forward propagation 402. In at least one embodiment ( Figure 4 ), using systems, methods, techniques, and operations such as those described herein to train a neural network (e.g., train neural network 110, which is described herein at least with reference to Figure 1 Related description) includes multiple backpropagations such as backpropagation 416.

[0119] Figure 5 is a block diagram 500 illustrating a first portion of a computing system in which partitioned neural network training data and activations are used to train a neural network in accordance with at least one embodiment. In at least one embodiment, processor 502A performs one or more operations to train a neural network using the partitioned neural network training data and activations, as described herein at least in connection with Figures 1 to 3 In at least one embodiment, processor 502A is a processor such as one or more processors 104 of a high performance computing system (such as computing system 102), both of which are at least Figure 1 In at least one embodiment ( Figure 5 ), processor 502A includes multiple processors that perform one or more operations to train a neural network using partitioned neural network training data and activations, at least in conjunction with Figures 1 to 3 In at least one embodiment, processor 502B performs one or more operations to train a neural network using the partitioned neural network training data and activations, which are described in at least Figures 1 to 3In at least one embodiment, processor 502B is a processor such as one or more processors 104 in a high performance computing system (such as computing system 102), both of which are at least Figure 1 In at least one embodiment ( Figure 5 ), processor 502B includes multiple processors that perform one or more operations to train a neural network using partitioned neural network training data and activations, at least in conjunction with Figures 1 to 3 In at least one embodiment, processor 502A and processor 502B together perform one or more operations to train a neural network using the partitioned neural network training data and activations, which are described in at least Figures 1 to 3 In at least one embodiment ( Figure 5 ), such as computing system 102 (at least as described herein). Figure 1 One or more additional processors of a high performance computing system (described in connection therewith) execute one or more instructions to train a neural network using the partitioned neural network training data and activations, as shown in block diagram 500.

[0120] In at least one embodiment, processor 502A receives input 504A. In at least one embodiment, input 504A includes input data "IN0" and input data "IN1." In at least one embodiment, "IN0" of input 504A includes a first portion of training data and activations, such as a subset of training data and a portion of activations 114, as described herein. Figure 1 In at least one embodiment, input 504A "IN1" includes a first portion of training data and activations, such as a subset of training data and a portion of activations 116, as described herein at least with reference to Figure 1 In at least one embodiment, processor 502B receives input 504B. In at least one embodiment, input 504B includes input data "IN2" and input data "IN3". In at least one embodiment, "IN2" of input 504B includes a second portion of training data and activations, such as a subset of training data and a portion of activations 114, as described herein. Figure 1 In at least one embodiment, input 504B "IN3" includes a second portion of training data and activations such as a subset of training data and a portion of activations 116, which is at least related to Figure 1 In at least one embodiment, "IN0" and "IN2" collectively include a training data subset and activations such as those described herein, and "IN1" and "IN3" collectively include a training data subset and activations such as those described herein.

[0121] In at least one embodiment, processor 502A and processor 502B execute one or more instructions to perform an all gather 506. In at least one embodiment, all gather 506 is an operation in which a processor for training a neural network and / or performing one or more inferences using a trained neural network aggregates values ​​into an output. In at least one embodiment, for example, if there are N processors and an all gather such as all gather 506 is to collect K values ​​from each of the N processors, an output of dimension N*K is generated (e.g., K values ​​are collected from each of the N processors).

[0122] In at least one embodiment, processor 502A and processor 502B execute one or more instructions to perform a reduce scatter 508. In at least one embodiment, reduce scatter 508 is an operation that performs a reduction (e.g., a sum operation, a maximum operation, a minimum operation, etc.) on data and distributes (or spreads) the results of the reduction to the processors. For example, in at least one embodiment, if each of N processors has K values ​​(e.g., as described above), a reduce scatter operation with a reduction operation of determining a maximum value for each set of K values ​​distributes the maximum value of the K values ​​to each of the N processors.

[0123] In at least one embodiment, processor 502A executes one or more instructions to generate a QKV tensor 510A (represented in block diagram 500 as "GENERATE Q, K, V"). In at least one embodiment, processor 502B executes one or more instructions to generate a QKV tensor 510B (represented in block diagram 500 as "GENERATE Q, K, V"). In at least one embodiment, generate QKV tensor 510A and generate QKV tensor 510B generate tensors including a Q vector, a K vector, and a V vector. In at least one embodiment, the Q vector is a vector of a linear output layer based at least in part on the content encoded by the layer (e.g., the output of an encoder layer or the output of a decoder layer). In at least one embodiment, the K vector is also a vector of a linear output layer based at least in part on the input (e.g., input 504A or input 504B). In at least one embodiment, the V vector is a learned vector based at least in part on one or more calculations and also based at least in part on an input (e.g., input 504A or input 504B). In at least one embodiment, processor 502A executes one or more instructions to generate QKV tensor 510A concurrently (e.g., at the same time) with processor 502B executing one or more instructions to generate QKV tensor 510B.

[0124] In at least one embodiment, processor 502A executes one or more instructions to perform all gather / reduce scatter 512A (denoted as "AG / RS" in block diagram 500). In at least one embodiment, processor 502B executes one or more instructions to perform all gather / reduce scatter 512B (denoted as "AG / RS" in block diagram 500). In at least one embodiment, all gather / reduce scatter 512A and all gather / reduce scatter 512B are joint operations, with all gather performed on the forward pass (as described herein) and reduce scatter performed on the backward pass (also as described herein). In at least one embodiment, processor 502A executes one or more instructions to perform all gather / reduce scatter 512A concurrently (e.g., at the same time) with processor 502B executing one or more instructions to perform all gather / reduce scatter 512B.

[0125] In at least one embodiment, processor 502A executes one or more instructions to perform attention 514A (denoted as "ATTENTION" in block diagram 500). In at least one embodiment, processor 502B executes one or more instructions to perform attention 514B (denoted as "ATTENTION" in block diagram 500). In at least one embodiment, attention 514A and attention 514B enhance some portions of input data (e.g., input 504A or input 504B) and de-emphasize other portions of the input data. In at least one embodiment, attention 514A and attention 514B enable a neural network to focus more on portions of the data (e.g., certain sentences, words, pixels, etc.) while being trained. In at least one embodiment, processor 502A executes one or more instructions to perform attention 514A concurrently (e.g., at the same time) with processor 502B executing one or more instructions to perform attention 514B.

[0126] In at least one embodiment, processor 502A executes one or more instructions to perform no-op / all gather 516A (denoted as "NO-OP / AG" in block diagram 500). In at least one embodiment, processor 502B executes one or more instructions to perform no-op / all gather 516B (denoted as "NO-OP / AG" in block diagram 500). In at least one embodiment, no-op / all gather 516A and no-op / all gather 516B are combined operations that perform no operations (e.g., perform no operations and / or perform no operations) on the forward pass and perform all gather on the backward pass, as described herein. In at least one embodiment, processor 502A executes one or more instructions to perform no-op / all gather 516A concurrently (e.g., at the same time) with processor 502B executing one or more instructions to perform no-op / all gather 516B.

[0127] In at least one embodiment, processor 502A executes one or more instructions to perform attention output 518A (represented as "ATTENTION OUTPUT" in block diagram 500). In at least one embodiment, processor 502B executes one or more instructions to perform attention output 518B (represented as "ATTENTION OUTPUT" in block diagram 500). In at least one embodiment, attention output 518A and attention output 518B generate the results of applying attention 514A or attention 514B for further processing. In at least one embodiment, processor 502A executes one or more instructions to perform attention output 518A concurrently (e.g., at the same time) with processor 502B executing one or more instructions to perform attention output 518B.

[0128] In at least one embodiment, processor 502A continues 520A to train the neural network using the partitioned neural network training data and activations, as shown in block diagram 600. In at least one embodiment, processor 502B continues 520B to train the neural network using the partitioned neural network training data and activations, as shown in block diagram 600.

[0129] In at least one embodiment, the following sequence is performed as shown in block diagram 500: Figure 5 The operations described (e.g., first gather all 506, then reduce spread 508, then generate QKV tensor 510A and generate QKV tensor 510B, then gather all / reduce spread 512A and gather all / reduce spread 512B, etc.). In at least one embodiment, Figure 5The operations described may be performed in a different order than shown in block diagram 500. In at least one embodiment, the operations may be performed simultaneously or in parallel. Figure 5 In at least one embodiment, the operations are performed simultaneously or in parallel. Figure 5 In at least one embodiment, Figure 5 The operations described are performed by multiple threads executing on a processor such as those described herein.

[0130] Figure 6 is a block diagram 600 illustrating a second portion of a computing system wherein partitioned neural network training data and activation for training a neural network are performed, according to at least one embodiment. In at least one embodiment, processor 502A (e.g., as described herein) Figure 5 500 ) proceeds to 604A to train a neural network using the partitioned neural network training data and activations, as shown in block diagram 500 . In at least one embodiment, processor 502B (e.g., Figure 5 ) proceed to 604B to train the neural network using the partitioned neural network training data and activations, as shown in block diagram 500. In at least one embodiment ( Figure 6 ), one or more additional processors of a high performance computing system such as computing system 102 (referred to herein as Figure 1 ) executes one or more instructions to train a neural network using the partitioned neural network training data and activations, as shown in block diagram 600.

[0131] In at least one embodiment, processor 502A and processor 502B execute one or more instructions to perform reduced spread 606. In at least one embodiment, reduced spread 606 is a reduced spread such as reduced spread 508, which is described herein at least in conjunction with Figure 5 Describe the relevant information.

[0132] In at least one embodiment, processor 502A and processor 502B execute one or more instructions to perform aggregate all 608. In at least one embodiment, aggregate all 608 is an aggregate all such as aggregate all 506, where at least Figure 5 Describe the relevant information.

[0133] In at least one embodiment, processor 502A executes one or more instructions to perform dropout 610A (denoted as "DROPOUT" in block diagram 600). In at least one embodiment, processor 502B executes one or more instructions to perform dropout 610B (denoted as "DROPOUT" in block diagram 600). In at least one embodiment, dropout 610A and dropout 610B are performed by a processor (e.g., processor 502A and / or processor 502B) to remove data and / or noise from a neural network during training. In at least one embodiment, dropout 610A and dropout 610B randomly remove data and / or noise from the neural network to improve training and processing time. In at least one embodiment, dropout 610A and dropout 610B remove a specified proportion of data and / or noise from the neural network (e.g., one-third). In at least one embodiment, one or more augmentations (e.g., weight increases) are performed on the data and / or noise that are not removed from the neural network. In at least one embodiment, processor 502A executes one or more instructions to perform deactivation 610A concurrently (eg, at the same time) with processor 502B executing one or more instructions to perform deactivation 610B.

[0134] In at least one embodiment, processor 502A executes one or more instructions to perform layer normalization 612A (denoted as "LAYER NORM" in block diagram 600). In at least one embodiment, processor 502B executes one or more instructions to perform layer normalization 612B (denoted as "LAYER NORM" in block diagram 600). In at least one embodiment, layer normalization 612A and layer normalization 612B are processes for estimating normalization statistics from the accumulated inputs within the hidden layer so that the normalization does not introduce new dependencies between training cases (e.g., with different input data) when training the neural network. In at least one embodiment, when performing layer normalization, the hidden layers share normalization terms, but different training cases (e.g., with different input data) have different normalization terms. In at least one embodiment, processor 502A executes one or more instructions to perform layer normalization 612B concurrently (e.g., at the same time) with processor 502B executing one or more instructions to perform layer normalization 612A.

[0135] In at least one embodiment, processor 502A and processor 502B execute one or more instructions to perform aggregate all 614. In at least one embodiment, aggregate all 614 is an aggregate all such as aggregate all 506, which is described herein at least in conjunction with Figure 5 Describe the relevant information.

[0136] In at least one embodiment, processor 502A and processor 502B execute one or more instructions to perform reduced spread 616. In at least one embodiment, reduced spread 616 is a reduced spread such as reduced spread 508, which is described herein at least in conjunction with Figure 5 Describe the relevant information.

[0137] In at least one embodiment, processor 502A executes one or more instructions to generate fully connected layer 1 618A (denoted as "FC1" in block diagram 600). In at least one embodiment, processor 502B executes one or more instructions to generate fully connected layer 1 618B (denoted as "FC1" in block diagram 600). In at least one embodiment, generating fully connected layer 1 618A and generating fully connected layer 1 618B are layer transformations that connect each neuron in a layer (e.g., the first hidden layer) to each neuron in another layer (e.g., the second hidden layer). In at least one embodiment, due to generating fully connected layer 1 618A and generating fully connected layer 1 618B, each input of the input vector affects each output of the output vector. In at least one embodiment, processor 502A and processor 502B execute one or more instructions to generate fully connected layer 1 618A concurrently (e.g., at the same time) with the execution of one or more instructions to generate fully connected layer 1 618B.

[0138] In at least one embodiment, processor 502A executes one or more instructions to execute Gaussian error linear unit 620A (denoted as "GeLU" in block diagram 600). In at least one embodiment, processor 502B executes one or more instructions to execute Gaussian error linear unit 620B (denoted as "GeLU" in block diagram 600). In at least one embodiment, Gaussian error linear unit 620A and Gaussian error linear unit 620B are activation functions that weight inputs according to a Gaussian distribution function (e.g., by percentile of the inputs). In at least one embodiment, processor 502A executes one or more instructions to execute Gaussian error linear unit 620B concurrently (e.g., at the same time) with processor 502B executing one or more instructions to execute Gaussian error linear unit 620A.

[0139] In at least one embodiment, processor 502A executes one or more instructions to generate fully connected layer 2 622A (denoted as "FC2" in block diagram 600). In at least one embodiment, processor 502B executes one or more instructions to generate fully connected layer 2 622B (denoted as "FC2" in block diagram 500). In at least one embodiment, generating fully connected layer 2 622A and generating fully connected layer 2 622B are described above in conjunction with generating fully connected layer 1 618A and generating fully connected layer 1 618B. In at least one embodiment, processor 502A and processor 502B execute one or more instructions to generate fully connected layer 2 622B concurrently (e.g., at the same time) with each other.

[0140] In at least one embodiment, processor 502A and processor 502B execute one or more instructions to perform reduced spread 624. In at least one embodiment, reduced spread 624 is a reduced spread such as reduced spread 508, which is described herein at least in conjunction with Figure 5 Describe the relevant information.

[0141] In at least one embodiment, processor 502A and processor 502B execute one or more instructions to perform aggregate all 626. In at least one embodiment, aggregate all 626 is an aggregate all such as aggregate all 506, which is described herein at least in conjunction with Figure 5 Describe the relevant information.

[0142] In at least one embodiment, the following sequence is performed as shown in block diagram 600: Figure 6 608, then dropout 610A and dropout 610B, then layer normalization 612A and layer normalization 612B, etc.). In at least one embodiment, Figure 6 The operations described may be performed in a different order than shown in block diagram 600. In at least one embodiment, the operations may be performed simultaneously or in parallel. Figure 6 In at least one embodiment, the operations described in Figure 6 In at least one embodiment, Figure 6 The operations described are performed by multiple threads executing on a processor such as those described herein.

[0143] distributed

[0144] Figure 7is a block diagram 700 illustrating training a neural network using partitioned neural network training data and activations according to at least one embodiment. In at least one embodiment, processor 716 (e.g., such as one or more of processors 104, described herein at least with reference to Figure 1 Receive training data 702 (e.g., training data 106, which is at least Figure 1 In at least one embodiment, the processor 716 first partitions the training data into training data subsets 704, as described herein in conjunction with Figures 1 to 3 In at least one embodiment, the processor 716 then determines the activation of the training data subset, also as described herein in conjunction with Figures 1 to 3 In at least one embodiment, the processor 716 then determines the activation for the training data subset 706, also as described herein in conjunction with Figures 1 to 3 Descriptive.

[0145] In at least one embodiment, high performance computing system 708 trains neural network 710 (e.g., trains neural network 110, at least as described herein) using the training data subset and activations. Figure 1 Related description), as described in this article Figures 1 to 3 In at least one embodiment, the high performance computing system 708 uses one or more processors (e.g., one or more processors of the processor 104, at least as described herein) Figure 1 Related description) to use at least Figure 5 and Figure 6 In at least one embodiment, the trained neural network 710 is used to train an untrained neural network 712 (e.g., untrained neural network 1006) to perform a neural network training operation such as that described herein. Figure 10 The operations described above are used to generate a trained neural network 714 (e.g., trained neural network 1008). In at least one embodiment, the trained neural network 714 is a large language model such as large language model 4312, which is at least related to Figure 43 In at least one embodiment, the trained neural network 714 is a diffusion model (e.g., an image generation model that uses one or more neural networks to generate images based on an understanding of the underlying structure of a dataset, such as an image dataset). In at least one embodiment, the trained neural network 714 is some other neural network such as those described herein.

[0146] Figure 88 is a block diagram 800 illustrating a processor and modules according to at least one embodiment. In at least one embodiment, the processor 802 executes one or more processes such as those described herein to cause reasoning about two or more connected portions of information to be distributed only between two or more corresponding processing cores. In at least one embodiment, the processor 802 executes one or more processes such as those described herein to use Figures 1 to 8 Related described systems, methods, operations, and techniques enable reasoning about two or more connected portions of information to be distributed solely between two or more corresponding processing cores.

[0147] In at least one embodiment, processor 802 includes a processor such as Figures 9A to 43 In at least one embodiment, processor 802 is a processor such as processor 122 and / or one or more processors 104, as described herein at least with reference to FIG. Figure 1 Related description. In at least one embodiment, the processor 802 is any suitable processing unit and / or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variants thereof. In at least one embodiment, the processor 802 includes or has access to the client computing module 804, the high performance computing module 806, the data partitioning module 808, the neural network training module 810, the activation module 812, and the neural network reasoning module 814. In at least one embodiment, one or more of the client computing module 804, the high performance computing module 806, the data partitioning module 808, the neural network training module 810, the activation module 812, and the neural network reasoning module 814 is part of the processor 802 and / or one or more other processors such as those described herein. In at least one embodiment, the client computing module 804, high performance computing module 806, data partitioning module 808, neural network training module 810, activation module 812, and neural network inference module 814 are distributed among multiple processors communicating over a bus, a network, by writing to a shared memory, and / or any suitable communication process as those described herein.

[0148] In at least one embodiment, unless the context clearly indicates otherwise or clearly indicates the contrary, a module for any implementation described herein refers to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functionality described herein. In at least one embodiment, software may be embodied as a software package, code, and / or instruction set or instructions, while "hardware" used in any implementation described herein (such as by a processor) may include, for example, individually or in any combination, hardwired circuitry, programmable circuitry, state machine circuitry, fixed function circuitry, execution unit circuitry, and / or firmware that stores instructions executed by programmable circuitry. In at least one embodiment, modules may be embodied collectively or individually as circuitry that constitutes part of a larger system, such as an integrated circuit (IC), a system on a chip (SoC), or the like. In at least one embodiment, a module performs one or more processes in association with any suitable processing unit and / or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variants thereof.

[0149] In at least one embodiment, the processor 802 uses the client computing module 804 to execute or otherwise implement one or more client environments such as those described herein. In at least one embodiment, the processor 802 uses the client computing module 804 to perform one or more operations to partition neural network training data and activations, as described herein. In at least one embodiment, the processor 802 uses the client computing module 804 in conjunction with one or more of the high performance computing module 806, the data partitioning module 808, the neural network training module 810, the activation module 812, and / or the neural network inference module 814 to perform one or more operations to partition neural network training data and activations. In at least one embodiment, the processor 802 uses the client computing module 804 to perform operations of the client computing system 108, as described herein. Figure 1 In at least one embodiment, the processor 802 uses the client computing module 804 to perform one or more processes such as those described herein by including or otherwise encoding instructions that cause execution or are otherwise usable to perform the one or more processes described (e.g., by the processor 802). In at least one embodiment, the processor 802 uses the client computing module 804 to perform one or more processes such as those described herein by including or otherwise encoding instructions that cause execution or are otherwise usable to perform the one or more processes described (e.g., by the processor 802). Figures 1 to 7 In at least one embodiment, the processor 802 uses the client computing module 804 to perform one or more operations such that reasoning about two or more connected portions of information is distributed only between two or more corresponding processing cores.

[0150] In at least one embodiment, the processor 802 uses the high performance computing module 806 to execute or otherwise implement one or more high performance computing environments such as those described herein. In at least one embodiment, the processor 802 uses the high performance computing module 806 to perform one or more operations to partition the neural network training data and activations, as described herein. In at least one embodiment, the processor 802 uses the high performance computing module 806 in conjunction with one or more of the client computing module 804, the data partitioning module 808, the neural network training module 810, the activation module 812, and / or the neural network inference module 814 to perform one or more operations to partition the neural network training data and activations. In at least one embodiment, the processor 802 uses the high performance computing module 806 to perform the operations of the computing system 102, as described herein. Figure 1 In at least one embodiment, the processor 802 uses the high performance computing module 806 to perform one or more processes such as those described herein by including or otherwise encoding instructions that cause execution or other use to perform the one or more processes described (e.g., by the processor 802). In at least one embodiment, the processor 802 uses the high performance computing module 806 to perform one or more processes such as those described herein by including or otherwise encoding instructions that cause execution or other use to perform the one or more processes described (e.g., by the processor 802). Figures 1 to 8 The systems, methods, operations, and techniques described herein implement or otherwise enable one or more computing environments. In at least one embodiment, the processor 802 utilizes the high performance computing module 806 to perform one or more operations such that reasoning about two or more connected portions of information is distributed only between two or more corresponding processing cores.

[0151] In at least one embodiment, the processor 802 uses the data partitioning module 808 to partition the neural network training data. In at least one embodiment, the processor 802 uses the data partitioning module 808 to partition the neural network training data as described herein. Figures 1 to 3In at least one embodiment, the processor 802 uses the data partitioning module 808 to perform one or more operations to partition the neural network training data and activations as described herein. In at least one embodiment, the processor 802 uses the data partitioning module 808 in conjunction with one or more of the client compute module 804, the high performance compute module 806, the neural network training module 810, the activation module 812, and / or the neural network inference module 814 to perform one or more operations to partition the neural network training data and activations. In at least one embodiment, the processor 802 uses the data partitioning module 808 to perform one or more operations to partition the neural network training data and activations as described herein. Figures 1 to 7 In at least one embodiment, the processor 802 uses the data partitioning module 808 to perform one or more operations such that reasoning about two or more connected portions of information is distributed only between two or more corresponding processing cores.

[0152] In at least one embodiment, the processor 802 trains the neural network using the neural network training module 810. In at least one embodiment, the processor 802 trains the neural network 110 using the neural network training module 810, as described herein at least in conjunction with Figure 1 In at least one embodiment, the processor 802 uses the neural network training module 810 to perform one or more operations to partition the neural network training data and activations as described herein. In at least one embodiment, the processor 802 uses the neural network training module 810 in conjunction with one or more of the client computing module 804, the high performance computing module 806, the data partitioning module 808, the activation module 812, and / or the neural network inference module 814 to perform one or more operations to partition the neural network training data and activations. In at least one embodiment, the processor 802 uses the neural network training module 810 to perform one or more operations to partition the neural network training data and activations as described herein. Figures 1 to 7 The systems, methods, operations, and techniques described herein perform or otherwise implement one or more environments. In at least one embodiment, the processor 802 uses the neural network training module 810 to perform one or more operations such that reasoning about two or more connected portions of information is distributed only between two or more corresponding processing cores.

[0153] In at least one embodiment, the processor 802 uses the activation module 812 to partition and distribute the neural network activations. In at least one embodiment, the processor 802 uses the activation module 812 to partition and distribute the neural network activations, as described herein at least in conjunction with Figures 1 to 3 In at least one embodiment, the processor 802 uses the activation module 812 to perform one or more processes such as those described herein by including or otherwise encoding instructions that cause execution or are otherwise usable to perform the one or more processes described (e.g., by the processor 802). In at least one embodiment, the processor 802 uses the activation module 812 to perform one or more operations to partition the neural network training data and activations as described herein. In at least one embodiment, the processor 802 uses the activation module 812 in conjunction with one or more of the client compute module 804, the high performance compute module 806, the data partitioning module 808, the neural network training module 810, and / or the neural network inference module 814 to perform one or more operations to partition one or more neural network training data and activations. In at least one embodiment, the processor 802 uses the activation module 812 to perform one or more operations to partition one or more neural network training data and activations as described herein. Figures 1 to 7 The systems, methods, operations, and techniques described herein perform or otherwise implement one or more environments. In at least one embodiment, the processor 802 uses the activation module 812 to perform one or more operations such that reasoning about two or more connected portions of information is distributed only between two or more corresponding processing cores.

[0154] In at least one embodiment, the processor 802 executes the trained neural network using the neural network inference module 814. In at least one embodiment, the processor 802 executes the trained neural network trained by the training neural network 110 using the neural network inference module 814, as described herein at least in conjunction with Figure 1In at least one embodiment, the processor 802 uses the neural network reasoning module 814 to perform one or more processes such as those described herein by including or otherwise encoding instructions that cause execution or are otherwise usable to perform the one or more processes described (e.g., by the processor 802). In at least one embodiment, the processor 802 uses the neural network reasoning module 814 to perform one or more operations to partition the neural network training data and activations as described herein. In at least one embodiment, the processor 802 uses the neural network reasoning module 814 in conjunction with one or more of the client compute module 804, the high performance compute module 806, the data partitioning module 808, the neural network training module 810, and / or the activation module 812 to perform one or more operations to partition the neural network training data and activations. In at least one embodiment, the processor 802 uses the neural network reasoning module 814 to perform one or more operations to partition the neural network training data and activations as described herein. Figures 1 to 7 The systems, methods, operations, and techniques described herein perform or otherwise implement one or more environments. In at least one embodiment, the processor 802 uses the neural network reasoning module 814 to perform one or more operations such that reasoning about two or more connected portions of information is distributed only between two or more corresponding processing cores.

[0155] In at least one embodiment, processor 802 includes circuitry for causing one or more circuits of processor 802 to use one or more of client computing module 804, high performance computing module 806, data partitioning module 808, neural network training module 810, activation module 812, and / or neural network inference module 814 using at least one of the methods described herein. Figures 1 to 7

[0014] Related described systems, methods, operations, and / or techniques distribute reasoning about two or more connected portions of information only between two or more corresponding processing cores.

[0156] logic

[0157] Figure 9A 915 is shown as logic as described elsewhere herein according to at least one embodiment can be used in one or more devices to perform operations such as those described herein. In at least one embodiment, logic 915 is used to perform reasoning and / or training operations related to one or more embodiments. In at least one embodiment, logic 915 is reasoning and / or training logic. Figure 9A and / or Figure 9BDetails are provided regarding logic 915. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and / or firmware logic to provide the functionality or operations described herein, where the logic may be collectively or individually embodied as circuitry forming part of a larger system such as an integrated circuit (IC), a system on a chip (SoC), or one or more processors (e.g., CPU, GPU).

[0158] In at least one embodiment, logic 915 may include, but is not limited to, code and / or data storage 901 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network being trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, logic 915 may include or be coupled to code and / or data storage 901 for storing graph code or other software to control timing and / or sequence, wherein weights and / or other parameter information are loaded to configure logic including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weights or other parameter information into a processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, code and / or data storage 901 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 901 may be included within other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0159] In at least one embodiment, any portion of code and / or data storage 901 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 901 may be cache memory, dynamic random access memory ("DRAM"), static random access memory ("SRAM"), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 901 is internal or external to a processor, for example, or including DRAM, SRAM, flash memory, or some other storage type, may depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in inference and / or training of the neural network, or some combination of these factors.

[0160] In at least one embodiment, logic 915 may include, but is not limited to, code and / or data storage 905 for storing backpropagation and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, code and / or data storage 905 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during backpropagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, logic 915 may include or be coupled to code and / or data storage 905 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic, which includes integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)).

[0161] In at least one embodiment, code (such as graph code) causes weights or other parameter information to be loaded into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, any portion of code and / or data storage 905 can be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 905 can be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 905 can be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 905 is internal or external to the processor, for example, including DRAM, SRAM, flash memory, or some other type of storage, can depend on the available on-chip or off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of data used in inference and / or training of the neural network, or some combination of these factors.

[0162] In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be separate storage structures. In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be the same storage structure. In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be partially combined and partially separated. In at least one embodiment, any portion of code and / or data storage 901 and code and / or data storage 905 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0163] In at least one embodiment, logic 915 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 910 (including integer and / or floating point units) for performing logical and / or mathematical operations based at least in part on or directed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​from a layer or neuron within a neural network) stored in activation storage 920, which are functions of input / output and / or weight parameter data stored in code and / or data storage 901 and / or code and / or data storage 905. In at least one embodiment, the activations stored in activation storage 920 are generated based on linear algebra and / or matrix-based math performed by ALU 910 in response to executing instructions or other code, with weight values ​​stored in code and / or data storage 905 and / or code and / or data storage 901 used as operands, as well as other values ​​such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 905 or code and / or data storage 901 or other on-chip or off-chip storage.

[0164] In at least one embodiment, one or more ALUs 910 are included in one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 910 may be external to the processor or other hardware logic devices or circuits that use them (e.g., coprocessors). In at least one embodiment, ALUs 910 may be included within an execution unit of a processor or otherwise included in an ALU bank accessible by the execution units of the processor, which may be within the same processor or distributed between different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data storage 901, code and / or data storage 905, and activation storage 920 may share a processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 920 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Additionally, inference and / or training code may be stored with other code accessible to a processor or other hardware logic or circuitry and may be retrieved and / or processed using the processor's fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0165] In at least one embodiment, activation storage 920 can be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 920 can be completely or partially internal or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether activation storage 920 is internal or external to the processor, for example, or including DRAM, SRAM, flash memory, or some other storage type, can depend on the available storage on-chip versus off-chip, the latency requirements for performing training and / or inference functions, the batch size of data used in inferring and / or training neural networks, or some combination of these factors.

[0166] In at least one embodiment, Figure 9A The logic 915 shown in FIG may be used in conjunction with an application specific integrated circuit (“ASIC”), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) or from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Figure 9A The illustrated logic 915 may be used in conjunction with central processing unit ("CPU") hardware, graphics processing unit ("GPU") hardware, or other hardware such as a field programmable gate array ("FPGA").

[0167] In at least one embodiment, using Figure 9A At least one component shown or described to perform in conjunction with Figures 1 to 8 In at least one embodiment, the techniques and / or functions described herein are Figure 9A At least one component is shown or described for distributing reasoning about two or more connected portions of information only between two or more corresponding processing cores. Figure 9A At least one component is shown or described for causing two or more other processors to each perform one or more operations of one or more neural networks based at least in part on two or more non-connected portions of an input sequence. In at least one embodiment, Figure 9AAt least one component shown or described is used to perform at least one aspect of the description with respect to block diagram 100, block diagram 200, block diagram 300, block diagram 400, block diagram 500, block diagram 600, block diagram 700, block diagram 800, and / or other systems, methods, or operations described herein. In at least one embodiment, reasoning and / or training logic 915 is used to perform at least one aspect of the description with respect to block diagram 100, block diagram 200, block diagram 300, block diagram 400, block diagram 500, block diagram 600, block diagram 700, block diagram 800, and / or other systems, methods, or operations described herein.

[0168] Figure 9B Logic 915 is shown in accordance with at least one embodiment. In at least one embodiment, logic 915 is inference and / or training logic. In at least one embodiment, logic 915 may include, but is not limited to, hardware logic where computing resources are dedicated or otherwise used exclusively with weight values ​​or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 9B The logic 915 shown in FIG can be used in conjunction with an application specific integrated circuit (ASIC), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) or from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Figure 9B The logic 915 shown in can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware such as a field programmable gate array (FPGA). In at least one embodiment, logic 915 includes, but is not limited to, code and / or data storage 901 and code and / or data storage 905, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 9B In at least one embodiment shown in FIG, code and / or data storage 901 and code and / or data storage 905 are each associated with dedicated computing resources, such as computing hardware 902 and computing hardware 906, respectively. In at least one embodiment, computing hardware 902 and computing hardware 906 each include one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) solely on the information stored in code and / or data storage 901 and code and / or data storage 905, respectively, with the results being stored in activation storage 920.

[0169] In at least one embodiment, each of the code and / or data stores 901 and 905 and the corresponding computing hardware 902 and 906 corresponds to a different layer of a neural network, such that activations from one storage / computation pair 901 / 902 of the code and / or data store 901 and computing hardware 902 are provided as inputs to the next storage / computation pair 905 / 906 of the code and / or data store 905 and computing hardware 906, reflecting the conceptual organization of the neural network. In at least one embodiment, each storage / computation pair 901 / 902 and 905 / 906 can correspond to more than one neural network layer. In at least one embodiment, additional storage / computation pairs (not shown) can be included in the logic 915 after or in parallel with the storage / computation pairs 901 / 902 and 905 / 906.

[0170] In at least one embodiment, using Figure 9B At least one component shown or described to perform in conjunction with Figures 1 to 8 In at least one embodiment, the techniques and / or functions described herein are Figure 9B At least one component is shown or described for distributing reasoning about two or more connected portions of information only between two or more corresponding processing cores. Figure 9B At least one component is shown or described for causing two or more other processors to each perform one or more operations of one or more neural networks based at least in part on two or more non-connected portions of an input sequence. In at least one embodiment, Figure 9B At least one component shown or described is used to perform at least one aspect of the description with respect to block diagram 100, block diagram 200, block diagram 300, block diagram 400, block diagram 500, block diagram 600, block diagram 700, block diagram 800, and / or other systems, methods, or operations described herein. In at least one embodiment, reasoning and / or training logic 915 is used to perform at least one aspect of the description with respect to block diagram 100, block diagram 200, block diagram 300, block diagram 400, block diagram 500, block diagram 600, block diagram 700, block diagram 800, and / or other systems, methods, or operations described herein.

[0171] Neural network training and deployment

[0172] Figure 10The training and deployment of a deep neural network according to at least one embodiment is shown. In at least one embodiment, an untrained neural network 1006 is trained using a training dataset 1002. In at least one embodiment, the training framework 1004 is the PyTorch framework, while in other embodiments, the training framework 1004 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 1004 trains the untrained neural network 1006 and enables it to be trained using the processing resources described herein to generate a trained neural network 1008. In at least one embodiment, the weights can be randomly selected or selected by pre-training using a deep belief network. In at least one embodiment, the training can be performed in a supervised, partially supervised, or unsupervised manner.

[0173] In at least one embodiment, untrained neural network 1006 is trained using supervised learning, where training dataset 1002 includes inputs paired with expected outputs for the inputs, or where training dataset 1002 includes inputs with known outputs and the outputs of neural network 1006 are manually graded. In at least one embodiment, untrained neural network 1006 is trained in a supervised manner, processing inputs from training dataset 1002 and comparing the resulting outputs to a set of expected or desired outputs. In at least one embodiment, errors are then backpropagated through untrained neural network 1006. In at least one embodiment, training framework 1004 adjusts the weights that control untrained neural network 1006. In at least one embodiment, training framework 1004 includes tools for monitoring the degree to which untrained neural network 1006 converges toward a model (such as trained neural network 1008) suitable for generating correct answers (such as results 1014) based on input data (such as new dataset 1012). In at least one embodiment, the training framework 1004 repeatedly trains the untrained neural network 1006 while adjusting the weights to refine the output of the untrained neural network 1006 using a loss function and an adjustment algorithm (such as stochastic gradient descent). In at least one embodiment, the training framework 1004 trains the untrained neural network 1006 until the untrained neural network 1006 reaches a desired accuracy. In at least one embodiment, the trained neural network 1008 can then be deployed to implement any number of machine learning operations.

[0174] In at least one embodiment, untrained neural network 1006 is trained using unsupervised learning, wherein untrained neural network 1006 attempts to train itself using unlabeled data. In at least one embodiment, unsupervised learning training dataset 1002 will include input data without any associated output data or "ground truth" data. In at least one embodiment, untrained neural network 1006 can learn groupings within training dataset 1002 and can determine how individual inputs relate to untrained dataset 1002. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in trained neural network 1008 that can perform operations useful for reducing the dimensionality of new dataset 1012. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows identification of data points in new dataset 1012 that deviate from the normal pattern of new dataset 1012.

[0175] In at least one embodiment, semi-supervised learning can be used, which is a technique in which a mixture of labeled and unlabeled data is included in the training dataset 1002. In at least one embodiment, the training framework 1004 can be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 1008 to adapt to new datasets 1012 without forgetting the knowledge that was infused into the trained neural network 1008 during initial training.

[0176] In at least one embodiment, the training framework 1004 is a framework that is processed in conjunction with a software development kit such as the OpenVINO (Open Visual Inference and Neural Network Optimization) toolkit. In at least one embodiment, the OpenVINO toolkit is a toolkit such as that developed by Intel Corporation of Santa Clara, California. In at least one embodiment, OpenVINO includes logic 915 or uses logic 915 to perform the operations described herein. In at least one embodiment, an SoC, an integrated circuit, or a processor uses OpenVINO to perform the operations described herein.

[0177] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications (particularly neural network applications) for various tasks and operations (such as human vision simulation, speech recognition, natural language processing, recommendation systems, and / or variants thereof). In at least one embodiment, OpenVINO supports neural networks, such as convolutional neural networks (CNNs), recurrent neural networks, and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries, such as OpenCV, OpenCL, and / or variants thereof.

[0178] In at least one embodiment, OpenVINO supports neural network models for various tasks and operations such as classification, partitioning, object detection, face recognition, speech recognition, pose estimation (e.g., people and / or objects), monocular depth estimation, image restoration, style transfer, action recognition, colorization, and / or their variants.

[0179] In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also referred to as a model optimizer. In at least one embodiment, the model optimizer is a command-line tool that facilitates the transition between training and deployment of a neural network model. In at least one embodiment, the model optimizer optimizes a neural network model for execution on various devices and / or processing units, such as GPUs, CPUs, PPUs, GPGPUs, and / or variants thereof. In at least one embodiment, the model optimizer generates an internal representation of the model and optimizes the model to generate an intermediate representation. In at least one embodiment, the model optimizer reduces the number of layers in the model. In at least one embodiment, the model optimizer removes layers from the model used for training. In at least one embodiment, the model optimizer performs various neural network operations, such as modifying the model's inputs (e.g., resizing the model's inputs), modifying the size of the model's inputs (e.g., modifying the model's batch size), modifying the model's structure (e.g., modifying the model's layers), normalization, standardization, quantization (e.g., converting the model's weights from a first representation, such as floating point, to a second representation, such as integers), and / or variants thereof.

[0180] In at least one embodiment, OpenVINO includes one or more software libraries for reasoning, also referred to as an inference engine. In at least one embodiment, the inference engine is a C++ library or any suitable programming language library. In at least one embodiment, the inference engine is used to reason about input data. In at least one embodiment, the inference engine implements various classes to reason about input data and generate one or more results. In at least one embodiment, the inference engine implements one or more API functions to process intermediate representations, set input and / or output formats, and / or execute models on one or more devices.

[0181] In at least one embodiment, OpenVINO provides various capabilities for heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computing processes and / or systems that utilize one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions to execute programs on one or more devices. In at least one embodiment, OpenVINO provides various software functions to execute programs and / or parts of programs on different devices. In at least one embodiment, OpenVINO provides various software functions, for example, to run a first code portion on a CPU and a second code portion on a GPU and / or FPGA. In at least one embodiment, OpenVINO provides various software functions to execute one or more layers of a neural network on one or more devices (for example, executing a first set of layers on a first device (e.g., a GPU) and executing a second set of layers on a second device (e.g., a CPU)).

[0182] In at least one embodiment, OpenVINO includes various functions similar to those associated with the CUDA programming model, such as various neural network model operations associated with frameworks such as TensorFlow, PyTorch, and / or their variants. In at least one embodiment, one or more CUDA programming model operations are performed using OpenVINO. In at least one embodiment, the various systems, methods, and / or techniques described herein are implemented using OpenVINO.

[0183] In at least one embodiment, using Figure 10 At least one component shown or described to perform in conjunction with Figures 1 to 8 In at least one embodiment, the techniques and / or functions described herein are Figure 10 At least one component is shown or described for distributing reasoning about two or more connected portions of information only between two or more corresponding processing cores. Figure 10 At least one component is shown or described for causing two or more other processors to each perform one or more operations of one or more neural networks based at least in part on two or more non-connected portions of an input sequence. In at least one embodiment, Figure 10 At least one component shown or described is used to perform at least one aspect of the description of block diagram 100, block diagram 200, block diagram 300, block diagram 400, block diagram 500, block diagram 600, block diagram 700, block diagram 800 and / or other systems, methods, or operations described herein. In at least one embodiment, Figure 10At least one component shown or described is used to perform at least one aspect of the description with respect to block diagram 100, block diagram 200, block diagram 300, block diagram 400, block diagram 500, block diagram 600, block diagram 700, block diagram 800 and / or other systems, methods, or operations described herein.

[0184] Data Center

[0185] Figure 11 An example data center 1100 is shown in which at least one embodiment may be used. In at least one embodiment, the data center 1100 includes a data center infrastructure layer 1110, a framework layer 1120, a software layer 1130, and an application layer 1140.

[0186] In at least one embodiment, Figure 11 As shown, the data center infrastructure layer 1110 may include a resource coordinator 1112, grouped computing resources 1114, and node computing resources ("node CRs") 1116(1)-1116(N), where "N" represents a positive integer (which may be an integer "N" different from the integers used in other figures). In at least one embodiment, the node CRs 1116(1)-1116(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 1118(1)-1118(N) (e.g., dynamic read-only memory, solid-state storage, or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules and cooling modules, etc. In at least one embodiment, one or more of the node CRs 1116(1)-1116(N) may be a server having one or more of the above-mentioned computing resources.

[0187] In at least one embodiment, the grouped computing resources 1114 may include separate groups of node CRs housed in one or more racks (not shown), or may be housed in many racks in data centers (also not shown) at various geographic locations. In at least one embodiment, the separate groups of node CRs within the grouped computing resources 1114 may include computing, networking, memory, or storage resources that may be configured or distributed to support groupings of one or more workloads. In at least one embodiment, several node CRs including CPUs or processors may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0188] In at least one embodiment, resource coordinator 1112 may configure or otherwise control one or more nodes CR 1116(1)-1116(N) and / or grouped computing resources 1114. In at least one embodiment, resource coordinator 1112 may comprise a software design infrastructure ("SDI") management entity for data center 1100. In at least one embodiment, resource coordinator 1112 may comprise hardware, software, or some combination thereof.

[0189] In at least one embodiment, Figure 11 As shown, framework layer 1120 includes a job scheduler 1122, a configuration manager 1124, a resource manager 1126, and a distributed file system 1128. In at least one embodiment, framework layer 1120 may include a framework that supports software 1132 of software layer 1130 and / or one or more applications 1142 of application layer 1140. In at least one embodiment, software 1132 or applications 1142 may respectively include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1120 may include, but is not limited to, a type of free and open source software web application framework, such as Apache Spark™ (hereinafter referred to as "Spark"), which can utilize distributed file system 1128 for large-scale data processing (e.g., "big data"). In at least one embodiment, job scheduler 1122 may include a Spark driver to facilitate scheduling workloads supported by various layers of data center 1100. In at least one embodiment, a configuration manager 1124 may be capable of configuring different layers, such as a software layer 1130 and a framework layer 1120 including Spark and a distributed file system 1128 for supporting large-scale data processing. In at least one embodiment, a resource manager 1126 may be capable of managing clustered or grouped computing resources that are mapped to or distributed to support the distributed file system 1128 and the job scheduler 1122. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 1114 at the data center infrastructure layer 1110. In at least one embodiment, the resource manager 1126 may coordinate with a resource coordinator 1112 to manage these mapped or distributed computing resources.

[0190] In at least one embodiment, the software 1132 included in the software layer 1130 may include software used by at least portions of the node CRs 1116(1)-1116(N), the grouped computing resources 1114, and / or the distributed file system 1128 of the framework layer 1120. In at least one embodiment, the one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0191] In at least one embodiment, the one or more applications 1142 included in the application layer 1140 may include one or more types of applications used by at least portions of the node CRs 1116(1)-1116(N), the grouped computing resources 1114, and / or the distributed file system 1128 of the framework layer 1120. In at least one embodiment, the one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, applications, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0192] In at least one embodiment, any of configuration manager 1124, resource manager 1126, and resource coordinator 1112 can implement any number and type of self-modification actions based on any number and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve a data center operator of data center 1100 from making potentially poor configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0193] In at least one embodiment, data center 1100 may include tools, services, software, or other resources for training one or more machine learning models or using one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 1100. In at least one embodiment, using the weight parameters calculated using one or more training techniques described herein, the resources described above with respect to data center 1100 may be used to infer or predict information using a trained machine learning model corresponding to one or more neural networks.

[0194] In at least one embodiment, the data center can use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to use the above resources to perform training and / or reasoning. In addition, one or more of the above software and / or hardware resources can be configured as a service to allow users to train or perform information reasoning, such as image recognition, speech recognition, or other artificial intelligence services.

[0195] Logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9B Details are provided regarding logic 915. In at least one embodiment, logic 915 can be used in data center 1100 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0196] In at least one embodiment, reference Figure 11 At least one component shown or described is used to perform the combination Figures 1 to 8 In at least one embodiment, the techniques and / or functions described herein are Figure 11 At least one component is shown or described for enabling reasoning about two or more connected portions of information to be distributed only between two or more corresponding processing cores. In at least one embodiment, Figure 11 At least one component is shown or described for causing two or more other processors to each perform one or more operations of one or more neural networks based at least in part on two or more non-connected portions of an input sequence. In at least one embodiment, Figure 11 At least one component is shown or described for performing at least one aspect described with respect to block diagram 100, block diagram 200, block diagram 300, block diagram 400, block diagram 500, block diagram 600, block diagram 700, block diagram 800 and / or other systems, methods, or operations described herein.

[0197] autonomous vehicles

[0198] Figure 12A An example of an autonomous vehicle 1200 is shown, according to at least one embodiment. In at least one embodiment, autonomous vehicle 1200 (alternatively referred to herein as "vehicle 1200") can be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, vehicle 1200 can be a semi-tractor-trailer truck for hauling cargo. In at least one embodiment, vehicle 1200 can be an aircraft, a robotic vehicle, or another type of vehicle.

[0199] Autonomous vehicles may be described according to the automation levels defined by the National Highway Traffic Safety Administration (“NHTSA”) and the Society of Automotive Engineers (“SAE”) of the U.S. Department of Transportation, “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806, dated June 15, 2018, Standard No. J3016-201609, dated September 30, 2016, and previous and future versions of the standards). In at least one embodiment, the vehicle 1200 may be capable of one or more of Levels 1 to 5 according to the autonomous driving levels. For example, in at least one embodiment, the vehicle 1200 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment.

[0200] In at least one embodiment, the vehicle 1200 may include, but is not limited to, components such as a chassis, a body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of the vehicle. In at least one embodiment, the vehicle 1200 may include, but is not limited to, a propulsion system 1250, such as an internal combustion engine, a hybrid power plant, an all-electric engine, and / or another type of propulsion system. In at least one embodiment, the propulsion system 1250 may be connected to a drive train of the vehicle 1200, which may include, but is not limited to, a transmission, for enabling propulsion of the vehicle 1200. In at least one embodiment, the propulsion system 1250 may be controlled in response to a signal received from a throttle / accelerator 1252.

[0201] In at least one embodiment, when propulsion system 1250 is operating (e.g., when vehicle 1200 is in motion), a steering system 1254 (which may include, but is not limited to, a steering wheel) is used to steer vehicle 1200 (e.g., along a desired path or route). In at least one embodiment, steering system 1254 may receive signals from steering actuator 1256. In at least one embodiment, a steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, brake sensor system 1246 may be used to operate vehicle brakes in response to signals received from brake actuator 1248 and / or brake sensors.

[0202] In at least one embodiment, one or more controllers 1236, which may include but are not limited to one or more system on a chip ("SoC") ( Figure 12A) and / or a graphics processing unit (“GPU”) to provide signals (e.g., representing commands) to one or more components and / or systems of vehicle 1200. For example, in at least one embodiment, one or more controllers 1236 can send signals to operate vehicle brakes via brake actuator 1248, operate steering system 1254 via one or more steering actuators 1256, and operate propulsion system 1250 via one or more throttle / accelerator 1252. In at least one embodiment, one or more controllers 1236 can include one or more on-board (e.g., integrated) computing devices that process sensor signals and output operational commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving vehicle 1200. In at least one embodiment, one or more controllers 1236 can include a first controller for autonomous driving functionality, a second controller for functional safety functionality, a third controller for artificial intelligence functionality (e.g., computer vision), a fourth controller for infotainment functionality, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the above functions, two or more controllers may handle a single function, and / or any combination thereof.

[0203] In at least one embodiment, the one or more controllers 1236 provide signals for controlling one or more components and / or systems of the vehicle 1200 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, the sensor data can be received from sensors such as, but not limited to, one or more global navigation satellite system ("GNSS") sensors 1258 (e.g., one or more global positioning system sensors), one or more RADAR sensors 1260, one or more ultrasonic sensors 1262, one or more LIDAR sensors 1264, one or more inertial measurement unit (IMU) sensors 1266 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1296, one or more stereo cameras 1268, one or more wide-angle cameras 1270 (e.g., fisheye cameras), one or more infrared cameras 1272, one or more surround cameras 1274 (e.g., 360-degree cameras), telemetry cameras (e.g., gyroscopes), and the like. Figure 12A Not shown), mid-range camera ( Figure 12A), one or more speed sensors 1244 (e.g., for measuring the speed of the vehicle 1200), one or more vibration sensors 1242, one or more steering sensors 1240, one or more brake sensors (e.g., as part of a brake sensor system 1246), and / or other sensor types.

[0204] In at least one embodiment, one or more controllers 1236 may receive input (e.g., represented by input data) from a dashboard 1232 of the vehicle 1200 and provide output (e.g., represented by output data, display data, etc.) via a human machine interface ("HMI") display 1234, an audible annunciator, a speaker, and / or via other components of the vehicle 1200. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high definition map ( Figure 12A ), location data (e.g., the location of the vehicle 1200, such as on a map), directions, the locations of other vehicles (e.g., an occupancy grid), information about objects and the states of objects sensed by the one or more controllers 1236, etc. For example, in at least one embodiment, the HMI display 1234 can display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about driving maneuvers the vehicle has, is, or will make (e.g., changing lanes now, reaching exit 34B in two miles, etc.).

[0205] In at least one embodiment, the vehicle 1200 further includes a network interface 1224 that can communicate over one or more networks using one or more wireless antennas 1226 and / or one or more modems. For example, in at least one embodiment, the network interface 1224 can be capable of communicating over Long Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile Communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000") networks, and the like. In at least one embodiment, the one or more wireless antennas 1226 can also enable communication between objects in the environment (e.g., vehicles, mobile devices, and the like) using one or more local area networks (such as Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, and the like) and / or one or more low power wide area networks ("LPWAN") (such as LoRaWAN, SigFox, and the like protocols).

[0206] Logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9BDetails are provided regarding logic 915. In at least one embodiment, logic 915 can be used in vehicle 1200 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0207] In at least one embodiment, Figure 12A At least one component shown or described is used to perform the combination Figures 1 to 8 In at least one embodiment, the techniques and / or functions described herein are Figure 12A At least one component is shown or described for distributing reasoning about two or more connected portions of information only between two or more corresponding processing cores. Figure 12A At least one component is shown or described for causing two or more other processors to each perform one or more operations of one or more neural networks based at least in part on two or more non-connected portions of an input sequence. In at least one embodiment, Figure 12A At least one component shown or described is used to perform at least one aspect described with respect to block diagram 100, block diagram 200, block diagram 300, block diagram 400, block diagram 500, block diagram 600, block diagram 700, block diagram 800 and / or other systems, methods, or operations described herein.

[0208] Figure 12B According to at least one embodiment, Figure 12A 1200. In at least one embodiment, the cameras and respective fields of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included, and / or the cameras may be located at different locations on vehicle 1200.

[0209] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera that may be suitable for use with components and / or systems of the vehicle 1200. In at least one embodiment, one or more cameras may operate at Automotive Safety Integrity Level ("ASIL") B and / or other ASILs. In at least one embodiment, the camera type may be capable of having any image capture rate, such as 60 frames per second (fps), 120fps, 240fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, other types of shutters, or combinations thereof. In at least one embodiment, the color filter array may include a red-clear-clear-clear ("RCCC") filter array, a red-clear-clear-blue ("RCCB") filter array, a red-blue-green-clear ("RBGC") filter array, a Foveon X3 filter array, a Bayer sensor ("RGGB") filter array, a monochrome sensor filter array, and / or other types of filter arrays. In at least one embodiment, a clear pixel camera, such as one having an RCCC, RCCB, and / or RBGC color filter array, may be used in an effort to increase photosensitivity.

[0210] In at least one embodiment, one or more cameras can be used to perform advanced driver assistance system ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function monocular camera can be installed to provide functions including lane departure warning, traffic sign assistance, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) can simultaneously record and provide image data (e.g., video).

[0211] In at least one embodiment, one or more cameras can be mounted in a mounting assembly, such as a custom designed (three-dimensional ("3D") printed) assembly, to remove stray light and reflected light from within the vehicle 1200 (e.g., reflected light from the dashboard reflecting in the windshield mirror) that may interfere with the camera's image data capture capabilities. With respect to the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly can be 3D printed custom so that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras can be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras can also be integrated into the four pillars at each corner of the cabin.

[0212] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view that includes portions of the environment in front of the vehicle 1200 can be used for surround vision to help identify the path ahead and obstacles, as well as to assist in providing information critical to generating an occupancy grid and / or determining a preferred vehicle path with the assistance of one or more controllers 1236 and / or control SoCs. In at least one embodiment, the forward-facing camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning ("LDW"), automatic cruise control ("ACC"), and / or other functions (such as traffic sign recognition).

[0213] In at least one embodiment, a variety of cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS ("Complementary Metal Oxide Semiconductor") color imager. In at least one embodiment, a wide-angle camera 1270 can be used to sense objects entering the view from the periphery (e.g., pedestrians, intersection traffic, or bicycles). Although in Figure 12B Only one wide-angle camera 1270 is shown, but in other embodiments, there can be any number (including zero) of wide-angle cameras on the vehicle 1200. In at least one embodiment, any number of remote cameras 1298 (e.g., a pair of telescopic stereo cameras) can be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, one or more remote cameras 1298 can also be used for object detection and classification and basic object tracking.

[0214] In at least one embodiment, any number of stereo cameras 1268 may also be included in the forward-facing configuration. In at least one embodiment, one or more stereo cameras 1268 may include an integrated control unit including an extensible processing unit that may provide programmable logic (“FPGA”) and a multi-core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the vehicle 1200's environment, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1268 may include, but are not limited to, a compact stereo vision sensor that may include, but are not limited to, two camera lenses (one on each side) and an image processing chip that may measure the distance from the vehicle 1200 to the target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1268 may be used in addition to or in place of those described herein.

[0215] In at least one embodiment, cameras having a field of view of portions of the environment including the sides of the vehicle 1200 (e.g., side view cameras) can be used for surround view, which provides information for creating and updating occupancy grids and generating side impact collision warnings. For example, in at least one embodiment, surround cameras 1274 (e.g., Figure 12B The four surround cameras shown (four surround cameras) can be positioned on the vehicle 1200. In at least one embodiment, the one or more surround cameras 1274 can include, but are not limited to, any number and combination of wide-angle cameras, one or more fisheye cameras, one or more 360-degree cameras, and / or the like. For example, in at least one embodiment, the four fisheye cameras can be located on the front, rear, and sides of the vehicle 1200. In at least one embodiment, the vehicle 1200 can use three surround cameras 1274 (e.g., left, right, and rear), and can utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround-view camera.

[0216] In at least one embodiment, a camera having a field of view that includes portions of the environment behind the vehicle 1200 (e.g., a rearview camera) can be used for parking assistance, surround view, rear collision warning, and creating and updating an occupancy grid. In at least one embodiment, a variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 1298 and / or one or more mid-range cameras 1276, one or more stereo cameras 1268, one or more infrared cameras 1272, etc.), as described herein.

[0217] In at least one embodiment, Figure 12B At least one component shown or described is used to perform the combination Figures 1 to 8 In at least one embodiment, the techniques and / or functions described herein are Figure 12B At least one component is shown or described for distributing reasoning about two or more connected portions of information only between two or more corresponding processing cores. Figure 12B At least one component is shown or described for causing two or more other processors to each perform one or more operations of one or more neural networks based at least in part on two or more non-connected portions of an input sequence. In at least one embodiment, Figure 12B At least one component shown or described is used to perform at least one aspect described with respect to block diagram 100, block diagram 200, block diagram 300, block diagram 400, block diagram 500, block diagram 600, block diagram 700, block diagram 800 and / or other systems, methods, or operations described herein.

[0218] Figure 12C is a diagram illustrating a method according to at least one embodiment Figure 12A A block diagram of an example system architecture for an autonomous vehicle 1200 is provided. In at least one embodiment, Figure 12C Each of the components, features, and systems of vehicle 1200 is shown as being connected via bus 1202. In at least one embodiment, bus 1202 may include, but is not limited to, a CAN data interface (alternatively referred to herein as a "CAN bus"). In at least one embodiment, CAN can be a network internal to vehicle 1200 that assists in controlling various features and functions of vehicle 1200, such as brake actuation, acceleration, braking, steering, wipers, etc. In at least one embodiment, bus 1202 can be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., CAN ID). In at least one embodiment, bus 1202 can be read to find steering wheel angle, ground speed, engine revolutions per minute ("RPM"), button positions, and / or other vehicle status indicators. In at least one embodiment, bus 1202 can be an ASIL B compliant CAN bus.

[0219] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or instead of CAN. In at least one embodiment, there may be any number of buses forming bus 1202, which may include, but are not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using different protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or may be used for redundancy. For example, a first bus may be used for collision avoidance functionality, and a second bus may be used for actuation control. In at least one embodiment, each bus in bus 1202 may communicate with any component of vehicle 1200, and two or more buses in bus 1202 may communicate with corresponding components. In at least one embodiment, each of any number of systems on a chip (“SoCs”) 1204 (e.g., SoC 1204(A) and SoC 1204(B)), each of one or more controllers 1236, and / or each computer within the vehicle can access the same input data (e.g., inputs from sensors of the vehicle 1200) and can be connected to a common bus, such as a CAN bus.

[0220] In at least one embodiment, the vehicle 1200 may include one or more controllers 1236, such as those described herein with respect to Figure 12AIn at least one embodiment, the controller 1236 can be used for a variety of functions. In at least one embodiment, the controller 1236 can be coupled to any of the various other components and systems of the vehicle 1200 and can be used to control the vehicle 1200, the artificial intelligence of the vehicle 1200, the infotainment and / or other functions of the vehicle 1200.

[0221] In at least one embodiment, the vehicle 1200 may include any number of SoCs 1204. In at least one embodiment, each of the SoCs 1204 may include, but is not limited to, a central processing unit ("CPU(s)") 1206, a graphics processing unit ("GPU(s")) 1208, one or more processors 1210, one or more caches 1212, one or more accelerators 1214, one or more data stores 1216, and / or other components and features not shown. In at least one embodiment, the one or more SoCs 1204 may be used to control the vehicle 1200 in a variety of platforms and systems. For example, in at least one embodiment, the one or more SoCs 1204 may be combined in a system (e.g., a system of the vehicle 1200) along with a high-definition ("HD") map 1222 that may be downloaded from one or more servers (e.g., a system of the vehicle 1200) via a network interface 1224. Figure 12C ) to obtain map refreshes and / or updates.

[0222] In at least one embodiment, one or more CPUs 1206 may include a CPU cluster or CPU complex (alternatively referred to herein as a "CCPLEX"). In at least one embodiment, one or more CPUs 1206 may include multiple cores and / or a second level ("L2") cache. For example, in at least one embodiment, one or more CPUs 1206 may include eight cores in a coherent multiprocessor configuration. In at least one embodiment, one or more CPUs 1206 may include four dual-core clusters, each with a dedicated L2 cache (e.g., a 2 megabyte (MB) L2 cache). In at least one embodiment, one or more CPUs 1206 (e.g., CCPLEX) may be configured to support simultaneous cluster operations, such that any combination of clusters of one or more CPUs 1206 may be active at any given time.

[0223] In at least one embodiment, one or more CPUs 1206 may implement power management functionality including, but not limited to, one or more of the following features: automatic clock gating of various hardware blocks when idle to save dynamic power; clock gating of each core when the core is not actively executing instructions due to executing a wait for interrupt ("WFI") / wait for event ("WFE") instruction; each core may be independently power gated; each core cluster may be independently clock gated when all cores are clock gated or power gated; and / or each core cluster may be independently power gated when all cores are power gated. In at least one embodiment, one or more CPUs 1206 may further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wakeup times are specified, and hardware / microcode determines the optimal power state to enter for the core, cluster, and CCPLEX. In at least one embodiment, the processing core may support a simplified power state entry sequence in software, wherein work is offloaded to the microcode.

[0224] In at least one embodiment, one or more GPUs 1208 may include an integrated GPU (alternatively referred to herein as an "iGPU"). In at least one embodiment, one or more GPUs 1208 may be programmable and efficient for parallel workloads. In at least one embodiment, one or more GPUs 1208 may utilize an enhanced tensor instruction set. In at least one embodiment, one or more GPUs 1208 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a level 1 ("L1") cache (e.g., an L1 cache having at least 96KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache having 512KB of storage capacity). In at least one embodiment, one or more GPUs 1208 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1208 may utilize one or more computing application programming interfaces (APIs). In at least one embodiment, one or more GPUs 1208 may utilize one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0225] In at least one embodiment, one or more GPUs 1208 may be power optimized for optimal performance in automotive and embedded use cases. For example, in at least one embodiment, one or more GPUs 1208 may be fabricated on fin field-effect transistor (“FinFET”) circuits. In at least one embodiment, each streaming microprocessor may include multiple mixed-precision processing cores partitioned into multiple blocks. For example, but not limited to, 64 FP32 cores and 32 FP64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be distributed with 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA tensor cores for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a scheduler (e.g., a warp scheduler) or sequencer, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths for providing efficient execution of workloads using a mix of compute and addressing operations. In at least one embodiment, the streaming microprocessor can include independent thread scheduling capabilities to enable finer-grained synchronization and cooperation between parallel threads. In at least one embodiment, the streaming microprocessor can include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0226] In at least one embodiment, one or more GPUs 1208 may include high bandwidth memory ("HBM") and / or a 16GB HBM2 memory subsystem, configured to provide a peak memory bandwidth of approximately 900 GB / s in some examples. In at least one embodiment, synchronous graphics random access memory ("SGRAM"), such as fifth generation graphics double data rate type synchronous random access memory ("GDDR5"), may be used in addition to or in place of HBM memory.

[0227] In at least one embodiment, one or more GPUs 1208 may include unified memory technology. In at least one embodiment, address translation service ("ATS") support may be used to allow one or more GPUs 1208 to directly access one or more CPU 1206 page tables. In at least one embodiment, when a memory management unit ("MMU") of a GPU in one or more GPUs 1208 experiences a miss, an address translation request may be sent to one or more CPUs 1206. In response, in at least one embodiment, two of the one or more CPUs 1206 may look up the virtual-to-physical mapping of the address in their page tables and send the translation back to the one or more GPUs 1208. In at least one embodiment, unified memory technology may allow a single unified virtual address space to be used for memory for both the one or more CPUs 1206 and the one or more GPUs 1208, thereby simplifying programming the one or more GPUs 1208 and porting applications to the one or more GPUs 1208.

[0228] In at least one embodiment, one or more GPUs 1208 may include any number of access counters that can track the frequency with which one or more GPUs 1208 access the memory of other processors. In at least one embodiment, the one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the page most frequently, thereby improving the efficiency of sharing memory ranges between processors.

[0229] In at least one embodiment, one or more SoCs 1204 may include any number of caches 1212, including those described herein. For example, in at least one embodiment, one or more caches 1212 may include a level 3 ("L3") cache that may be used for both (e.g., connected to) one or more CPUs 1206 and one or more GPUs 1208. In at least one embodiment, one or more caches 1212 may include a write-back cache that may track the state of each line, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4MB of memory or more, depending on the embodiment, although smaller cache sizes may be used.

[0230] In at least one embodiment, one or more SoCs 1204 may include one or more accelerators 1214 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoCs 1204 may include a hardware acceleration cluster that may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1208 and offload some tasks of one or more GPUs 1208 (e.g., to free up more cycles of one or more GPUs 1208 to perform other tasks). In at least one embodiment, one or more accelerators 1214 may be used for target workloads that are sufficiently stable to withstand acceleration (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, the CNNs may include region-based or region-based convolutional neural networks (“RCNNs”) and fast RCNNs (e.g., as used for object detection) or other types of CNNs.

[0231] In at least one embodiment, one or more accelerators 1214 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators ("DLAs"). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more tensor processing units ("TPUs"), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized to perform image processing functions (e.g., for CNN, RCNN, etc.). In at least one embodiment, one or more DLAs may be further optimized for a specific set of neural network types and floating-point operations and inference. In at least one embodiment, the design of one or more DLAs may provide higher performance per millimeter than a typical general-purpose GPU, and often significantly exceeds the performance of a CPU. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions that support, for example, INT8, INT16, and FP16 data types for features and weights, as well as post-processor functions. In at least one embodiment, one or more DLAs can quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, but not limited to: a CNN for object recognition and detection using data from a camera sensor; a CNN for distance estimation using data from a camera sensor; a CNN for emergency vehicle detection and recognition and detection using data from a microphone; a CNN for face recognition and vehicle owner recognition using data from a camera sensor; and / or a CNN for protection and / or safety related events.

[0232] In at least one embodiment, one or more DLAs can perform any function of one or more GPUs 1208, and by using an inference accelerator, for example, a designer can target any function to either one or more DLAs or one or more GPUs 1208. For example, in at least one embodiment, a designer can focus CNN processing and floating-point operations on one or more DLAs and leave other functions to one or more GPUs 1208 and / or one or more accelerators 1214.

[0233] In at least one embodiment, one or more accelerators 1214 may include a programmable vision accelerator ("PVA"), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems ("ADAS") 1238, autonomous driving, augmented reality ("AR") applications, and / or virtual reality ("VR") applications. In at least one embodiment, the PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may include, for example, but not limited to, any number of reduced instruction set computer ("RISC") cores, direct memory access ("DMA"), and / or any number of vector processors.

[0234] In at least one embodiment, the RISC core can interact with an image sensor (e.g., an image sensor of any camera described herein), an image signal processor, and the like. In at least one embodiment, each RISC core can include any amount of memory. In at least one embodiment, the RISC core can use any of a variety of protocols, depending on the embodiment. In at least one embodiment, the RISC core can execute a real-time operating system ("RTOS"). In at least one embodiment, the RISC core can be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, the RISC core can include an instruction cache and / or tightly coupled RAM.

[0235] In at least one embodiment, the DMA can enable components of the PVA to access system memory independently of the one or more CPUs 1206. In at least one embodiment, the DMA can support any number of features for providing optimizations to the PVA, including, but not limited to, support for multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA can support up to six or more dimensions of addressing, which can include, but are not limited to, block width, block height, block depth, horizontal block stride, vertical block stride, and / or depth stride.

[0236] In at least one embodiment, the vector processor can be a programmable processor that can be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA can include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core can include a processor subsystem, one or more DMA engines (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem can operate as the main processing engine of the PVA and can include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU core can include a digital signal processor, such as, for example, a single instruction multiple data ("SIMD"), a very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can increase throughput and speed.

[0237] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. Thus, in at least one embodiment, each vector processor may be configured to execute independently of the other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to exploit data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute a common computer vision algorithm, but on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on an image, or even different algorithms on a sequence of images or portions of an image. In at least one embodiment, any number of PVAs may be included in a hardware acceleration cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVAs may include additional error correction code ("ECC") memory to enhance overall system security.

[0238] In at least one embodiment, one or more accelerators 1214 may include an on-chip computer vision network and static random access memory ("SRAM") to provide high bandwidth, low latency SRAM to one or more accelerators 1214. In at least one embodiment, the on-chip memory may include at least 4MB of SRAM, including, for example, but not limited to, eight field-configurable memory blocks that can be accessed by both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus ("APB") interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and the DLA may access the memory via a backbone that provides high-speed access to the memory for the PVA and the DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and the DLA to the memory (e.g., using APB).

[0239] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for sending control signals / addresses / data, as well as burst-type communication for continuous data transmission. In at least one embodiment, the interface may comply with the International Organization for Standardization ("ISO") 26262 or International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0240] In at least one embodiment, one or more SoCs 1204 may include a real-time ray tracing hardware accelerator. In at least one embodiment, the real-time ray tracing hardware accelerator may be used to quickly and efficiently determine the position and extent of objects (e.g., within a world model) to generate real-time visual simulations for use in RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulations, for comparison with LIDAR data for positioning and / or other functions, and / or for other uses.

[0241] In at least one embodiment, one or more accelerators 1214 may have a wide range of uses for autonomous driving. In at least one embodiment, the PVA may be used in key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the ability of the PVA at low power and low latency is well matched to the algorithmic domain that requires predictable processing. In other words, the PVA excels at semi-intensive or intensive conventional computations, even on small data sets, which may require predictable runtimes with low latency and low power. In at least one embodiment, such as in vehicle 1200, the PVA may be designed to run classic computer vision algorithms because they can be efficient at object detection and integer math operations.

[0242] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, but this is not meant to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching in operation (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0243] In at least one embodiment, the PVA can be used to perform dense optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA is used to perform time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data.

[0244] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, for example, but not limited to, a neural network that outputs a confidence measurement for each object detection. In at least one embodiment, the confidence can be expressed or interpreted as a probability, or as providing a relative "weight" of each detection compared to other detections. In at least one embodiment, the confidence measurement enables the system to make further decisions about which detections should be considered true positive detections rather than false positive detections. In at least one embodiment, the system can set a threshold for the confidence and only consider detections that exceed the threshold as true positive detections. In embodiments using an automatic emergency braking ("AEB") system, a false positive detection will cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a high confidence detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence value. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), outputs of one or more IMU sensors 1266 associated with vehicle 1200 heading, distance, 3D position estimates of objects obtained from the neural network and / or other sensors (e.g., one or more LIDAR sensors 1264 or one or more RADAR sensors 1260).

[0245] In at least one embodiment, one or more SoCs 1204 may include one or more data stores 1216 (e.g., memory). In at least one embodiment, one or more data stores 1216 may be on-chip memory of one or more SoCs 1204 that may store neural networks to be executed on one or more GPUs 1208 and / or DLAs. In at least one embodiment, one or more data stores 1216 may have a capacity large enough to store multiple instances of a neural network for redundancy and safety. In at least one embodiment, one or more data stores 1216 may include one or more L2 or L3 caches.

[0246] In at least one embodiment, one or more SoCs 1204 may include any number of processors 1210 (e.g., embedded processors). In at least one embodiment, one or more processors 1210 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions and associated secure execution. In at least one embodiment, the boot and power management processor may be part of the boot sequence of one or more SoCs 1204 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in system low-power state transitions, manage one or more SoCs 1204 thermal and temperature sensors, and / or manage one or more SoCs 1204 power states. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and one or more SoCs 1204 may use the ring oscillator to detect the temperature of one or more CPUs 1206, one or more GPUs 1208, and / or one or more accelerators 1214. In at least one embodiment, if the temperature is determined to exceed a threshold, the boot and power management processor can enter a temperature fault routine and place one or more SoCs 1204 into a lower power state and / or place the vehicle 1200 into a driver's safe parking mode (e.g., bringing the vehicle 1200 to a safe stop).

[0247] In at least one embodiment, one or more processors 1210 may further include a set of embedded processors that can function as an audio processing engine, which can be an audio subsystem that implements full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core having a digital signal processor with dedicated RAM.

[0248] In at least one embodiment, one or more processors 1210 may further include an always-on processor engine that may provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0249] In at least one embodiment, one or more processors 1210 may further include a safety cluster engine, which may include but is not limited to a dedicated processor subsystem for handling safety management of automotive applications. In at least one embodiment, the safety cluster engine may include but is not limited to two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In safety mode, in at least one embodiment, the two or more cores may operate in lockstep mode and may function as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 1210 may further include a real-time camera engine, which may include but is not limited to a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1210 may further include a high dynamic range signal processor, which may include but is not limited to an image signal processor, which is a hardware engine that is part of the camera processing pipeline.

[0250] In at least one embodiment, one or more processors 1210 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements the video post-processing functions required by a video playback application to produce a final image for use in a player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1270, one or more surround cameras 1274, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, the in-cabin monitoring camera sensors are preferably monitored by a neural network running on another instance of SoC 1204, the neural network being configured to identify in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform, but is not limited to, lip reading to activate cellular service and place calls, dictate emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain features are available to the driver when the vehicle is operating in autonomous mode that would otherwise be disabled.

[0251] In at least one embodiment, the video image compositor can include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, in the presence of motion in the video, the noise reduction appropriately weights spatial information, thereby reducing the weight of information provided by successive frames. In at least one embodiment, in the presence of motion in an image or portion of an image, the temporal noise reduction performed by the video image compositor can use information from previous images to reduce noise in the current image.

[0252] In at least one embodiment, the video image compositor can also be configured to perform stereo rectification on the input stereo footage frames. In at least one embodiment, the video image compositor can also be used for user interface composition when the operating system desktop is being used, and does not require the one or more GPUs 1208 to continuously render new surfaces. In at least one embodiment, when the one or more GPUs 1208 are powered and active for 3D rendering, the video image compositor can be used to offload the one or more GPUs 1208 to improve performance and responsiveness.

[0253] In at least one embodiment, one or more of the SoCs 1204 may further include a Mobile Industry Processor Interface ("MIPI") camera serial interface for receiving video and input from a camera, a high-speed interface, and / or a video input block that may be used for a camera and associated pixel input functionality. In at least one embodiment, one or more of the SoCs 1204 may further include an input / output controller that may be controlled by software and may be used to receive I / O signals that are not assigned to a specific role.

[0254] In at least one embodiment, one or more of the SoCs 1204 may further include a wide range of peripheral interfaces for enabling communication with peripheral devices, audio encoders / decoders (“codecs”), power management, and / or other devices. In at least one embodiment, one or more of the SoCs 1204 may be configured to process data from cameras (e.g., connected via a Gigabit multimedia serial link and an Ethernet channel), sensors (e.g., one or more LIDAR sensors 1264, one or more RADAR sensors 1260, etc., which may be connected via an Ethernet channel), data from the bus 1202 (e.g., vehicle 1200 speed, steering wheel position, etc.), data from one or more GNSS sensors 1258 (e.g., connected via an Ethernet bus or a CAN bus), and the like. In at least one embodiment, one or more of the SoCs 1204 may further include dedicated high-performance large-scale memory controllers, which may include their own DMA engines and may be used to offload one or more of the CPUs 1206 from routine data management tasks.

[0255] In at least one embodiment, one or more SoCs 1204 can be an end-to-end platform with a flexible architecture that spans automation levels 3-5, thereby providing a comprehensive functional safety architecture that leverages and effectively uses computer vision and ADAS technologies to achieve diversity and redundancy, and provides a platform for flexible, reliable driving software stacks and deep learning tools. In at least one embodiment, one or more SoCs 1204 can be faster, more reliable, and even more energy-efficient and space-efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 1214, when combined with one or more CPUs 1206, one or more GPUs 1208, and one or more data stores 1216, can provide a fast, efficient platform for level 3-5 autonomous vehicles.

[0256] In at least one embodiment, computer vision algorithms can be executed on a CPU, which can be configured using a high-level programming language (e.g., C) to execute various processing algorithms on various visual data. However, in at least one embodiment, CPUs generally cannot meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real time, which are used in in-vehicle ADAS applications and actual Level 3-5 autonomous vehicles.

[0257] The embodiments described herein allow for the execution of multiple neural networks simultaneously and / or sequentially, and for the results to be combined to achieve Level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN executed on a DLA or a discrete GPU (e.g., one or more GPUs 1220) may include text and word recognition, thereby allowing for the reading and understanding of traffic signs, including signs for which the neural network has not been specifically trained. In at least one embodiment, the DLA may also include a neural network that is capable of recognizing, interpreting, and providing semantic understanding of signs, and passing this semantic understanding to a path planning module running on the CPU complex.

[0258] In at least one embodiment, for Level 3, 4, or 5 driving, multiple neural networks can be run simultaneously. For example, in at least one embodiment, a warning sign stating "Caution: Flashing lights indicate icy conditions," along with electric lights, can be interpreted independently or collectively by several neural networks. In at least one embodiment, the warning sign itself can be recognized as a traffic sign by a first deployed neural network (e.g., an already trained neural network), and the text "Flashing lights indicate icy conditions" can be interpreted by a second deployed neural network, which notifies the vehicle's path planning software (preferably executing on a CPU complex) that icy conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network over multiple frames, notifying the vehicle's path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within the DLA and / or on one or more GPUs 1208.

[0259] In at least one embodiment, a CNN for face recognition and vehicle owner recognition can use data from the camera sensor to identify the presence of an authorized driver and / or owner of the vehicle 1200. In at least one embodiment, an always-on sensor processing engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and in security mode, can be used to disable the vehicle when the owner leaves the vehicle. In this way, one or more SoCs 1204 provide protection against theft and / or carjacking.

[0260] In at least one embodiment, a CNN for emergency vehicle detection and identification can use data from microphone 1296 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 1204 use a CNN to classify environmental and urban sounds, as well as classify visual data. In at least one embodiment, a CNN running on a DLA is trained to identify the relative approaching speed of an emergency vehicle (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles specific to the local area in which the vehicle is operating, as identified by one or more GNSS sensors 1258. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while when operating in North America, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used with the assistance of one or more ultrasonic sensors 1262 to execute emergency vehicle safety routines, slow the vehicle, pull over, stop the vehicle, and / or idle the vehicle until the emergency vehicle passes.

[0261] In at least one embodiment, the vehicle 1200 may include one or more CPUs 1218 (e.g., one or more discrete CPUs or one or more dCPUs) that may be coupled to one or more SoCs 1204 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, the one or more CPUs 1218 may include, for example, an X86 processor. The one or more CPUs 1218 may be used to perform any of a variety of functions, including, for example, arbitrating potentially inconsistent results between ADAS sensors and the one or more SoCs 1204, and / or monitoring the status and health of one or more controllers 1236 and / or an infotainment system on a chip ("infotainment SoC") 1230. In at least one embodiment, the SoC 1204 includes one or more interconnects, and the interconnect may include a Peripheral Component Interconnect Express (PCIe).

[0262] In at least one embodiment, the vehicle 1200 may include one or more GPUs 1220 (e.g., one or more discrete GPUs or one or more dGPUs) that may be coupled to the one or more SoCs 1204 via a high-speed interconnect (e.g., NVIDIA's NVLINK channel). In at least one embodiment, the one or more GPUs 1220 may provide additional artificial intelligence functionality, such as by executing redundant and / or different neural networks, and may be used to train and / or update the neural network based at least in part on input from sensors of the vehicle 1200 (e.g., sensor data).

[0263] In at least one embodiment, vehicle 1200 may further include a network interface 1224, which may include, but is not limited to, one or more wireless antennas 1226 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, network interface 1224 may be used to enable wireless connectivity to internet cloud services (e.g., to servers and / or other network devices), to other vehicles, and / or to computing devices (e.g., a passenger's client device). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 1200 and the other vehicle, and / or an indirect link may be established (e.g., via a network and the internet). In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide the direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1200 with information about vehicles in its vicinity (e.g., vehicles in front of, to the sides of, and / or behind vehicle 1200). In at least one embodiment, this functionality may be part of the cooperative adaptive cruise control functionality of vehicle 1200.

[0264] In at least one embodiment, the network interface 1224 may include a SoC that provides modulation and demodulation functionality and enables one or more controllers 1236 to communicate over a wireless network. In at least one embodiment, the network interface 1224 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by a well-known process and / or using a super-heterodyne process. In at least one embodiment, the radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functionality for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0265] In at least one embodiment, the vehicle 1200 may further include one or more data stores 1228, which may include, but are not limited to, off-chip (e.g., one or more off-chip SoCs 1204) storage. In at least one embodiment, the one or more data stores 1228 may include, but are not limited to, one or more storage elements including RAM, SRAM, dynamic random access memory ("DRAM"), video random access memory ("VRAM"), flash memory, a hard disk, and / or other components and / or devices that can store at least one bit of data.

[0266] In at least one embodiment, the vehicle 1200 may further include one or more GNSS sensors 1258 (e.g., GPS and / or assisted GPS sensors) to assist with mapping, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1258 may be used, including, for example, but not limited to, GPS using a USB connector with an Ethernet to serial interface (e.g., RS-232) bridge.

[0267] In at least one embodiment, the vehicle 1200 may further include one or more RADAR sensors 1260. In at least one embodiment, the one or more RADAR sensors 1260 may be used by the vehicle 1200 for remote vehicle detection, even in darkness and / or in adverse weather conditions. In at least one embodiment, the RADAR functional safety level may be ASILB. In at least one embodiment, the one or more RADAR sensors 1260 may use a CAN bus and / or bus 1202 (e.g., for transmitting data generated by the one or more RADAR sensors 1260) for control and access to object tracking data, and in some examples, an Ethernet channel may be accessed to access raw data. In at least one embodiment, a variety of RADAR sensor types may be used. For example, but not limited to, the one or more RADAR sensors 1260 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more of the one or more RADAR sensors 1260 are pulsed Doppler RADAR sensors.

[0268] In at least one embodiment, one or more RADAR sensors 1260 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, the long-range RADAR can be used for adaptive cruise control functionality. In at least one embodiment, the long-range RADAR system can provide a wide field of view achieved by two or more independent scans (e.g., within a range of 250m). In at least one embodiment, one or more RADAR sensors 1260 can help distinguish between static objects and moving objects and can be used by the ADAS system 1238 for emergency brake assistance and forward collision warning. In at least one embodiment, the one or more sensors 1260 included in the long-range RADAR system may include, but are not limited to, a monostatic multimodal RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, using six antennas, the central four antennas can create a focused beam pattern designed to record the surrounding environment of the vehicle 1200 at a higher speed with minimal interference from traffic in the continuous lane. In at least one embodiment, the additional two antennas may extend the field of view, enabling it to quickly detect vehicles entering or leaving the lane of vehicle 1200 .

[0269] In at least one embodiment, as an example, a medium-range RADAR system may include a range of up to 160m (front) or 80m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1260 designed to be mounted on both ends of the rear bumper. When mounted on both ends of the rear bumper, in at least one embodiment, the RADAR sensor system can generate two light beams that continuously monitor the rear direction of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system can be used in the ADAS system 1238 for blind spot detection and / or lane change assistance.

[0270] In at least one embodiment, the vehicle 1200 may further include one or more ultrasonic sensors 1262. In at least one embodiment, one or more ultrasonic sensors 1262, which may be positioned at the front, rear, and / or side of the vehicle 1200, may be used for parking assistance and / or for creating and updating an occupancy grid. In at least one embodiment, a variety of ultrasonic sensors 1262 may be used, and different ultrasonic sensors 1262 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensors 1262 may operate at an ASIL B functional safety level.

[0271] In at least one embodiment, the vehicle 1200 can include one or more LIDAR sensors 1264. In at least one embodiment, the one or more LIDAR sensors 1264 can be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the one or more LIDAR sensors 1264 can operate at a functional safety level of ASIL B. In at least one embodiment, the vehicle 1200 can include multiple (e.g., two, four, six, etc.) LIDAR sensors 1264 that can use an Ethernet channel (e.g., to provide data to a Gigabit Ethernet switch).

[0272] In at least one embodiment, one or more LIDAR sensors 1264 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available one or more LIDAR sensors 1264 may, for example, have an advertised range of approximately 100 meters, an accuracy of 2-3 cm, and support 100 Mbps Ethernet connectivity. In at least one embodiment, one or more non-obtrusive LIDAR sensors may be used. In such an embodiment, one or more LIDAR sensors 1264 may comprise small devices that can be embedded in the front, rear, sides, and / or corners of the vehicle 1200. In at least one embodiment, one or more LIDAR sensors 1264 may provide up to 120 degrees of horizontal field of view and 35 degrees of vertical field of view, even for low-reflectivity objects, and have a range of 200 meters. In at least one embodiment, the forward-mounted one or more LIDAR sensors 1264 may be configured for a horizontal field of view between 45 and 135 degrees.

[0273] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate up to approximately 200 meters around vehicle 1200. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and the reflected light at each pixel, which in turn corresponds to the range from vehicle 1200 to the object. In at least one embodiment, flash LIDAR can allow for the generation of highly accurate and distortion-free images of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors can be deployed, one on each side of vehicle 1200. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D staring array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use 5 nanosecond Class I (eye-safe) laser pulses per frame and can capture the reflected laser light as a 3D range point cloud and co-registered intensity data.

[0274] In at least one embodiment, the vehicle 1200 may also include one or more IMU sensors 1266. In at least one embodiment, the one or more IMU sensors 1266 may be located at the center of the rear axle of the vehicle 1200. In at least one embodiment, the one or more IMU sensors 1266 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other sensor types. In at least one embodiment, for example, in a six-axis application, the one or more IMU sensors 1266 may include, but not limited to, accelerometers and gyroscopes. In at least one embodiment, for example, in a nine-axis application, the one or more IMU sensors 1266 may include, but not limited to, accelerometers, gyroscopes, and magnetometers.

[0275] In at least one embodiment, the one or more IMU sensors 1266 can be implemented as a miniature, high-performance GPS-aided inertial navigation system ("GPS / INS") that combines microelectromechanical systems ("MEMS") inertial sensors, a high-sensitivity GPS receiver, and an advanced Kalman filter algorithm to provide estimates of position, velocity, and attitude. In at least one embodiment, the one or more IMU sensors 1266 can enable the vehicle 1200 to estimate its heading by directly observing and correlating velocity changes from GPS to the one or more IMU sensors 1266, without the need for input from a magnetic sensor. In at least one embodiment, the one or more IMU sensors 1266 and the one or more GNSS sensors 1258 can be combined in a single integrated unit.

[0276] In at least one embodiment, the vehicle 1200 can include one or more microphones 1296 positioned within and / or around the vehicle 1200. In at least one embodiment, the one or more microphones 1296 can be used for emergency vehicle detection and identification.

[0277] In at least one embodiment, the vehicle 1200 may further include any number of camera types, including one or more stereo cameras 1268, one or more wide angle cameras 1270, one or more infrared cameras 1272, one or more surround cameras 1274, one or more long range cameras 1298, one or more mid range cameras 1276, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire periphery of the vehicle 1200. In at least one embodiment, the type of camera used depends on the vehicle 1200. In at least one embodiment, any combination of camera types may be used to provide the necessary coverage around the vehicle 1200. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, the vehicle 1200 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, the cameras may support, by way of example but not limitation, Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet communications. In at least one embodiment, the present disclosure previously referred to herein may provide a description of the various embodiments of the present invention. Figure 12A and Figure 12B Each camera is described in more detail.

[0278] In at least one embodiment, vehicle 1200 may further include one or more vibration sensors 1242. In at least one embodiment, one or more vibration sensors 1242 may measure vibration of a component (e.g., an axle) of vehicle 1200. For example, in at least one embodiment, a change in vibration may indicate a change in the road surface. In at least one embodiment, when two or more vibration sensors 1242 are used, the difference between the vibrations may be used to determine friction or slippage in the road surface (e.g., when there is a vibration difference between a powered drive shaft and a freely rotating shaft).

[0279] In at least one embodiment, the vehicle 1200 may include an ADAS system 1238. In at least one embodiment, the ADAS system 1238 may include, in some examples, but is not limited to, an SoC. In at least one embodiment, the ADAS system 1238 may include, but is not limited to, any number and any combination of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward collision warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keeping assist ("LKA") systems, blind spot alert ("BSW") systems, rear cross traffic alert ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functions.

[0280] In at least one embodiment, the ACC system may utilize one or more RADAR sensors 1260, one or more LIDAR sensors 1264, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle immediately in front of the vehicle 1200 and automatically adjusts the speed of the vehicle 1200 to maintain a safe distance from the vehicle in front. In at least one embodiment, the lateral ACC system performs distance keeping and recommends that the vehicle 1200 change lanes when needed. In at least one embodiment, lateral ACC is associated with other ADAS applications, such as LC and CW.

[0281] In at least one embodiment, the CACC system uses information from other vehicles, which may be received from the other vehicles indirectly via a wireless link or through a network connection (e.g., through the Internet) via a network interface 1224 and / or one or more wireless antennas 1226. In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle ("V2V") communication link, while the indirect link may be provided by an infrastructure-to-vehicle ("I2V") communication link. Typically, V2V communications provide information about the vehicle immediately ahead (e.g., the vehicle immediately ahead of vehicle 1200 and in the same lane as it), while I2V communications provide information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about the vehicle ahead of vehicle 1200, the CACC system may be more reliable and have the potential to improve the smoothness of traffic flow and reduce road congestion.

[0282] In at least one embodiment, the FCW system is designed to warn the driver of hazards so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 1260, which are coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system can provide warnings, such as in the form of audible, visual warnings, vibrations, and / or rapid brake pulses.

[0283] In at least one embodiment, an AEB system detects an impending forward collision with another vehicle or other object and can automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system can utilize one or more forward-facing cameras and / or one or more RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid the collision, and, if the driver does not take corrective action, the AEB system can automatically apply the brakes to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system can include technologies such as dynamic brake support and / or collision approach braking.

[0284] In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver when the vehicle 1200 crosses a lane marking. In at least one embodiment, the LDW system is deactivated when the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system may utilize a forward-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration assembly. In at least one embodiment, the LKA system is a variation of the LDW system. In at least one embodiment, if the vehicle 1200 begins to leave its lane, the LKA system provides steering input or braking to correct the vehicle 1200.

[0285] In at least one embodiment, the BSW system detects and warns the driver that a vehicle is in the car's blind spot. In at least one embodiment, the BSW system can provide visual, audible, and / or tactile alerts to indicate that it is unsafe to merge or change lanes. In at least one embodiment, the BSW system can provide additional warnings when the driver uses a turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to driver feedback such as a display, speaker, and / or vibration component.

[0286] In at least one embodiment, the RCTW system can provide visual, audible, and / or tactile notifications when the vehicle 1200 detects an object outside the range of the rear camera while in reverse. In at least one embodiment, the RCTW system includes an AEB system to ensure that the vehicle's brakes are applied to avoid a collision. In at least one embodiment, the RCTW system can use one or more rear-facing RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback such as a display, speaker, and / or vibration component.

[0287] In at least one embodiment, conventional ADAS systems can be prone to generating false positive results, which can be annoying and distracting to the driver, but are generally not catastrophic because conventional ADAS systems alert the driver and allow the driver to decide whether a safe condition truly exists and take action accordingly. In at least one embodiment, in the event of conflicting results, the vehicle 1200 independently decides whether to follow the results of the primary computer or the secondary computer (e.g., the first or second controller in controller 1236). For example, in at least one embodiment, the ADAS system 1238 can be a backup and / or secondary computer that provides perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor can run redundant software on hardware components to detect failures in perception and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 1238 can be provided to a supervisory MCU. In at least one embodiment, if the output from the primary computer and the output from the secondary computer conflict, the supervisory MCU determines how to reconcile the conflict to ensure safe operation.

[0288] In at least one embodiment, the primary computer can be configured to provide a confidence score to the supervisory MCU that indicates the primary computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU can follow the primary computer's instructions regardless of whether the secondary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the primary and secondary computers indicate different results (e.g., a conflict), the supervisory MCU can arbitrate between the computers to determine the appropriate result.

[0289] In at least one embodiment, the supervisory MCU can be configured to run a neural network that is trained and configured to determine conditions under which the secondary computer provides a false alarm based, at least in part, on output from the primary computer and output from the secondary computer. In at least one embodiment, the one or more neural networks in the supervisory MCU can learn when the output of the secondary computer can be trusted and when it cannot be trusted. For example, in at least one embodiment, when the secondary computer is a RADAR-based FCW system, the one or more neural networks in the supervisory MCU can learn when the FCW system is identifying a metal object that is not actually a danger, such as a drain grate or manhole cover, that would trigger an alarm. In at least one embodiment, when the secondary computer is a camera-based LDW system, the neural network in the supervisory MCU can learn to override LDW when a cyclist or pedestrian is present and lane departure is actually the safest action. In at least one embodiment, the supervisory MCU can include at least one of a DLA or a GPU suitable for running one or more neural networks with associated memory. In at least one embodiment, the supervisory MCU can include and / or be included as a component of one or more SoCs 1204.

[0290] In at least one embodiment, the ADAS system 1238 may include an auxiliary computer that performs ADAS functions using traditional computer vision rules. In at least one embodiment, the auxiliary computer may use classical computer vision rules (if-then), and the presence of one or more neural networks in the supervisory MCU may improve reliability, safety, and performance. For example, in at least one embodiment, the diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functions. For example, in at least one embodiment, if there is a software vulnerability or bug in the software running on the main computer, and the non-identical software code running on the auxiliary computer provides a consistent overall result, the supervisory MCU can have greater confidence that the overall result is correct and that the vulnerability in the software or hardware on the main computer did not cause a significant error.

[0291] In at least one embodiment, the output of the ADAS system 1238 can be fed into the primary computer's perception block and / or the primary computer's dynamic driving task block. For example, in at least one embodiment, if the ADAS system 1238 indicates a forward collision warning due to an object directly ahead, the perception block can use this information when the object is identified. In at least one embodiment, the secondary computer can have its own neural network that has been trained, as described herein, to reduce the risk of false positives.

[0292] In at least one embodiment, the vehicle 1200 may further include an infotainment SoC 1230 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system SoC 1230 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 1230 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total distance covered, brake fuel level, oil level, door open / closed, air filter information, etc.) to the vehicle 1200. For example, the infotainment SoC 1230 may include a radio, a disk player, a navigation system, a video player, USB and Bluetooth connectivity, an onboard computer, an onboard entertainment system, WiFi, steering wheel audio controls, hands-free voice control, a head-up display ("HUD"), an HMI display 1234, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, the infotainment SoC 1230 may further be used to provide information (e.g., visual and / or auditory information) to one or more users of the vehicle 1200, such as information from the ADAS system 1238, autonomous driving information (such as planned vehicle maneuvers), trajectory, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0293] In at least one embodiment, the infotainment SoC 1230 can include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 1230 can communicate with other devices, systems, and / or components of the vehicle 1200 via the bus 1202. In at least one embodiment, the infotainment SoC 1230 can be coupled to a supervisory MCU so that the infotainment system's GPU can perform some autonomous driving functions in the event that one or more of the main controllers 1236 (e.g., the vehicle's 1200 main computer and / or backup computer) fails. In at least one embodiment, the infotainment SoC 1230 can place the vehicle 1200 in a driver-to-safety parking mode, as described herein.

[0294] In at least one embodiment, the vehicle 1200 may further include an instrument panel 1232 (e.g., a digital instrument panel, an electronic instrument panel, a digital instrument panel, etc.). In at least one embodiment, the instrument panel 1232 may include, but is not limited to, a controller and / or a supercomputer (e.g., a separate controller or a supercomputer). In at least one embodiment, the instrument panel 1232 may include, but is not limited to, a set of instruments in any number and combination, such as a speedometer, a fuel level, an oil pressure, a tachometer, an odometer, a turn indicator, a shift position indicator, one or more seat belt warning lights, one or more parking brake warning lights, one or more engine check lights, supplemental restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between the infotainment SoC 1230 and the instrument panel 1232. In at least one embodiment, the instrument panel 1232 may be included as part of the infotainment SoC 1230, or vice versa.

[0295] In at least one embodiment, Figure 12C At least one component shown or described is used to perform the combination Figures 1 to 8 In at least one embodiment, the techniques and / or functions described herein are Figure 12C At least one component is shown or described for distributing reasoning about two or more connected portions of information only between two or more corresponding processing cores. Figure 12C At least one component is shown or described for causing two or more other processors to each perform one or more operations of one or more neural networks based at least in part on two or more non-connected portions of an input sequence. In at least one embodiment, Figure 12C At least one component shown or described is used to perform at least one aspect described with respect to block diagram 100, block diagram 200, block diagram 300, block diagram 400, block diagram 500, block diagram 600, block diagram 700, block diagram 800 and / or other systems, methods, or operations described herein.

[0296] Figure 12D In accordance with at least one embodiment, one or more cloud-based servers and Figure 12AFIG2 is a diagram of a system for communicating between autonomous vehicles 1200. In at least one embodiment, the system may include, but is not limited to, one or more servers 1278, one or more networks 1290, and any number and type of vehicles, including vehicle 1200. In at least one embodiment, one or more servers 1278 may include, but is not limited to, multiple GPUs 1284(A)-1284(H) (collectively referred to herein as GPUs 1284), PCIe switches 1282(A)-1282(D) (collectively referred to herein as PCIe switches 1282), and / or CPUs 1280(A)-1280(B) (collectively referred to herein as CPUs 1280). In at least one embodiment, GPUs 1284, CPUs 1280, and PCIe switches 1282 may be interconnected using a high-speed interconnect, such as, for example, but not limited to, NVLink interface 1288 and / or PCIe connection 1286 developed by NVIDIA. In at least one embodiment, the GPUs 1284 are connected via NVLink and / or NVSwitch SoCs, and the GPUs 1284 and PCIe switches 1282 are connected via PCIe interconnects. Although eight GPUs 1284, two CPUs 1280, and four PCIe switches 1282 are shown, this is not intended to be limiting. In at least one embodiment, each of the one or more servers 1278 may include, but is not limited to, any number of GPUs 1284, CPUs 1280, and / or PCIe switches 1282 in any combination. For example, in at least one embodiment, one or more servers 1278 may each include eight, sixteen, thirty-two, and / or more GPUs 1284.

[0297] In at least one embodiment, one or more servers 1278 may receive image data representing an image from a vehicle via one or more networks 1290 that depicts an unexpected or altered road condition, such as a recently begun road project. In at least one embodiment, one or more servers 1278 may transmit an updated neural network 1292 and / or map information 1294 to the vehicle via one or more networks 1290, including, but not limited to, information regarding traffic and road conditions. In at least one embodiment, updates to the map information 1294 may include, but not limited to, updates to the HD map 1222, such as information regarding construction sites, potholes, service roads, flooding, and / or other obstacles. In at least one embodiment, the neural network 1292 and / or map information 1294 may be generated from new training and / or experience represented by data received from any number of vehicles in the environment, and / or based at least on training performed at a data center (e.g., using one or more servers 1278 and / or other servers).

[0298] In at least one embodiment, one or more servers 1278 can be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. In at least one embodiment, the training data can be generated by the vehicle and / or can be generated in simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other pre-processing. In at least one embodiment, no amount of the training data is labeled and / or pre-processed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model can be used by the vehicle (e.g., sent to the vehicle via one or more networks 1290, and / or the machine learning model can be used by one or more servers 1278 to remotely monitor the vehicle.

[0299] In at least one embodiment, one or more servers 1278 can receive data from the vehicle and apply the data to the latest real-time neural networks for real-time intelligent reasoning. In at least one embodiment, one or more servers 1278 can include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 1284, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1278 can include the deep learning infrastructure of a data center using CPU power.

[0300] In at least one embodiment, the deep learning infrastructure of one or more servers 1278 may be capable of fast, real-time inference and may use this capability to assess and verify the health of the processors, software, and / or associated hardware in the vehicle 1200. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from the vehicle 1200, such as an image sequence and / or objects that the vehicle 1200 has located in the image sequence (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to those identified by the vehicle 1200, and if the results do not match and the deep learning infrastructure concludes that the AI ​​in the vehicle 1200 is malfunctioning, the one or more servers 1278 may send a signal to the vehicle 1200 instructing the vehicle's 1200 fail-safe computer to take control, notify passengers, and complete a safe parking maneuver.

[0301] In at least one embodiment, one or more servers 1278 may include one or more GPUs 1284 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3 devices). In at least one embodiment, the combination of GPU-driven servers and inference acceleration can enable real-time responses. In at least one embodiment, such as in situations where performance is less critical, servers driven by CPUs, FPGAs, and other processors can be used for inference. In at least one embodiment, one or more hardware structures 915 are used to execute one or more embodiments. Figure 9A and / or Figure 9B Provides details about the hardware structure 915.

[0302] In at least one embodiment, Figure 12D At least one component shown or described is used to perform the combination Figures 1 to 8 In at least one embodiment, the techniques and / or functions described herein are Figure 12D At least one component is shown or described for distributing reasoning about two or more connected portions of information only between two or more corresponding processing cores. Figure 12D At least one component is shown or described for causing two or more other processors to each perform one or more operations of one or more neural networks based at least in part on two or more non-connected portions of an input sequence. In at least one embodiment, Figure 12D At least one component shown or described is used to perform at least one aspect described with respect to block diagram 100, block diagram 200, block diagram 300, block diagram 400, block diagram 500, block diagram 600, block diagram 700, block diagram 800 and / or other systems, methods, or operations described herein.

[0303] Computer system

[0304] Figure 13 13 is a block diagram illustrating an exemplary computer system according to at least one embodiment, which may be a system of interconnected devices and components, a system on a chip (SOC), or some combination thereof formed with a processor that may include an execution unit for executing instructions. In at least one embodiment, in accordance with the present disclosure, such as in the embodiments described herein, computer system 1300 may include, but is not limited to, components such as processor 1302 for executing algorithms for processing data using execution units (including logic). In at least one embodiment, computer system 1300 may include a processor such as the Intel Corporation of Santa Clara, California. Processor family, XeonTM, XScaleTM and / or StrongARMTM, CoreTM or The computer system 1300 may be based on a Nervana™ microprocessor, although other systems may be used (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.). In at least one embodiment, the computer system 1300 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0305] Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0306] In at least one embodiment, computer system 1300 may include, but is not limited to, a processor 1302, which may include, but is not limited to, one or more execution units 1308 for performing machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, computer system 1300 is a single-processor desktop or server system, but in another embodiment, computer system 1300 may be a multi-processor system. In at least one embodiment, processor 1302 may include, but is not limited to, for example, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor that implements an instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1302 may be coupled to a processor bus 1310, which may transmit data signals between processor 1302 and other components in computer system 1300.

[0307] In at least one embodiment, processor 1302 may include, but is not limited to, level 1 ("L1") internal cache memory ("cache") 1304. In at least one embodiment, processor 1302 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 1302. Other embodiments may include a combination of internal and external caches, depending on the specific implementation and requirements. In at least one embodiment, register file 1306 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and an instruction pointer register.

[0308] In at least one embodiment, an execution unit 1308, including but not limited to logic for performing integer and floating-point operations, is also located in the processor 1302. In at least one embodiment, the processor 1302 may also include a microcode ("ucode") read-only memory ("ROM") that stores microcode for certain macroinstructions. In at least one embodiment, the execution unit 1308 may include logic for processing a packed instruction set 1309. In at least one embodiment, by including the packed instruction set 1309 in the instruction set of a general-purpose processor and the associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in the processor 1302. In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently by using the full width of the processor's data bus to perform operations on packed data, which may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations on one data element at a time.

[0309] In at least one embodiment, execution unit 1308 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1300 may include, but is not limited to, memory 1320. In at least one embodiment, memory 1320 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other memory device. In at least one embodiment, memory 1320 may store one or more instructions 1319 and / or data 1321 represented by data signals that processor 1302 may execute.

[0310] In at least one embodiment, the system logic chip can be coupled to the processor bus 1310 and the memory 1320. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 1316, and the processor 1302 can communicate with the MCH 1316 via the processor bus 1310. In at least one embodiment, the MCH 1316 can provide a high-bandwidth memory path 1318 to the memory 1320 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1316 can direct data signals between the processor 1302, the memory 1320, and other components in the computer system 1300, and bridge data signals between the processor bus 1310, the memory 1320, and the system I / O interface 1322. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1316 may be coupled to the memory 1320 via a high-bandwidth memory path 1318 , and the graphics / video card 1312 may be coupled to the MCH 1316 via an accelerated graphics port (“AGP”) interconnect 1314 .

[0311] In at least one embodiment, computer system 1300 may use system I / O interface 1322 as a proprietary hub interface bus to couple MCH 1316 to I / O controller hub ("ICH") 1330. In at least one embodiment, ICH 1330 may provide direct connection to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to memory 1320, chipset, and processor 1302. Examples may include, but are not limited to, an audio controller 1329, a firmware hub ("flash BIOS") 1328, a wireless transceiver 1326, a data store 1324, a legacy I / O controller 1323 including a user input and keyboard interface 1325, a serial expansion port 1327 (such as a universal serial bus ("USB") port), and a network controller 1334. In at least one embodiment, data store 1324 may include a hard drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0312] In at least one embodiment, Figure 13 The system is shown as comprising interconnected hardware devices or "chips", while in other embodiments, Figure 13 An exemplary SoC may be shown. In at least one embodiment, Figure 13The devices shown in FIG1300 can be interconnected using a proprietary interconnect, a standardized interconnect (eg, PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1300 are interconnected using a Compute Express Link (CXL) interconnect.

[0313] Logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9B Details are provided regarding logic 915. In at least one embodiment, logic 915 can be used in computer system 1300 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0314] In at least one embodiment, Figure 13 At least one component shown or described is used to perform the combination Figures 1 to 8 In at least one embodiment, the techniques and / or functions described herein are Figure 13 At least one component shown or described is used to cause reasoning about two or more connected portions of information to be distributed only between two or more corresponding processing cores. In at least one embodiment, at least one component shown or described with respect to 13 is used to cause two or more other processors to each perform one or more operations of one or more neural networks based at least in part on two or more non-connected portions of an input sequence. In at least one embodiment, Figure 13 At least one component shown or described is used to perform at least one aspect described with respect to block diagram 100, block diagram 200, block diagram 300, block diagram 400, block diagram 500, block diagram 600, block diagram 700, block diagram 800 and / or other systems, methods, or operations described herein.

[0315] Figure 14 1 is a block diagram illustrating an electronic device 1400 for utilizing a processor 1410 in accordance with at least one embodiment. In at least one embodiment, the electronic device 1400 may be, for example, but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0316] In at least one embodiment, the electronic device 1400 may include, but is not limited to, a processor 1410 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, the processor 1410 is coupled using a bus or interface, such as an I2C bus, a system management bus ("SMBus"), a low pin count (LPC) bus, a serial peripheral interface ("SPI"), a high-definition audio ("HDA") bus, a serial advanced technology attachment ("SATA") bus, a universal serial bus ("USB") (versions 1, 2, 3, etc.), or a universal asynchronous receiver / transmitter ("UART") bus. In at least one embodiment, Figure 14 shows a system comprising interconnected hardware devices or "chips", while in other embodiments, Figure 14 An exemplary SoC may be shown. In at least one embodiment, Figure 14 The devices shown in can be interconnected using a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 14 One or more components of the system are interconnected using a Compute Express Link (CXL) interconnect.

[0317] In at least one embodiment, Figure 14 It may include a display 1424, a touch screen 1425, a touchpad 1430, a near field communication unit (“NFC”) 1445, a sensor hub 1440, a thermal sensor 1446, an express chipset (“EC”) 1435, a trusted platform module (“TPM”) 1438, BIOS / firmware / flash memory (“BIOS, FW Flash”) 1422, a DSP 1460, a drive 1420 (such as a solid state disk (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1450, a Bluetooth unit 1452, a wireless wide area network unit (“WWAN”) 1456, a global positioning system (GPS) unit 1455, a camera (“USB 3.0 camera”) 1454 (such as a USB 3.0 camera), and / or a low power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1415 implemented with, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0318] In at least one embodiment, other components may be communicatively coupled to processor 1410 via the components described herein. In at least one embodiment, accelerometer 1441, ambient light sensor (“ALS”) 1442, compass 1443, and gyroscope 1444 may be communicatively coupled to sensor hub 1440. In at least one embodiment, thermal sensor 1439, fan 1437, keyboard 1436, and touchpad 1430 may be communicatively coupled to EC 1435. In at least one embodiment, speaker 1463, earphone 1464, and microphone (“mic”) 1465 may be communicatively coupled to audio unit (“audio codec and class-D amplifier”) 1462, which in turn may be communicatively coupled to DSP 1460. In at least one embodiment, audio unit 1462 may include, for example, but not limited to, an audio codec / decoder (“codec”) and a class-D amplifier. In at least one embodiment, SIM card (“SIM”) 1457 may be communicatively coupled to WWAN unit 1456. In at least one embodiment, components such as the WLAN unit 1450 and the Bluetooth unit 1452 and the WWAN unit 1456 may be implemented as a next generation form factor ("NGFF").

[0319] Logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9B Details are provided regarding logic 915. In at least one embodiment, logic 915 may be used in electronic device 1400 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0320] In at least one embodiment, Figure 14 At least one component shown or described is used to perform the combination Figures 1 to 8 In at least one embodiment, the techniques and / or functions described herein are Figure 14 At least one component shown or described is used to cause reasoning about two or more connected portions of information to be distributed only between two or more corresponding processing cores. In at least one embodiment, at least one component shown or described with respect to 14 is used to cause two or more other processors to each perform one or more operations of one or more neural networks based at least in part on two or more non-connected portions of an input sequence. In at least one embodiment, Figure 14 At least one component shown or described is used to perform at least one aspect described with respect to block diagram 100, block diagram 200, block diagram 300, block diagram 400, block diagram 500, block diagram 600, block diagram 700, block diagram 800 and / or other systems, methods, or operations described herein.

[0321] Figure 15 A computer system 1500 is shown in accordance with at least one embodiment. In at least one embodiment, the computer system 1500 is configured to implement the various processes and methods described throughout this disclosure.

[0322] In at least one embodiment, computer system 1500 includes, but is not limited to, at least one central processing unit ("CPU") 1502 connected to a communication bus 1510 implemented using any suitable protocol, such as PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1500 includes, but is not limited to, main memory 1504 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in main memory 1504, which may take the form of random access memory ("RAM"). In at least one embodiment, a network interface subsystem ("network interface") 1522 provides an interface to other computing devices and networks for receiving data from and sending data to other systems using computer system 1500.

[0323] In at least one embodiment, computer system 1500 includes, but is not limited to, input device 1508, parallel processing system 1512, and display device 1506, which can be implemented using conventional cathode ray tubes ("CRTs"), liquid crystal displays ("LCDs"), light emitting diode ("LED") displays, plasma displays, or other suitable display technologies. In at least one embodiment, user input is received from input device 1508 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the modules described herein can be located on a single semiconductor platform to form a processing system.

[0324] Logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9B Details are provided regarding logic 915. In at least one embodiment, logic 915 can be used in computer system 1500 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0325] In at least one embodiment, Figure 15 At least one component shown or described is used to perform the combination Figures 1 to 8 In at least one embodiment, the techniques and / or functions described herein are Figure 15At least one component shown or described is used to cause reasoning about two or more connected portions of information to be distributed only between two or more corresponding processing cores. In at least one embodiment, at least one component shown or described with respect to 15 is used to cause two or more other processors to each perform one or more operations of one or more neural networks based at least in part on two or more non-connected portions of an input sequence. In at least one embodiment, Figure 15 At least one component shown or described is used to perform at least one aspect described with respect to block diagram 100, block diagram 200, block diagram 300, block diagram 400, block diagram 500, block diagram 600, block diagram 700, block diagram 800 and / or other systems, methods, or operations described herein.

[0326] Figure 16 A computer system 1600 is shown in accordance with at least one embodiment. In at least one embodiment, computer system 1600 includes, but is not limited to, a computer 1610 and a USB drive 1620. In at least one embodiment, computer 1610 may include, but is not limited to, any number and type of processors (not shown) and memories (not shown). In at least one embodiment, computer 1610 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0327] In at least one embodiment, the USB disk 1620 includes, but is not limited to, a processing unit 1630, a USB interface 1640, and USB interface logic 1650. In at least one embodiment, the processing unit 1630 may be any instruction execution system, device, or apparatus capable of executing instructions. In at least one embodiment, the processing unit 1630 may include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1630 includes an application specific integrated circuit ("ASIC") that is optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing unit 1630 is a tensor processing unit ("TPC") that is optimized to perform machine learning reasoning operations. In at least one embodiment, the processing unit 1630 is a vision processing unit ("VPU") that is optimized to perform machine vision and machine learning reasoning operations.

[0328] In at least one embodiment, USB interface 1640 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, USB interface 1640 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, USB interface 1640 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1650 can include any number and type of logic that enables processing unit 1630 to interface with a device (e.g., computer 1610) via USB connector 1640.

[0329] Logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9B Details are provided regarding logic 915. In at least one embodiment, logic 915 can be used in computer system 1600 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0330] In at least one embodiment, Figure 16 At least one component shown or described is used to perform the combination Figures 1 to 8 In at least one embodiment, the techniques and / or functions described herein are Figure 16 At least one component shown or described is used to cause reasoning about two or more connected portions of information to be distributed only between two or more corresponding processing cores. In at least one embodiment, at least one component shown or described with respect to 16 is used to cause two or more other processors to each perform one or more operations of one or more neural networks based at least in part on two or more non-connected portions of an input sequence. In at least one embodiment, Figure 16 At least one component shown or described is used to perform at least one aspect described with respect to block diagram 100, block diagram 200, block diagram 300, block diagram 400, block diagram 500, block diagram 600, block diagram 700, block diagram 800 and / or other systems, methods, or operations described herein.

[0331] Figure 17AAn exemplary architecture is shown in which a plurality of GPUs 1710(1)-1710(N) are communicatively coupled to a plurality of multi-core processors 1705(1)-1705(M) via high-speed links 1740(1)-1740(N) (e.g., a bus, a point-to-point interconnect, etc.). In at least one embodiment, the high-speed links 1740(1)-1740(N) support 4 GB / s, 30 GB / s, 80 GB / s, or higher communication throughput. In at least one embodiment, various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, "N" and "M" represent positive integers, the values ​​of which may vary from figure to figure. In at least one embodiment, one or more of the plurality of GPUs 1710(1)-1710(N) include, for example, Figure 20A and Figure 20B , one or more graphics cores (also referred to simply as "cores") 2000 disclosed in

[0065] . In at least one embodiment, one or more graphics cores 2000 may be referred to as a streaming multiprocessor ("SM"), a streaming processor ("SP"), a streaming processing unit ("SPU"), a compute unit ("CU"), an execution unit ("EU"), and / or a slice, where, in this context, a slice may refer to a portion of processing resources in a processing unit (e.g., 16 cores, a ray tracing unit, a thread director, or a scheduler).

[0332] Furthermore, in at least one embodiment, two or more GPUs 1710 are interconnected via high-speed links 1729(1)-1729(2), which may be implemented using protocols / links similar to or different from those used for high-speed links 1740(1)-1740(N). Similarly, two or more multi-core processors 1705 may be connected via high-speed link 1728, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, similar protocols / links may be used (e.g., via a common interconnect fabric) to accomplish this. Figure 17A All communications between the various system components shown in .

[0333] In at least one embodiment, each multi-core processor 1705 is communicatively coupled to processor memory 1701(1)-1701(M) via memory interconnects 1726(1)-1726(M), respectively, and each GPU 1710(1)-1710(N) is communicatively coupled to GPU memory 1720(1)-1720(N) via GPU memory interconnects 1750(1)-1750(N), respectively. In at least one embodiment, memory interconnects 1726 and 1750 can utilize similar or different memory access technologies. By way of example and not limitation, processor memory 1701(1)-1701(M) and GPU memory 1720 can be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram. In at least one embodiment, some portion of the processor memory 1701 may be volatile memory, while another portion may be non-volatile memory (eg, using a two-level memory (2LM) hierarchy).

[0334] As described herein, although each multi-core processor 1705 and GPU 1710 can be physically coupled to a specific memory 1701, 1720, respectively, and / or a unified memory architecture can be implemented in which a virtual system address space (also referred to as an "effective address" space) is distributed among the various physical memories. For example, processor memories 1701(1)-1701(M) can each include 64GB of system memory address space, and GPU memories 1720(1)-1720(N) can each include 32GB of system memory address space, resulting in a total of 256GB of addressable memory when M=2 and N=4. Other values ​​of N and M are possible.

[0335] In at least one embodiment, Figure 17A At least one component shown or described is used to perform the combination Figures 1 to 8 In at least one embodiment, the techniques and / or functions described herein are Figure 17A At least one component shown or described with respect to 17A is configured to cause inference of two or more connected portions of information to be distributed only between two or more corresponding processing cores. In at least one embodiment, at least one component shown or described with respect to 17A is configured to cause two or more other processors to each perform one or more operations of one or more neural networks based at least in part on two or more non-connected portions of an input sequence ... Figure 17AAt least one component shown or described is used to perform at least one aspect described with respect to block diagram 100, block diagram 200, block diagram 300, block diagram 400, block diagram 500, block diagram 600, block diagram 700, block diagram 800 and / or other systems, methods, or operations described herein.

[0336] Figure 17B Additional details are shown for the interconnection between the multi-core processor 1707 and the graphics acceleration module 1746 according to an exemplary embodiment. In at least one embodiment, the graphics acceleration module 1746 may include one or more GPU chips integrated on a line card that is coupled to the processor 1707 via a high-speed link 1740 (e.g., a PCIe bus, NVLink, etc.). In at least one embodiment, the graphics acceleration module 1746 may alternatively be integrated on a package or chip with the processor 1707.

[0337] In at least one embodiment, the processor 1707 includes a plurality of cores 1760A-1760D (which may be referred to as "execution units"), each core having a translation lookaside buffer ("TLB") 1761A-1761D and one or more caches 1762A-1762D. In at least one embodiment, the cores 1760A-1760D may include various other components, not shown, for executing instructions and processing data. In at least one embodiment, the caches 1762A-1762D may include level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 1756 may be included in the caches 1762A-1762D and shared by each group of cores 1760A-1760D. For example, one embodiment of the processor 1707 includes 24 cores, each core having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, two consecutive cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1707 and the graphics acceleration module 1746 are connected to the system memory 1714, which may include Figure 17A Processor memory 1701(1)-1701(M) in.

[0338] In at least one embodiment, coherence is maintained for data and instructions stored in the various caches 1762A-1762D, 1756, and system memory 1714 via inter-core communication over a coherence bus 1764. In at least one embodiment, for example, each cache may have cache coherence logic / circuitry associated therewith to communicate over the coherence bus 1764 in response to detecting a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented over the coherence bus 1764 to snoop cache accesses.

[0339] In at least one embodiment, proxy circuitry 1725 communicatively couples graphics acceleration module 1746 to coherence bus 1764, thereby allowing graphics acceleration module 1746 to participate in a cache coherence protocol as a peer of cores 1760A-1760D. In particular, in at least one embodiment, interface 1735 provides connectivity to proxy circuitry 1725 via high-speed link 1740, and interface 1737 connects graphics acceleration module 1746 to high-speed link 1740.

[0340] In at least one embodiment, the accelerator integrated circuit 1736 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 1731(1)-1731(N) of the graphics acceleration module 1746. In at least one embodiment, the graphics processing engines 1731(1)-1731(N) may each include a separate graphics processing unit (GPU). In at least one embodiment, the multiple graphics processing engines 1731(1)-1731(N) of the graphics acceleration module 1746 include, for example, a combination of Figure 20A and Figure 20B The one or more graphics cores 2000 discussed. In at least one embodiment, the graphics processing engines 1731(1)-1731(N) may alternatively include different types of graphics processing engines within a GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module 1746 may be a GPU having multiple graphics processing engines 1731(1)-1731(N), or the graphics processing engines 1731(1)-1731(N) may be individual GPUs integrated on a common package, circuit card, or chip.

[0341] In at least one embodiment, the accelerator integrated circuit 1736 includes a memory management unit (MMU) 1739 for performing various memory management functions, such as virtual to physical memory translation (also known as effective to real memory translation), and a memory access protocol for accessing system memory 1714. In at least one embodiment, the MMU 1739 may also include a translation lookaside buffer ("TLB") (not shown) for caching virtual / effective to physical / real address translations. In at least one embodiment, a cache 1738 may store commands and data for efficient access by the graphics processing engines 1731(1)-1731(N). In at least one embodiment, a fetch unit 1744 may be used to keep data stored in the cache 1738 and graphics memory 1733(1)-1733(M) consistent with the core caches 1762A-2062D, 1756, and system memory 1714. As previously described, this can be implemented on behalf of cache 1738 and memory 1733(1)-1733(M) via proxy circuit 1725 (e.g., sending updates related to modifications / accesses of cache lines on processor caches 1762A-1762D, 1756 to cache 1738 and receiving updates from cache 1738).

[0342] In at least one embodiment, a set of registers 1745 stores context data for threads executed by graphics processing engines 1731(1)-1731(N), and context management circuitry 1748 manages thread contexts. For example, context management circuitry 1748 can perform save and restore operations to save and restore the contexts of various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, context management circuitry 1748 can store current register values ​​to a designated area in memory (e.g., identified by a context pointer) upon context switching. The register values ​​can then be restored upon returning to the context. In at least one embodiment, interrupt management circuitry 1747 receives and processes interrupts received from system devices.

[0343] In at least one embodiment, the MMU 1739 converts virtual / effective addresses from the graphics processing engine 1731 into real / physical addresses in the system memory 1714. In at least one embodiment, the accelerator integrated circuit 1736 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1746 and / or other accelerator devices. In at least one embodiment, the graphics accelerator module 1746 can be dedicated to a single application executing on the processor 1707, or can be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 1731 (1)-1731 (N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, the resources can be subdivided into "slices" that are distributed to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0344] In at least one embodiment, the accelerator integrated circuit 1736 acts as a bridge to the system for the graphics acceleration module 1746 and provides address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuit 1736 can provide virtualization facilities for the host processor to manage virtualization, interrupts, and memory management for the graphics processing engines 1731(1)-1731(N).

[0345] In at least one embodiment, because the hardware resources of graphics processing engines 1731(1)-1731(N) are explicitly mapped into the real address space seen by host processor 1707, any host processor can directly address these resources using effective address values. In at least one embodiment, one function of accelerator integrated circuit 1736 is the physical separation of graphics processing engines 1731(1)-1731(N) so that they appear to the system as independent units.

[0346] In at least one embodiment, one or more graphics memories 1733(1)-1733(M) are coupled to each graphics processing engine 1731(1)-1731(N), respectively, with N=M. In at least one embodiment, graphics memories 1733(1)-1733(M) store instructions and data being processed by each graphics processing engine 1731(1)-1731(N). In at least one embodiment, graphics memories 1733(1)-1733(M) can be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram.

[0347] In at least one embodiment, to reduce data traffic on high-speed link 1740, biasing techniques may be used to ensure that the data stored in graphics memory 1733(1)-1733(M) is the data most frequently used by graphics processing engines 1731(1)-1731(N), and preferably is not used (at least not frequently) by cores 1760A-1760D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep data needed by the cores (and preferably not needed by graphics processing engines 1731(1)-1731(N)) in caches 1762A-1762D, 1756, and system memory 1714.

[0348] In at least one embodiment, Figure 17B At least one component shown or described is used to perform the combination Figures 1 to 8 In at least one embodiment, the techniques and / or functions described herein are Figure 17B At least one component shown or described with respect to FIG17B is configured to cause inference of two or more connected portions of information to be distributed only between two or more corresponding processing cores. In at least one embodiment, at least one component shown or described with respect to FIG17B is configured to cause two or more other processors to each perform one or more operations of one or more neural networks based at least in part on two or more non-connected portions of an input sequence ... Figure 17B At least one component shown or described is used to perform at least one aspect described with respect to block diagram 100, block diagram 200, block diagram 300, block diagram 400, block diagram 500, block diagram 600, block diagram 700, block diagram 800 and / or other systems, methods, or operations described herein.

[0349] Figure 17C Another exemplary embodiment is shown in which an accelerator integrated circuit 1736 is integrated within the processor 1707. In this embodiment, the graphics processing engines 1731(1)-1731(N) communicate directly with the accelerator integrated circuit 1736 via interface 1737 and interface 1735 (again, which can be any form of bus or interface protocol) over a high-speed link 1740. In at least one embodiment, the accelerator integrated circuit 1736 can perform operations related to Figure 17B The operations described above are similar to those described above, but may have higher throughput due to its close proximity to the coherence bus 1764 and caches 1762A-1762D, 1756. In at least one embodiment, the accelerator integrated circuit supports different programming models, including a process-specific programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integrated circuit 1736 and a programming model controlled by the graphics acceleration module 1746.

[0350] In at least one embodiment, graphics processing engines 1731(1)-1731(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 1731(1)-1731(N), thereby providing virtualization within a VM / partition.

[0351] In at least one embodiment, graphics processing engines 1731(1)-1731(N) can be shared by multiple VM / application partitions. In at least one embodiment, the sharing model can use a hypervisor to virtualize graphics processing engines 1731(1)-1731(N) to allow each operating system to access them. In at least one embodiment, for a single partition system without a hypervisor, the operating system owns graphics processing engines 1731(1)-1731(N). In at least one embodiment, the operating system can virtualize graphics processing engines 1731(1)-1731(N) to provide access to each process or application.

[0352] In at least one embodiment, the graphics acceleration module 1746 or individual graphics processing engines 1731(1)-1731(N) use a process handle to select a process element. In at least one embodiment, the process element is stored in system memory 1714 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle can be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engine 1731(1)-1731(N) (i.e., calling system software to add the process element to a linked list of process elements). In at least one embodiment, the lower 16 bits of the process handle can be the offset of the process element in the linked list of process elements.

[0353] In at least one embodiment, Figure 17C At least one component shown or described is used to perform the combination Figures 1 to 8 In at least one embodiment, the techniques and / or functions described herein are Figure 17C At least one component shown or described with respect to 17C is configured to cause inference of two or more connected portions of information to be distributed only between two or more corresponding processing cores. In at least one embodiment, at least one component shown or described with respect to 17C is configured to cause two or more other processors to each perform one or more operations of one or more neural networks based at least in part on two or more non-connected portions of an input sequence ... Figure 17CAt least one component shown or described is used to perform at least one aspect described with respect to block diagram 100, block diagram 200, block diagram 300, block diagram 400, block diagram 500, block diagram 600, block diagram 700, block diagram 800 and / or other systems, methods, or operations described herein.

[0354] Figure 17D An exemplary accelerator integrated slice 1790 is shown. In at least one embodiment, a "slice" comprises a designated portion of the processing resources of the accelerator integrated circuit 1736. In at least one embodiment, the application is an effective address space 1782 in system memory 1714 that stores a process element 1783. In at least one embodiment, the process element 1783 is stored in response to a GPU call 1781 from an application 1780 executing on the processor 1707. In at least one embodiment, the process element 1783 includes the process state of the corresponding application 1780. In at least one embodiment, the work descriptor (WD) 1784 included in the process element 1783 can be a single job requested by the application, or can include a pointer to a job queue. In at least one embodiment, the WD 1784 is a pointer to a job request queue in the effective address space 1782 of the application.

[0355] In at least one embodiment, the graphics acceleration module 1746 and / or the individual graphics processing engines 1731(1)-1731(N) can be shared by all processes or a subset of processes in the system. In at least one embodiment, infrastructure can be included for setting process state and sending WD 1784 to the graphics acceleration module 1746 to start a job in a virtualized environment.

[0356] In at least one embodiment, the process-specific programming model is implementation-specific. In at least one embodiment, in this model, a single process owns either a graphics acceleration module 1746 or an individual graphics processing engine 1731. In at least one embodiment, when a graphics acceleration module 1746 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and when a graphics acceleration module 1746 is assigned, the operating system initializes the accelerator integrated circuit 1736 for the owned process.

[0357] In at least one embodiment, in operation, a WD fetch unit 1791 in the accelerator integrated slice 1790 fetches the next WD 1784, which includes an indication of work to be performed by one or more graphics processing engines of the graphics acceleration module 1746. In at least one embodiment, data from the WD 1784 can be stored in registers 1745 and used by the MMU 1739, interrupt management circuitry 1747, and / or context management circuitry 1748, as shown. For example, one embodiment of the MMU 1739 includes segment / page walk circuitry for accessing segment / page tables 1786 within the OS virtual address space 1785. In at least one embodiment, the interrupt management circuitry 1747 can process interrupt events 1792 received from the graphics acceleration module 1746. In at least one embodiment, when performing graphics operations, effective addresses 1793 generated by the graphics processing engines 1731(1)-1731(N) are converted to real addresses by the MMU 1739.

[0358] In at least one embodiment, registers 1745 are replicated for each graphics processing engine 1731(1)-1731(N) and / or graphics acceleration module 1746 and can be initialized by a hypervisor or operating system. In at least one embodiment, each of these replicated registers can be included in an accelerator integration slice 1790. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0359] Table 1 – Registers initialized by the hypervisor

[0360] Register# Description

[0361] 1 Slice Control Register

[0362] 2 Real Address (RA) Scheduling Process Area Pointer

[0363] 3 Permission Mask Overwrite Register

[0364] 4 Interrupt vector table entry offset

[0365] 5 Interrupt Vector Table Entry Limitations

[0366] 6 Status Register

[0367] 7 Logical Partition ID

[0368] 8 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer

[0369] 9 Storage Description Register

[0370] Example registers that may be initialized by the operating system are shown in Table 2.

[0371] Table 2 – Registers initialized by the operating system

[0372] Register# Description

[0373] 1 Process and thread identification

[0374] 2 Effective Address (EA) context save / restore pointer

[0375] 3 Virtual Address (VA) Accelerator Utilization Record Pointer

[0376] 4 Virtual Address (VA) Segment Table Pointer

[0377] 5. Permission Mask

[0378] 6 Job Descriptors

[0379] In at least one embodiment, each WD 1784 is specific to a particular graphics acceleration module 1746 and / or graphics processing engine 1731(1)-1731(N). In at least one embodiment, it includes all the information needed by the graphics processing engine 1731(1)-1731(N) to complete its work, or it may be a pointer to a memory location where an application has set up a command queue for work to be done.

[0380] In at least one embodiment, Figure 17D At least one component shown or described is used to perform the combination Figures 1 to 8 In at least one embodiment, the techniques and / or functions described herein are Figure 17D At least one component shown or described with respect to 17D is configured to cause inference of two or more connected portions of information to be distributed only between two or more corresponding processing cores. In at least one embodiment, at least one component shown or described with respect to 17D is configured to cause two or more other processors to each perform one or more operations of one or more neural networks based at least in part on two or more non-connected portions of an input sequence. In at least one embodiment, at least one component shown or described with respect to Figure 17D At least one component shown or described is used to perform at least one aspect described with respect to block diagram 100, block diagram 200, block diagram 300, block diagram 400, block diagram 500, block diagram 600, block diagram 700, block diagram 800 and / or other systems, methods, or operations described herein.

[0381] Figure 17E1796 virtualizes the graphics acceleration module engine for the operating system 1795.

[0382] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1746. In at least one embodiment, there are two programming models where the graphics acceleration module 1746 is shared by multiple processes and partitions, namely, time-sliced ​​sharing and graphics-directed sharing.

[0383] In at least one embodiment, in this model, the hypervisor 1796 owns the graphics acceleration module 1746 and makes its functionality available to all operating systems 1795. In at least one embodiment, for the graphics acceleration module 1746 to support virtualization through the hypervisor 1796, the graphics acceleration module 1746 may adhere to certain requirements, such as (1) the application's job requests must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1746 must provide a context save and restore mechanism, (2) the graphics acceleration module 1746 guarantees that the application's job requests are completed within a specified amount of time, including any transition errors, or the graphics acceleration module 1746 provides the ability to preempt job processing, and (3) the graphics acceleration module 1746 must ensure fairness between processes when operating in a directed shared programming model.

[0384] In at least one embodiment, the application 1780 is required to make an operating system 1795 system call using a graphics acceleration module type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1746 and can take the form of a graphics acceleration module 1746 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure that describes the work to be performed by the graphics acceleration module 1746.

[0385] In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to the application that set the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1736 (not shown) and the graphics acceleration module 1746 does not support the User Authority Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1796 may selectively apply the current Authority Mask Override Register (AMOR) value before placing the AMR into the process element 1783. In at least one embodiment, the CSRP is one of the registers 1745 that contains the effective address of an area in the application's effective address space 1782 for the graphics acceleration module 1746 to save and restore context state. In at least one embodiment, this pointer is optional if state does not need to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area may be fixed system memory.

[0386] Upon receiving the system call, the operating system 1795 can verify that the application 1780 has been registered and granted permission to use the graphics acceleration module 1746. Then, in at least one embodiment, the operating system 1795 calls the hypervisor 1796 using the information shown in Table 3.

[0387] Table 3 – OS to Hypervisor call parameters

[0388] Parameter#Description

[0389] 1. Work Descriptor (WD)

[0390] 2. Access Mask Register (AMR) value (may be masked)

[0391] 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP)

[0392] 4. Process ID (PID) and optional thread ID (TID)

[0393] 5Virtual Address (VA) Accelerator Utilization Record Pointer (AURP)

[0394] 6 Virtual address of the storage segment table pointer (SSTP)

[0395] 7. Logical Interrupt Service Number (LISN)

[0396] In at least one embodiment, upon receiving the hypervisor call, hypervisor 1796 verifies that operating system 1795 has registered and been granted permission to use graphics acceleration module 1746. Then, in at least one embodiment, hypervisor 1796 places process element 1783 into a linked list of process elements of the corresponding type of graphics acceleration module 1746. In at least one embodiment, the process element may include the information shown in Table 4.

[0397] Table 4 – Process element information

[0398] Element#Description

[0399] 1. Work Descriptor (WD)

[0400] 2. Access Mask Register (AMR) value (may be masked)

[0401] 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP)

[0402] 4. Process ID (PID) and optional thread ID (TID)

[0403] 5Virtual Address (VA) Accelerator Utilization Record Pointer (AURP)

[0404] 6 Virtual address of the storage segment table pointer (SSTP)

[0405] 7. Logical Interrupt Service Number (LISN)

[0406] 8 Interrupt vector table derived from hypervisor call parameters

[0407] 9 Status register (SR) value

[0408] 10 Logical Partition ID (LPID)

[0409] 11 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer

[0410] 12 Storage Descriptor Register (SDR)

[0411] In at least one embodiment, the hypervisor initializes the plurality of accelerator integrated slice 1790 registers 1745 .

[0412] In at least one embodiment, Figure 17E At least one component shown or described is used to perform the combination Figures 1 to 8 In at least one embodiment, the techniques and / or functions described herein are Figure 17EAt least one component shown or described with respect to 17E is configured to cause inference of two or more connected portions of information to be distributed only between two or more corresponding processing cores. In at least one embodiment, at least one component shown or described with respect to 17E is configured to cause two or more other processors to each perform one or more operations of one or more neural networks based at least in part on two or more non-connected portions of an input sequence. In at least one embodiment, at least one component shown or described with respect to Figure 17E At least one component shown or described is used to perform at least one aspect described with respect to block diagram 100, block diagram 200, block diagram 300, block diagram 400, block diagram 500, block diagram 600, block diagram 700, block diagram 800 and / or other systems, methods, or operations described herein.

[0413] like Figure 17F As shown, in at least one embodiment, a unified memory is used that is addressable via a common virtual memory address space for accessing physical processor memory 1701(1)-1701(N) and GPU memory 1720(1)-1720(N). In this implementation, operations executed on GPUs 1710(1)-1710(N) utilize the same virtual / effective memory address space to access processor memory 1701(1)-1701(M), and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1701(1), a second portion is allocated to second processor memory 1701(N), a third portion is allocated to GPU memory 1720(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memory 1701 and GPU memory 1720, allowing any processor or GPU to access any physical memory using a virtual address that maps to that memory.

[0414] In at least one embodiment, bias / coherency management circuitry 1794A-1794E within one or more MMUs 1739A-1739E ensures cache coherency between the caches of one or more host processors (e.g., 1705) and GPU 1710 and implements biasing techniques that indicate the physical memory where certain types of data should be stored. In at least one embodiment, while Figure 17F Multiple instances of bias / coherence management circuits 1794A- 1794E are shown in , but bias / coherence circuits may be implemented within an MMU of one or more host processors 1705 and / or within an accelerator integrated circuit 1736 .

[0415] One embodiment allows GPU memory 1720 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without the performance drawbacks associated with system-wide cache coherence. In at least one embodiment, the ability to access GPU memory 1720 as system memory without the heavy cache coherence overhead provides a favorable operating environment for GPU offloading. In at least one embodiment, this arrangement allows host processor 1705 software to set operands and access computation results without the overhead of traditional I / O DMA data copying. In at least one embodiment, such traditional copying includes driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU memory 1720 without cache coherence overhead can be critical to the execution time of offloaded computations. In at least one embodiment, for example, in situations with heavy streaming write-to-memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPU 1710. In at least one embodiment, the efficiency of operand setup, result access, and GPU computation can play a role in determining the effectiveness of GPU offloading.

[0416] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table can be used, which can be a page-granular structure (e.g., controlled at the granularity of a memory page) that includes 1 or 2 bits per GPU additional memory page. In at least one embodiment, the bias table can be implemented in a stolen memory range of one or more GPU memories 1720, with or without a bias cache in GPU 1710 (e.g., to cache frequently / recently used entries of the bias table). Alternatively, in at least one embodiment, the entire bias table can be maintained within the GPU.

[0417] In at least one embodiment, the bias table entry associated with each access to GPU-attached memory 1720 is accessed before the GPU memory is actually accessed, resulting in the following operations. In at least one embodiment, local requests from GPU 1710 whose pages are found in the GPU bias are forwarded directly to the corresponding GPU memory 1720. In at least one embodiment, local requests from the GPU whose pages are found in the host bias are forwarded to processor 1705 (e.g., via the high-speed link described herein). In at least one embodiment, requests from processor 1705 that find the requested page in the host processor bias complete the request similarly to a normal memory read. Alternatively, requests directed to GPU-biased pages can be forwarded to GPU 1710. In at least one embodiment, if the GPU is not currently using the page, the GPU can migrate the page to the host processor bias. In at least one embodiment, the bias state of a page can be changed via a software-based mechanism, a hardware-assisted software-based mechanism, or, in a limited set of cases, a purely hardware-based mechanism.

[0418] In at least one embodiment, a mechanism for changing bias states employs an API call (e.g., OpenCL), which in turn calls a device driver for the GPU, which in turn sends a message (or queues a command descriptor) to the GPU, directing the GPU to change the bias state and, in some migrations, to perform a cache flush operation in the host. In at least one embodiment, the cache flush operation is used for migrations from host processor 1705 bias to GPU bias, but not for the reverse migration.

[0419] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages that cannot be cached by host processor 1705. In at least one embodiment, to access these pages, processor 1705 may request access from GPU 1710, which may or may not immediately grant access. Therefore, in at least one embodiment, to reduce communication between processor 1705 and GPU 1710, it is beneficial to ensure that GPU-biased pages are the pages required by the GPU and not the host processor 1705, and vice versa.

[0420] One or more hardware structures 915 are used to execute one or more embodiments. Figure 9A and / or Figure 9B Details regarding one or more hardware structures 915 are provided.

[0421] In at least one embodiment, Figure 17F At least one component shown or described is used to perform the combination Figures 1 to 8In at least one embodiment, the techniques and / or functions described herein are Figure 17F At least one component shown or described with respect to 17F is configured to cause inference of two or more connected portions of information to be distributed only between two or more corresponding processing cores. In at least one embodiment, at least one component shown or described with respect to 17F is configured to cause two or more other processors to each perform one or more operations of one or more neural networks based at least in part on two or more non-connected portions of an input sequence. In at least one embodiment, at least one component shown or described with respect to Figure 17F At least one component shown or described is used to perform at least one aspect described with respect to block diagram 100, block diagram 200, block diagram 300, block diagram 400, block diagram 500, block diagram 600, block diagram 700, block diagram 800 and / or other systems, methods, or operations described herein.

[0422] Figure 18 An exemplary integrated circuit and associated graphics processor according to at least one embodiment described herein is shown, which can be manufactured using one or more IP cores. In addition to the illustrated example, other logic and circuitry can be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0423] Figure 18 is a block diagram illustrating an exemplary system on a chip integrated circuit 1800 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, integrated circuit 1800 includes one or more application processors 1805 (e.g., CPUs), at least one graphics processor 1810, and may additionally include an image processor 1815 and / or a video processor 1820, any of which may be modular IP cores. In at least one embodiment, integrated circuit 1800 includes peripheral or bus logic, including a USB controller 1825, a UART controller 1830, an SPI / SDIO controller 1835, and an I2S / I2C controller 1840. In at least one embodiment, integrated circuit 1800 may include a display device 1845 coupled to one or more of a High-Definition Multimedia Interface (HDMI) controller 1850 and a Mobile Industry Processor Interface (MIPI) display interface 1855. In at least one embodiment, storage may be provided by a flash memory subsystem 1860, which includes flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1865 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1870 .

[0424] Logic 915 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 9A and / or Figure 9B Details are provided regarding logic 915. In at least one embodiment, logic 915 may be used in integrated circuit 1800 to perform inference or prediction operations...

Claims

1. A processor, comprising: One or more circuits for distributing reasoning about two or more connected portions of information only between two or more corresponding processing cores.

2. The processor of claim 1, wherein the one or more circuits are configured to further distribute reasoning about the two or more second connected portions of information only between the two or more corresponding processing cores.

3. The processor of claim 1, wherein a processing core of the first computing device performs reasoning on one or more non-connected portions of the information.

4. The processor of claim 1, wherein the inference is used to train one or more neural networks.

5. The processor of claim 1, wherein a first processing core of the two or more corresponding processing cores is to communicate one or more intermediate results of the inference to a second processing core of the two or more corresponding processing cores.

6. The processor of claim 1, wherein one or more activations of two or more connected portions based at least in part on the information are to be distributed to the two or more corresponding processing cores.

7. The processor of claim 1, wherein the two or more contiguous portions of the information are partitioned based at least in part on resources of the processor.

8. A method comprising: Distribute reasoning about two or more connected portions of information only between two or more corresponding processing cores.

9. The method of claim 8, further comprising: The reasoning on the two or more second connected portions of information is distributed only between the two or more corresponding processing cores.

10. The method of claim 8, wherein the reasoning is performed using a large language model.

11. The method of claim 8, wherein the inference is used to train a large language model.

12. The method of claim 8, wherein a first processing core of the two or more corresponding processing cores is used to pass one or more intermediate results of the reasoning to a second processing core of the two or more corresponding processing cores.

13. The method of claim 8, wherein one or more activations based at least in part on a first portion of two or more contiguous portions of the information are distributed to one or more processing cores to which the first portion of the two or more contiguous portions of the information is distributed.

14. The method of claim 8, wherein the two or more contiguous portions of information are partitioned based at least in part on a set of resources of the two or more respective processing cores.

15. A computer system comprising: One or more processors and memory storing instructions that, when executed by the one or more processors, cause reasoning about two or more connected portions of information to be distributed only between two or more respective processing cores.

16. The computer system of claim 15, wherein the instructions, when executed by the one or more processors, further cause reasoning about two or more second connected portions of information to be distributed only among the two or more corresponding processing cores.

17. The computer system of claim 15, wherein the reasoning is to be performed using a diffusion model.

18. The computer system of claim 15, wherein the inference is used to train a diffusion model.

19. The computer system of claim 15, wherein a first processing core of the two or more corresponding processing cores is configured to communicate one or more intermediate results of the inference to a second processing core of the two or more corresponding processing cores.

20. The computer system of claim 15, wherein one or more activations based at least in part on a first portion of the two or more contiguous portions of the information are to be distributed to one or more processing cores to which the first portion of the two or more contiguous portions of the information is to be distributed.

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