Circuit Structure and Method for Matching Asymmetric Read and Write Currents of STT-MRAM

Abstract

The present invention, belonging to the field of memory technology, discloses a circuit structure and method for matching asymmetric read and write currents in STT-MRAM. The circuit comprises a current matching circuit connected in series between a transition line TL and an STT-MRAM source line SL. The circuit comprises: N connected transistors, where N is greater than or equal to 2; three control signals connected to the gates of one or more transistors: a write "1" operation activation signal WR1, a write "0" operation activation signal WR0, and a read operation activation signal RD. When the N transistors are connected in parallel or in series, the matching circuit satisfies the following conditions: when WR1 is activated, the equivalent resistance of the current matching circuit is R1; when WR0 is activated, the equivalent resistance of the current matching circuit is R2; when RD is activated, the equivalent resistance of the current matching circuit is R3; and R3>R2>R1. This invention can match the current magnitudes of different operations while reducing the area overhead of the matching structure.

Description

Technical Field

[0001] The present invention belongs to the field of memory technology, and more specifically, relates to a circuit structure and method for matching asymmetric read and write currents of STT-MRAM. Background Art

[0002] Spin-transfer torque magnetoresistive random access memory (STT-MRAM) has attracted much attention due to its non-volatility, high endurance, high speed, high density, and long retention time. Its theoretical high density and simple structure lead to lower process costs and have also attracted a lot of attention. However, the magnetic tunnel junction (MTJ), the core device of STT-MRAM, is affected by its magnetization reversal mechanism, energy barriers, and MTJ design and material properties, resulting in inconsistent currents required to write "1" and "0". In addition, to prevent the MTJ from flipping during the read process, the read current is usually set lower than the minimum write current and a certain safety margin must be maintained, which makes the actual required read current much smaller than the write current.

[0003] In the prior art, the current mismatch problem is mainly solved by introducing additional transistors into the bit cell structure composed of a magnetic tunnel junction (MTJ) and transistors. For example, the 2T1MTJ structure can match the different currents required to write "1" and "0", and the 3T2MTJ structure can match different write currents and read currents. However, these designs, on the one hand, cannot completely and simultaneously match the different currents required to write "1" and "0", as well as the different write currents and read currents. On the other hand, and more importantly, the existing designs all design the matching operation from the perspective of the bit cell design, which means that additional transistors need to be integrated into each bit cell. Since the size of the transistor is significantly larger than the size of the magnetic tunnel junction (MTJ), this integration method will lead to a significant reduction in storage density when integrating multiple cells, which is not conducive to small-area integration. Therefore, it is very necessary to study a method that can reduce the area overhead while matching the current size of different operations. Summary of the Invention

[0004] In response to the above-mentioned defects or improvement needs of the prior art, the present invention provides a circuit structure and method for matching the asymmetric read and write currents of STT-MRAM, the purpose of which is to match the current sizes of different operations while reducing the area overhead of the matching structure.

[0005] To achieve the above objectives, according to a first aspect of the present invention, a circuit structure for matching asymmetric read and write currents of an STT-MRAM is provided, comprising a current matching circuit connected in series between a transition line TL and a source line SL of the STT-MRAM. The STT-MRAM includes a bit cell array reference layer, each bit cell in the bit cell array is connected in parallel between a bit line BL of the STT-MRAM and the transition line TL, and the STT-MRAM is powered by a single power supply.

[0006] The current matching circuit includes: N connected transistors, N ≥ 2; wherein a write "1" operation activation signal WR1 is connected to the gate of one or more of the transistors, a write "0" operation activation signal WR0 is connected to the gate of one or more of the transistors, and a read operation activation signal RD is connected to the gate of one or more of the transistors;

[0007] When N transistors are connected in parallel or in series and parallel, the matching circuit satisfies:

[0008] When the WR1 is activated, the equivalent resistance of the current matching circuit is R1;

[0009] When WR0 is activated, the equivalent resistance of the current matching circuit is R2;

[0010] When the RD is activated, the equivalent resistance of the current matching circuit is R3; and R3>R2>R1.

[0011] Furthermore, when N transistors are connected in parallel, or when there is only one transistor in a branch after series-parallel connection, the transition line TL is connected to the source or drain of the branch transistor, and the source line SL is correspondingly connected to the drain or source of the branch transistor;

[0012] When N transistors are connected in parallel, or there are multiple transistors connected in series in a branch after the series-parallel connection, the transition line TL connects the source or drain of the transistor in the branch close to the transition line TL side, and the source line SL connects the source or drain of the transistor in the branch close to the source line SL side.

[0013] Furthermore, when N=3, the current matching circuit includes: three transistors T1-T3 with different width-to-length ratios connected in parallel; wherein the width-to-length ratios of the transistors T1-T3 decrease in sequence;

[0014] The WR1 is connected to the gate of the transistor T1, the WR0 is connected to the gate of the transistor T2, and the RD is connected to the gate of the transistor T3;

[0015] The transition line TL is connected to the source or drain of the transistors T1 - T3 , and the source line SL is correspondingly connected to the drain or source of the transistors T1 - T3 .

[0016] Furthermore, when N=3, the current matching circuit includes: transistors T1-T3; wherein transistors T1 and T2 are connected in series and then connected in parallel with transistor T3;

[0017] The WR1 is connected to the gates of transistors T1-T3, the WR0 is connected to the gate of transistor T3, and the RD is connected to the gates of transistors T1 and T2.

[0018] The transition line TL is connected to the source or drain of the transistor T3, and the source line SL is correspondingly connected to the drain or source of the transistor T3; the transition line TL is also connected to the source or drain of the transistor T1 close to the side of the transition line TL, and the source line SL is also connected to the source or drain of the transistor T2 close to the side of the source line SL.

[0019] Furthermore, when N=2, the current matching circuit includes: two transistors T1 and T2 connected in parallel with different width-to-length ratios, wherein the width-to-length ratio of the transistor T1 is greater than the width-to-length ratio of the transistor T2;

[0020] The WR1 is connected to the gates of transistors T1 and T2, the WR0 is connected to the gate of transistor T1, and the RD is connected to the gate of transistor T2;

[0021] The transition line TL is connected to the source or drain of the transistors T1 and T2 , and the source line SL is connected to the drain or source of the transistors T1 and T2 .

[0022] Furthermore, the bit unit is a bit unit of a 1T1R structure, and the free layer of the magnetic tunnel junction of each bit unit is connected to the bit line BL, and the transistor end of each bit unit is connected to the transition line TL.

[0023] Furthermore, the transistor is NMOS or PMOS.

[0024] According to a second aspect of the present invention, a method for performing asymmetric read and write current matching for STT-MRAM using the circuit structure described in any one of the first aspects is provided, comprising:

[0025] When "1" is written to a specific bit unit, the WR1 is activated;

[0026] When writing "0" to a specific bit unit, the WR0 is activated;

[0027] When data stored in a specific cell is read, the RD is activated.

[0028] According to a third aspect of the present invention, there is provided an STT-MRAM comprising a plurality of bit cell arrays and corresponding current matching circuits;

[0029] Wherein, the current matching circuit is the current matching circuit in the circuit structure described in any one of the first aspects.

[0030] Furthermore, each bit unit in the bit unit array is a bit unit of a 1T1R structure.

[0031] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects:

[0032] (1) The current matching circuit of the present invention adds a transition line TL between the bit line BL and the source line SL of the STT-MRAM, and sets a matching circuit structure between the transition line TL and the source line SL for matching the different current sizes required for different operations of the STT-MRAM. Since the current required for the write "1" operation, the write "0" operation, and the read operation of the STT-MRAM decreases in sequence, when the STT-MRAM is powered by a single power supply, the voltage difference between the bit line BL and the source line SL is the same. Therefore, when the equivalent resistance of the matching circuit is small, the current passing through the MTJ in the bit unit is large. Based on this, when the write "1" operation activation signal WR1, the write "0" operation activation signal WR0, and the read operation activation signal RD connected to the gate of one or more transistors are correspondingly activated, the equivalent resistance of the corresponding matching circuit is set to satisfy R3>R2>R1 (R1, R2, and R3 are the equivalent resistances of the current matching circuit when WR1, WR0, and RD are activated, respectively). This can cause the current passing through the MTJ in the bit cell to decrease accordingly, thereby matching the current required for the STT-MRAM write "1" operation, write "0" operation, and read operation. At the same time, the bit cell array shares a matching circuit, eliminating the need to introduce additional transistors on each bit cell, saving space and significantly reducing area overhead. Especially when performing large-scale integration, the advantages of the current matching circuit structure of the present invention are even more prominent.

[0033] (2) Preferably, when N=3, the structure of the corresponding current matching circuit uses only three transistors to achieve asymmetric current matching for the STT-MRAM composed of a bit cell array, which greatly reduces the area overhead required for matching asymmetric current.

[0034] (3) Preferably, when N=2, the structure of the corresponding current matching circuit uses a minimum number of transistors to achieve asymmetric current matching for the STT-MRAM composed of a bit cell array, thereby minimizing the area overhead required for matching the asymmetric current. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 Schematic diagram of a current matching circuit structure when N=3 in an embodiment of the present invention.

[0036] Figure 2 FIG. 4 is a schematic diagram of another current matching circuit structure when N=3 in an embodiment of the present invention.

[0037] Figure 3 Schematic diagram of a current matching circuit structure when N=2 in an embodiment of the present invention. DETAILED DESCRIPTION

[0038] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only intended to illustrate the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

[0039] Example 1

[0040] like Figure 1 As shown, an embodiment of the present invention provides a circuit structure for matching the asymmetric read and write currents of STT-MRAM, wherein the STT-MRAM includes a bit cell array. In an embodiment of the present invention, the bit cell array is an m*n array composed of bit cells of a 1T1R structure. The 1T1R structure is a bit cell composed of one transistor and one magnetic tunnel junction (MTJ). Each bit cell of the 1T1R structure is connected in parallel between the bit line (BL) and the transition line (TL) of the STT-MRAM to store binary data. Specifically, the reference layer of each MTJ of the 1T1R structure is connected to the bit line BL, and the transistor end of each 1T1R structure is connected to the transition line TL; and the STT-MRAM is powered by a single power supply.

[0041] In an embodiment of the present invention, a current matching circuit is connected in series between the transition line TL and the source line (SL) of the STT-MRAM to match the different current sizes required for different operations (write and read operations on the STT-MRAM). The source line and bit line of the STT-MRAM are used to provide a high level or reference ground during write and read operations to provide current through the magnetic tunnel junction (MTJ). The transition line is used to transitionally connect the bit cell array and the current matching circuit.

[0042] The current matching circuit structure mainly includes: N connected transistors, N≥2; among them, the gate of one or more transistors is connected to the write "1" operation activation signal WR1, the gate of one or more transistors is connected to the write "0" operation activation signal WR0, and the gate of one or more transistors is connected to the read operation activation signal RD.

[0043] When N transistors are connected in parallel, or in series and parallel, the matching circuit satisfies:

[0044] When WR1 is activated, the equivalent resistance of the current matching circuit is R1;

[0045] When WR0 is activated, the equivalent resistance of the current matching circuit is R2;

[0046] When RD is activated, the equivalent resistance R3 of the current matching circuit is R3; and R3>R2>R1.

[0047] In the embodiment of the present invention, the transistor of the current matching circuit can be NMOS or PMOS. When it is NMOS, the corresponding signal is activated when the transistor inputs a high level; when it is PMOS, the corresponding signal is activated when the transistor inputs a low level.

[0048] It should be noted that since the parameters of the MTJ selected by STT-MRAM vary greatly, in actual applications, the equivalent resistances R1-R3 can be accurately designed according to the parameters of the MTJ to match the different current sizes required for different operations.

[0049] Specifically, when N transistors are connected in parallel, or when there is only one transistor in a branch after N transistors are connected in series and parallel, the transition line TL connects the source or drain of the branch transistor, and the source line SL connects the drain or source of the branch transistor accordingly. That is, when the transition line TL connects the source of the branch transistor, the source line SL connects the drain of the branch transistor accordingly, and when the transition line TL connects the drain of the branch transistor, the source line SL connects the source of the branch transistor accordingly. When N transistors are connected in parallel, or when there are multiple transistors connected in series in a branch after N transistors are connected in series and parallel, the transition line TL connects the source or drain of the transistor in the branch close to the transition line TL side, and the source line SL connects the source or drain of the transistor in the branch close to the source line SL side.

[0050] As a preferred implementation, when N=3, as Figure 1The current matching circuit structure shown in the dashed box includes three transistors T1-T3 with different width-to-length ratios connected in parallel. The width-to-length ratios of transistors T1-T3 decrease sequentially. A write-"1" activation signal WR1 is connected to the gate of transistor T1, a write-"0" activation signal WR0 is connected to the gate of transistor T2, and a read-operation activation signal RD is connected to the gate of transistor T3. The three transistors are connected in parallel to form three branches, each containing only one transistor. A transition line TL connects the source or drain of T1-T3, and a source line SL connects the drain or source of T1-T3 accordingly. Because the width-to-length ratios of T1-T3 decrease sequentially, when transistors T1-T3 are connected in parallel, the equivalent resistance of the current matching circuit satisfies R3>R2>R1 when WR1, WR0, and RD are activated.

[0051] As a preferred implementation, when N=3, as Figure 2 As shown, the current matching circuit consists of three transistors T1-T3 connected in series and in parallel. Specifically, transistors T1 and T2 are connected in series and then in parallel with transistor T3. The write "1" operation activation signal WR1 is connected to the gates of T1-T3 simultaneously, the write "0" operation activation signal WR0 is connected to the gate of transistor T3, and the read operation activation signal RD is connected to the gates of transistors T1 and T2 simultaneously. For the branch containing only transistor T3, the transition line TL is connected to the source or drain of transistor T3, and the source line SL is connected to the drain or source of transistor T3 accordingly. For the branch containing both transistors T1 and T2 in series, the transition line TL is connected to the source or drain of transistor T1 on the side closest to the transition line TL, and the source line SL is connected to the source or drain of transistor T2 on the side closest to the source line SL. Because the equivalent resistance of the transistors connected in parallel is less than the resistance of the transistors between the parallel connections, the above connection method can ensure that when WR1, WR0, and RD are activated, the equivalent resistance of the current matching circuit satisfies R3>R2>R1.

[0052] In the above two specific implementations, only three transistors are used to achieve asymmetric current matching for the STT-MRAM composed of m*n bit cells, which greatly reduces the area overhead required for matching the asymmetric current.

[0053] As a preferred implementation, when N=2, Figure 3As shown, the current matching circuit includes two parallel transistors T1 and T2 with different width-to-length ratios, wherein the width-to-length ratio of transistor T1 is greater than that of transistor T2; a write "1" operation activation signal WR1 is connected to the gates of transistors T1 and T2 simultaneously, a write "0" operation activation signal WR0 is connected to the gate of transistor T1, and a read operation activation signal RD is connected to the gate of transistor T2; the two transistors are connected in parallel to form two branches, each branch having only one transistor, a transition line TL connecting the source or drain of transistors T1 and T2, and a source line SL correspondingly connecting the drain or source of transistors T1 and T2. Through the above connection method, when WR1, WR0, and RD are correspondingly activated, the equivalent resistance of the current matching circuit satisfies R3>R2>R1, and asymmetric current matching is achieved for an STT-MRAM consisting of m*n bit cells using a minimum number of transistors, minimizing the area overhead required for matching asymmetric currents.

[0054] The current matching circuit of the present invention adds a transition line TL between the bit line BL and the source line SL of an STT-MRAM, and sets a matching circuit structure between the transition line TL and the source line SL to match the different currents required for different STT-MRAM operations. Since the currents required for the STT-MRAM write "1" operation, write "0" operation, and read operation decrease in sequence, when the STT-MRAM is powered by a single power supply, the voltage difference between the bit line BL and the source line SL is the same. Therefore, when the equivalent resistance of the matching circuit is small, the current passing through the MTJ in the bit cell is large. Based on this, when the write "1" operation activation signal WR1, the write "0" operation activation signal WR0, and the read operation activation signal RD connected to the gate of one or more transistors are correspondingly activated, the equivalent resistance of the corresponding matching circuit is set to satisfy R3>R2>R1, which can cause the current passing through the MTJ in the bit cell to decrease in sequence, thereby matching the currents required for the STT-MRAM write "1" operation, write "0" operation, and read operation. At the same time, since m*n bit units share a matching circuit, there is no need to introduce additional transistors in each bit unit, which saves space and significantly reduces area overhead. The matching circuit structure of the present invention has more prominent advantages, especially in large-scale integration.

[0055] Example 2

[0056] An embodiment of the present invention provides a method for performing asymmetric read and write current matching of STT-MRAM using the current matching circuit in the above-mentioned embodiment 1, comprising:

[0057] When writing “1” to a specific bit cell, the word line corresponding to the specific bit cell in the bit cell array is activated, e.g. Figure 1The middle word line WLx is activated, that is, the bit unit corresponding to the word line WLx is activated. At this time, the write "1" operation activation signal WR1 is activated, and all transistors with gates connected to WR1 in the current matching circuit are activated. The current generated in the current matching circuit is consistent with the current required for the corresponding write "1" operation, which can allow a larger write current to pass through a specific bit unit.

[0058] When writing "0" to a specific bit cell, the word line corresponding to the specific bit cell in the bit cell array is activated. At this time, the write "0" operation activation signal WR0 is activated, and all transistors with gates connected to WR0 in the current matching circuit are activated. The current matching circuit generates a current that is consistent with the current required for the corresponding write "0" operation, allowing a smaller write current to pass through the specific bit cell.

[0059] When reading data stored in a specific cell, the word line corresponding to the specific bit cell in the bit cell array is activated. At this time, the read operation activation signal RD is activated, and all transistors with gates connected to RD in the current matching circuit are activated. The current matching circuit generates a current consistent with the current required for the corresponding read operation, allowing the minimum read current to pass through the specific bit cell.

[0060] Example 3

[0061] An embodiment of the present invention provides an STT-MRAM, comprising a plurality of bit cell arrays and the current matching circuit in the above-mentioned embodiment 1, wherein one current matching circuit corresponds to one bit cell array to match different current sizes required for write and read operations.

[0062] For the related technical solutions, please refer to the corresponding description in Example 1 and will not be repeated here.

[0063] It will be easily understood by those skilled in the art that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A circuit structure for matching asymmetric read and write currents of STT-MRAM, characterized in that: A current matching circuit is connected in series between a transition line TL and a source line SL of an STT-MRAM, wherein the STT-MRAM includes a bit cell array, each bit cell in the bit cell array is connected in parallel between a bit line BL of the STT-MRAM and the transition line TL, and the STT-MRAM is powered by a single power supply; The current matching circuit includes: N connected transistors, N ≥ 2; wherein a write "1" operation activation signal WR1 is connected to the gate of one or more of the transistors, a write "0" operation activation signal WR0 is connected to the gate of one or more of the transistors, and a read operation activation signal RD is connected to the gate of one or more of the transistors; When N transistors are connected in parallel or in series and parallel, the matching circuit satisfies: When the WR1 is activated, the equivalent resistance of the current matching circuit is R1; When WR0 is activated, the equivalent resistance of the current matching circuit is R2; When the RD is activated, the equivalent resistance of the current matching circuit is R3; and R3>R2>R1; When N transistors are connected in parallel, or there is only one transistor in a branch after series-parallel connection, the transition line TL is connected to the source or drain of the branch transistor, and the source line SL is correspondingly connected to the drain or source of the branch transistor; When N transistors are connected in parallel, or there are multiple transistors connected in series in a branch after the series-parallel connection, the transition line TL connects the source or drain of the transistor in the branch close to the transition line TL side, and the source line SL connects the source or drain of the transistor in the branch close to the source line SL side.

2. The circuit structure according to claim 1, wherein: When N=3, the current matching circuit includes: three transistors T1-T3 with different width-to-length ratios connected in parallel; wherein the width-to-length ratios of the transistors T1-T3 decrease in sequence; The WR1 is connected to the gate of the transistor T1, the WR0 is connected to the gate of the transistor T2, and the RD is connected to the gate of the transistor T3; The transition line TL is connected to the source or drain of the transistors T1 - T3 , and the source line SL is correspondingly connected to the drain or source of the transistors T1 - T3 .

3. The circuit structure according to claim 1, wherein: When N=3, the current matching circuit includes transistors T1-T3; wherein transistors T1 and T2 are connected in series and then connected in parallel with transistor T3; The WR1 is connected to the gates of transistors T1-T3, the WR0 is connected to the gate of transistor T3, and the RD is connected to the gates of transistors T1 and T2. The transition line TL is connected to the source or drain of the transistor T3, and the source line SL is correspondingly connected to the drain or source of the transistor T3; the transition line TL is also connected to the source or drain of the transistor T1 close to the side of the transition line TL, and the source line SL is also connected to the source or drain of the transistor T2 close to the side of the source line SL.

4. The circuit structure according to claim 1, wherein: When N=2, the current matching circuit includes: two parallel-connected transistors T1 and T2 with different width-to-length ratios, wherein the width-to-length ratio of the transistor T1 is greater than the width-to-length ratio of the transistor T2; The WR1 is connected to the gates of transistors T1 and T2, the WR0 is connected to the gate of transistor T1, and the RD is connected to the gate of transistor T2; The transition line TL is connected to the source or drain of the transistors T1 and T2 , and the source line SL is connected to the drain or source of the transistors T1 and T2 .

5. The circuit structure according to claim 1, wherein: The bit cells are bit cells of a 1T1R structure, and the free layer of the magnetic tunnel junction of each bit cell is connected to the bit line BL, and the transistor end of each bit cell is connected to the transition line TL.

6. The circuit structure according to claim 1, wherein: The transistor is NMOS or PMOS.

7. A method for performing asymmetric read and write current matching of STT-MRAM using the circuit structure according to any one of claims 1 to 6, characterized in that: include: When "1" is written to a specific bit unit, the WR1 is activated; When "0" is written to a specific bit unit, the WR0 is activated; When data stored in a specific cell is read, the RD is activated.

8. An STT-MRAM, characterized in that: comprising a plurality of bit unit arrays and corresponding current matching circuits; Wherein, the current matching circuit is the current matching circuit in the circuit structure according to any one of claims 1 to 6.

9. The STT-MRAM according to claim 8, wherein: Each bit unit in the bit unit array is a bit unit of a 1T1R structure.

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