Reading circuit and method based on three-transistor memory

Abstract

The invention discloses a readout circuit and a readout method based on a three-transistor memory. The reading circuit comprises a three-transistor storage unit, a transmission gate switch, a CMOS (Complementary Metal Oxide Semiconductor) inverter and an inverter chain with driving capability, the output end of the three-transistor storage unit is respectively connected with the input end of the transmission gate switch and the input end of the CMOS phase inverter; the output end of the transmission gate switch is connected to a level VP and the CMOS inverter. The output end of the CMOS inverter is connected with the input end of the inverter chain, and the output end of the inverter chain outputs digital signals. The parallel read-out circuit is simple in structure, small in occupied area, high in read-out speed, low in power consumption and suitable for parallel read-out operation of a large-scale memory array.

Description

Technical Field

[0001] The invention relates to a high-efficiency readout circuit designed for a three-transistor memory device and a three-transistor memory array, and belongs to the field of analog integrated circuits. Background Art

[0002] As an important component of modern integrated circuits, on-chip cache usually adopts static random access memory (SRAM) technology. SRAM has high read and write speeds and good data retention capabilities, so it is widely used in many high-performance applications. However, the SRAM cell structure is complex and occupies a large silicon wafer area, resulting in high manufacturing costs, especially in large-scale on-chip cache. Therefore, how to reduce the cost of on-chip cache while ensuring performance has become a key technical problem.

[0003] In order to solve the high cost problem, patent application CN118629456A proposed a three-transistor memory technology. Compared with traditional SRAM, the three-transistor memory is an embedded DRAM (eDRAM) device with an area of ​​up to 16F. 2 , significantly smaller than SRAM's 150F 2 Compared with other types of eDRAM, it has a small area, low operating voltage, large dynamic range, and strong weight retention capability. Therefore, the three-transistor memory can achieve stable operation at a lower operating voltage, reducing overall power consumption; it can support a larger voltage dynamic range and is suitable for a variety of application scenarios; within a certain period of time, it can effectively maintain the written weight, and the weight retention time reaches seconds or even longer.

[0004] Due to these advantages, three-transistor memory performs well in some applications that do not need to retain data for a long time, especially in inter-layer pipeline applications in storage and computing integrated architectures, where it can quickly and flexibly access data and is suitable for short-term data storage and processing. This allows three-transistor memory to reduce on-chip cache costs while providing a new solution for efficient storage and computing.

[0005] However, despite these advantages of three-transistor memory, current technology still lacks a high-speed, low-power readout circuit that can fully adapt to the characteristics of three-transistor memory. In many application scenarios, the speed and power consumption of the readout circuit directly affect the performance of the entire system, while the traditional readout circuit design, such as the 1T1C DRAM readout circuit, precharges the bit line to a certain voltage through a precharge circuit, and then amplifies the voltage difference of the storage cell through a sense amplifier. Its readout speed is limited by its precharge process and cannot fully meet the requirements of parallel readout and high-speed operation. These deficiencies are particularly evident in areas with higher performance requirements. For example, in an integrated storage and computing architecture, the readout circuit needs to process a large amount of data at the same time and perform frequent read and write operations. These limitations of the readout circuit design limit its application in more high-performance fields, such as the Internet of Things, artificial intelligence, mobile devices, and other scenarios that require efficient and low-power storage. Summary of the invention

[0006] The present invention provides a readout circuit and method for efficiently reading out the weights of a three-transistor memory device. Through optimized design, the circuit has the characteristics of high speed and low power consumption and is particularly suitable for parallel readout operations in a three-transistor memory array, thereby solving the speed and power consumption bottleneck problems of the readout circuit in the prior art.

[0007] The technical solution adopted by the circuit of the present invention is:

[0008] A readout circuit based on a three-transistor memory comprises a three-transistor storage unit, a transmission gate switch, a CMOS inverter and an inverter chain with driving capability; the output end of the three-transistor storage unit is respectively connected to the input end of the transmission gate switch and the input end of the CMOS inverter; the output end of the transmission gate switch is respectively connected to a level VP and a CMOS inverter; the output end of the CMOS inverter is connected to the input end of the inverter chain, and the output end of the inverter chain outputs a digital signal.

[0009] The present invention also provides a working method using the above-mentioned readout circuit based on a three-transistor memory, wherein the readout circuit includes two working stages: a standby stage φ1 and a readout stage φ2; when in the standby stage φ1, the transmission gate switch of the readout circuit is turned on, so that the drain voltage of the electronic readout tube of the three-transistor storage unit maintains a positive level VP, and the digital signal output through the CMOS inverter and the inverter chain is 0; when in the readout stage φ2, the transmission gate switch of the readout circuit is turned off, and according to the different weights of the electronic readout tube of the three-transistor storage unit, two different digital outputs are generated at the output end of the inverter chain: if the weight is 1, the voltage at the input end of the CMOS inverter is zero, and the digital signal output through the CMOS inverter and the inverter chain is 1; if the weight is 0, the voltage at the input end of the CMOS inverter is a positive level VP, and the digital signal output through the CMOS inverter and the inverter chain is 0.

[0010] The present invention also provides a chip based on a three-transistor memory, including the above-mentioned readout circuit, wherein the chip includes an array composed of M×N three-transistor storage units, wherein the drain ends of the electron write tubes of all three-transistor storage units in each column are connected to the same bit line, and their source ends are connected to the same source line; the gate ends of the three-transistor storage units in each row are connected to the same word line to form a cross structure; the bit lines of each column are respectively connected to the input ends of the CMOS inverters in the readout circuit, and N readout circuits are configured for parallel readout of N columns of storage units.

[0011] The present invention also provides a working method using the above-mentioned chip based on three-transistor memory, which includes: when array reading is not performed, the word line voltage of each row is set to 0 level, and the outputs of all readout circuits are low level, indicating that the array is not read out; when array reading is performed, a readout pulse is applied to the word line of the selected row, the pulse width is the time required to read the weight value, and the pulse height is the readout voltage; when the storage cells of a certain row are read out, the weight values ​​of its N columns of storage cells are read out in parallel through N readout circuits; after the readout of the row is completed, the next readout operation can be performed in the same way.

[0012] Compared with the prior art, the present invention has the following beneficial effects:

[0013] (1) Fast readout speed. By adopting a design combining a transmission gate and a CMOS inverter in the readout circuit, the present invention realizes fast detection and conversion of the state of a three-transistor memory device. The readout circuit can meet the parallel readout requirements of multiple cells in a memory array, effectively improving the readout speed of the entire storage system, and is particularly suitable for large-scale array applications.

[0014] (2) Low power consumption. The transmission gate of the present invention fixes the drain voltage of the three-transistor memory at a positive level VP during the non-reading cycle, thereby avoiding unnecessary current leakage and greatly reducing static power consumption. In addition, during the reading cycle, the circuit achieves low-power operation through simplified logic control, making the circuit very suitable for power-sensitive application scenarios, especially in mobile devices and embedded systems.

[0015] (3) Suitable for large-scale array parallel operation. The present invention provides a parallel readout scheme suitable for a three-transistor memory array. By connecting the bit line of each column to an independent readout circuit, N memory cells in the entire memory array can be read out in parallel at the same time. This parallel readout architecture greatly improves the readout efficiency of the array and is particularly suitable for fast readout operations of large-scale memory arrays.

[0016] (4) Simple circuit design and low cost. Compared with the existing high-cost SRAM solution, the design structure of the three-transistor memory and readout circuit of the present invention is simpler, occupies a small area, and has a low manufacturing cost. This not only solves the problem of high on-chip cache cost in the prior art, but also provides a competitive storage solution without sacrificing performance, which is suitable for large-scale integrated circuit applications.

[0017] (5) Wide application. The present invention is suitable for application scenarios of short-term data retention and fast access, especially in the pipeline operation of the storage and computing integrated architecture, and can efficiently complete the storage and reading of inter-layer data. In addition, the readout circuit of the present invention can also be used in various electronic devices that require high-speed, low-power storage, including but not limited to embedded systems, Internet of Things devices and mobile devices.

[0018] In summary, the present invention provides an efficient and low-cost three-transistor memory readout circuit, which can significantly improve the readout speed and reduce power consumption. It is particularly suitable for large-scale parallel readout operations, solves a series of problems in the prior art, and has broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a structural schematic diagram of the readout circuit of the present invention;

[0020] Figure 2 It is a schematic diagram of the structure of the buffer in the readout circuit of the present invention;

[0021] Figure 3 It is a schematic diagram of the structure of the three-transistor memory array of the present invention. DETAILED DESCRIPTION

[0022] The technical solution of the present invention will be described in more detail below with reference to the accompanying drawings.

[0023] Figure 1 The present invention provides a schematic diagram of a high-efficiency readout circuit based on a three-transistor memory, which includes a three-transistor memory cell 1, a transmission gate switch 2, a CMOS inverter 3, and an inverter chain 4 with driving capability. The output end of the three-transistor memory cell 1 is respectively connected to the input end of the transmission gate switch 2 and the input end of the CMOS inverter 3; the output end of the transmission gate switch 2 is connected to the level VP; the output end of the CMOS inverter 3 is connected to the input end of the inverter chain 4, and the output end of the inverter chain 4 outputs a digital signal.

[0024] In this embodiment, the three-transistor storage unit 1 (3T memory) is composed of three MOS transistors, namely, an electron collection tube, an electron write tube and an electron read tube. Among them, the electron write tube is used to erase the weight into the electron collection tube; the electron collection tube is used to collect electrons transmitted from the drain end of the electron write tube, and couple and control the floating gate potential. The electron collection tube changes the threshold voltage of the electron read tube according to the number of electrons erased by the electron write tube, thereby realizing the writing of the storage weight; the electron read tube reads different sizes of source-drain current through different floating gate potentials, that is, reads the weight. In this embodiment, the threshold voltage of the electron read tube is changed by the number of electrons erased by the electron collection tube and the electron write tube, thereby realizing the writing and storage of the weight. The circuit structure has the characteristics of small area, low operating voltage, and long weight maintenance time, and is particularly suitable for short-term data storage and processing in the on-chip cache and storage-computing integrated architecture. The three-transistor storage unit 1 includes six ports: the drain terminal WBL of the electron write tube, the gate terminal WWL of the electron write tube, the gate terminal RWL of the electron collection tube, the drain terminal RBL of the electron read tube, the source terminal RSL of the electron read tube and the substrate Sub; in the read mode, the gate terminal WWL is connected to a negative voltage to turn off the electron write tube, the drain terminal WBL is floating, the gate terminal RWL is connected to a positive voltage for series capacitor voltage division, and the substrate Sub is a negative voltage.

[0025] The drain end RBL of the electronic readout tube of the three-transistor storage unit 1 is connected to the input end of the transmission gate switch 2 and the input end of the CMOS inverter 3 as the output end of the unit. The transmission gate switch 2 includes a P-type doped MOSFET (called PMOS) and an N-type doped MOSFET (called NMOS). The positive clock control signal CLK and the negative clock control signal CLK_N are respectively applied to the gates of the NMOS and PMOS of the transmission gate switch 2 to control the on and off states of the transmission gate. The input end of the transmission gate switch 2 is connected to the drain end of the electronic readout tube of the three-transistor storage unit 1, and the output end is connected to the fixed level VP and the CMOS inverter 3 respectively. The CMOS inverter 3 includes an NMOS and a PMOS, and its input end is connected to the drain end of the electronic readout tube of the three-transistor storage unit 1, and the output end is connected to the inverter chain 4 (BUFFER). The output end of the inverter chain 4 with driving capability is output as a digital signal. In addition to the device driving voltage, there is an external connection voltage in the circuit: VP, which is connected to the output end of the transmission gate switch 2 and is used as the power supply voltage of the CMOS inverter 3 and the inverter chain 4 with driving capability.

[0026] Specifically, the transmission gate switch 2 includes a pair of parallel PMOS and NMOS, whose drain terminals are connected as outputs to the positive level VP, and whose sources are connected as input terminals to the drain terminal of the electronic readout tube of the three-transistor storage unit 1, the gate of the NMOS is connected to the positive clock control signal CLK, and the gate of the PMOS is connected to the negative clock control signal CLK_N, and the width-to-length ratio of each of the two tubes is the inverse of the ratio of the hole to the electron mobility (typical value is 2.5:1), so as to ensure that the on-resistance of the transmission gate switch remains basically unchanged for different VP voltages. The switching state of the transmission gate switch 2 is controlled by two logic control signals CLK and CLK_N, so as to ensure that the drain voltage of the three-transistor memory is fixed at VP during the non-readout cycle, so as to avoid the interference of different threshold states on the drain voltage, thereby improving the readout accuracy.

[0027] The CMOS inverter 3 includes a pair of PMOS and NMOS connected in series, the source of the PMOS is connected to the output end of the transmission gate switch 2 and the voltage VP, the source of the NMOS is connected to 0 potential, the gates of the two are connected as the input end connected to the drain end of the electronic readout tube of the three-transistor storage unit 1, and the drains of the two are connected as the output end of the CMOS inverter 3, and the width-to-length ratio of the two tubes is the inverse of the ratio of the hole to the electron mobility (typical value is 2.5:1), so as to ensure that when the input and output ends are both at the intermediate level (0.5*VP), the two tubes are in the saturation working area. By detecting the drain voltage of the electronic readout tube, the CMOS inverter 3 can output the corresponding logic level under different threshold voltage states of the electronic readout tube to characterize the switch state of the three-transistor memory.

[0028] The inverter chain 4 with driving capability has a structure as shown in FIG. Figure 2 , used to enhance the driving capability of the signal and ensure the stability and quality of the output signal. Inverter chain 4 is composed of 4 inverters in cascade. Each inverter is composed of a PMOS and an NMOS in series like CMOS inverter 3. The gate ends of the two are connected as inputs and the drain ends are connected as outputs for further data processing or driving of downstream circuits; the source end of the PMOS is connected to the high potential VP, and the source end of the NMOS is grounded. The size ratio of the gate width to the gate length of these four inverters is roughly 1:2.8:8:22.6. Such a size ratio of the inverter chain meets the optimal fan-out ratio of the inverter chain, which can minimize the transmission delay. The size of the first-stage inverter can be roughly consistent with the size of CMOS inverter 3. The threshold voltage of NMOS in inverter chain 4 should be greater than or equal to 0.5*VP, and the absolute value of the threshold voltage of PMOS should be less than or equal to 0.5*VP. If the threshold cannot be adjusted to meet the above requirements, it is necessary to increase the width-to-length ratio of the PMOS tube to several times (5-10 times) of the width-to-length ratio of the NMOS tube to improve the pull-up capability of the PMOS tube when the input intermediate level is high. The input terminal of the first stage inverter is connected to the output terminal of the CMOS inverter 3, and the output terminal of the last stage inverter is output as a digital signal. For an input level of potential VP, the inverter chain 4 outputs a 0V level; for an input level of potential 0V, the inverter chain 4 outputs a VP level.

[0029] The specific working mode of the efficient readout circuit based on the three-transistor memory of this embodiment is described below:

[0030] There are two external connection voltages in the circuit: the first voltage VP can be a positive voltage of 0.6 to 1.2V, which is used as the power supply voltage of the CMOS inverter 3 and the inverter chain 4, and is connected to the output end of the transmission gate switch 2; the voltages at each port of the device have no fixed values, and can meet the readout requirements of the embodiment.

[0031] During the operation of the circuit, the switch enable signal is divided into two time periods: φ1 and φ2. During the time period when the enable signal is φ1, the transmission gate switch 2 is turned on (called the φ1 phase), and during the time period when the enable signal is φ2, the transmission gate switch 2 is turned off (called the φ2 phase), that is, the φ1 phase is the standby phase, and the φ2 phase is the readout phase.

[0032] In the φ1 phase, when the control signal CLK is high, the CLK_N signal is low, and the transmission gate switch 2 is turned on, the drain voltage of the electronic readout tube of the three-transistor storage unit 1 is kept at a positive level VP to avoid the drain voltage fluctuation caused by the threshold voltage difference. The digital signal output by the CMOS inverter 3 and the inverter chain 4 is 0, and the circuit is in standby state. However, since the entire circuit is in standby state at this time, the output signal is meaningless. Therefore, it can be ignored.

[0033] In the φ2 phase, when the control signal CLK is at a low level, the CLK_N signal is at a high level, the transmission gate switch 2 is closed, and the circuit enters the read state. The drain voltage of the electronic readout tube of the three-transistor storage unit 1 changes with its threshold voltage state. The drain voltage is detected by the CMOS inverter 3, and then the corresponding logic signal is output to represent the state of the storage unit. According to the different weights of the electronic readout tube of the three-transistor storage unit 1, two different digital outputs are generated at the output end of the inverter chain 4: if the weight is 1, that is, the threshold voltage of the electronic readout tube is low, the applied readout gate voltage is sufficient to make the device channel inverted, and the electrons can move along the electric field direction through the device channel to discharge the charge stored in the inverter gate capacitor connected to the drain end, so that the input voltage of the CMOS inverter 3 is 0, and the level output through the CMOS inverter 3 and the inverter chain 4 is VP; if the device weight is 0, that is, the threshold voltage of the electronic readout tube is high, the applied readout gate voltage is insufficient to make the device channel inverted, and the charge stored in the gate capacitor of the CMOS inverter 3 does not have a low-resistance discharge path, and the input end of the CMOS inverter 3 will be maintained at a positive level VP for a long time, and the level output through the CMOS inverter 3 and the inverter chain 4 is 0.

[0034] Generally, the transmission gate switch 2 is in the φ1 stage, that is, standby. When reading is required, it enters the φ2 stage. In other words, φ1 and φ2 are performed alternately.

[0035] Example 2

[0036] Figure 3 Schematic diagram of the structure of a three-transistor memory array. In this embodiment, the three-transistor memory device is arranged in the form of an M×N array, and each memory cell in the array is composed of the structure of the three-transistor memory cell 1 in Example 1. The drain terminal RBL, source terminal RSL and gate terminal RWL of each memory cell are respectively connected to the bit line (BL), source line (SL) and word line (WL), forming a cross-structured memory array. The bit line (BL) of each column in the array is connected to a readout circuit.

[0037] In the M×N memory array: the drains of the electronic readout tubes of all three-transistor memory cells in the same column share a bit line BL, which is used to transfer the readout voltage of the memory cells in each column to the corresponding readout circuit during the readout process. The source terminals of all three-transistor memory cells in the same column are connected to the same source line SL, which is used to provide a fixed level. The gate terminals of all three-transistor memory cells in the same row are connected to the same word line WL, which is used to control the read and write operations of the memory cells. In order to improve the readout efficiency of the array, N readout circuits are configured for parallel readout of N columns of memory devices, and each column bit line (BL) is connected to the input terminal of an independent readout circuit CMOS inverter, that is, the three-transistor memory device in each column reads data through an independent CMOS inverter and BUFFER. A total of N independent readout circuits are configured, and each readout circuit corresponds to a bit line, forming a parallel readout structure, which greatly improves the readout efficiency of the array.

[0038] The specific working method of the array-level readout of the high-efficiency readout circuit based on the three-transistor memory array of this embodiment is described below:

[0039] In the non-read state, the voltage on all word lines (WL) is set to 0V (low level). At this time, the gate voltage of the electron collector of the three-transistor memory cell is not enough to turn on the memory cell, and all memory devices remain in the off state. Since the bit line (BL) is connected to the transmission gate switch, the output of each read circuit remains at a low level, and the entire memory array is in a standby state.

[0040] When entering the read operation, the control logic applies a pulse voltage to the word line (WL) of a specific row. The height of the pulse is the operation voltage required for reading, and the duration of the pulse is the time window of the read operation.

[0041] When a row of memory devices is selected, a pulse voltage is applied to the word line (WL) of the row, so that the memory devices of the row are in the read state. At the same time, the transmission gate is closed, and the drain voltage of each memory device on the bit line (BL) changes according to the threshold voltage state of the memory device, and enters the CMOS inverter for signal processing. The CMOS inverter converts different input voltages into corresponding logic levels (0 or 1). The memory cell with a lower threshold voltage will turn on, the drain voltage drops to nearly 0V, and the output high-level signal indicates the "1" state; the memory cell with a higher threshold voltage will not turn on, the drain voltage remains at a high level, and the output low-level signal indicates the "0" state.

[0042] In this array, since each column of bit lines (BL) is connected to an independent readout circuit, when the memory cells in the same row are read out, the weights of the N columns of memory cells can be read out in parallel through N readout circuits, which greatly improves the readout efficiency. Each readout operation can complete the weight reading of an entire row, and repeating the operation N times can complete the weight reading of all memory cells in the entire N×N array.

[0043] After the read operation of a row of memory cells is completed, the control logic restores the word line (WL) voltage of the row to 0V, and applies a pulse voltage to the word line of the next row to continue the read operation of the next row. By operating each row in sequence, the weights of all memory cells in the array can be read in parallel.

[0044] The array structure of this embodiment not only improves the readout efficiency, but also significantly reduces power consumption, and is suitable for high-performance, low-power storage and computing integrated application scenarios.

Claims

1. A readout circuit based on a three-transistor memory, characterized in that: The readout circuit comprises a three-transistor storage unit, a transmission gate switch, a CMOS inverter and an inverter chain with driving capability; the output end of the three-transistor storage unit is respectively connected to the input end of the transmission gate switch and the input end of the CMOS inverter; the output end of the transmission gate switch is respectively connected to the level VP and the CMOS inverter; the output end of the CMOS inverter is connected to the input end of the inverter chain, and the output end of the inverter chain outputs a digital signal.

2. A readout circuit based on a three-transistor memory according to claim 1, characterized in that: The three-transistor storage unit includes an electron write tube, an electron collection tube and an electron read tube; the electron write tube is used to erase the weight value into the electron collection tube; the electron collection tube is used to collect electrons transmitted from the drain end of the electron write tube, and couple and control the floating gate potential; the electron read tube reads source-drain currents of different sizes through the floating gate potential, that is, reads the weight value.

3. A readout circuit based on a three-transistor memory according to claim 2, characterized in that: The three-transistor storage unit 1 includes six ports: a drain terminal WBL of an electron write tube, a gate terminal WWL of an electron write tube, a gate terminal RWL of an electron collection tube, a drain terminal RBL of an electron read tube, a source terminal RSL of an electron read tube and a substrate Sub; in the read mode, the gate terminal WWL of the electron write tube is connected to a negative voltage to turn off the electron write tube, the drain terminal WBL of the electron write tube is floating, the gate terminal RWL of the electron collection tube is connected to a positive voltage for voltage division of the series capacitor, and the substrate Sub is a negative voltage.

4. A readout circuit based on a three-transistor memory according to claim 1, characterized in that: The CMOS inverter comprises a pair of P-type doped MOSFET transistors and N-type doped MOSFET transistors connected in series; the source of the P-type doped MOSFET transistor is connected to the voltage level VP, and the source of the N-type doped MOSFET transistor is connected to the zero level; the gates of the P-type doped MOSFET transistor and the N-type doped MOSFET transistor are connected as input terminals, and the drains of the two are connected as output terminals.

5. The readout circuit based on a three-transistor memory according to claim 1, characterized in that: The transmission gate switch includes a pair of parallel P-type doped MOSFET transistors and N-type doped MOSFET transistors; the drains of the P-type doped MOSFET transistor and the N-type doped MOSFET transistor are connected as output terminals, and the sources of the P-type doped MOSFET transistor and the N-type doped MOSFET transistor are connected as input terminals; the gate of the P-type doped MOSFET transistor is connected to a negative clock control signal CLK_N, and the gate of the N-type doped MOSFET transistor is connected to a positive clock control signal CLK.

6. A readout circuit based on a three-transistor memory according to claim 1, characterized in that: The inverter chain is composed of four inverters in cascade, each inverter includes a pair of P-type doped MOSFET transistors and N-type doped MOSFET transistors connected in series; the source of the P-type doped MOSFET transistor is connected to the voltage level VP, and the source of the N-type doped MOSFET transistor is connected to the zero level; the gates of the P-type doped MOSFET transistor and the N-type doped MOSFET transistor are connected as input terminals, and the drains of the two are connected as output terminals.

7. A readout circuit based on a three-transistor memory according to claim 6, characterized in that: The threshold voltage of the N-type doped MOSFET transistor in the inverter chain is greater than or equal to 0.5*VP, and the absolute value of the threshold voltage of the P-type doped MOSFET transistor is less than or equal to 0.5*VP.

8. A method for operating a readout circuit based on a three-transistor memory according to any one of claims 1 to 7, characterized in that: The readout circuit includes two working stages: a standby stage φ1 and a readout stage φ2; when in the standby stage φ1, the transmission gate switch of the readout circuit is turned on, so that the drain voltage of the electronic readout tube of the three-transistor storage unit maintains a positive level VP, and the digital signal output through the CMOS inverter and the inverter chain is 0; when in the readout stage φ2, the transmission gate switch of the readout circuit is closed, and according to the different weights of the electronic readout tube of the three-transistor storage unit, two different digital outputs are generated at the output end of the inverter chain: if the weight is 1, the voltage at the input end of the CMOS inverter is zero, and the digital signal output through the CMOS inverter and the inverter chain is 1; if the weight is 0, the voltage at the input end of the CMOS inverter is a positive level VP, and the digital signal output through the CMOS inverter and the inverter chain is 0.

9. A chip based on a three-transistor memory, comprising the readout circuit according to any one of claims 1 to 7, characterized in that: The chip includes an array consisting of M×N three-transistor storage cells, wherein the drain ends of the electron write tubes of all three-transistor storage cells in each column are connected to the same bit line, and their source ends are connected to the same source line; the gate ends of the three-transistor storage cells in each row are connected to the same word line to form a cross structure; the bit lines of each column are respectively connected to the input ends of the CMOS inverters in the readout circuit, and N readout circuits are configured for parallel readout of N columns of storage cells.

10. A working method using a chip based on a three-transistor memory as claimed in claim 9, characterized in that: The working method includes: when the array is not read out, the word line voltage of each row is set to 0 level, and the outputs of all readout circuits are low level, indicating that the array is not read out; when the array is read out, a readout pulse is applied to the word line of the selected row, the pulse width is the time required for reading the weight value, and the pulse height is the readout voltage; when the storage cells of a row are read out, the weight values ​​of its N columns of storage cells are read out in parallel through N readout circuits; after the readout of the row is completed, the next readout operation can be performed in the same way.

Images