Bit line voltage transmission circuit

Abstract

The invention discloses a bit line voltage transmission circuit, which is characterized in that grid voltages of a first NMOS (N-channel Metal Oxide Semiconductor) tube and a PMOS (P-channel Metal Oxide Semiconductor) tube of a transmission gate between an IO (Input / Output) node and a bit line are respectively connected with a first control signal and a second control signal, and a pad electrode of the first PMOS tube is connected with a third control signal. When the first to third control signals are power supply voltage, first negative voltage and first positive voltage, the transmission gate is switched on. The first positive voltage is greater than or equal to the IO voltage and less than the power supply voltage, and is provided by the positive voltage signal generation circuit. The positive voltage signal generating circuit comprises a second NMOS tube, a third NMOS tube and a second PMOS tube. The grid electrode of the second NMOS tube and the drain electrode of the third NMOS tube are connected to a first node. The source electrode of the second NMOS tube and the grid electrode of the third NMOS tube are connected to a second node, and the second node serves as the output end of the first positive voltage. The source electrode of the third NMOS tube is connected with the source electrode of the second PMOS tube, and the drain electrode of the second PMOS tube is grounded. A first pull-up circuit is formed between the first node and the power supply voltage. The first pull-up circuit and the second PMOS tube are both controlled by a first enable signal.

Description

Technical Field

[0001] The present invention relates to a semiconductor integrated circuit, and in particular to a bit line voltage transmission circuit. Background Art

[0002] Embedded flash memory is an important part of MCU. Figure 1 , which is a circuit diagram of an existing select gate shared split gate (NORD) flash memory cell; the flash memory cell 101 includes three sequentially arranged first gate structures 102a, second gate structures and third gate structures 102b between the source Source and the drain Drain, and the first gate structure 102a and the third gate structure 102b both include a floating gate and a control gate, and the floating gate is used to store information, so the first gate structure 102a and the third gate structure 102b can store one bit of data respectively. Figure 1 In the embodiment, the data stored in the first gate structure 102a is marked as Bit1, and the data stored in the third gate structure 102b is marked as Bit2. The second gate structure is located between the first gate structure 102a and the third gate structure 102b, the control gate of the first gate structure 102a is connected to the control gate CG1, the control gate of the third gate structure 102b is connected to the control gate CG2, and the polysilicon gate of the second gate structure is connected to the selection gate SG.

[0003] When performing a read operation, such as reading Bit1, high voltage needs to be applied to the three terminals CG1, CG2, and SG, the Drain terminal is connected to a potential of approximately 0.7V, and the Source terminal is grounded. The potential of the Drain terminal is generally generated by a sense amplifier. The IO voltage generated by the sense amplifier is transmitted to the corresponding BL through a multiplexer (YMUX).

[0004] When the IO voltage is transmitted to the BL, a voltage drop is inevitable. As the cell current increases, the voltage drop will also increase, causing the BL voltage to be lower than the designed IO voltage value. When the BL voltage decreases, the cell read current will decrease, which will affect the distinction between "0" cells and "1" cells, especially for weakly erased and weakly programmed cells, which will cause read errors. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a bit line voltage transmission circuit, which can provide accurate control voltage for the PMOS tube of the transmission gate, i.e., the first PMOS tube, and can keep the voltage drop on both sides of the transmission gate, i.e., the voltage drop from the IO voltage to the bit line voltage at a low value when the cell current on the bit line is large, thereby increasing the reading accuracy and providing the reliability of the flash memory system.

[0006] The bit line voltage transmission circuit provided by the present invention comprises: a transmission gate.

[0007] The transmission gate is connected between the IO node and the selected bit line.

[0008] The transmission gate includes a first NMOS tube and a first PMOS tube.

[0009] The drain of the first NMOS tube and the source of the first PMOS tube are connected to the IO node.

[0010] The source of the first NMOS tube and the drain of the first PMOS tube are connected to the selected bit line.

[0011] The gate of the first NMOS tube is connected to a first control signal, the gate of the first PMOS tube is connected to a second control signal, and the pad electrode of the first PMOS tube is connected to a third control signal.

[0012] When the first control signal is a power supply voltage, the second control signal is a first negative voltage, and the third control signal is a first positive voltage, the transmission gate is in an on state, and the IO voltage of the IO node is transmitted to the selected bit line to form a bit line voltage.

[0013] The first positive voltage is greater than or equal to an IO voltage of the IO node and is less than the power supply voltage. The first positive voltage is provided by a positive voltage signal generating circuit.

[0014] The first negative voltage is less than or equal to a difference between a minimum value of the IO voltage and an absolute value of a first threshold voltage of the first PMOS tube.

[0015] The positive voltage signal generating circuit includes: a second NMOS tube, a third NMOS tube and a second PMOS tube.

[0016] The gate of the second NMOS tube and the drain of the third NMOS tube are both connected to the first node.

[0017] The source of the second NMOS tube and the gate of the third NMOS tube are both connected to a second node, and the second node serves as an output end of the first positive voltage.

[0018] The source of the third NMOS tube is connected to the source of the second PMOS tube, and the drain of the second PMOS tube is grounded.

[0019] A first pull-up circuit is formed between the first node and the power supply voltage.

[0020] The first control terminal of the first pull-up circuit and the gate of the second PMOS tube are both connected to a first enable signal.

[0021] The second NMOS transistor and the third NMOS transistor form a first negative feedback loop between the voltages of the first node and the second node and stabilize the first positive voltage.

[0022] When the first enable signal is at a low level, the first pull-up circuit and the second PMOS tube are both turned on. The series structure of the second PMOS tube and the third NMOS tube stabilizes the first positive voltage between the difference between the power supply voltage and the second threshold voltage and the sum of the absolute values ​​of the second threshold voltage and the third threshold voltage, the second threshold voltage is the threshold voltage of the second NMOS tube, the third threshold voltage is the threshold voltage of the second PMOS tube, and the threshold voltage of the third NMOS tube is equal to the threshold voltage of the second NMOS tube.

[0023] A further improvement is that the first negative voltage is provided by a negative voltage signal generating circuit, and the negative voltage signal generating circuit includes: a charge pump, a voltage divider circuit and a comparator.

[0024] The output end of the charge pump outputs the first negative voltage.

[0025] The power supply end of the charge pump is connected to the power supply voltage, and the maximum negative voltage that can be generated by the output end of the charge pump is the negative value of the power supply voltage.

[0026] The voltage divider circuit is connected between the power supply voltage and the first negative voltage.

[0027] The voltage divider circuit provides a first divided voltage.

[0028] The first divided voltage is connected to a first input terminal of the comparator, and a second input terminal of the comparator is grounded.

[0029] The output terminal of the comparator outputs a first feedback signal to a clock signal control terminal of the charge pump.

[0030] A clock input terminal of the charge pump is connected to a clock input signal, and the clock input signal is input to the charge pump under the control of the first feedback signal to thereby control the magnitude of the first negative pressure.

[0031] The first feedback signal controls the time when the clock input signal is input into the charge pump according to the size of the first divided voltage, thereby controlling the size of the first negative voltage.

[0032] A further improvement is that the charge pump comprises a symmetrical first subunit and a second subunit.

[0033] The first subunit and the second subunit have the same first circuit structure.

[0034] The first circuit structure includes: a pump capacitor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a third PMOS transistor and a fourth PMOS transistor.

[0035] A first end of the pump capacitor is connected to a first clock signal, and a second end of the pump capacitor is a first internal node.

[0036] The source of the fourth NMOS tube, the drain of the fifth NMOS tube and the drain of the sixth NMOS tube are all connected to the first internal node.

[0037] The drain of the fourth NMOS tube, the gate of the fifth NMOS tube and the drain of the fourth PMOS tube are all connected to the second internal node.

[0038] The source of the fifth NMOS tube and the gate of the fourth PMOS tube are both grounded.

[0039] The drain of the third PMOS tube is connected to the source of the fourth PMOS tube.

[0040] The source of the third PMOS tube is connected to the power supply voltage.

[0041] The gate of the third PMOS transistor and the gate of the fourth NMOS transistor are both connected to the inverted signal of the first clock signal.

[0042] The gate of the sixth NMOS tube is connected to the inverted signal of the first internal node.

[0043] The source of the sixth NMOS tube outputs the first negative voltage.

[0044] In the charge pump, the connection relationship between the first subunit and the second subunit is:

[0045] The first clock signal of the first subunit adopts an internal clock inversion signal, and the first clock signal of the second subunit adopts an internal clock signal. The internal clock signal and the internal clock inversion signal are inverted to each other and are both formed by the clock input signal.

[0046] The first internal node of the first subunit is connected to the gate of the sixth NMOS transistor of the second subunit; the first internal node of the second subunit is connected to the gate of the sixth NMOS transistor of the first subunit.

[0047] A further improvement is that the voltage divider circuit includes a first resistor and a second resistor.

[0048] A first end of the first resistor is connected to the power supply voltage.

[0049] The second end of the first resistor and the first end of the second resistor are connected together and serve as an output end of the first voltage divider.

[0050] The second end of the second resistor is connected to the output end of the charge pump.

[0051] The absolute value of the ratio of the first negative voltage to the power supply voltage is the ratio of the second resistor to the first resistor, and the first negative voltage is adjusted by adjusting the ratio of the second resistor to the first resistor.

[0052] A further improvement is that a fifth PMOS tube is connected between the first resistor and the first end and the power supply voltage, the source of the fifth PMOS tube is connected to the power supply voltage, and the drain of the fifth PMOS tube is connected to the first end of the first resistor.

[0053] The gate of the fifth PMOS tube is connected to the first enable signal.

[0054] A further improvement is that a decoupling capacitor is connected between the output end of the charge pump and the ground.

[0055] A further improvement is that the negative voltage signal generating circuit further includes a first inverter.

[0056] The input end of the first inverter is connected to the first feedback signal, the output end of the first inverter outputs a second feedback signal, and the second feedback signal is output to a clock signal control end of the charge pump.

[0057] A further improvement is that the first pull-up circuit includes: a sixth PMOS tube, a seventh PMOS tube and an eighth PMOS tube.

[0058] The source of the sixth PMOS tube is connected to the power supply voltage.

[0059] The drain of the sixth PMOS tube, the source of the seventh PMOS tube and the source of the eighth PMOS tube are connected together.

[0060] The gate of the seventh PMOS tube is connected to the first enable signal.

[0061] The drain of the seventh PMOS tube, the gate of the eighth PMOS tube and the drain of the eighth PMOS tube are connected to the first node.

[0062] A further improvement is that the positive pressure signal generating circuit further includes:

[0063] A ninth PMOS tube, wherein the source of the ninth PMOS tube is connected to the power supply voltage, the drain of the ninth PMOS tube is connected to the drain of the second NMOS tube, and the gate of the ninth PMOS tube is grounded.

[0064] A further improvement is that the positive pressure signal generating circuit further includes:

[0065] A tenth PMOS tube, wherein the source of the tenth PMOS tube is connected to the power supply voltage, the drain of the ninth PMOS tube is connected to the second node, and the gate of the ninth PMOS tube is connected to a first enable inverted signal, wherein the first enable inverted signal is an inverted signal of the first enable signal.

[0066] A further improvement is that the positive voltage signal generating circuit further includes: an eleventh PMOS tube, a seventh NMOS tube and an eighth NMOS tube.

[0067] The source of the eleventh PMOS tube and the drain of the seventh NMOS tube are both connected to the second node.

[0068] The drain of the eleventh PMOS tube and the source of the seventh NMOS tube are both connected to the drain of the eighth NMOS tube.

[0069] The source of the eighth NMOS tube is grounded.

[0070] The gate of the eleventh PMOS transistor is connected to the first enable signal, and the gate of the seventh NMOS transistor is connected to a first enable inverted signal, which is an inverted signal of the first enable signal.

[0071] The gate of the eighth NMOS tube is connected to a current control signal.

[0072] A further improvement is that the selected bit line is the bit line selected from a plurality of bit lines of a storage array by a column address signal.

[0073] The storage array is composed of a plurality of storage units arranged in an array.

[0074] A further improvement is that the storage unit includes a select gate sharing split gate flash memory unit.

[0075] A further improvement is that the IO node is a node where a sense amplifier and the bit line are connected, and the IO voltage is generated by the sense amplifier.

[0076] A further improvement is that the second NMOS tube adopts an intrinsic NMOS tube, and the third NMOS tube adopts an intrinsic NMOS tube.

[0077] The present invention makes a special arrangement for the voltage of the substrate electrode and the gate of the first PMOS tube when the transmission gate of the bit line voltage transmission circuit is turned on. The voltage of the substrate electrode of the first PMOS tube adopts a first positive voltage, and the gate voltage adopts a first negative voltage. The first positive voltage is provided by a positive voltage signal generating circuit. The second NMOS tube and the third NMOS tube in the positive voltage signal generating circuit are connected to form a first negative feedback loop structure, wherein the second NMOS tube can make the voltage of the second node change in phase with the voltage of the first node and make the voltage of the second node smaller than the voltage of the first node by a threshold voltage of the second NMOS tube, i.e., a second threshold voltage, and the third NMOS tube can make the voltage of the first node change in antiphase with the voltage of the second node, and finally make the potential of the first node and the second node stable; by setting the second PMOS tube and the third NMOS tube in a series structure with the source electrodes connected, finally the voltage of the second node can be greater than the voltage of the second PMOS tube. The gate voltage of the MOS tube is added to the threshold voltage of the second PMOS, that is, the absolute value of the third threshold voltage and the second threshold voltage, and finally the first positive voltage can be stabilized between the difference between the power supply voltage and the second threshold voltage and the sum of the absolute values ​​of the second threshold voltage and the third threshold voltage. Therefore, the first positive voltage of the present invention can ensure that the substrate electrode voltage of the first PMOS tube when turned on is kept at a relatively small value under the condition that it is greater than or equal to the IO voltage. At the same time, combined with the setting of the first negative voltage, the first PMOS tube can maintain the best turn-on condition, and when the cell current on the bit line is relatively large, the voltage drop on both sides of the transmission gate, that is, the voltage drop from the IO voltage to the bit line voltage, can be kept at a relatively low value; therefore, the present invention can provide an accurate control voltage for the PMOS tube of the transmission gate, and when the cell current on the bit line is relatively large, the voltage drop on both sides of the transmission gate, that is, the voltage drop from the IO voltage to the bit line voltage, can be kept at a relatively low value, thereby increasing the accuracy of reading and providing the reliability of the flash memory system.

[0078] The present invention is particularly suitable for reading storage cells when the power supply voltage is continuously reduced and the cell current to be read is relatively large. When the power supply voltage is relatively low, the present invention can keep the bit line voltage at a relatively large value by precisely controlling the voltage drop on both sides of the transmission gate, thereby preventing the cell current to be read from being reduced. This is beneficial for distinguishing storage cells with storage information of 0 and 1, and can especially increase the distinction between weakly erased and weakly programmed storage cells, thereby preventing read errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0080] Figure 1 This is the circuit diagram of the existing NORD flash memory unit;

[0081] Figure 2 is a circuit diagram of a transmission gate of a bit line voltage transmission circuit according to an embodiment of the present invention;

[0082] Figure 3 is a circuit diagram of a positive voltage signal generating circuit of a bit line voltage transmission circuit according to an embodiment of the present invention;

[0083] Figure 4 is a circuit diagram of a negative voltage signal generating circuit of a bit line voltage transmission circuit according to an embodiment of the present invention;

[0084] Figure 5 is a circuit diagram of a charge pump of a negative voltage signal generating circuit of a bit line voltage transmission circuit according to an embodiment of the present invention;

[0085] Figure 6 yes Figure 5 Timing diagram of each node in;

[0086] Figure 7 It is a simulation diagram of the first positive voltage and the first negative voltage of the bit line voltage transmission circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0087] like Figure 2 , which is a circuit diagram of a transmission gate 201 of a bit line voltage transmission circuit according to an embodiment of the present invention; the bit line voltage transmission circuit according to the embodiment of the present invention includes: a transmission gate 201.

[0088] The transmission gate 201 is connected between the IO node and the selected bit line BL. Figure 2 In the example, the IO node is directly represented by IO.

[0089] The transmission gate 201 includes a first NMOS transistor NM1 and a first PMOS transistor PM1.

[0090] The drain of the first NMOS transistor NM1 and the source of the first PMOS transistor PM1 are connected to the IO node.

[0091] The source of the first NMOS transistor NM1 and the drain of the first PMOS transistor PM1 are connected to the selected bit line BL.

[0092] A gate of the first NMOS transistor NM1 is connected to a first control signal, a gate of the first PMOS transistor PM1 is connected to a second control signal, and a pad electrode of the first PMOS transistor PM1 is connected to a third control signal.

[0093] When the first control signal is the power supply voltage VDD, the second control signal is the first negative voltage VNEG, and the third control signal is the first positive voltage VDDA, the transmission gate 201 is in the on state, and the IO voltage of the IO node is transmitted to the selected bit line BL to form a bit line BL voltage. Figure 2Specific signals of the three control signals of the transmission gate 201 in the on state are shown in FIG. 2 , and VDD is directly used to represent the first control signal, VNEG is used to represent the second control signal, and VDDA is used to represent the third control signal.

[0094] The first positive voltage VDDA is greater than or equal to the IO voltage of the IO node and is less than the power supply voltage VDD. The first positive voltage VDDA is provided by a positive voltage signal generating circuit.

[0095] The first negative voltage VNEG is smaller than or equal to a difference between a minimum value of the IO voltage and an absolute value of a first threshold voltage of the first PMOS transistor PM1 .

[0096] like Figure 3 , is a circuit diagram of a positive voltage signal generating circuit of a bit line voltage transmission circuit according to an embodiment of the present invention; the positive voltage signal generating circuit comprises: a second NMOS tube NM2, a third NMOS tube NM3 and a second PMOS tube PM2.

[0097] The gate of the second NMOS transistor NM2 and the drain of the third NMOS transistor NM3 are both connected to the first node C.

[0098] The source of the second NMOS transistor NM2 and the gate of the third NMOS transistor NM3 are both connected to a second node, and the second node serves as an output end of the first positive voltage VDDA.

[0099] A source of the third NMOS transistor NM3 is connected to a source of the second PMOS transistor PM2 , and a drain of the second PMOS transistor PM2 is grounded GND.

[0100] A first pull-up circuit is formed between the first node C and the power supply voltage VDD.

[0101] The first control terminal of the first pull-up circuit and the gate of the second PMOS transistor PM2 are both connected to a first enable signal EN.

[0102] The second NMOS transistor NM2 and the third NMOS transistor NM3 form a first negative feedback loop between the voltages of the first node C and the second node and stabilize the first positive voltage VDDA.

[0103] When the first enable signal EN is at a low level, the first pull-up circuit and the second PMOS transistor PM2 are both turned on. The series structure of the second PMOS transistor PM2 and the third NMOS transistor NM3 stabilizes the first positive voltage VDDA between the difference between the power supply voltage VDD and the second threshold voltage and the sum of the absolute values ​​of the second threshold voltage and the third threshold voltage, the second threshold voltage being the threshold voltage of the second NMOS transistor NM2, the third threshold voltage being the threshold voltage of the second PMOS transistor PM2, and the threshold voltage of the third NMOS transistor NM3 being equal to the threshold voltage of the second NMOS transistor NM2.

[0104] In the embodiment of the present invention, the second NMOS transistor NM2 is an intrinsic NMOS transistor, and the third NMOS transistor NM3 is an intrinsic NMOS transistor. The threshold voltage of the intrinsic NMOS transistor is relatively small, for example, less than 150 mV.

[0105] In the embodiment of the present invention, the first pull-up circuit includes: a sixth PMOS transistor PM6, a seventh PMOS transistor PM7 and an eighth PMOS transistor PM8.

[0106] A source of the sixth PMOS transistor PM6 is connected to the power supply voltage VDD.

[0107] The drain of the sixth PMOS transistor PM6 , the source of the seventh PMOS transistor PM7 , and the source of the eighth PMOS transistor PM8 are connected together.

[0108] A gate of the seventh PMOS transistor PM7 is connected to the first enable signal EN.

[0109] The drain of the seventh PMOS transistor PM7 , the gate of the eighth PMOS transistor PM8 , and the drain of the eighth PMOS transistor PM8 are connected to the first node C.

[0110] The positive pressure signal generating circuit further includes:

[0111] A ninth PMOS transistor PM9, wherein a source of the ninth PMOS transistor PM9 is connected to the power supply voltage VDD, a drain of the ninth PMOS transistor PM9 is connected to the drain of the second NMOS transistor NM2, and a gate of the ninth PMOS transistor PM9 is grounded GND.

[0112] A tenth PMOS tube PM10, a source of the tenth PMOS tube PM10 is connected to the power supply voltage VDD, a drain of the ninth PMOS tube PM9 is connected to the second node, and a gate of the ninth PMOS tube PM9 is connected to a first enable inverted signal ENb, wherein the first enable inverted signal ENb is an inverted signal of the first enable signal EN, and the first enable signal EN is input to an input end of an inverter, and the first enable inverted signal ENb can be obtained at the output end of the inverter.

[0113] The positive voltage signal generating circuit further includes: an eleventh PMOS transistor PM11, a seventh NMOS transistor NM7 and an eighth NMOS transistor NM8.

[0114] The source of the eleventh PMOS transistor PM11 and the drain of the seventh NMOS transistor NM7 are both connected to the second node.

[0115] The drain of the eleventh PMOS transistor PM11 and the source of the seventh NMOS transistor NM7 are both connected to the drain of the eighth NMOS transistor NM8 .

[0116] The source of the eighth NMOS transistor NM8 is grounded GND.

[0117] The gate of the eleventh PMOS transistor PM11 is connected to the first enable signal EN, and the gate of the seventh NMOS transistor NM7 is connected to a first enable inverted signal ENb, which is an inverted signal of the first enable signal EN.

[0118] The gate of the eighth NMOS transistor NM8 is connected to the current control signal Ic.

[0119] In the embodiment of the present invention, the first negative voltage VNEG is provided by a negative voltage signal generating circuit. Figure 4 , is a circuit diagram of a negative voltage signal generating circuit of a bit line voltage transmission circuit according to an embodiment of the present invention; the negative voltage signal generating circuit comprises: a charge pump 202 , a voltage divider circuit 203 and a comparator 204 .

[0120] The output terminal of the charge pump 202 outputs the first negative voltage VNEG.

[0121] The power supply terminal of the charge pump 202 is connected to the power supply voltage VDD, and the maximum negative voltage that can be generated by the output terminal of the charge pump 202 is the negative value of the power supply voltage VDD, that is, −VDD.

[0122] The voltage divider circuit 203 is connected between the power supply voltage VDD and the first negative voltage VNEG.

[0123] The voltage divider circuit 203 provides a first divided voltage. Figure 4In the embodiment, the first divided voltage is outputted from the node Z.

[0124] The first divided voltage is connected to a first input terminal of the comparator 204 , and a second input terminal of the comparator 204 is grounded GND. Figure 4 In the embodiment, the first input terminal of the comparator 204 is a + input terminal, and the second input terminal of the comparator 204 is a - input terminal.

[0125] The output terminal of the comparator 204 outputs a first feedback signal to a clock signal control terminal of the charge pump 202 .

[0126] A clock input terminal of the charge pump 202 is connected to a clock input signal CLK. The clock input signal CLK is input to the charge pump 202 under the control of the first feedback signal and thereby controls the magnitude of the first negative voltage VNEG.

[0127] The first feedback signal controls the time when the clock input signal CLK is input into the charge pump 202 according to the size of the first divided voltage, and thereby controls the size of the first negative voltage VNEG.

[0128] The voltage divider circuit 203 includes a first resistor R1 and a second resistor R2.

[0129] A first end of the first resistor R1 is connected to the power supply voltage VDD.

[0130] The second end of the first resistor R1 and the first end of the second resistor R2 are connected together and serve as the output end of the first voltage division, namely, node Z.

[0131] The second end of the second resistor R2 is connected to the output end of the charge pump 202 .

[0132] The absolute value of the ratio of the first negative voltage VNEG to the power supply voltage VDD is the ratio of the second resistor R2 to the first resistor R1 , and the first negative voltage VNEG is adjusted by adjusting the ratio of the second resistor R2 to the first resistor R1 .

[0133] A fifth PMOS transistor PM5 is further connected between the first end of the first resistor R1 and the power supply voltage VDD, a source of the fifth PMOS transistor PM5 is connected to the power supply voltage VDD, and a drain of the fifth PMOS transistor PM5 is connected to the first end of the first resistor R1.

[0134] A gate of the fifth PMOS transistor PM5 is connected to the first enable signal EN.

[0135] A decoupling capacitor C101 is further connected between the output end of the charge pump 202 and the ground.

[0136] The negative voltage signal generating circuit further includes a first inverter 205 .

[0137] The input end of the first inverter 205 is connected to the first feedback signal, and the output end of the first inverter 205 , namely the node FB, outputs the second feedback signal, which is output to the clock signal control end of the charge pump 202 .

[0138] Figure 4 In the figure, the charge pump 202 is also represented by pump_N0P4.

[0139] like Figure 5 , is a circuit diagram of a charge pump 202 of a negative voltage signal generating circuit of a bit line voltage transmission circuit according to an embodiment of the present invention; in the embodiment of the present invention, the charge pump 202 includes a symmetrical first subunit 202a and a second subunit 202b.

[0140] The first subunit 202a and the second subunit 202b have the same first circuit structure, and the difference between them is that the signals connected thereto are different.

[0141] Below Figure 5 The structure of the first subunit 202a shown in the figure illustrates the first circuit structure, which includes: a pump capacitor C1, a fourth NMOS tube NM4, a fifth NMOS tube NM5, a sixth NMOS tube NM6, a third PMOS tube PM3 and a fourth PMOS tube PM4.

[0142] A first end of the pump capacitor C1 is connected to a first clock signal, and a second end of the pump capacitor C1 is a first internal node B1.

[0143] The source of the fourth NMOS transistor NM4 , the drain of the fifth NMOS transistor NM5 , and the drain of the sixth NMOS transistor NM6 are all connected to the first internal node B1 .

[0144] The drain of the fourth NMOS transistor NM4 , the gate of the fifth NMOS transistor NM5 , and the drain of the fourth PMOS transistor PM4 are all connected to the second internal node A1 .

[0145] The source of the fifth NMOS transistor NM5 and the gate of the fourth PMOS transistor PM4 are both connected to the ground GND.

[0146] The drain of the third PMOS transistor PM3 is connected to the source of the fourth PMOS transistor PM4.

[0147] A source of the third PMOS transistor PM3 is connected to the power supply voltage VDD.

[0148] The gate of the third PMOS transistor PM3 and the gate of the fourth NMOS transistor NM4 are both connected to the inverted signal of the first clock signal.

[0149] A gate of the sixth NMOS transistor NM6 is connected to the inverted signal of the first internal node B1.

[0150] The source of the sixth NMOS transistor NM6 outputs the first negative voltage VNEG.

[0151] Figure 5 In the second subunit 202b, the fourth NMOS tube is individually labeled NM4a, the fifth NMOS tube is individually labeled NM5a, the sixth NMOS tube is individually labeled NM6a, the third PMOS tube is individually labeled PM3a, and the fourth PMOS tube is individually labeled PM4a.

[0152] The first internal node in the second subunit 202b is individually labeled with B2, and the second internal node is individually labeled with A1. In combination with the above labels, the connection relationship between the first subunit 202a and the second subunit 202b is further described as follows:

[0153] In the charge pump 202, the connection relationship between the first subunit 202a and the second subunit 202b is:

[0154] The first clock signal of the first subunit 202a uses the internal clock inversion signal CKb, and the first clock signal of the second subunit 202b uses the internal clock signal CK. The internal clock signal CK and the internal clock inversion signal CKb are inverted and are both formed by the clock input signal CLK.

[0155] The first internal node B1 of the first subunit 202a is connected to the gate of the sixth NMOS transistor NM6 of the second subunit 202b; the first internal node B1 of the second subunit 202b is connected to the gate of the sixth NMOS transistor NM6 of the first subunit 202a.

[0156] In the embodiment of the present invention, the selected bit line BL is the bit line BL selected from a plurality of bit lines BL of a memory array by a column address signal.

[0157] The storage array is composed of a plurality of storage units arranged in an array.

[0158] The storage unit includes a select gate sharing split gate flash memory unit. The structure of the select gate sharing split gate flash memory unit can be found in Figure 1 No further detailed description is given here.

[0159] The IO node is a node where a sense amplifier and the bit line BL are connected, and the IO voltage is generated by the sense amplifier.

[0160] The embodiment of the present invention makes a special arrangement for the voltages of the substrate electrode and the gate of the first PMOS transistor PM1 when the transmission gate 201 of the bit line voltage transmission circuit is turned on. The voltage of the substrate electrode of the first PMOS transistor PM1 adopts a first positive voltage VDDA, and the gate voltage adopts a first negative voltage VNEG. The first positive voltage VDDA is provided by a positive voltage signal generating circuit. The second NMOS transistor NM2 and the third NMOS transistor NM3 in the positive voltage signal generating circuit are connected to form a first negative feedback loop structure, wherein the second NMOS transistor NM2 can make the voltage of the second node change in phase with the voltage of the first node C and make the voltage of the second node lower than the voltage of the first node C by a threshold voltage of the second NMOS transistor NM2, i.e., a second threshold voltage, and the third NMOS transistor NM3 can make the voltage of the first node C change in antiphase with the voltage of the second node, and finally make the potential of the first node C and the second node stable; by setting the second PMOS transistor PM2 and the third NMOS transistor NM3 in a series structure with their sources connected, finally the voltage of the second node can be greater than the voltage of the first node C. The gate voltage of the second PMOS transistor PM2 is added to the threshold voltage of the second PMOS, that is, the absolute value of the third threshold voltage and the second threshold voltage, and finally the first positive voltage VDDA can be stabilized between the difference between the power supply voltage VDD and the second threshold voltage and the sum of the absolute values ​​of the second threshold voltage and the third threshold voltage. Therefore, the first positive voltage VDDA in the embodiment of the present invention can ensure that the substrate electrode voltage of the first PMOS transistor PM1 when turned on is kept at a small value under the condition that it is greater than or equal to the IO voltage. At the same time, combined with the setting of the first negative voltage VNEG, the first PMOS transistor PM1 can maintain the best turn-on condition, and when the cell current on the bit line BL is large, the voltage drop on both sides of the transmission gate 201, that is, the voltage drop from the IO voltage to the bit line BL voltage, can be kept at a low value; therefore, the present invention can provide a precise control voltage for the PMOS transistor of the transmission gate 201, and when the cell current on the bit line BL is large, the voltage drop on both sides of the transmission gate 201, that is, the voltage drop from the IO voltage to the bit line BL voltage, can be kept at a low value, thereby increasing the accuracy of reading and providing the reliability of the flash memory system.

[0161] The embodiment of the present invention is particularly suitable for reading storage cells when the power supply voltage VDD is continuously reduced and the cell current to be read is relatively large. The embodiment of the present invention can keep the voltage of the bit line BL at a relatively large value by precisely controlling the voltage drop on both sides of the transmission gate 201 when the power supply voltage VDD is relatively low, thereby preventing the cell current to be read from being reduced. This is beneficial for distinguishing storage cells storing information of 0 and 1, and can especially increase the distinction between weakly erased and weakly programmed storage cells, thereby preventing read errors.

[0162] The bit line voltage transmission circuit of the embodiment of the present invention is based on a positive and negative voltage transmission structure, and includes a positive and negative voltage generating circuit for bit line transmission. The bit line voltage transmission circuit can be used as a YMUX to ensure that the positive and negative voltage YMUX can still have a small voltage drop under a large cell current, further improving the accuracy of embedded flash memory reading and enhancing the reliability of the flash memory system. The working principle of each component of the bit line voltage transmission circuit of the embodiment of the present invention is further explained below:

[0163] The working principle of the positive pressure signal generating circuit is:

[0164] Combination Figure 3 As shown, NM2 and NM3 are intrinsic MOS tubes, and their threshold voltage is relatively low, generally around 150mV. When the EN signal is 0, the circuit starts to work, and point C is quickly pulled up to VDD. At this time, VDDA = VDD-V_THNZ, where V_THNZ is the threshold voltage of NM2; at this time, NM3 is turned on, and since NM3 and PM2 have strong driving capabilities, point C is pulled down, causing VDDA to drop with point C. NM2, NM3 and PM2 form a negative feedback structure, which ultimately stabilizes VDDA at a potential of about 0.8V. Above, directly with Figure 3 Corresponding symbols in the figure indicate corresponding transistors and nodes.

[0165] The working principle of the negative pressure signal generating circuit is:

[0166] Figure 4 In the figure, the negative voltage signal generating circuit is mainly composed of PUMP_N0P4 and a feedback control circuit. PUMP_N0P4 can generate a voltage as low as -VDD. When the potential of node Z is lower than 0V, the output signal of comparator 204, i.e., the signal of node FB, stops PUMP_N0P4 from working; when the potential of node Z is higher than 0V, PUMP_N0P4 starts working. VNEG = -R2 / R1*VDD. Since the node G corresponding to the first negative voltage VNEG is externally connected to a larger capacitor C101, VNEG can be stabilized at a set value. For example, when VDD = 1.1V, R2 / R1 = 0.36, and a VNEG signal of about -0.4V can be obtained. In the above, PUMP_N0P4 is used to directly represent the charge pump 202, and each signal or node is also directly represented by a corresponding mark.

[0167] The working principle of the VNEG signal generating circuit, i.e. the charge pump, is as follows:

[0168] like Figure 6 As shown, Figure 5 The timing diagram of each node in the first subunit 202a is used as an example to illustrate and combine Figure 5 and Figure 6As shown, CK and CKb are clock signals with amplitudes of VDD and GND. When CK is GND, PM3 is turned on, PM4 is normally open, A1 is pulled up to VDD, NM5 is turned on, and B1 is pulled down to GND. When CK is VDD, PM3 is turned off, the path from A1 to VDD is cut off, NM4 is turned on, and the potentials of A1 and B1 remain consistent. At this time, CKb jumps from VDD to GND. Based on the law of conservation of capacitor charge, B1 jumps to -VDD, A1 follows B1 to -VDD, NM5 is turned off, and the path from B1 to GND is cut off. At the same time, B2 is pulled down to GND, so NM4 is turned on. Due to the very large decoupling capacitor connected to VNEG and the influence of the external modulation circuit, the potentials of A1, B1 and VNEG are finally consistent, close to the design value of -0.4V. Above, the corresponding transistors or nodes are directly represented by corresponding marks. Figure 6 In the figure, the nodes corresponding to each curve are marked on the left side of the curve.

[0169] like Figure 7 , which is a simulation diagram of the first positive voltage and the first negative voltage of the bit line voltage transmission circuit according to an embodiment of the present invention, Figure 7 In the figure, the nodes corresponding to each simulation curve are marked on the left side of the curve. It can be seen that when the EN signal is low, VDDA will self-stabilize at about 0.83V through feedback, and VNEG will reach near the design value, that is, -0.4V, after multiple pumping, such as the values ​​of VDDA and VNEG corresponding to line AA.

[0170] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A bit line voltage transmission circuit, characterized in that: include: Transmission gate; The transmission gate is connected between the IO node and the selected bit line; The transmission gate includes a first NMOS tube and a first PMOS tube; The drain of the first NMOS tube and the source of the first PMOS tube are connected to the IO node; The source of the first NMOS tube and the drain of the first PMOS tube are connected to the selected bit line; The gate of the first NMOS transistor is connected to a first control signal, the gate of the first PMOS transistor is connected to a second control signal, and the pad electrode of the first PMOS transistor is connected to a third control signal; When the first control signal is a power supply voltage, the second control signal is a first negative voltage, and the third control signal is a first positive voltage, the transmission gate is in a conducting state, and the IO voltage of the IO node is transmitted to the selected bit line to form a bit line voltage; The first positive voltage is greater than or equal to the IO voltage of the IO node and is less than the power supply voltage, and the first positive voltage is provided by a positive voltage signal generating circuit; The first negative voltage is less than or equal to the difference between the minimum value of the IO voltage and the absolute value of the first threshold voltage of the first PMOS tube; The positive voltage signal generating circuit comprises: a second NMOS tube, a third NMOS tube and a second PMOS tube; The gate of the second NMOS tube and the drain of the third NMOS tube are both connected to the first node; The source of the second NMOS tube and the gate of the third NMOS tube are both connected to a second node, and the second node serves as an output end of the first positive voltage; The source of the third NMOS tube is connected to the source of the second PMOS tube, and the drain of the second PMOS tube is grounded; A first pull-up circuit is formed between the first node and the power supply voltage; The first control terminal of the first pull-up circuit and the gate of the second PMOS tube are both connected to a first enable signal; The second NMOS transistor and the third NMOS transistor form a first negative feedback loop between the voltages of the first node and the second node and stabilize the first positive voltage; When the first enable signal is at a low level, the first pull-up circuit and the second PMOS tube are both turned on; the series structure of the second PMOS tube and the third NMOS tube stabilizes the first positive voltage between the difference between the power supply voltage and the second threshold voltage and the sum of the absolute values ​​of the second threshold voltage and the third threshold voltage, the second threshold voltage is the threshold voltage of the second NMOS tube, the third threshold voltage is the threshold voltage of the second PMOS tube, and the threshold voltage of the third NMOS tube is equal to the threshold voltage of the second NMOS tube.

2. The bit line voltage transmission circuit according to claim 1, wherein: The first negative voltage is provided by a negative voltage signal generating circuit, and the negative voltage signal generating circuit comprises: a charge pump, a voltage dividing circuit and a comparator; The output end of the charge pump outputs the first negative pressure; The power supply terminal of the charge pump is connected to the power supply voltage, and the maximum negative voltage that can be generated by the output terminal of the charge pump is the negative value of the power supply voltage; The voltage divider circuit is connected between the power supply voltage and the first negative voltage; The voltage divider circuit provides a first divided voltage; The first divided voltage is connected to a first input terminal of the comparator, and a second input terminal of the comparator is grounded; The output terminal of the comparator outputs a first feedback signal to a clock signal control terminal of the charge pump; The clock input terminal of the charge pump is connected to a clock input signal, and the clock input signal is input to the charge pump under the control of the first feedback signal to control the magnitude of the first negative pressure; The first feedback signal controls the time when the clock input signal is input into the charge pump according to the size of the first divided voltage, thereby controlling the size of the first negative voltage.

3. The bit line voltage transmission circuit according to claim 2, wherein: The charge pump comprises a symmetrical first subunit and a second subunit; The first subunit and the second subunit have the same first circuit structure; The first circuit structure includes: a pump capacitor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a third PMOS transistor and a fourth PMOS transistor; A first end of the pump capacitor is connected to a first clock signal, and a second end of the pump capacitor is a first internal node; The source of the fourth NMOS tube, the drain of the fifth NMOS tube and the drain of the sixth NMOS tube are all connected to the first internal node; The drain of the fourth NMOS tube, the gate of the fifth NMOS tube and the drain of the fourth PMOS tube are all connected to the second internal node; The source of the fifth NMOS tube and the gate of the fourth PMOS tube are both grounded; The drain of the third PMOS tube is connected to the source of the fourth PMOS tube; The source of the third PMOS tube is connected to the power supply voltage; The gate of the third PMOS tube and the gate of the fourth NMOS tube are both connected to the inverted signal of the first clock signal; The gate of the sixth NMOS tube is connected to the inverted signal of the first internal node; The source of the sixth NMOS tube outputs the first negative voltage; In the charge pump, the connection relationship between the first subunit and the second subunit is: The first clock signal of the first subunit adopts an internal clock inversion signal, and the first clock signal of the second subunit adopts an internal clock signal, the internal clock signal and the internal clock inversion signal are inverted to each other and are both formed by the clock input signal; The first internal node of the first subunit is connected to the gate of the sixth NMOS transistor of the second subunit; the first internal node of the second subunit is connected to the gate of the sixth NMOS transistor of the first subunit.

4. The bit line voltage transmission circuit according to claim 3, wherein: The voltage divider circuit includes a first resistor and a second resistor; The first end of the first resistor is connected to the power supply voltage; The second end of the first resistor and the first end of the second resistor are connected together and serve as an output end of the first voltage divider; The second end of the second resistor is connected to the output end of the charge pump; The absolute value of the ratio of the first negative voltage to the power supply voltage is the ratio of the second resistor to the first resistor, and the first negative voltage is adjusted by adjusting the ratio of the second resistor to the first resistor.

5. The bit line voltage transmission circuit according to claim 4, wherein: A fifth PMOS tube is further connected between the first resistor and the first end and the power supply voltage, the source of the fifth PMOS tube is connected to the power supply voltage, and the drain of the fifth PMOS tube is connected to the first end of the first resistor; The gate of the fifth PMOS tube is connected to the first enable signal.

6. The bit line voltage transmission circuit according to claim 4, wherein: A decoupling capacitor is also connected between the output end of the charge pump and the ground.

7. The bit line voltage transmission circuit according to claim 2, wherein: The negative voltage signal generating circuit further includes a first inverter; The input end of the first inverter is connected to the first feedback signal, the output end of the first inverter outputs a second feedback signal, and the second feedback signal is output to a clock signal control end of the charge pump.

8. The bit line voltage transmission circuit according to claim 1, wherein: The first pull-up circuit includes: a sixth PMOS tube, a seventh PMOS tube and an eighth PMOS tube; The source of the sixth PMOS tube is connected to the power supply voltage; The drain of the sixth PMOS tube, the source of the seventh PMOS tube and the source of the eighth PMOS tube are connected together; The gate of the seventh PMOS tube is connected to the first enable signal; The drain of the seventh PMOS tube, the gate of the eighth PMOS tube and the drain of the eighth PMOS tube are connected to the first node.

9. The bit line voltage transmission circuit according to claim 8, wherein: The positive pressure signal generating circuit further includes: A ninth PMOS tube, wherein the source of the ninth PMOS tube is connected to the power supply voltage, the drain of the ninth PMOS tube is connected to the drain of the second NMOS tube, and the gate of the ninth PMOS tube is grounded.

10. The bit line voltage transmission circuit according to claim 8, wherein: The positive pressure signal generating circuit further includes: A tenth PMOS tube, wherein the source of the tenth PMOS tube is connected to the power supply voltage, the drain of the ninth PMOS tube is connected to the second node, and the gate of the ninth PMOS tube is connected to a first enable inverted signal, wherein the first enable inverted signal is an inverted signal of the first enable signal.

11. The bit line voltage transmission circuit according to claim 8, wherein: The positive voltage signal generating circuit further includes: an eleventh PMOS tube, a seventh NMOS tube and an eighth NMOS tube; The source of the eleventh PMOS tube and the drain of the seventh NMOS tube are both connected to the second node; The drain of the eleventh PMOS tube and the source of the seventh NMOS tube are both connected to the drain of the eighth NMOS tube; The source of the eighth NMOS tube is grounded; The gate of the eleventh PMOS transistor is connected to the first enable signal, and the gate of the seventh NMOS transistor is connected to a first enable inverted signal, where the first enable inverted signal is an inverted signal of the first enable signal; The gate of the eighth NMOS tube is connected to a current control signal.

12. The bit line voltage transmission circuit according to claim 1, wherein: The selected bit line is the bit line selected from a plurality of bit lines of the memory array by a column address signal; The storage array is composed of a plurality of storage units arranged in an array.

13. The bit line voltage transmission circuit according to claim 12, wherein: The memory cell comprises a select gate sharing split gate flash memory cell.

14. The bit line voltage transmission circuit according to claim 13, wherein: The IO node is a node where a sense amplifier and the bit line are connected, and the IO voltage is generated by the sense amplifier.

15. The bit line voltage transmission circuit according to claim 13, wherein: The second NMOS tube is an intrinsic NMOS tube, and the third NMOS tube is an intrinsic NMOS tube.

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