Chip structure with heat dissipation cover and manufacturing method thereof

Abstract

The invention relates to a manufacturing method of a chip structure with a heat dissipation cover and the chip structure. The manufacturing method of the chip structure with the heat dissipation cover comprises the following steps of: attaching the back surface of a wafer to a first carrier, performing a cutting process to form a plurality of separated chips on the wafer and form grooves among the chips, attaching the active surface of the wafer to a second carrier, removing the first carrier, and forming the heat dissipation cover on the first carrier. The method comprises the following steps of: forming a plurality of grooves on the back surface and the side surface of each chip so as to expose the back surface, the side surface and the grooves of each chip, and then forming a heat dissipation cover on the back surface and the side surface of each chip so as to form a plurality of chip structures with the heat dissipation covers, so that the heat dissipation efficiency of each chip can be improved, metal scraps can be prevented from being generated to pollute each chip, and the heat dissipation covers can be prevented from being separated from the chips.

Description

Technical Field

[0001] The present invention relates to a manufacturing method and structure of a chip structure with a heat dissipation cover, and in particular to a manufacturing method and structure for increasing the heat dissipation efficiency of the chip, avoiding the generation of metal debris and preventing the heat dissipation cover from separating from the chip. Background Art

[0002] As the computing speed of integrated circuits becomes faster and faster, the chip will generate high temperature, and the demand for chip size to continue to shrink is not conducive to chip heat dissipation. When the chip temperature is overheated, it will reduce the computing speed or cause chip damage.

[0003] See also Figure 8 In order to increase the heat dissipation performance of the chip, the active surface 11 of the wafer 10 is first attached to the carrier 20 before the cutting process, and the back side 12 of the wafer 10 is exposed. Then, a heat dissipation layer 30 is formed on the back side 12. Please refer to Fig. 9 Next, the cutting process is performed, with a cutting tool (not shown) cutting the heat dissipation layer 30 and the wafer 10 from the heat dissipation layer 30 toward the active surface 11 of the wafer 10, so that the wafer 10 is formed with a plurality of isolated chips 10a, and the heat dissipation layer 30 is formed with a plurality of heat dissipation fins 30a respectively located on the back side 12a of each chip 10a. Since each heat dissipation fin 30a is formed by cutting the heat dissipation layer 30 and the wafer 10 at the same time, the heat dissipation area of ​​each heat dissipation fin 30a arranged on the back side 12a of each chip 10a is the same as the area of ​​each back side 12a, which will limit the heat dissipation performance of each chip 10a.

[0004] See also Figure 8 and Fig. 9 Since the heat dissipation layer 30 is first formed on the back side 12 of the wafer 10 before the cutting process, when the heat dissipation layer 30 and the wafer 10 are cut simultaneously by the cutting tool, a plurality of metal scraps P will be generated in the heat dissipation layer 30, and the plurality of metal scraps P will be attached to the exposed surface of the carrier 20 and each of the chips 10a.

[0005] See also Fig. 9 When taking and placing each chip 10a, the plurality of metal scraps P remaining on the carrier 20 and the exposed surface of each chip 10a will contaminate the active surface 11a of the chip 10a. In addition, when the heat dissipation layer 20 is cut with the cutting tool, the stress generated will cause the heat dissipation sheet 20a to separate from the chip 10a, thereby affecting the quality and yield of the chip 10a. Summary of the invention

[0006] The main purpose of the present invention is to provide a chip structure manufacturing method with a heat dissipation cover and its structure, which forms a heat dissipation cover on the back and side of the chip after the wafer cutting process to increase the heat dissipation area of ​​the heat dissipation cover and improve the heat dissipation efficiency, and can avoid the cutting tool cutting the heat dissipation cover to generate metal debris, and can increase the mechanical strength of the heat dissipation cover to prevent the heat dissipation cover from detaching from the chip.

[0007] The present invention provides a method for manufacturing a chip structure with a heat dissipation cover, comprising attaching a wafer to a first carrier, the wafer having a plurality of unseparated chips, the wafer being attached to the first carrier with the back side of the chips and exposing the active side of the chips; then, performing a cutting process, cutting the wafer through the cutting paths between the active sides of the chips to separate the chips and forming grooves between the chips, the grooves exposing the side surfaces of the chips; then, attaching the wafer to a second carrier, the wafer being attached to the second carrier with the active sides of the separated chips; then, removing the first carrier to expose the back side, the side side and the grooves between the chips; then, forming a heat dissipation cover on each chip to form a plurality of chip structures with the heat dissipation cover, the heat dissipation cover covering and directly formed on the back side and the side side, the heat dissipation cover having a first portion, a second portion and a connecting portion that are integrally connected, the connecting portion The part is located between the first part and the second part, the first part is formed on the back side, the second part is formed on the side via the groove, the connecting part is located at the outer corner of the back side, there is a first gap between the connecting parts of adjacent chip structures, there is a second gap between the second parts of adjacent chip structures, the first gap is smaller than the second gap, and the first gap and the second gap gradually decrease from the second carrier toward the notch direction of the groove, the first part has a first exposed surface, the second part has a second exposed surface, the connecting part has a third exposed surface connected to the first exposed surface and a fourth exposed surface connected to the second exposed surface, along the axial direction perpendicular to the back side, the first part has a first thickness, along the axial direction perpendicular to the axial direction, the second part has a second thickness, the first thickness is greater than the second thickness, and the second thickness gradually decreases from the connecting part toward the active surface, so that the second exposed surface of the second part is inclined toward the second carrier.

[0008] Preferably, a first extension line extends along the back surface, a second extension line extends along the side surface, the first extension line is located between the second portion and the connecting portion, the second extension line is located between the first portion and the second portion, and the area of ​​the second exposed surface is larger than the area of ​​the side surface.

[0009] Preferably, a first extension line is extended along the back surface, and a second extension line is extended along the side surface, the first extension line L1 is located between the second portion and the connecting portion, the second extension line is located between the first portion and the second portion, the second portion covers a first area of ​​the side surface adjacent to the back surface and exposes a second area of ​​the side surface adjacent to the active surface, and the area of ​​the second exposed surface is larger than the area of ​​the first area.

[0010] Preferably, a first extension line is extended along the back side, and the connecting portion has a first connecting surface located on the first extension line. A second extension line is extended along the side side, and the connecting portion has a second connecting surface located on the second extension line. The area of ​​the second connecting surface is greater than that of the first connecting surface.

[0011] Preferably, along a direction perpendicular to the axis, the connecting portion has a third thickness, the third thickness is greater than the second thickness, the third thickness gradually decreases from the connecting portion toward the second portion, and the fourth exposed surface of the second portion is inclined toward the second carrier.

[0012] Preferably, the width of the groove is not less than 10 μm.

[0013] Preferably, the first thickness is not less than 0.5 μm.

[0014] A chip structure with a heat dissipation cover of the present invention is prepared according to a manufacturing method of the chip structure with a heat dissipation cover. The chip structure includes a chip and a heat dissipation cover. The chip has an active surface, a back surface and a side surface. The heat dissipation cover covers and is directly formed on the back surface and the side surface. The heat dissipation cover has a first part, a second part and a connecting part that are integrally connected. The connecting part is located between the first part and the second part. The first part is formed on the back surface, the second part is formed on the side surface, and the connecting part is located at the outer corner of the back surface. The first part has a first exposed surface, the second part has a second exposed surface, and the connecting part has a third exposed surface connected to the first exposed surface and a fourth exposed surface connected to the second exposed surface. Along the axial direction perpendicular to the back surface, the first part has a first thickness, and along the axial direction perpendicular to the axial direction, the second part has a second thickness, the first thickness is greater than the second thickness, and the second thickness gradually decreases from the connecting part toward the active surface, and an acute angle is formed between the second exposed surface and the side surface.

[0015] Preferably, a first extension line extends along the back surface, a second extension line extends along the side surface, the first extension line is located between the second portion and the connecting portion, the second extension line is located between the first portion and the second portion, and the area of ​​the second exposed surface is larger than the area of ​​the side surface.

[0016] Preferably, a first extension line extends along the back surface, and a second extension line extends along the side surface, the first extension line is located between the second portion and the connecting portion, the second extension line is located between the first portion and the second portion, the second portion covers a first area of ​​the side surface adjacent to the back surface and exposes a second area of ​​the side surface adjacent to the active surface, and the area of ​​the second exposed surface is larger than the area of ​​the first area.

[0017] Preferably, a first extension line is extended along the back side, and the connecting portion has a first connecting surface located on the first extension line. A second extension line is extended along the side side, and the connecting portion has a second connecting surface located on the second extension line. The area of ​​the second connecting surface is greater than that of the first connecting surface.

[0018] Preferably, along a direction perpendicular to the axis, the connecting portion has a third thickness, the third thickness is greater than the second thickness, and the third thickness gradually decreases from the connecting portion toward the second portion.

[0019] Preferably, the first thickness is not less than 0.5 μm.

[0020] The present invention forms the heat dissipation cover on the back side and the side of each chip after cutting the wafer, so as to increase the heat dissipation area of ​​the heat dissipation cover by means of the second part and the connecting part of the heat dissipation cover. Moreover, since the heat dissipation cover is formed on the back side and the side of each chip after the cutting process, it is avoided that the heat dissipation cover is cut by a cutting tool to generate metal debris. In addition, it is also avoided that the heat dissipation cover is separated from the chip due to the stress generated by cutting the heat dissipation cover by the cutting tool. Moreover, the mechanical strength of the heat dissipation cover is increased by means of the second part and the connecting part of the heat dissipation cover to avoid the heat dissipation cover being separated from the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figures 1 to 5 : A schematic diagram of a method for manufacturing a chip structure with a heat dissipation cover according to the present invention.

[0022] Figure 6 and Figure 7 : A cross-sectional view of a chip structure with a heat dissipation cover according to the present invention.

[0023] Figures 8 to 9 : A schematic diagram of a conventional chip manufacturing method.

[0024]

Main component symbol description

[0025] 10: Wafer 10a: Chip

[0026] 11: Active surface 11a: Active surface

[0027] 12: Back 12a: Back

[0028] 20: Carrier 30: Heat dissipation layer

[0029] 30a: Heat sink P: Metal debris

[0030] 100: Wafer 110: Chip

[0031] 111: Active surface 111a: Pad

[0032] 112: back 113: side

[0033] 113a: First zone 113b: Second zone

[0034] 120: cutting road 130: groove

[0035] 131: Notch 140: Heat sink

[0036] 141: Part 1 141a: First exposure surface

[0037] 142: Second part 142a: Second revealing surface

[0038] 143: connection part 143a: third exposed surface

[0039] 143b: fourth exposed surface 143c: first connecting surface

[0040] 143d: second connection surface 200: first carrier

[0041] 300: Second carrier A: Chip structure

[0042] B: acute angle D1: first thickness

[0043] D2: Second thickness D3: Third thickness

[0044] L1: first extension line L2: second extension line

[0045] S1: First gap S2: Second gap

[0046] W: Width Y: Axis DETAILED DESCRIPTION

[0047] See also Figures 1 to 7 , a method for manufacturing a chip structure with a heat dissipation cover of the present invention, which is used to prepare a chip structure A with a heat dissipation cover (see Figure 6 and Figure 7 ).

[0048] The chip structure manufacturing method with heat dissipation cover comprises the following steps. First, refer to Figure 1, a wafer 100 is attached to a first carrier 200, the wafer 100 has a plurality of chips 110 that are not separated into individual pieces, the first carrier 200 can be selected from adhesive tapes, etc., the wafer 100 is attached to the first carrier 200 with the back side 112 of the chip 110, and the active surface 111 of the chip 110 is exposed, the active surface 111 has a plurality of pads 111a, and a redistribution line layer (RDL) (not shown) and / or bumps (not shown) electrically connected to the plurality of pads 111a can be formed on the active surface 111.

[0049] See also Figure 1 and Figure 2 Next, a cutting process is performed, where a cutting tool (not shown) is used to cut the wafer 100 from the active surface 111 toward the back surface 112 along the cutting lanes 120 between the active surfaces 111 of each chip 110 to separate the chips 110 and form grooves 130 between the chips 110, wherein the grooves 130 expose the side surfaces 113 of each chip 110 and the first carrier 200.

[0050] See also Figure 3 Next, the wafer 100 is attached to a second carrier 300. The second carrier 300 may be selected from adhesive tapes, etc. The wafer 100 is attached to the second carrier 300 with the active surface 111 of the individual chip 110 separated. The second carrier 300 covers the active surface 111 and the groove 130. Next, refer to Figure 4 , remove the first carrier 200 to expose the back side 112, the side side 113 of each chip 110 and the groove 130 located between the chips 110. In the present embodiment, the wafer 100, the first carrier 200 and the second carrier 300 bonded together are flipped by a mechanism (not shown) to facilitate the removal of the first carrier 200, but the present invention is not limited thereto.

[0051] See also Figure 5 and Figure 6Then, a heat dissipation cover 140 is formed on the back side 112 and the side 113 of each chip 110 to form a plurality of chip structures A having the heat dissipation cover 140. The method for forming the heat dissipation cover 140 may be selected from physical vapor deposition (PVD), sputtering, evaporation, etc. The heat dissipation cover 140 covers and is directly formed on the back side 112 and the side 113. The heat dissipation cover 140 has a first portion 141, a second portion 142 and a connecting portion 143 that are integrally connected. Preferably, the width W of the groove 130 between the chips 110 is not less than 10 μm and not more than 2000 μm, so as to form a covering The second portion 142 of the side surface 113, the connecting portion 143 is located between the first portion 141 and the second portion 142, the first portion 141 is formed on the back surface 112, the second portion 142 is formed on the side surface 113 via the groove 130, and the connecting portion 143 is located at the outer corner of the back surface 112. In the present embodiment, a first extension line L1 is extended along the back surface 112, and a second extension line L2 is extended along the side surface 113. The first extension line L1 is located between the second portion 142 and the connecting portion 143, and the second extension line L2 is located between the first portion 141 and the second portion 142.

[0052] See also Figure 5 and Figure 6 In this embodiment, the heat dissipation cover 140 covers the back surface 112 and the side surface 113 in a full-cover manner. The second portion 142 of the heat dissipation cover 140 completely covers the side surface 113. The back surface 112 is projected onto the first portion 141, so that the first portion 141 has a first exposed surface 141a corresponding to the back surface 112. The area of ​​the first exposed surface 141a is substantially the same as the area of ​​the back surface 112. The second portion 142 has a second exposed surface 141a corresponding to the side surface 113. The second exposed surface 142a has an area greater than that of the side surface 113, the connecting portion 143 has a third exposed surface 143a connected to the first exposed surface 141a and a fourth exposed surface 143b connected to the second exposed surface 142a, the first extension line L1 is located between the second exposed surface 142a and the fourth exposed surface 143b, the second extension line L2 is located between the first exposed surface 141a and the third exposed surface 143a, or, see Figure 7 The heat dissipation cover 140 covers the back surface 112 and a portion of the side surface 113 in a half-cover manner. Figure 6 The difference between the embodiments is that the second portion 142 of the heat dissipation cover 140 covers the first area 113a of the side surface 113 adjacent to the back surface 112 and exposes the second area 113b of the side surface 113 adjacent to the active surface 111, and the area of ​​the second exposed surface 142a of the second portion 142 is larger than the area of ​​the first area 113a.

[0053] See also Figure 5When forming the heat dissipation cover 140, a first gap S1 is provided between the connecting portions 143 of the adjacent chip structures A, and a second gap S2 is provided between the second portions 142 of the adjacent chip structures A. The first gap S1 is smaller than the second gap S2, and the first gap S1 and the second gap S2 gradually decrease from the second carrier 300 toward the notch 131 of the groove 130. Please refer to Figure 5 , along the axis Y direction perpendicular to the back surface 112, the first portion 141 has a first thickness D1, along the axis Y direction perpendicular to the back surface 112, the second portion 142 has a second thickness D2, the first thickness D1 is greater than the second thickness D2, the second thickness D2 gradually decreases from the connecting portion 143 toward the active surface 111, so that the second exposed surface 142a of the second portion 142 is inclined toward the second carrier 300, even if the second exposed surface 142a and the side surface 113 form an acute angle B, so that the area of ​​the second exposed surface 142A is greater than the area of ​​the side surface 113, the first thickness D1 is not less than 0.5μm, so as to increase the first portion 141 and the second portion 142 are uniform, and along the direction perpendicular to the axis Y, the connecting portion 143 has a third thickness D3, the third thickness D3 is greater than the second thickness D2, and the third thickness D3 gradually decreases from the connecting portion 143 toward the second portion 142, so that the fourth exposed surface 143b of the second portion 142 is inclined toward the second carrier 300 to increase the exposed area of ​​the fourth exposed surface 143b, and by gradually reducing the third thickness D3 from the connecting portion 143 toward the second portion 142, the mechanical strength of the heat dissipation cover 140 is increased to prevent the second portion 142 of the heat dissipation cover 140 from detaching from the side surface 113.

[0054] See also Figure 5 and Figure 6 The connecting portion 143 has a first connecting surface 143c located on the first extension line L1 and a second connecting surface 143d located on the second extension line L2. The third thickness D3 of the connecting portion 143 gradually decreases from the connecting portion 143 toward the second portion 142, so that the area of ​​the second connecting surface 143d is larger than the area of ​​the first connecting surface 143c, thereby increasing the areas of the third exposed surface 143a and the fourth exposed surface 143b of the connecting portion 143.

[0055] See also Figures 5 to 7 The chip structure A prepared according to the chip structure manufacturing method is separated from the second carrier 300 after a pick & place process. The chip structure A includes the chip 110 and the heat dissipation cover 140 directly formed on the back side 112 and the side side 113.

[0056] When the chip structure A is used for a long time due to the operation speed, the heat dissipation area of ​​the heat dissipation cover 140 is increased by the third exposed surface 143a of the connecting portion 143, the fourth exposed surface 143b and the second exposed surface 142a of the second portion 142. Since the heat dissipation cover 140 is formed on the back side 112 and the side side 113 of the chip 110 after the cutting process, the heat dissipation cover 140 can be prevented from being cut by a cutting tool to generate metal debris. The mechanical strength of the heat dissipation cover 140 can be increased by the connecting portion 143 to prevent the heat dissipation cover 140 from being separated from the chip 110.

[0057] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with the profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A method for manufacturing a chip structure with a heat dissipation cover, characterized in that: Include: Attaching a wafer to a first carrier, the wafer having a plurality of unseparated chips, the wafer being attached to the first carrier with the back side of the chips and the active side of the chips exposed; Performing a dicing process to diced the wafer through dicing paths between the active surfaces of the chips to separate the chips and form grooves between the chips, the grooves exposing the side surfaces of the chips; Attaching the wafer to a second carrier, wherein the wafer is attached to the second carrier with the active surface of the separated chips; Removing the first carrier to expose the back side, the side surface and the groove between the chips; and A heat dissipation cover is formed on each of the chips to form a plurality of chip structures having the heat dissipation cover, the heat dissipation cover covers and is directly formed on the back surface and the side surface, the heat dissipation cover has a first portion, a second portion and a connecting portion that are integrally connected, the connecting portion is located between the first portion and the second portion, the first portion is formed on the back surface, the second portion is formed on the side surface via the groove, the connecting portion is located at the outer corner of the back surface, a first gap is provided between the connecting portions of adjacent chip structures, a second gap is provided between the second portions of adjacent chip structures, the first gap is smaller than the second gap, and the first gap is smaller than the second gap. A gap and a second gap gradually decrease from the second carrier toward the notch of the groove, the first part has a first exposed surface, the second part has a second exposed surface, the connecting part has a third exposed surface connected to the first exposed surface and a fourth exposed surface connected to the second exposed surface, along the axial direction perpendicular to the back side, the first part has a first thickness, along the axial direction perpendicular to the back side, the second part has a second thickness, the first thickness is greater than the second thickness, and the second thickness gradually decreases from the connecting part toward the active surface, so that the second exposed surface of the second part is inclined toward the second carrier.

2. The method for manufacturing a chip structure with a heat dissipation cover according to claim 1, characterized in that: A first extension line is extended along the back surface, and a second extension line is extended along the side surface. The first extension line is located between the second portion and the connecting portion, and the second extension line is located between the first portion and the second portion. The area of ​​the second exposed surface is larger than that of the side surface.

3. The method for manufacturing a chip structure with a heat dissipation cover according to claim 1, characterized in that: A first extension line is extended along the back surface, and a second extension line is extended along the side surface. The first extension line L1 is located between the second portion and the connecting portion, and the second extension line is located between the first portion and the second portion. The second portion covers a first area of ​​the side surface adjacent to the back surface and exposes a second area of ​​the side surface adjacent to the active surface. The area of ​​the second exposed surface is larger than that of the first area.

4. The method for manufacturing a chip structure with a heat dissipation cover according to claim 1, characterized in that: A first extension line is extended along the back surface, and the connecting portion has a first connecting surface located on the first extension line. A second extension line is extended along the side surface, and the connecting portion has a second connecting surface located on the second extension line. The area of ​​the second connecting surface is greater than that of the first connecting surface.

5. The method for manufacturing a chip structure with a heat dissipation cover according to claim 1, characterized in that: Along a direction perpendicular to the axis, the connecting portion has a third thickness, the third thickness is greater than the second thickness, and the third thickness gradually decreases from the connecting portion toward the second portion, and the fourth exposed surface of the second portion is inclined toward the second carrier.

6. The method for manufacturing a chip structure with a heat dissipation cover according to claim 1, characterized in that: The width of the groove is not less than 10 μm.

7. The method for manufacturing a chip structure with a heat dissipation cover according to claim 1, characterized in that: The first thickness is not less than 0.5 μm.

8. A chip structure with a heat dissipation cover, prepared by the method for manufacturing the chip structure with a heat dissipation cover as claimed in claim 1, characterized in that: The chip structure includes: A chip having an active surface, a back surface and side surfaces; and A heat dissipation cover covers and is directly formed on the back surface and the side surface. The heat dissipation cover comprises a first portion, a second portion and a connecting portion which are integrally connected. The connecting portion is located between the first portion and the second portion. The first portion is formed on the back surface, the second portion is formed on the side surface, and the connecting portion is located at an outer corner of the back surface. The first portion has a first exposed surface, the second portion has a second exposed surface, and the connecting portion has a third exposed surface connected to the first exposed surface and a fourth exposed surface connected to the second exposed surface. Along an axial direction perpendicular to the back surface, the first portion has a first thickness, and along a direction perpendicular to the axial direction, the second portion has a second thickness, the first thickness is greater than the second thickness, and the second thickness gradually decreases from the connecting portion toward the active surface, and an acute angle is formed between the second exposed surface and the side surface.

9. The chip structure with a heat dissipation cover according to claim 8, characterized in that: A first extension line is extended along the back surface, and a second extension line is extended along the side surface. The first extension line is located between the second portion and the connecting portion, and the second extension line is located between the first portion and the second portion. The area of ​​the second exposed surface is larger than that of the side surface.

10. The chip structure with a heat dissipation cover according to claim 8, characterized in that: A first extension line is extended along the back surface, and a second extension line is extended along the side surface, wherein the first extension line is located between the second portion and the connecting portion, and the second extension line is located between the first portion and the second portion, wherein the second portion covers a first area of ​​the side surface adjacent to the back surface and exposes a second area of ​​the side surface adjacent to the active surface, and an area of ​​the second exposed surface is larger than an area of ​​the first area.

11. The chip structure with a heat dissipation cover according to claim 8, characterized in that: A first extension line is extended along the back surface, and the connecting portion has a first connecting surface located on the first extension line. A second extension line is extended along the side surface, and the connecting portion has a second connecting surface located on the second extension line. The area of ​​the second connecting surface is greater than that of the first connecting surface.

12. The chip structure with a heat dissipation cover according to claim 8, characterized in that: Along a direction perpendicular to the axis, the connecting portion has a third thickness, the third thickness is greater than the second thickness, and the third thickness gradually decreases from the connecting portion toward the second portion.

13. The chip structure with a heat dissipation cover according to claim 8, characterized in that: The first thickness is not less than 0.5 μm.

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