Wafer and chip thereof
By covering the inhibitory parts in the wafer cutting process to increase the tensile strength of the metal layer, the problem of the remnants of the metal layer residue formed a metal wool edge, and the normal combination of the chip and the circuit substrate is avoided, avoiding short circuit or electrical properties. abnormal.
Patent Information
- Application Number
- CN202311019114.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-07-25
- Filing Date
- 2023-08-14
- Publication Date
- 2025-01-28
AI Technical Summary
In the wafer cutting process, the residual portion of the metal layer is easily lifted or metal burrs are formed, resulting in short circuits or electrical abnormalities when the chip is bonded to the circuit substrate.
By covering the inhibitory parts on the cutway and the chip next to it, the tensile strength of the metal layer is increased to prevent the residue from being lifted, and the inhibitory department is retained after the cutting track is removed to support the joint.
Effectively prevent the metal residue from being lifted or formed by the formation of metal hair edges, avoiding short -circuit or electrical abnormal problems of chips and circuit substrates.
Smart Images
Figure CN119381351A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a wafer and a chip thereof, in particular to a wafer and a chip thereof which can prevent a metal layer from being lifted or metal burrs from being generated during a cutting process. Background Art
[0002] See also Figures 1 to 3 The conventional wafer 10 includes a plurality of chips 11, a plurality of scribe lines 12 and at least one metal layer 13. The scribe lines 12 are located between the adjacent chips 11. The metal layer 13 is disposed on the scribe lines 12 and extends to the chips 110 adjacent to the scribe lines 12. Figure 2 and Figure 3 The metal layer 13 may be a test pad, a mark or a circuit located on the cutting path 12 .
[0003] See also Figures 1 to 3 In the cutting process, the wafer 10 is cut along the multiple cutting lanes 12 to separate the multiple chips 11. In the cutting process, the cut metal layer 13 will leave a residual portion 13a on the multiple chips 11. Due to the ductility of the material of the metal layer 13, the residual portion 13a will be lifted up or a metal burr 13b will be formed.
[0004] See also Figure 3 When the pin 21 of the circuit substrate is connected to the bump 14 of the chip 11, if the pin 21 contacts the lifted residual portion 13c or the metal burr 13d, a short circuit or electrical abnormality may occur between the chip 11 and the circuit substrate. Summary of the invention
[0005] The main purpose of the present invention is to provide a wafer and a chip thereof, which covers the cutting path and the chip next to the cutting path by an inhibitor to increase the tensile strength of the metal layer arranged on the cutting path and extending to the chip, so as to prevent the residual part of the metal layer after cutting from being lifted up or forming metal burrs.
[0006] A wafer of the present invention comprises a plurality of chips, at least one cutting path and at least one metal layer, wherein the cutting path is located between adjacent chips, and the metal layer is arranged on the cutting path and extends to the chip beside the cutting path. The wafer further comprises an inhibitory member, which is formed of a non-conductive material and covers at least the cutting path and the chip beside the cutting path. The inhibitory member has a first portion to be removed and an inhibitory member, wherein the first portion to be removed is located above the second portion to be removed of the metal layer, and the inhibitory member is located above the residual portion of the metal layer. During the cutting process, the cutting path, the first portion to be removed and the second portion to be removed located on the cutting path are removed, and the inhibitory member and the residual portion are retained on the chip.
[0007] Preferably, the protective layer of the chip covers the residual portion and exposes the second portion to be removed, the first portion to be removed covers the second portion to be removed, the inhibition member covers the protective layer, the protective layer is located between the inhibition portion and the residual portion, the inhibition portion has a first height, the protective layer has a second height, and the first height is greater than the second height.
[0008] Preferably, each chip includes at least one pad and a sealing ring, the sealing ring surrounds the pad, the suppression portion has a first side wall adjacent to the sealing ring, the residual portion has a second side wall adjacent to the sealing ring, a first edge line extends along the first side wall, a second edge line extends along the second side wall, and a first distance from the first edge line to the second edge line is not less than 5μm.
[0009] Preferably, the second distance between the sealing ring and the first edge line is not less than 1 μm.
[0010] Preferably, each of the chips has at least one bump, the bump has a third height protruding from the protection layer, and the first height is not greater than the third height.
[0011] Preferably, the first height is smaller than the third height, and the difference between the third height and the first height is no more than 7 μm.
[0012] Preferably, the active surface of each chip has a bump arrangement area, and adjacent inhibition members have openings therebetween, the openings being connected to the bump arrangement area.
[0013] Preferably, the active surface of each chip has a bump setting area, and along the axial direction of the bump setting area toward the inhibitor, the cutting path has a first width, the metal layer has a second width, and the inhibitor has a third width, the first width is smaller than the second width, and the second width is smaller than the third width.
[0014] Preferably, along a direction perpendicular to the axis, the inhibitor has a length that is not less than 60 μm.
[0015] A chip of the present invention has an active surface and a side wall. The chip includes an inhibition portion and a residual portion. The inhibition portion is formed of a non-conductive material. The inhibition portion is retained on the active surface after the first portion to be removed of the inhibition member is removed. The inhibition portion has a first section exposed on the side wall and a first side wall relative to the first section. The residual portion is retained on the chip after the second portion to be removed of the metal layer is removed. The inhibition portion is located above the residual portion. The residual portion includes a second section exposed on the side wall and a second side wall relative to the second section.
[0016] Preferably, a protective layer is further included, the protective layer covers the residual portion, the suppression portion covers the protective layer, the protective layer is located between the suppression portion and the residual portion, the suppression portion has a first height, the protective layer has a second height, and the first height is greater than the second height.
[0017] Preferably, a first sideline is extended along the first side wall, a second sideline is extended along the second side wall, and a first distance between the first sideline and the second sideline is not less than 5 μm.
[0018] Preferably, the first section and the second section are flush with the side wall.
[0019] Preferably, each of the chips comprises at least one pad and a sealing ring, the sealing ring surrounds the pad, and a second distance between the sealing ring and the first edge is not less than 1 μm.
[0020] Preferably, each chip has a bump, the bump has a third height protruding from the protection layer, and the first height is not greater than the third height.
[0021] Preferably, the first height is smaller than the third height, and the difference between the third height and the first height is no more than 7 μm.
[0022] Preferably, the active surface of each chip has a bump arrangement area, and adjacent inhibition members have openings therebetween, the openings communicating with the bump arrangement area.
[0023] Preferably, the active surface of each chip has a bump setting area, and along the axial direction of the bump setting area toward the inhibitor, the cutting path has a first width, the metal layer has a second width, and the inhibitor has a third width, the first width is smaller than the second width, and the second width is smaller than the third width.
[0024] Preferably, along a direction perpendicular to the axis, the inhibiting portion has a length that is not less than 60 μm.
[0025] The present invention covers the cutting path and the chip beside the cutting path by the suppression member to increase the tensile strength of the metal layer, so as to prevent the residual portion remaining on the chip from being lifted by the cutting tool or forming metal burrs when removing the cutting path and the first portion to be removed and the second portion to be removed located on the cutting path. After removing the cutting path and the first portion to be removed and the second portion to be removed located on the cutting path, the suppression member retained on the chip supports the pins of the circuit board (not shown) connected to the chip to avoid the pins contacting the first section of the suppression member and the second section of the residual portion, thereby preventing short circuits or electrical abnormalities from occurring. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 : Schematic diagram of a conventional wafer.
[0027] Figure 2 : A cross-sectional view of a conventional wafer.
[0028] Figure 3 : A cross-sectional view of a conventional chip.
[0029] Figure 4 : A partial schematic diagram of the wafer of the present invention.
[0030] Figure 5 : A cross-sectional view of a wafer of the present invention.
[0031] Figure 6 : A cross-sectional view of a wafer of the present invention.
[0032] Figure 7 : A cross-sectional view of a chip of the present invention.
[0033] Figure 8 : A cross-sectional view of a chip of the present invention.
[0034]
Main component symbol description
[0035] 10: Wafer 11: Chip
[0036] 12: Cutting road 13: Metal layer
[0037] 13a: Residual part 13b: Metal burrs
[0038] 14: Bump 21: Pin
[0039] 100: Wafer 110: Chip
[0040] 110a: Active surface 110b: Bump setting area
[0041] 110c: side wall 111: protective layer
[0042] 112: pad 113: sealing ring
[0043] 114: Bump 120: Cutting path
[0044] 130: metal layer 131: second portion to be removed
[0045] 132: Remaining portion 132a: Second side wall
[0046] 132b: Second section 140: Inhibitor
[0047] 141: first portion to be removed 142: suppression portion
[0048] 142a: first side wall 142b: first section
[0049] 143: Opening D1: First distance
[0050] D2: Second distance S1: First sideline
[0051] S2: Second sideline H1: First height
[0052] H2: Second height H3: Third height
[0053] L: length W1: first width
[0054] W2: second width W3: third width
[0055] X: Axis DETAILED DESCRIPTION
[0056] See also Figures 4 to 6 A wafer 100 of the present invention comprises a plurality of chips 110, at least one cutting path 120, at least one metal layer 130 and an inhibitor 140, wherein the inhibitor 140 is formed of a non-conductive material, which may be selected from a polymer material, but is not limited thereto, wherein the cutting path 120 is located between the plurality of adjacent chips 110, wherein an active surface 110a of each of the chips 110 has a bump setting area 110b, wherein each of the chips 110 comprises a protective layer 111, at least one pad 112, a sealing ring 113 and at least one bump 114, wherein the sealing ring 113 surrounds the pad 111, wherein the active surface 110a is a surface of the protective layer 111, wherein the protective layer 111 covers the sealing ring 113 and exposes the pad 112, wherein the pad 112 is disposed in the bump setting area 110b, and wherein the bump 114 is electrically connected to the pad 112.
[0057] See also Figure 5 and Figure 6 The metal layer 130 is disposed on the scribe line 120 and extends to the chip 110 beside the scribe line 120. The metal layer 130 can be a test pad, a mark (see Figure 5 ) and or lines (see Figure 6 ), the metal layer 130 has a second portion to be removed 131 and a residual portion 132, the second portion to be removed 131 is located at the dicing street 120, the residual portion 132 is located at the chip 110, and the protective layer 111 at least covers the residual portion 132, see Figure 5 When the metal layer 130 is a test pad and / or a mark, the protective layer 111 reveals the second portion to be removed 131, see Figure 6 When the metal layer 130 is a circuit, the protection layer 111 covers the second portion to be removed 131 .
[0058] See also Figure 4 , Figure 5 and Figure 6The suppressor 140 at least covers the scribe line 120 and the chip 110 beside the scribe line 120. Figure 4 There is an opening 143 between adjacent inhibitors 140, and the opening 143 is connected to the bump setting area 110b. The opening 143 is used for filling glue (not shown) to flow to the bump setting area 110b to seal the bump 114 and the pin (not shown) connected to the bump 114. When the metal layer 130 can be a test pad or a mark, along the axis X direction from the bump setting area 110b to the inhibitor 140, the cutting road 120 has a first width W1, the metal layer 130 has a second width W2, and the inhibitor 140 has a third width W3, the first width W1 is smaller than the second width W2, and the second width W2 is smaller than the third width W3, and along the direction perpendicular to the axis X, the inhibitor 140 has a length L, and the length L is not less than 60μm, so as to increase the adhesion of the inhibitor 140 to the wafer 100.
[0059] See also Figure 5 and Figure 6 The inhibiting member 140 has a first portion to be removed 141 and an inhibiting portion 142. The first portion to be removed 141 is located above the second portion to be removed 131 of the metal layer 130. Figure 5 When the metal layer 130 is a test pad and / or a mark, the first portion to be removed 141 covers the second portion to be removed 131, see Figure 6 When the metal layer 130 is a circuit, the first portion to be removed 141 covers the protective layer 111, the protective layer 111 covers the second portion to be removed 131, the inhibition portion 142 is located above the residual portion 132 of the metal layer 130, the inhibition member 140 covers the protective layer 111, and the protective layer 111 is located between the inhibition portion 142 and the residual portion 132.
[0060] See also Figure 5 and Figure 6 The suppression portion 142 has a first height H1, and the protective layer 111 has a second height H2. The first height H1 is greater than the second height H2, so that the flexural strength of the protective layer 111 is increased by the suppression portion 142. The bump 114 has a third height H3 protruding from the protective layer 111, and the first height H1 is not greater than the third height H3. Preferably, the first height H1 is less than the third height H3, and the difference between the third height H3 and the first height H1 is not greater than 7μm.
[0061] See also Figure 5 and Figure 6The suppression portion 142 has a first side wall 142a adjacent to the sealing ring 113, the residual portion 132 has a second side wall 132a adjacent to the sealing ring 113, a first side line S1 extends along the first side wall 142a, a second side line S2 extends along the second side wall 132a, a first distance D1 from the first side line S1 to the second side line S2 is not less than 5 μm, and a second distance D2 from the sealing ring 113 to the first side line S1 is not less than 1 μm.
[0062] See also Figures 5 to 8 In the dicing process, a dicing tool (not shown) is used to dicing the wafer 100 along the dicing road 120 to separate the plurality of chips 110 and to make the chip 110 have a sidewall 110c, see Figure 7 and Figure 8 In the cutting process, the tool removes the cutting path 120 and the first to-be-removed portion 141 and the second to-be-removed portion 131 located on the cutting path 120, so that the inhibiting portion 142 and the residual portion 132 are retained on the chip 110, and the inhibiting portion 142 and the residual portion 132 respectively have a first section 142b and a second section 132b exposed on the side wall 110c, the first section 142b of the inhibiting portion 142 is relative to the first side wall 142a, the second section 132b of the residual portion 132 is relative to the second side wall 132a, and the first section 142b and the second section 132b are flush with the side wall 110c.
[0063] See also Figure 7 and Figure 8 In the cutting process, since the inhibiting portion 142 is retained on the active surface 110a of the chip 110 after removing the first portion to be removed 141, the length of the inhibiting portion 142 is the same as the length L of the inhibiting member 140. The inhibiting member 140 covers the cutting path 120 and the chip 110 beside the cutting path 120 to increase the tensile strength of the metal layer 130, so as to prevent the residual portion 132 remaining on the chip 110 from being lifted by the cutting tool. The suppressing portion 142 is retained on the chip 110 and the first height H1 of the suppressing portion 142 is not greater than the third height H3 of the bump 114, so that the residual portion 132 can support the pin 210 of the circuit board (not shown) connected to the bump 114, so as to avoid the pin 210 contacting the first section 142b of the suppressing portion 142 and the second section 132b of the residual portion 132, thereby preventing a short circuit or electrical abnormality from occurring.
[0064] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with the profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the technical solution of the present invention.
Claims
1. A wafer comprising a plurality of chips, at least one scribe line and at least one metal layer, wherein the scribe line is located between the plurality of adjacent chips, the metal layer is disposed on the scribe line and extends to the chip next to the scribe line, wherein: The wafer further includes an inhibition member, which is formed of a non-conductive material. The inhibition member at least covers the cutting path and the chip next to the cutting path. The inhibition member has a first portion to be removed and an inhibition member. The first portion to be removed is located above the second portion to be removed of the metal layer. The inhibition member is located above the residual portion of the metal layer. During the cutting process, the cutting path, the first portion to be removed and the second portion to be removed located on the cutting path are removed, and the inhibition member and the residual portion are retained on the chip.
2. The wafer according to claim 1, characterized in that: The protective layer of the chip covers the residual portion and exposes the second portion to be removed, the first portion to be removed covers the second portion to be removed, the inhibition member covers the protective layer, the protective layer is located between the inhibition portion and the residual portion, the inhibition portion has a first height, the protective layer has a second height, and the first height is greater than the second height.
3. The wafer according to claim 1, characterized in that: Each chip includes at least one pad and a sealing ring, the sealing ring surrounds the pad, the suppression portion has a first side wall adjacent to the sealing ring, the residual portion has a second side wall adjacent to the sealing ring, a first edge line extends along the first side wall, a second edge line extends along the second side wall, and a first distance between the first edge line and the second edge line is not less than 5μm.
4. The wafer according to claim 3, characterized in that: A second distance between the sealing ring and the first edge line is not less than 1 μm.
5. The wafer according to claim 2, characterized in that: Each chip has at least one bump, and the bump has a third height protruding from the protection layer, and the first height is not greater than the third height.
6. The wafer according to claim 5, characterized in that: The first height is smaller than the third height, and a difference between the third height and the first height is no greater than 7 μm.
7. The wafer according to claim 1, characterized in that: The active surface of each chip has a bump setting area, and adjacent inhibition members have openings between them, and the openings are connected to the bump setting area.
8. The wafer according to claim 1, characterized in that: The active surface of each chip has a bump setting area. Along the axial direction of the bump setting area toward the inhibitor, the cutting path has a first width, the metal layer has a second width, and the inhibitor has a third width. The first width is smaller than the second width, and the second width is smaller than the third width.
9. The wafer according to claim 8, characterized in that: The suppressing member has a length along a direction perpendicular to the axis, and the length is not less than 60 μm.
10. A chip having an active surface and a side wall, characterized in that: The chip contains: an inhibiting portion formed of a non-conductive material, the inhibiting portion being retained on the active surface after the first to-be-removed portion of the inhibiting member is removed, the inhibiting portion having a first section exposed on the side wall and a first side wall opposite to the first section; and The residual portion is retained on the chip after the second to-be-removed portion of the metal layer is removed. The inhibiting portion is located above the residual portion. The residual portion includes a second section exposed on the side wall and a second side wall opposite to the second section.
11. The chip according to claim 10, characterized in that: It also includes a protective layer, which covers the residual part, the suppression part covers the protective layer, the protective layer is located between the suppression part and the residual part, the suppression part has a first height, the protective layer has a second height, and the first height is greater than the second height.
12. The chip according to claim 10, characterized in that: A first sideline is extended along the first side wall, and a second sideline is extended along the second side wall. A first distance between the first sideline and the second sideline is not less than 5 μm.
13. The chip according to claim 10, characterized in that: The first section and the second section are flush with the side wall.
14. The chip according to claim 12, characterized in that: Each chip includes at least one pad and a sealing ring. The sealing ring surrounds the pad, and a second distance between the sealing ring and the first edge is not less than 1 μm.
15. The chip according to claim 11, characterized in that: Each chip has a bump, and the bump has a third height protruding from the protection layer, and the first height is not greater than the third height.
16. The chip according to claim 15, characterized in that: The first height is smaller than the third height, and a difference between the third height and the first height is no greater than 7 μm.
17. The chip according to claim 10, characterized in that: The active surface of each chip has a bump setting area, and adjacent inhibition members have openings between them, and the openings are connected to the bump setting area.
18. The chip according to claim 10, characterized in that: The active surface of each chip has a bump setting area. Along the axial direction of the bump setting area toward the inhibitor, the cutting path has a first width, the metal layer has a second width, and the inhibitor has a third width. The first width is smaller than the second width, and the second width is smaller than the third width.
19. The chip according to claim 18, characterized in that: The inhibiting portion has a length along a direction perpendicular to the axis, and the length is not less than 60 μm.