Semiconductor chip package and manufacturing method thereof

Abstract

The invention relates to a semiconductor chip package and a manufacturing method thereof. The semiconductor chip package includes: a lead frame having a first side and a second side opposite to each other, the lead frame having a first groove recessed from the first side of the lead frame; the first groove is filled with the adhesive; and a semiconductor chip disposed on the first side of the lead frame and the adhesive; wherein the width of the first groove is not greater than the width of the semiconductor chip.

Description

Technical Field

[0001] The present invention relates to a semiconductor chip package and a method for manufacturing the same, and more particularly, to a semiconductor chip package with a lead frame. Background Art

[0002] The semiconductor chip can be mounted on the chip pad of the lead frame by an adhesive and electrically connected to the lead contact of the lead frame by a conductive wire. A molding compound is then formed to encapsulate the power chip and the lead frame. As the package structure becomes smaller, the area of ​​the chip pad is reduced and the distance from the edge of the power chip to the chip pad is also shortened, so that the adhesive may overflow. In addition, since the lead frame is usually thin and has a fine pattern, it may be damaged or deformed due to mechanical or thermal stress during the manufacturing process. One of the objectives of the present invention is to avoid adhesive overflow and improve the stability of the lead frame, thereby improving the process yield. Summary of the invention

[0003] An embodiment of the present disclosure relates to a semiconductor chip package. The semiconductor chip package includes: a lead frame having a first side and a second side opposite to each other, and the lead frame having a first groove recessed from the first side of the lead frame; an adhesive filled in the first groove; and a semiconductor chip disposed on the first side of the lead frame and the adhesive; wherein the width of the first groove is not greater than the width of the semiconductor chip.

[0004] An embodiment of the present disclosure relates to a semiconductor chip package. The semiconductor chip package includes: a lead frame having a first side and a second side opposite to each other, and the lead frame having a first groove recessed from the first side of the lead frame; an adhesive filled in the first groove; a semiconductor chip disposed on the first side of the lead frame and the adhesive; and a carrier disposed on the second side of the lead frame.

[0005] The embodiment of the present disclosure relates to a method for manufacturing a semiconductor chip package. The method includes: obtaining a lead frame having a first side and a second side opposite to each other, and the lead frame having a first groove recessed from the first side of the lead frame; filling an adhesive in the first groove; and arranging a semiconductor chip on the first side of the lead frame and the adhesive, wherein the width of the first groove is not greater than the width of the semiconductor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of several embodiments of the present disclosure may be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that various structures may not be drawn to scale. In fact, the dimensions of various structures may be arbitrarily enlarged or reduced for clarity of discussion.

[0007] Figure 1A Shown is a perspective view of a portion of a semiconductor chip package according to some embodiments of the present case;

[0008] Figure 1B Shown is a perspective view of a portion of a semiconductor chip package according to some embodiments of the present case;

[0009] Figure 1C Shown is a cross-sectional view of a semiconductor chip package according to some embodiments of the present invention;

[0010] Figure 2A , 2B One or more stages in a method of manufacturing a semiconductor chip package according to some embodiments of the present invention are shown;

[0011] Figure 3A-1 , 3A-2 , 3B, 3C, 3D-1, 3D-2, 3E-1, 3E-2, 3F, 3G, 3H show one or more stages in a method of manufacturing a semiconductor chip package according to some embodiments of the present invention;

[0012] Figure 4A Shown is a perspective view of a portion of a semiconductor chip package according to some embodiments of the present case;

[0013] Figure 4B Shown are one or more stages in a method of manufacturing a semiconductor chip package according to some embodiments of the present disclosure.

[0014] The same or similar components are marked with the same reference numerals in the drawings and detailed description. Several embodiments of the present disclosure will be immediately understood from the following detailed description in conjunction with the accompanying drawings. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below. Of course, these are only examples and are not intended to be restrictive. In the present disclosure, references to forming a first feature above or on a second feature may include embodiments in which the first feature and the second feature are formed to be in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] The following is a detailed discussion of embodiments of the present disclosure. However, it should be understood that the present disclosure provides many applicable concepts that can be embodied in a variety of specific environments. The specific embodiments discussed are merely illustrative and do not limit the scope of the present disclosure.

[0017] The present disclosure provides a semiconductor chip package and a method for manufacturing the same.

[0018] The semiconductor chip package disclosed in the present invention mounts the semiconductor chip on the chip pad of the lead frame by means of an adhesive, and is electrically connected to the lead contact of the lead frame by means of a conductive member (such as a wire or a copper strip). The adhesive is filled into the groove of the chip pad to prevent the adhesive from overflowing and to improve the stability of the lead frame, thereby improving the process yield. In addition, the semiconductor chip package disclosed in the present invention uses a clamp to fix the lead frame on the carrier during the manufacturing process to prevent the lead frame from warping. The portion of the carrier used to carry the chip pad uses a material with relatively high thermal conductivity to improve the thermal conductivity of the semiconductor chip package.

[0019] Figure 1A FIG. 1 is a perspective view of a portion of a semiconductor chip package 1 a according to some embodiments of the present invention.

[0020] The semiconductor chip package 1a may include a carrier 20 , a lead frame 10 , and a semiconductor chip 11 . The carrier 20 , the lead frame 10 , and the semiconductor chip 11 may be stacked on each other in one direction. The semiconductor chip 11 and the carrier 20 may be disposed on opposite sides of the lead frame 10 .

[0021] The carrier 20 may include a portion 11ac having a relatively high thermal conductivity (or referred to as a first portion) and portions 11gm, 11sm, and 11dm having a relatively low thermal conductivity (or referred to as a first portion). The portion 11ac, the portion 11gm, the portion 11sm, and the portion 11dm may be physically separated. The portion 11ac, the portion 11gm, the portion 11sm, and the portion 11dm may not be in direct contact with each other. The portion 11ac, the portion 11gm, the portion 11sm, and the portion 11dm may be separated by an insulating layer (e.g., Figure 1C The insulating layer 30) is used to separate the two layers.

[0022] The portion 11ac may overlap with the semiconductor chip 11. For example, the portion 11ac, a portion of the lead frame 10 (eg, the die pad 11a), and the semiconductor chip 11 may be stacked on each other in one direction. The portion 11gm, the portion 11sm, and the portion 11dm may not overlap with the semiconductor chip 11.

[0023] The sizes (e.g., width, thickness, area, etc.) of the portions 11ac, 11gm, 11sm, and 11dm may be the same as or different from each other. The width of the portion 11ac may be greater than the width of the portion 11gm, 11sm, or 11dm. In addition, the thicknesses of the portions 11ac, 11gm, 11sm, and 11dm may be the same as each other.

[0024] The portion 11ac may include a ceramic material, such as an oxide (e.g., beryllium oxide (BeO), aluminum oxide (Al2O3)), a nitride (e.g., aluminum nitride (AlN), silicon nitride (Si3N4)), a boride (e.g., boron nitride (BN)), a carbide (e.g., silicon carbide (SiC)), other ceramic materials (e.g., diamond (C)), or a combination of two or more thereof. The thermal conductivity of the portion 11ac may be higher than 100 Wm -1 K -1 , higher than 150Wm -1 K -1 , higher than 200Wm -1 K -1 For example, the portion 11ac may include aluminum nitride (AlN), which may have a thermal conductivity between 170 Wm -1 K -1 With 230Wm -1 K -1 between.

[0025] The portion 11ac may be configured to conduct the heat of the semiconductor chip 11 to the outside through a portion of the lead frame 10 (e.g., the chip pad 11a). By using the portion 11ac having a relatively high thermal conductivity, the thermal conductivity may be increased by at least 10% compared to the exemplary embodiment in which the material having a relatively high thermal conductivity is not used, thereby achieving the effect of reducing the device resistance.

[0026] The portion 11gm, the portion 11sm, and the portion 11dm may include a metal material, such as a conductive material including a metal, a metal alloy, or a silicided metal. Examples of the conductive material may include gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), other metals or alloys, or a combination of two or more thereof.

[0027] The portion 11gm, the portion 11sm, and the portion 11dm may be configured to serve as external terminals to provide electrical connections between the semiconductor chip package 1a and external devices (eg, a printed circuit board (PCB), other packages, or other electronic components).

[0028] In some embodiments, portion 11ac may include a metallic material, such as the materials listed for portion 11gm, portion 11sm, and portion 11dm.

[0029] The lead frame 10 may include a die pad 11a, a gate lead contact 11g, a source lead contact 11s, and a drain lead contact 11d. The die pad 11a, the gate lead contact 11g, the source lead contact 11s, and the drain lead contact 11d may be physically separated. The die pad 11a, the gate lead contact 11g, the source lead contact 11s, and the drain lead contact 11d may not be in direct contact with each other. The die pad 11a, the gate lead contact 11g, the source lead contact 11s, and the drain lead contact 11d may be connected to each other by an encapsulant (e.g. Figure 1C The encapsulating agent 14) is separated from each other.

[0030] The dimensions (e.g., width, thickness, area, etc.) of the die pad 11a, the gate lead contact 11g, the source lead contact 11s, and the drain lead contact 11d may be the same or different from each other. The width of the die pad 11a may be greater than the width of the gate lead contact 11g, the source lead contact 11s, or the drain lead contact 11d. In addition, the thicknesses of the die pad 11a, the gate lead contact 11g, the source lead contact 11s, and the drain lead contact 11d may be the same as each other.

[0031] The lead frame 10 may include a metal material, such as a conductive material such as a metal or a metal alloy. Examples of the conductive material may include gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), other metals or alloys, or a combination of two or more thereof.

[0032] The chip pad 11a may be configured to carry the semiconductor chip 11. For example, the semiconductor chip 11 may be disposed on the chip pad 11a. The gate lead contact 11g, the source lead contact 11s, and the drain lead contact 11d may each be configured to couple (or electrically connect) the electrical terminals of the semiconductor chip 11. The gate lead contact 11g, the source lead contact 11s, and the drain lead contact 11d may each be configured to couple (or electrically connect) the electrical terminals of the semiconductor chip 11 to external terminals (e.g., portions 11gm, 11sm, and 11dm of the carrier 20).

[0033] Reference Figure 1B , Figure 1B Depiction Figure 1A A lead frame 10 of a semiconductor chip package 1 a.

[0034] The lead frame 10 may have a surface (or first surface, first side) 101 and a surface (or second surface, second side) 102 opposite to each other. The chip pad 11a of the lead frame 10 may have a groove (or first groove) 11ar recessed from the surface 101. The gate lead contact 11g and the source lead contact 11s of the lead frame 10 may have grooves (or second grooves) 11gr and 11sr recessed from the surface 102. Although Figure 1B The groove 11ar in the embodiment is square or rectangular, but the present disclosure is not limited thereto. In some embodiments, the top view of the groove 11ar may be rectangular, circular, hexagonal or any other shape. In some embodiments, the position, shape, area ratio, quantity, etc. of the groove 11ar may be adjusted to be applied to different packages.

[0035] The adhesive 13 may be filled in the groove 11ar of the die pad 11a of the lead frame 10. The adhesive 13 may have a surface 131 substantially coplanar with the surface 101 of the lead frame 10. The adhesive 13 may include a conductive adhesive, a conductive epoxy, and / or solder.

[0036] Return to reference Figure 1A , when the semiconductor chip 11 is placed on the chip pad 11a, Figure 1B The adhesive 13 can be completely covered by the semiconductor chip 11, which prevents the adhesive 13 from overflowing and improves the stability of the lead frame 10, thereby improving the process yield.

[0037] The semiconductor chip 11 may include circuit components such as transistors, resistors, capacitors, and interconnect structures to form an integrated circuit (IC). In some embodiments, the semiconductor chip 11 may include a metal-oxide-semiconductor field-effect transistor (MOSFET), such as NMOS, PMOS, CMOS, a voltage feedback device, and / or a switch. In some embodiments, the semiconductor chip 11 may include a double-diffused MOSFET (DMOSFET), an insulated-gate bipolar transistor (IGBT), a junction gate field-effect transistor (JFET), a power bipolar transistor, or a power diode (such as a power Schottky diode).

[0038] The semiconductor chip 11 may have a surface 111 and a surface 112 opposite to the surface 111. The surface 112 may contact (eg, directly contact) an adhesive (eg, Figure 1B The surface 112 may contact (eg, directly contact) a surface of the lead frame 10 (eg, Figure 1B surface 101 ) to conduct heat to portion 11ac of the carrier 20 .

[0039] One or more electrical terminals may be exposed from the surface 111 and / or the surface 112 of the semiconductor chip 11. For example, the gate G and the source S of the semiconductor chip 11 may be located on the same side of the semiconductor chip 11 and the drain D may be located on the opposite side. The gate G and the source S of the semiconductor chip 11 may be located on the surface 111, and the drain D may be located on the surface 112.

[0040] The gate G of the semiconductor chip 11 may be coupled (or electrically connected) to the gate lead contact 11g of the lead frame 10 through a wire 11gw. The gate lead contact 11g may be configured to couple (or electrically connect) the gate G of the semiconductor chip 11 to an external terminal (e.g., a portion 11gm of the carrier 20).

[0041] The source S of the semiconductor chip 11 may be coupled (or electrically connected) to the source lead contact 11s of the lead frame 10 through a wire 11sw. The source lead contact 11s may be configured to couple (or electrically connect) the source S of the semiconductor chip 11 to an external terminal (eg, a portion 11sm of the carrier 20).

[0042] The drain D of the semiconductor chip 11 may be coupled (or electrically connected) to the adhesive 13. The drain D of the semiconductor chip 11 may be coupled (or electrically connected) to the drain lead contact 11d of the lead frame 10 through the adhesive 13, the chip pad 11a, and the wire 11dw. The drain lead contact 11d may be configured to couple (or electrically connect) the drain D of the semiconductor chip 11 to an external terminal (e.g., a portion 11dm of the carrier 20).

[0043] In some embodiments, the wires 11gw, 11sw, and 11dw may be replaced by copper strips or copper sheets, and the electrical terminals of the semiconductor chip 11 are connected to the lead frame 10 by copper clip bonding.

[0044] In some embodiments, in order to improve thermal conductivity, the portion 11ac may be made of non-conductive ceramic material. Since the chip pad 11a is carried on the portion 11ac, the portion 11ac may be non-conductive, so the wire 11dw and the drain lead contact 11d are required to couple (or electrically connect) the drain D of the semiconductor chip 11 to the external terminal (for example, the portion 11dm of the carrier 20). In some embodiments, the portion 11ac may be made of conductive metal material to provide the drain D with an optimal conductive path.

[0045] Figure 1CFIG. 1 is a cross-sectional view of a semiconductor chip package 1a according to some embodiments of the present invention. Figure 1C The cross-sectional diagram is Figure 1A The same or similar elements are denoted by the same symbols, and the detailed description of the same or similar elements will not be repeated.

[0046] The semiconductor chip package 1a may include an encapsulant 14 and an insulating layer 30 in addition to the carrier 20, the lead frame 10 and the semiconductor chip 11. Figure 1A The encapsulant 14 and the insulating layer 30 are omitted in the perspective view of FIG. Figure 1C The cross-sectional view omits a portion 11gm and a portion 11sm of the carrier 20 , and a gate lead contact 11g and a source lead contact 11s of the lead frame 10 .

[0047] The insulating layer 30 may be filled in the carrier 20. For example, the insulating layer 30 may be filled between any two of the portion 11ac, the portion 11gm, the portion 11sm, and the portion 11dm of the carrier 20. The insulating layer 30 may contact a portion of the encapsulant 14.

[0048] The encapsulant 14 may contact, cover or encapsulate the semiconductor chip 11. Figure 1B The encapsulant 14 may contact, cover or encapsulate the chip pad 11a, gate lead contact 11g, source lead contact 11s and drain lead contact 11d of the lead frame 10. The encapsulant 14 may contact, cover or encapsulate the surface 101 of the lead frame 10. The encapsulant 14 may not contact the adhesive 13. The encapsulant 14 may be filled in the grooves 11gr and 11sr to improve the structural stability of the lead frame 10.

[0049] The insulating layer 30 and the encapsulant 14 may each include an insulating material or a dielectric material. Examples of the insulating material may include epoxy resin with fillers, molding materials or molding compounds, polyimide, phenolic compounds, silicone-containing materials, or combinations thereof. Examples of dielectric materials may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (Si2N2O), borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), undoped silicon glass (USG), fluorosilicate glass (FSG), spin-on glass (SOG), any combination of two or more thereof, and the like. The insulating layer 30 and the encapsulant 14 may include the same material. The insulating layer 30 and the encapsulant 14 may include different materials.

[0050] In some embodiments, the insulating layer 30 may be made of ceramic material to reduce the coefficient of thermal expansion (CTE) between the carrier 20 (which may include metal material) and the encapsulant 14 (which may include insulating material) and improve thermal conductivity.

[0051] As described above, the adhesive 13 may be filled in the groove 11ar of the die pad 11a of the lead frame 10 and completely covered by the semiconductor chip 11. The width w1 of the adhesive 13 or the groove 11ar may not be greater than the width w2 of the semiconductor chip 11. The width w1 of the adhesive 13 or the groove 11ar may be substantially equal to the width w2 of the semiconductor chip 11. The width w1 of the adhesive 13 or the groove 11ar may be less than the width w2 of the semiconductor chip 11.

[0052] Figure 2A , 2B 1 is a diagram showing one or more stages in a method of manufacturing a semiconductor chip package according to some embodiments of the present invention. Figure 2B The cross-sectional diagram is Figure 2A At least some of these drawings have been simplified to facilitate a better understanding of the aspects of the present disclosure.

[0053] Reference Figure 2AThe manufacturing method includes obtaining a lead frame 10, and fixing the lead frame 10 on a carrier 20 using a clamp 21. The lead frame 10 is clamped between the clamp 21 and the carrier 20. The clamp 21 and the carrier 20 are disposed on opposite sides of the lead frame 10. The clamp 21 and the lead frame 10 may define a plurality of through holes 21h together. The fastening bolts 21p may pass through the through holes 21h to fix the clamp 21 and the lead frame 10 on the carrier 20.

[0054] The fixture 21 may have two openings for exposing the device area of ​​the lead frame 10. The position, shape, area ratio, number, etc. of the openings may be adjusted to be applied to different packages, not limited to Figure 2A Depicted style.

[0055] The lead frame 10 may include a device region exposed from the jig 21 and an edge region where the through hole 21h is provided. The edge region surrounds the device region. The device region may include a plurality of units, one of which may be separated from another unit by singulation. Figure 1A , Figure 1B ,and Figure 1C The semiconductor chip package 1a may include one unit. Figure 3A-1 The lead frame region 3a may include two units.

[0056] Reference Figure 2B , the carrier 20 may include a portion (or referred to as the first portion) 20c with relatively high thermal conductivity and a portion (or referred to as the first portion) 20m with relatively low thermal conductivity. The portion 20c may include a ceramic material, such as the materials listed above for the portion 11ac. The portion 20m may include a metal material, such as the materials listed above for the portion 11gm, the portion 11sm, and the portion 11dm. The portion 20c may be arranged in the portion 20m at intervals. In some embodiments, the position of the portion 20c may correspond to a chip pad in the lead frame 10 for carrying a semiconductor chip.

[0057] Figure 3A-1 , 3A-2 , 3B, 3C, 3D-1, 3D-2, 3E-1, 3E-2, 3F, 3G, 3H show one or more stages in a method of manufacturing a semiconductor chip package according to certain embodiments of the present invention. At least some of these figures have been simplified to facilitate a better understanding of the present disclosure. For the sake of simplicity, the following figures present the process on the lead frame area 3a of the lead frame 10, which may include two units. The processes for other areas of the lead frame 10 are also similar.

[0058] Reference Figure 3A-1 and Figure 3A-2 , in some embodiments, Figure 3A-2 The cross-sectional diagram is Figure 3A-1The lead frame region 3a of the lead frame 10 is a cross-sectional view along the cut line CC'. The manufacturing method includes obtaining the lead frame 10. The lead frame 10 may include interconnected chip pads 11a and 12a, gate lead contacts 11g and 12g, source lead contacts 11s and 12s, and drain lead contacts 11d and 12d before being singulated. The chip pad 12a may be configured to carry another semiconductor chip (e.g., Figure 3D-1 The gate lead contact 12g, the source lead contact 12s, and the drain lead contact 12d may each be configured to couple (or electrically connect) an electrical terminal of the aforementioned other semiconductor chip. The gate lead contact 12g, the source lead contact 12s, and the drain lead contact 12d may each be configured to couple (or electrically connect) an electrical terminal of the aforementioned other semiconductor chip to an external terminal (e.g., Figure 3G The portions 12gm and 12sm of the carrier 20 are as follows. Figure 3A-2 As shown, the die pad 11a of the lead frame 10 may have a recess 11ar recessed from the surface 101. The gate lead contact 12g and the source lead contact 12s of the lead frame 10 may have recesses 12gr and 12sr recessed from the surface 102.

[0059] Reference Figure 3B The manufacturing method includes placing a carrier 20 on a surface 102 of a lead frame 10. A portion 20c of the carrier 20 may be located corresponding to a chip pad 11a of the lead frame 10. In some embodiments, the manufacturing method may include placing a fastening bolt (e.g., Figure 2A The fastening bolt 21p) is inserted into the through hole (for example, Figure 2A In some embodiments, the manufacturing method may include using a jig (e.g., Figure 2A The lead frame 10 is fixed on the carrier 20 by a clamp 21 .

[0060] Reference Figure 3C The manufacturing method includes filling the groove 11ar with an adhesive 13. In some embodiments, the adhesive 13 can be formed by screen printing or dispensing. The adhesive 13 can have a surface 131 that is substantially coplanar with the surface 101 of the lead frame 10.

[0061] Reference Figure 3D-1 and Figure 3D-2 , in some embodiments, Figure 3D-2 The cross-sectional diagram is Figure 3D-1The manufacturing method includes disposing a semiconductor chip 11 on the surface 101 of the lead frame 10 and the adhesive 13. In some embodiments, the manufacturing method may further include disposing a semiconductor chip 12. The gate G and the source S of the semiconductor chip 12 may be located on the same side of the semiconductor chip 12 and the drain D may be located on the other opposite side. The detailed description of the semiconductor chip 12 may refer to the semiconductor chip 11 and will not be repeated here. Figure 3D-2 As shown, the adhesive 13 may be completely covered by the semiconductor chip 11. The width w1 of the adhesive 13 or the groove 11ar may not be greater than the width w2 of the semiconductor chip 11. The width w1 of the adhesive 13 or the groove 11ar may be substantially equal to the width w2 of the semiconductor chip 11. The width w1 of the adhesive 13 or the groove 11ar may be less than the width w2 of the semiconductor chip 11.

[0062] Reference Figure 3E-1 and Figure 3E-2 , in some embodiments, Figure 3E-2 The cross-sectional diagram is Figure 3E-1 The manufacturing method includes forming a wire to couple (or electrically connect) an electrical terminal of the semiconductor chip 11. For example, the gate G of the semiconductor chip 11 is coupled (or electrically connected) to the gate lead contact 11g of the lead frame 10 through a wire 11gw. The source S of the semiconductor chip 11 is coupled (or electrically connected) to the source lead contact 11s of the lead frame 10 through a wire 11sw. The drain D of the semiconductor chip 11 is coupled (or electrically connected) to the drain lead contact 11d of the lead frame 10 through an adhesive 13, a chip pad 11a and a wire 11dw.

[0063] In some embodiments, the manufacturing method may further include forming a wire coupling (or electrically connecting) an electrical terminal of the semiconductor chip 12. For example, the gate G of the semiconductor chip 12 is coupled (or electrically connected) to the gate lead contact 12g of the lead frame 10 through the wire 12gw. The source S of the semiconductor chip 12 is coupled (or electrically connected) to the source lead contact 12s of the lead frame 10 through the wire 12sw. The drain D of the semiconductor chip 12 is coupled (or electrically connected) to the drain lead contact 12d of the lead frame 10 through the adhesive, the chip pad 12a and the wire 12dw.

[0064] Reference Figure 3F The manufacturing method includes covering the lead frame 10, the semiconductor chip 11, and other semiconductor chips (such as Figure 3E-1 The encapsulant 14 may be filled in the groove recessed from the surface 102, for example Figure 3A-2 The groove 12gr and the groove 12sr, and for example Figure 1AIn some embodiments, the encapsulant 14 may be formed by molding, such as printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable processes.

[0065] Reference Figure 3G The manufacturing method includes removing a portion of the carrier 20 to form a groove 20r. In some embodiments, the manufacturing method includes removing a portion of the carrier 20 having a relatively low thermal conductivity (or a metal portion, such as Figure 3B The portion with relatively high thermal conductivity (or ceramic portion, for example Figure 3B The portion 20c) does not contact the portion with relatively low thermal conductivity. Figure 3G As shown, the portion with relatively high thermal conductivity (or ceramic portion, such as Figure 3B The portion 20c) of the carrier 20 is separated from other portions of the carrier 20 to form a portion 11ac. In some embodiments, the width of the portion 11ac may be substantially the same as the width of the chip pad 11a.

[0066] Parts with relatively low thermal conductivity (or metal parts, such as Figure 3B The portion 20m) is separated from each other to form a portion 11dm, a portion 12gm and a portion 12sm. The portion 11dm and the portion 11ac are Figure 1A The portion 12gm and the portion 12sm are another semiconductor chip (such as Figure 3E-1 A portion of a semiconductor chip 12) package.

[0067] In some embodiments, the groove 20r may be formed by a laser drilling process. In some embodiments, the groove 20r may expose a portion of the encapsulant 14. In some embodiments, the groove 20r may have a substantially constant width. In some embodiments, the groove 20r may have different slopes, may widen toward the encapsulant 14, or may narrow toward the encapsulant 14.

[0068] Reference Figure 3HThe manufacturing method includes filling the groove 20r with an insulating layer 30. The insulating layer 30 can be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD) or other deposition processes. In some embodiments, a grinding process, such as a chemical mechanical polishing (CMP) process, can be performed to grind and remove the insulating layer 30 outside the groove 20r.

[0069] In some embodiments, the manufacturing method includes performing singulation to separate individual structures. The singulation can be performed, for example, using a dicing saw, a laser, or other suitable cutting techniques. The semiconductor structure formed by the above steps can be Figure 1A The semiconductor chip packages 1a shown are identical.

[0070] Figure 4A FIG. 4 is a perspective view of a portion of a semiconductor chip package 4a according to some embodiments of the present invention. Figure 1A The semiconductor chip package 1a is similar to the semiconductor chip package 1a shown, except that the gate G, source S and drain D of the semiconductor chip 11 of the semiconductor chip package 4a are located on the same side, such as the surface 111. The drain D can be coupled (or electrically connected) to the drain lead contact 11d of the lead frame 10 through a wire 11dw.

[0071] Figure 4B Shown are one or more stages in a method of manufacturing a semiconductor chip package according to some embodiments of the present disclosure. Figure 4B and Figure 3E-1 Similar, but different Figure 4B The gate G, source S and drain D of the semiconductor chip 12 are located on the same side. The drain D can be coupled (or electrically connected) to the drain lead contact 11d of the lead frame 10 through a copper strip 12dp. The source S can be coupled (or electrically connected) to the source lead contact 12s of the lead frame 10 through a copper strip 12sp.

[0072] Spatially relative terms such as "under," "below," "lower," "above," "upper," "left," "right," and the like may be used herein for ease of description to describe the relationship of one component or feature to another or more components or features as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device when in use or operating in addition to the orientation depicted in the accompanying drawings. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that when a component is referred to as being "connected to" or "coupled to" another component, it may be directly connected to or coupled to the other component, or there may be intermediate components.

[0073] As used herein, the terms "approximately", "substantially", "substantially" and "about" are used to describe and explain small changes. When used in conjunction with an event or situation, the term can refer to an instance where the event or situation occurs precisely and an instance where the event or situation is close to occurring. As used herein with respect to a given value or range, the term "approximately" generally means within ±10%, ±5%, ±1% or ±0.5% of a given value or range. The range can be expressed as one endpoint to another endpoint or between two endpoints herein. All ranges disclosed herein include endpoints unless otherwise specified. The term "substantially coplanar" can refer to a position difference of two surfaces positioned along the same plane within a few microns (μm), such as a position difference positioned along the same plane within 10 μm, within 5 μm, within 1 μm or within 0.5 μm. When a numerical value or characteristic is referred to as being "substantially" the same, the term can refer to a value within ±10%, ±5%, ±1% or ±0.5% of the average value of the value.

[0074] The foregoing summarizes the features of several embodiments and detailed aspects of the present disclosure. The embodiments described in the present disclosure can be easily used as a basis for designing or modifying other processes and structures to facilitate the implementation of the same or similar purposes and / or to achieve the same or similar advantages of the embodiments introduced herein. Such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor chip package, characterized in that: include: A lead frame having a first side and a second side opposite to each other, and the lead frame having a first groove recessed from the first side of the lead frame; An adhesive filled in the first groove; and a semiconductor chip disposed on the first side of the lead frame and on the adhesive; The width of the first groove is not greater than the width of the semiconductor chip. 2 . The semiconductor chip package of claim 1 , wherein the adhesive has a surface that is substantially coplanar with a surface of the first side of the lead frame. 3 . The semiconductor chip package according to claim 1 , wherein the adhesive is completely covered by the semiconductor chip. 4 . The semiconductor chip package according to claim 1 , wherein the lead frame has a second groove recessed from the second side of the lead frame, and the semiconductor chip package further comprises an encapsulant filled in the second groove. 5 . The semiconductor chip package according to claim 1 , wherein the lead frame has a chip pad for carrying the semiconductor chip and a drain lead contact physically separated from the chip pad.

6. A semiconductor chip package according to claim 5, wherein the semiconductor chip has a gate, a source and a drain, wherein the drain is located on one side of the semiconductor chip, the gate and the source are located on the other side of the semiconductor chip, and wherein the drain is coupled to the drain lead contact through the adhesive, the chip pad, and the wire.

7. The semiconductor chip package according to claim 1, further comprising: A carrier is disposed on the second side of the lead frame. 8 . The semiconductor chip package according to claim 7 , wherein the carrier has a first portion and a second portion, wherein a thermal conductivity of the first portion is greater than a thermal conductivity of the second portion. 9 . The semiconductor chip package of claim 8 , wherein the first portion comprises a ceramic portion and the second portion comprises a metal portion. 10 . The semiconductor chip package of claim 8 , wherein the first portion of the carrier overlaps with the semiconductor chip, and the second portion of the carrier does not overlap with the semiconductor chip. 11 . The semiconductor chip package of claim 8 , wherein the second portion of the carrier comprises first, second, and third external terminals of the semiconductor chip package.

12. A semiconductor chip package, characterized in that: include: a lead frame having a first side and a second side opposite to each other, and the lead frame having a first groove recessed from the first side of the lead frame; An adhesive filled in the first groove; a semiconductor chip disposed on the first side of the lead frame and on the adhesive; and A carrier is disposed on the second side of the lead frame. 13 . The semiconductor chip package according to claim 12 , wherein the carrier has a first portion and a second portion, wherein a thermal conductivity of the first portion is greater than a thermal conductivity of the second portion. 14 . The semiconductor chip package of claim 13 , wherein the first portion comprises a ceramic portion and the second portion comprises a metal portion. 15 . The semiconductor chip package of claim 13 , wherein the first portion of the carrier overlaps with the semiconductor chip, and the second portion of the carrier does not overlap with the semiconductor chip. 16 . The semiconductor chip package of claim 13 , wherein the second portion of the carrier comprises first, second, and third external terminals of the semiconductor chip package.

17. A method for manufacturing a semiconductor chip package, characterized in that: include: obtaining a lead frame having a first side and a second side opposite to each other, and the lead frame having a first groove recessed from the first side of the lead frame; Filling the first groove with adhesive; A semiconductor chip is disposed on the first side of the lead frame and the adhesive, wherein a width of the first groove is not greater than a width of the semiconductor chip.

18. The manufacturing method according to claim 17, further comprising: A carrier is disposed on the second side of the lead frame.

19. The manufacturing method according to claim 18, wherein the step of arranging the carrier on the second side of the lead frame comprises: The lead frame is fixed on the carrier by using a clamp. 20 . The manufacturing method according to claim 18 , wherein the carrier comprises a first portion and a second portion, wherein a thermal conductivity coefficient of the first portion is greater than a thermal conductivity coefficient of the second portion.

21. The manufacturing method according to claim 20, further comprising: After positioning the carrier on the second side of the lead frame, a portion of the second portion of the carrier is removed so that the second portion does not contact the first portion.

22. The manufacturing method according to claim 21, wherein the step of removing a portion of the second portion of the carrier comprises: The second portion is formed into a first external terminal, a second external terminal, and a third external terminal that are separated from each other.

23. The manufacturing method according to claim 22, further comprising: An insulating layer is filled between the first external terminal, the second external terminal, and the third external terminal.

24. The manufacturing method according to claim 17, further comprising: The drain of the semiconductor chip is coupled to the drain lead contact of the lead frame through a wire.

25. The manufacturing method according to claim 17, further comprising: The lead frame and the semiconductor chip are covered with an encapsulant, wherein the encapsulant fills a second groove recessed from the second side of the lead frame.

Images