RBCOT architecture buck converter, chip and electronic equipment
By introducing inclined wave signals to generate circuit and sampling maintenance circuits in the RBCOT architecture antihypertensive converter, the deviation voltage of the oblique signal during the pitch mode is eliminated, and the RBCOT architecture antihypertensive converter is solved. The poor problem realizes a faster output voltage response and a more stable output voltage.
Patent Information
- Application Number
- CN202411635870.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-15
- Publication Date
- 2025-01-28
Smart Images
Figure CN119382509A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of power management chips, and in particular to a RBCOT architecture buck converter, chip and electronic device. Background Art
[0002] Ripple based constant on time buck converter (RBCOT BUCK) is widely used because it can achieve simple and good transient characteristics, as well as high light load efficiency. In the related art, the RBCOT architecture buck converter generates information about the on-stage or off-stage according to the changes in input voltage and output voltage. In this way, based on the information of the on-stage or off-stage, the capacitor in the RBCOT architecture buck converter can generate a ramp signal V by charging and discharging. C_RAMP At the same time, compared with the continuous conduction mode (CCM), in the discontinuous conduction mode (DCM), the ramp signal V C_RAMP Lower, while the ramp signal V C_RAMP The rising slope can be smaller. Thus, the stability of the RBCOT architecture buck converter in DCM can be guaranteed. In DCM, the load of the RBCOT architecture buck converter is light load. In CCM, the load of the RBCOT architecture buck converter is heavy load.
[0003] However, in the RBCOT buck converter of the related art, the ramp signal VC_RAMP will continue to increase until it reaches the power supply voltage in DCM. Therefore, in the instantaneous transition from light load to heavy load, that is, in the instantaneous transition from DCM to CCM, the ramp signal V C_RAMP There will be a large deviation. Therefore, eliminating the deviation through the integrator in the RBCOT architecture buck converter will greatly increase the stabilization time of the output voltage, resulting in poor transient response characteristics of the RBCOT architecture buck converter. Summary of the invention
[0004] The present application provides a RBCOT architecture buck converter, chip and electronic device, which can avoid eliminating the deviation of the ramp signal through an integrator and improve the transient response characteristics of the RBCOT architecture buck converter.
[0005] In a first aspect, the present application provides a RBCOT architecture buck converter, the RBCOT architecture buck converter comprising: a buck conversion circuit and a ramp signal generating circuit electrically connected to the buck conversion circuit;
[0006] The step-down conversion circuit comprises: a pulse width modulation comparator and an integrator; the positive phase input terminal of the pulse width modulation comparator is electrically connected to the first output terminal of the ramp signal generating circuit and the output terminal of the integrator respectively, and the negative phase input terminal of the pulse width modulation comparator is electrically connected to the second output terminal of the ramp signal generating circuit;
[0007] The ramp signal generating circuit is used to transmit a ramp signal to the pulse width modulation comparator, and the ramp signal is used to stabilize the output voltage of the RBCOT architecture buck converter;
[0008] The ramp signal generating circuit is further used for sampling and holding the maximum voltage value of the ramp signal to obtain a first voltage signal, and transmitting the first voltage signal to the pulse width modulation comparator, wherein the first voltage signal includes: a second voltage signal and a third voltage signal;
[0009] The pulse width modulation comparator is used to eliminate the deviation voltage generated by the ramp signal when the RBCOT architecture buck converter instantly jumps from the discontinuous conduction mode to the continuous conduction mode by using the first voltage signal;
[0010] Among them, the deviation voltage is the voltage difference between the second voltage signal and the third voltage signal, the second voltage signal is the maximum voltage value corresponding to the ramp signal in the discontinuous conduction mode, and the third voltage signal is the maximum voltage value corresponding to the ramp signal in the continuous conduction mode.
[0011] Through the RBCOT architecture buck converter provided in the first aspect, the ramp signal generating circuit can transmit a ramp signal of the output voltage of the RBCOT architecture buck converter to the pulse width modulation comparator to stabilize the ramp signal, so that the pulse width modulation comparator can obtain the ramp signal. The ramp signal generating circuit can sample and hold the maximum voltage value of the ramp signal to obtain a first voltage signal, and transmit the first voltage signal to the pulse width modulation comparator, so that the pulse width modulation comparator can obtain the first voltage signal. Because when the RBCOT architecture buck converter instantly jumps from the discontinuous conduction mode to the continuous conduction mode, the ramp signal will generate a voltage difference between the second voltage signal and the third voltage signal, that is, the deviation voltage. At the same time, the first voltage signal will also change from the second voltage signal to the third voltage signal. In this way, the pulse width modulation comparator can use the first voltage signal to eliminate the deviation voltage generated by the ramp signal. Furthermore, the RBCOT architecture buck converter 1000 does not need to eliminate the deviation voltage through an integrator, which greatly reduces the stabilization time of the output voltage. Thereby, the transient response characteristics can be improved, and the output voltage will not have a deviation voltage, so that the output voltage tends to be stable.
[0012] In one possible design, the ramp signal generating circuit includes: a ramp signal generating circuit and a sample-and-hold circuit;
[0013] The output end of the ramp signal generating circuit is electrically connected to the positive phase input end of the pulse width modulation comparator and the input end of the sampling and holding circuit respectively, and the output end of the sampling and holding circuit is electrically connected to the negative phase input end of the pulse width modulation comparator;
[0014] The ramp signal generating circuit is used to generate the ramp signal and transmit the ramp signal to the sampling and holding circuit and the pulse width modulation comparator respectively;
[0015] The sample-and-hold circuit is used to sample and hold the maximum voltage value of the ramp signal to obtain a first voltage signal.
[0016] In a possible design, the ramp signal generating circuit includes: a current source, a first capacitor, a first switch tube and a clamping device;
[0017] The output end of the current source is electrically connected to the upper plate of the first capacitor, the drain end of the first switch tube, the first end of the clamp device and the input end of the sample and hold circuit are all electrically connected between the output end of the current source and the upper plate of the first capacitor, and the lower plate of the first capacitor, the source end of the first switch tube and the second end of the clamp device are all grounded;
[0018] The current source is used to output a first current so that the ramp signal generating circuit generates the ramp signal;
[0019] The clamping device is used to clamp the ramp signal in the discontinuous conduction mode to obtain the second voltage signal.
[0020] In a possible design, the clamping device includes: a second switch tube and a first resistor;
[0021] The first end of the first resistor is electrically connected between the output end of the current source and the upper plate of the first capacitor, the second end of the first resistor is electrically connected to the drain end of the second switch tube, and the source end of the second switch tube is grounded.
[0022] In a possible design, the sample-and-hold circuit includes: a third switch tube and a second capacitor;
[0023] The drain end of the third switch tube is electrically connected to the output end of the ramp signal generating circuit, the source end of the third switch tube is electrically connected to the upper plate of the second capacitor, and the lower plate of the second capacitor is grounded.
[0024] In one possible design, the sample-and-hold circuit further includes: a low-pass filter;
[0025] The first end of the low-pass filter is electrically connected to the source end of the third switch tube, and the second end of the low-pass filter is grounded;
[0026] The low-pass filter is used to determine the time required for the first voltage signal to jump from the second voltage signal to the third voltage signal, and the time constant of the low-pass filter is smaller than the time constant of the integrator.
[0027] In one possible design, the low-pass filter includes: a second resistor and a third capacitor;
[0028] A first end of the second resistor is electrically connected to the source end of the third switch tube, a second end of the second resistor is electrically connected to the upper plate of the third capacitor, and a lower plate of the third capacitor is grounded.
[0029] In one possible design, the ramp signal generating circuit further includes: a control circuit;
[0030] The output end of the control circuit is electrically connected to the gate end of the first switch tube, the gate end of the second switch tube and the gate end of the third switch tube respectively;
[0031] The control circuit is used to control the first switch tube to be turned on and the second switch tube to be turned off during the on phase of the RBCOT architecture buck converter, and to control the first switch tube and the second switch tube to be turned off during the off phase of the RBCOT architecture buck converter;
[0032] The control circuit is further used to control the second switch tube to be turned on in the discontinuous conduction mode, or to control the second switch tube to be always turned off in the continuous conduction mode;
[0033] The control circuit is further used to control the third switch tube to be turned on after the shutdown phase ends.
[0034] In a second aspect, the present application provides a chip, comprising: the RBCOT architecture buck converter in the above-mentioned first aspect and each possible design of the above-mentioned first aspect.
[0035] The beneficial effects of the chip provided in the above-mentioned second aspect and each possible design of the above-mentioned second aspect can be referred to the beneficial effects brought about by the above-mentioned first aspect and each possible implementation method of the first aspect, and will not be repeated here.
[0036] In a third aspect, the present application provides an electronic device, comprising: the chip in the above-mentioned second aspect.
[0037] The above description is only an overview of the technical solution of the embodiment of the present application. In order to more clearly understand the technical means of the embodiment of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiment of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present application, a brief introduction will be given below to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0039] Figure 1 It is a structural schematic diagram of a RBCOT architecture buck converter in the related art;
[0040] Figure 2 It is a structural schematic diagram of another RBCOT architecture buck converter in the related art;
[0041] Figure 3 It is a structural schematic diagram of another RBCOT architecture buck converter in the related art;
[0042] Figure 4 for Figure 3 Schematic diagram of the working waveform of the RBCOT architecture buck converter in DCM;
[0043] Figure 5 It is a structural schematic diagram of another RBCOT architecture buck converter in the related art;
[0044] Figure 6 A schematic diagram of the structure of a RBCOT architecture buck converter provided in one embodiment of the present application;
[0045] Figure 7 for Figure 6 Schematic diagram of transient response characteristics of the RBCOT architecture buck converter;
[0046] Figure 8 for Figure 6 Schematic diagram of the structure of the ramp signal generation circuit in the RBCOT architecture buck converter;
[0047] Fig. 9 for Figure 8 A schematic diagram of a waveform of a ramp signal VRAMP' generated by the ramp signal generating circuit;
[0048] Fig.10 for Figure 6The schematic diagram of the structure of the ramp signal generating circuit in the RBCOT architecture buck converter;
[0049] Fig.11 for Fig.10 A schematic diagram of the working timing of the third switch tube in the ramp signal generating circuit;
[0050] Fig.12 A schematic diagram of a steady-state waveform of a RBCOT architecture buck converter in CCM provided in one embodiment of the present application;
[0051] Fig.13 A schematic diagram of a steady-state waveform of an RBCOT architecture buck converter in DCM provided in one embodiment of the present application. DETAILED DESCRIPTION
[0052] In this application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c alone can represent: a, b, c, a and b, a and c, or a, b, and c, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.
[0053] The directions or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "up", "down", "left", "right", "front", and "back" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.
[0054] The terms "connected" and "connected" should be understood in a broad sense. For example, the "connected" or "connected" of a circuit structure can refer to not only physical connection, but also electrical connection or signal connection. For example, it can be directly connected, that is, physically connected, or indirectly connected through at least one intermediate element, as long as the circuit is connected, or it can be the internal connection of two elements; signal connection can refer to signal connection through a circuit or through a media medium, such as radio waves. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0055] Reference Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a structure of a RBCOT architecture buck converter in the related art. Figure 1 As shown in the figure, the RBCOT architecture buck converter includes: an inner loop and an outer loop. The inner loop directly transmits the output voltage Vo to the negative phase input terminal of the modulator PWM, so that the ripple signal of the output voltage can be used to generate the output signal of the modulator PWM. The outer loop integrates the deviation between the output voltage and the reference voltage Vref through the integrator Hv, and transmits it to the positive phase input terminal of the modulator PWM through the compensation network CCOMP. Since the time constant of the integrator Hv is large. Therefore, the speed of the outer loop will be slower than the inner loop.
[0056] When the equivalent series resistance ESR of the output capacitor Co is relatively large, Figure 1 The RBCOT buck converter in the figure can work stably. However, when the equivalent series resistance ESR of the output capacitor Co is relatively small, the information of the inductor current IL is submerged, resulting in the RBCOT buck converter being unable to work stably. Therefore, it is necessary to add a ramp signal VRAMP in the inner loop to ensure the stability of the RBCOT buck converter, as shown in the following figure. Figure 2 The RBCOT architecture buck converter shown in Figure 2 It is a structural schematic diagram of another RBCOT architecture buck converter in the related art.
[0057] Combine the following Figure 3 and Figure 5 This article introduces how to obtain the ramp signal VRAMP in the RBCOT architecture buck converter in related technologies. The content is as follows:
[0058] Reference Figure 3 , Figure 3 FIG. 1 is a schematic diagram of a structure of another RBCOT architecture buck converter in the related art. Figure 3 As shown, the ramp signal VRAMP is based on the node V LXThe internal virtual inductor current circuit (VIC) collects the node V LX The voltage change first passes through R LPF and C LPF Perform low-pass filtering and then pass it through R DC and C DC Subtract the DC component to get the ramp signal V that is consistent with the inductor current phase VIC In this way, the ramp signal V VIC Superimposed on the reference voltage V REF On, get the ramp signal V RAMP . Through the ramp signal V RAMP With the voltage signal V FB Comparison is made to achieve the purpose of stabilizing the output voltage.
[0059] Figure 3 The RBCOT buck converter in the figure can work stably in CCM. However, it has stability problems in DCM. Figure 4 The working waveform shown is Figure 4 for Figure 3 The operating waveform diagram of the RBCOT architecture buck converter in DCM. This is because in DCM, both switch tubes S1 and S2 are turned off, and node V LX Floating, it will resonate with the circuit parasitics. As a result, the inductor current information is lost, causing the circuit control to enter an unstable state.
[0060] Based on this, Figure 3 Based on this, the RBCOT architecture buck converter is improved and the following is obtained: Figure 5 The RBCOT architecture buck converter shown in Figure 5 FIG. 1 is a schematic diagram of a structure of another RBCOT architecture buck converter in the related art. Figure 5 As shown, the RBCOT architecture buck converter is based on the input voltage V IN and output voltage V OUT changes, generating information of the on-phase Ton or off-phase Toff, so that the time generating circuit Ton generates a signal V DRV . Thus, when the signal V DRV Under the action of the RBCOT architecture buck converter, the capacitor C RP The charging and discharging of the ramp signal V C_RAMP .
[0061] At the same time, in DCM, since the voltage VFB is higher than the voltage VREF, the voltage Vc is lower. Therefore, the pull-up current provided by Gm1 is smaller. Furthermore, compared with CCM, the ramp signal V C_RAMPLower, while the ramp signal V C_RAMP The rising slope can be smaller. Thus, the stability of the RBCOT architecture buck converter in DCM can be guaranteed.
[0062] However, Figure 5 When the RBCOT buck converter is in deep DCM, that is, when the on-time Ton is fixed and the off-time Toff is long, the ramp signal V C_RAMP It will continue to rise to the power supply voltage of Gm1. In CCM, the voltage Vc is equal to the reference voltage V REF The deviation is VRAMP_CCM+Vout_ripple / 2. In DCM, the voltage Vc is different from the reference voltage V REF The deviation is VRAMP_MAX+Vout_ripple / 2.
[0063] Where VRAMP_CCM is the ramp signal V in CCM. C_RAMP The maximum voltage value, Vout_ripple is the output voltage V OUT Ripple voltage. VRAMP_MAX is the ramp signal V in DCM C_RAMP The maximum voltage value.
[0064] Therefore, when the load changes from light to heavy, the compensation network C COMP The voltage Vc cannot change immediately. C_RAMP A large deviation of VRAMP_MAX-VRAMP_CCM will be introduced. Therefore, eliminating this deviation through an integrator will greatly increase the stabilization time of the output voltage, resulting in poor transient response characteristics of the RBCOT architecture buck converter.
[0065] In addition, the ramp signal V C_RAMP is based on the additional input voltage V IN , output voltage V OUT and reference voltage V REF As a result, the design cost of the RBCOT architecture buck converter is greatly increased, resulting in a high design cost.
[0066] In order to solve the above problems, the present application provides a RBCOT architecture buck converter, chip and electronic device.
[0067] Among them, the RBCOT architecture buck converter can be a chip or a circuit module.
[0068] In this application, electronic devices may include, but are not limited to: power management systems, electric vehicle chargers, renewable energy systems, and battery-powered devices.
[0069] Reference Figure 6 , Figure 6 This is a schematic diagram of a structure of a RBCOT architecture buck converter provided in one embodiment of the present application. Figure 6 As shown, the RBCOT architecture buck converter 1000 may include: a buck conversion circuit 200 and a ramp signal generating circuit 100 electrically connected to the buck conversion circuit 200 .
[0070] The buck conversion circuit 200 may include a pulse width modulation comparator 210 and an integrator 220 .
[0071] The positive input terminal of the PWM comparator 210 is electrically connected to the first output terminal of the ramp signal generating circuit 100 and the output terminal of the integrator 220 respectively, and the negative input terminal of the PWM comparator 210 is electrically connected to the second output terminal of the ramp signal generating circuit 100 .
[0072] The step-down conversion circuit 200 and the ramp signal generating circuit 100 may be separately or integrated, and this is not specifically limited in the embodiment of the present application.
[0073] The ramp signal generating circuit 100 can transmit the ramp signal VRAMP′ to the pulse width modulation comparator 210 , so that the pulse width modulation comparator 210 can obtain the ramp signal VRAMP′.
[0074] The ramp signal VRAMP′ is used to stabilize the output voltage of the RBCOT architecture buck converter 1000 .
[0075] The ramp signal generating circuit 100 can sample and hold the maximum voltage value of the ramp signal VRAMP' to obtain the first voltage signal VHOLD. In addition, the ramp signal generating circuit 100 can transmit the first voltage signal VHOLD to the pulse width modulation comparator 210 so that the pulse width modulation comparator 210 can obtain the first voltage signal VHOLD.
[0076] The first voltage signal VHOLD may include: a second voltage signal and a third voltage signal. The second voltage signal is the maximum voltage value of the ramp signal VRAMP' in the discontinuous conduction mode DCM, and the third voltage signal is the maximum voltage value of the ramp signal VRAMP' in the continuous conduction mode CCM.
[0077] When the RBCOT architecture buck converter 1000 changes from the discontinuous conduction mode DCM to the continuous conduction mode CCM instantaneously, the ramp signal VRAMP' will immediately change from the second voltage signal to the third voltage signal. In this way, the ramp signal VRAMP' will generate a deviation voltage.
[0078] Since the ramp signal generating circuit 100 can sample and hold the maximum voltage value of the ramp signal VRAMP'. Therefore, the first voltage signal VHOLD will also change from the second voltage signal to the third voltage signal. In this way, the pulse width modulation comparator 210 can use the first voltage signal VHOLD to eliminate the deviation voltage generated by the ramp signal VRAMP'. Furthermore, the RBCOT architecture buck converter 1000 does not need to eliminate the deviation voltage through the integrator 220, which greatly reduces the stabilization time of the output voltage. Thereby, the transient response characteristics can be improved, and the output voltage Vo' will not have a deviation voltage, so that the output voltage Vo' tends to be stable.
[0079] The deviation voltage is a voltage difference between the second voltage signal and the third voltage signal.
[0080] Reference Figure 7 , Figure 7 Shows Figure 6 Schematic diagram of transient response characteristics of RBCOT buck converter. Figure 7 As shown by the dotted line in , when the RBCOT architecture buck converter 1000 instantly changes from the discontinuous conduction mode DCM to the continuous conduction mode CCM, the output voltage Vo' responds at a faster speed, shortening the stabilization time of the output voltage Vo' and improving the transient response characteristics. Figure 7 As shown by the solid line in the middle, the RBCOT architecture buck converter in the related art responds at a very slow speed, which greatly prolongs the stabilization time of the output voltage and has poor transient response characteristics.
[0081] The RBCOT architecture buck converter provided by the present application, the ramp signal generating circuit can transmit the ramp signal of the output voltage of the RBCOT architecture buck converter to the pulse width modulation comparator to stabilize the output voltage of the RBCOT architecture buck converter, so that the pulse width modulation comparator can obtain the ramp signal. The ramp signal generating circuit can sample and hold the maximum voltage value of the ramp signal to obtain the first voltage signal, and transmit the first voltage signal to the pulse width modulation comparator, so that the pulse width modulation comparator can obtain the first voltage signal. Because when the RBCOT architecture buck converter instantly jumps from the discontinuous conduction mode to the continuous conduction mode, the ramp signal will generate the voltage difference between the second voltage signal and the third voltage signal, that is, the deviation voltage. At the same time, the first voltage signal will also change from the second voltage signal to the third voltage signal. In this way, the pulse width modulation comparator can use the first voltage signal to eliminate the deviation voltage generated by the ramp signal. Furthermore, the RBCOT architecture buck converter does not need to eliminate the deviation voltage through an integrator, which greatly reduces the stabilization time of the output voltage. Thus, the transient response characteristics can be improved, and the output voltage will not have a deviation voltage, so that the output voltage tends to be stable.
[0082] Based on the description of the above embodiment, a possible implementation of the ramp signal generating circuit 100 is exemplified. Figure 6 As shown, the ramp signal generating circuit 100 may include: a ramp signal generating circuit 110 and a sample-and-hold circuit 120 .
[0083] The output terminal of the ramp signal generating circuit 110 is electrically connected to the positive phase input terminal of the PWM comparator 210 and the input terminal of the sampling and holding circuit 120 , respectively. The output terminal of the sampling and holding circuit 120 is electrically connected to the negative phase input terminal of the PWM comparator 210 .
[0084] The output end of the ramp signal generating circuit 110 is the first output end of the ramp signal generating circuit 100 , and the output end of the sampling and holding circuit 120 is the second output end of the ramp signal generating circuit 100 .
[0085] The ramp signal generating circuit 110 can generate a ramp signal VRAMP' and transmit the ramp signal VRAMP' to the sampling and holding circuit 120 so that the sampling and holding circuit 120 can obtain the ramp signal VRAMP' and the pulse width modulation comparator 210 can obtain the ramp signal VRAMP'.
[0086] In this way, the sample-and-hold circuit 120 can sample and hold the maximum voltage value of the ramp signal VRAMP' to obtain the first voltage signal VHOLD. Thus, the ramp signal generating circuit 100 can obtain the first voltage signal VHOLD.
[0087] Based on the description of the above embodiment, a possible implementation of the ramp signal generating circuit 110 is exemplified. Figure 8 , Figure 8 Shows Figure 6 Schematic diagram of the structure of the ramp signal generation circuit in the RBCOT architecture buck converter. Figure 8 As shown, the ramp signal generating circuit 110 may include: a current source, a first capacitor C1 ′, a first switch tube S1 ′ and a clamping device 111 .
[0088] The output end of the current source is electrically connected to the upper plate of the first capacitor C1', the drain end of the first switch tube S1', the first end of the clamp device 111 and the input end of the sample and hold circuit 120 are all electrically connected between the output end of the current source and the upper plate of the first capacitor C1', and the lower plate of the first capacitor C1', the source end of the first switch tube S1' and the second end of the clamp device 111 are all grounded.
[0089] The output end of the ramp signal generating circuit 110 is located between the output end of the current source and the upper plate of the first capacitor C1 ′.
[0090] In some examples, the ramp signal generating circuit 100 may further include: a control circuit.
[0091] The output end of the control circuit is electrically connected to the gate end of the first switch tube S1 ′, the gate end of the second switch tube S2 ′, and the gate end of the third switch tube S3 ′ respectively.
[0092] In the on-phase Ton′ of the RBCOT architecture buck converter 1000 , the control circuit may control the first switch tube S1 ′ to be on and the second switch tube S2 ′ to be off.
[0093] In the off phase Toff′ of the RBCOT architecture buck converter 1000 , the control circuit may control both the first switch tube S1 ′ and the second switch tube S2 ′ to be turned off.
[0094] Since the total duration of the off phase Toff' and the delay duration Tdly is greater than the switching period of the continuous conduction mode CCM, the second switch tube S2' is always in the off state in the continuous conduction mode CCM. In the discontinuous conduction mode DCM, the control circuit can control the second switch tube S2' to conduct.
[0095] After the off phase Toff' ends, the control circuit can control the third switch tube S3' to turn on.
[0096] The current source can output the first current I1 to enable the ramp signal generating circuit 110 to generate the ramp signal VRAMP′.
[0097] In the case of continuous conduction mode CCM, in the on-phase Ton', the first switch S1' is on and the second switch S2' is off. In this way, the voltage value of the ramp signal VRAMP' is 0. In the off-phase Toff', the first switch S1' and the second switch S2' are both off. In this way, the first current I1 can charge the first capacitor C1', so that the first capacitor C1' is in a charging state, so that the voltage value of the ramp signal VRAMP' gradually increases from 0. Thus, the ramp signal generating circuit 110 can generate the following Fig. 9 The waveform of the ramp signal VRAMP' is shown.
[0098] In the case of discontinuous conduction mode DCM, in the conduction phase Ton', the first switch tube S1' is turned on and the second switch tube S2' is turned off. In this way, the voltage value of the ramp signal VRAMP' is 0. In the off phase Toff', the first switch tube S1' and the second switch tube S2' are both turned off. In this way, the first current I1 can charge the first capacitor C1', so that the first capacitor C1' is in a charging state, so that the voltage value of the ramp signal VRAMP' gradually increases from 0. After the delay time Tdly, the clamping device 111 can clamp the ramp signal VRAMP' to obtain a second voltage signal. Thus, the ramp signal generating circuit 110 can generate the following Fig. 9 The waveform of the ramp signal VRAMP' is shown.
[0099] In the off phase Toff', the rising slope of the ramp signal VRAMP' is I1 / C1.
[0100] Based on the description of the above embodiment, a possible implementation of the clamping device 111 is exemplified. Figure 8 As shown, the clamping device 111 may include: a second switch tube S2 ′ and a first resistor R1 ′.
[0101] The first end of the first resistor R1' is electrically connected between the output end of the current source and the upper plate of the first capacitor C1', the second end of the first resistor R1' is electrically connected to the drain end of the second switch tube S2', and the source end of the second switch tube S2' is grounded.
[0102] The first end of the first resistor R1 ′ is the first end of the clamp device 111 , and the source end of the second switch tube S2 ′ is the second end of the clamp device 111 .
[0103] In the discontinuous conduction mode DCM, the second switch tube S2 ′ is turned on, so that the ramp signal VRAMP′ is clamped to the second voltage signal.
[0104] The second voltage signal is specifically the product of the first current I1 and the resistance value r1 of the first resistor, ie, I1*r1.
[0105] Based on the description of the above embodiment, a possible implementation of the sample and hold circuit 120 is exemplified. Fig.10 , Fig.10 for Figure 6 Schematic diagram of the ramp signal generating circuit in the RBCOT architecture buck converter. Fig.10 As shown, the sample-and-hold circuit 120 may include: a third switch tube S3 ′ and a second capacitor C2 ′.
[0106] The drain end of the third switch tube S3 ′ is electrically connected to the output end of the ramp signal generating circuit 110 , the source end of the third switch tube S3 ′ is electrically connected to the upper plate of the second capacitor C2 ′, and the lower plate of the second capacitor C2 ′ is grounded.
[0107] The drain end of the third switch tube S3 ′ is the input end of the sample-and-hold circuit 120 , and the upper plate of the second capacitor C2 ′ is the output end of the sample-and-hold circuit 120 .
[0108] The first switch tube S1 ′, the second switch tube S2 ′ and the third switch tube S3 ′ may include but are not limited to metal-oxide semiconductor field effect transistors and gallium nitride transistors.
[0109] Reference Fig.11 , Fig.11 Shows Fig.10 The working sequence diagram of the third switch tube in the ramp signal generating circuit is shown in FIG. Fig.11 As shown, after the off phase Toff' ends, the third switch tube S3' is turned on, so that the maximum voltage value of the ramp signal VRAMP' is sampled onto the second capacitor C2' to obtain the first voltage signal VHOLD.
[0110] Based on the description of the above embodiment, another possible implementation of the sample and hold circuit 120 is exemplified. Fig.10 As shown, the sample-and-hold circuit 120 may further include: a low-pass filter 112 - 1 .
[0111] A first end of the low-pass filter 112 - 1 is electrically connected to the source end of the third switch tube S3 ′, and a second end of the low-pass filter 112 - 1 is grounded.
[0112] The low-pass filter 112 - 1 can determine the time required for the first voltage signal VHOLD to jump from the second voltage signal to the third voltage signal, so as to ensure the stability of the RBCOT architecture buck converter 1000 .
[0113] The time constant of the low-pass filter 112 - 1 is smaller than the time constant of the integrator 220 .
[0114] Based on the description of the above embodiment, a possible implementation of the low-pass filter 112-1 is exemplified. Fig.10 As shown, the low pass filter 112 - 1 may include: a second resistor R2 ′ and a third capacitor C3 ′.
[0115] A first end of the second resistor R2' is electrically connected to the source end of the third switch tube S3', a second end of the second resistor R2' is electrically connected to the upper plate of the third capacitor C3', and a lower plate of the third capacitor C3' is grounded.
[0116] The first end of the second resistor R2 ′ is the first end of the low-pass filter 112 - 1 , and the lower plate of the third capacitor C3 ′ is the second end of the low-pass filter 112 - 1 .
[0117] In some examples, the buck converter circuit 200 may further include: a constant on-time circuit 230 , a drive circuit 240 , an upper tube S3 ′, a lower tube S4 ′, an inductor L′, a resistor Rco′, a resistor RL′, and a capacitor Co′.
[0118] The drain end of the upper tube S3' is used to connect to the input voltage Vin' of the RBCOT architecture buck converter 1000, the source end of the upper tube S3' is electrically connected to the drain end of the lower tube S4', the first end of the inductor L' is electrically connected between the source end of the upper tube S3' and the drain end of the lower tube S4', the second end of the inductor L' is electrically connected to the first end of the resistor Rco', the first end of the resistor RL', the first input end of the integrator 220 and the negative phase input end of the pulse width modulation comparator 210, respectively, and the second input end of the integrator 220 is used to connect to The reference voltage Vref', the second end of the resistor Rco' is electrically connected to the upper plate of the capacitor Co', the output end of the pulse width modulation comparator 210 is electrically connected to the input end of the constant on-time circuit 230, the output end of the constant on-time circuit 230 is electrically connected to the input end of the drive circuit 240, the output end of the drive circuit 240 is electrically connected to the gate end of the upper tube S3' and the gate end of the lower tube S4', respectively, and the second end of the inductor L' is also used to output the output voltage Vo' of the RBCOT architecture buck converter 1000. The source end of the lower tube S4', the lower plate of the capacitor Co' and the second end of the resistor RL' are all grounded.
[0119] Combine the following Fig.12 and Fig.13 The steady-state waveforms of the RBCOT architecture buck converter under CCM and DCM are introduced in detail.
[0120] Reference Fig.12 , Fig.12 Schematic diagram of steady-state waveform of a RBCOT architecture buck converter in CCM provided by an embodiment of the present application. Fig.12 As shown, in the off phase Toff', the ramp signal VRAMP' starts to rise from 0 until the output voltage Vo' is lower than the voltage Vc', and the ramp signal VRAMP' instantly decreases from the maximum value to 0. Thus, the RBCOT architecture buck converter starts the next cycle.
[0121] Since the sample-and-hold circuit 120 can sample and hold the maximum voltage value of the ramp signal VRAMP', the first voltage signal VHOLD is the maximum voltage value of the ramp signal VRAMP'. Therefore, the difference between the reference voltage Vref' and the voltage Vc' is only half the ripple voltage of the output voltage Vo'.
[0122] The voltage difference between the reference voltage Vref′ and the average value of the output voltage Vo′ is eliminated by the integrator 220 .
[0123] The conduction phase Ton' is a constant time.
[0124] Reference Fig.13 , Fig.13 Schematic diagram of steady-state waveform of a RBCOT architecture buck converter in DCM provided by an embodiment of the present application. Fig.13 As shown, after the delay time Tdly, the ramp signal VRAMP' is slowly clamped to the second voltage signal I1*r1 and remains unchanged. At the same time, the sample and hold circuit 120 can sample and hold the maximum voltage value of the ramp signal VRAMP', that is, the first voltage signal VHOLD is I1*r1. Therefore, the reference voltage Vref' and the voltage Vc' are still half the ripple voltage of the output voltage Vo'.
[0125] The ripple voltage of the output voltage Vo' under DCM is slightly greater than the ripple voltage of the output voltage Vo' under CCM.
[0126] Finally, it should be noted that the above embodiments are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.
Claims
1. A RBCOT architecture buck converter, characterized in that: The RBCOT architecture buck converter comprises: a buck conversion circuit and a ramp signal generating circuit electrically connected to the buck conversion circuit; The step-down conversion circuit comprises: a pulse width modulation comparator and an integrator; the positive phase input terminal of the pulse width modulation comparator is electrically connected to the first output terminal of the ramp signal generating circuit and the output terminal of the integrator respectively, and the negative phase input terminal of the pulse width modulation comparator is electrically connected to the second output terminal of the ramp signal generating circuit; The ramp signal generating circuit is used to transmit a ramp signal to the pulse width modulation comparator, and the ramp signal is used to stabilize the output voltage of the RBCOT architecture buck converter; The ramp signal generating circuit is further used for sampling and holding the maximum voltage value of the ramp signal to obtain a first voltage signal, and transmitting the first voltage signal to the pulse width modulation comparator, wherein the first voltage signal includes: a second voltage signal and a third voltage signal; The pulse width modulation comparator is used to eliminate the deviation voltage generated by the ramp signal when the RBCOT architecture buck converter instantly jumps from the discontinuous conduction mode to the continuous conduction mode by using the first voltage signal; Among them, the deviation voltage is the voltage difference between the second voltage signal and the third voltage signal, the second voltage signal is the maximum voltage value corresponding to the ramp signal in the discontinuous conduction mode, and the third voltage signal is the maximum voltage value corresponding to the ramp signal in the continuous conduction mode.
2. The RBCOT architecture buck converter according to claim 1, characterized in that: The ramp signal generating circuit comprises: a ramp signal generating circuit and a sampling and holding circuit; The output end of the ramp signal generating circuit is electrically connected to the positive phase input end of the pulse width modulation comparator and the input end of the sampling and holding circuit respectively, and the output end of the sampling and holding circuit is electrically connected to the negative phase input end of the pulse width modulation comparator; The ramp signal generating circuit is used to generate the ramp signal and transmit the ramp signal to the sampling and holding circuit and the pulse width modulation comparator respectively; The sample-and-hold circuit is used to sample and hold the maximum voltage value of the ramp signal to obtain a first voltage signal.
3. The RBCOT architecture buck converter according to claim 2, characterized in that: The ramp signal generating circuit comprises: a current source, a first capacitor, a first switch tube and a clamping device; The output end of the current source is electrically connected to the upper plate of the first capacitor, the drain end of the first switch tube, the first end of the clamp device and the input end of the sample and hold circuit are all electrically connected between the output end of the current source and the upper plate of the first capacitor, and the lower plate of the first capacitor, the source end of the first switch tube and the second end of the clamp device are all grounded; The current source is used to output a first current so that the ramp signal generating circuit generates the ramp signal; The clamping device is used to clamp the ramp signal in the discontinuous conduction mode to obtain the second voltage signal.
4. The RBCOT architecture buck converter according to claim 3, characterized in that: The clamping device comprises: a second switch tube and a first resistor; The first end of the first resistor is electrically connected between the output end of the current source and the upper plate of the first capacitor, the second end of the first resistor is electrically connected to the drain end of the second switch tube, and the source end of the second switch tube is grounded.
5. The RBCOT architecture buck converter according to claim 2, characterized in that: The sampling and holding circuit comprises: a third switch tube and a second capacitor; The drain end of the third switch tube is electrically connected to the output end of the ramp signal generating circuit, the source end of the third switch tube is electrically connected to the upper plate of the second capacitor, and the lower plate of the second capacitor is grounded.
6. The RBCOT architecture buck converter according to claim 5, characterized in that: The sample-and-hold circuit further comprises: a low-pass filter; The first end of the low-pass filter is electrically connected to the source end of the third switch tube, and the second end of the low-pass filter is grounded; The low-pass filter is used to determine the time required for the first voltage signal to jump from the second voltage signal to the third voltage signal, and the time constant of the low-pass filter is smaller than the time constant of the integrator.
7. The RBCOT architecture buck converter according to claim 6, characterized in that: The low-pass filter comprises: a second resistor and a third capacitor; A first end of the second resistor is electrically connected to the source end of the third switch tube, a second end of the second resistor is electrically connected to the upper plate of the third capacitor, and a lower plate of the third capacitor is grounded.
8. The RBCOT architecture buck converter according to claim 3 or 5, characterized in that: The ramp signal generating circuit further includes: a control circuit; The output end of the control circuit is electrically connected to the gate end of the first switch tube, the gate end of the second switch tube and the gate end of the third switch tube respectively; The control circuit is used to control the first switch tube to be turned on and the second switch tube to be turned off during the on phase of the RBCOT architecture buck converter, and to control the first switch tube and the second switch tube to be turned off during the off phase of the RBCOT architecture buck converter; The control circuit is further used to control the second switch tube to be turned on in the discontinuous conduction mode, or to control the second switch tube to be always turned off in the continuous conduction mode; The control circuit is further used to control the third switch tube to be turned on after the shutdown phase ends.
9. A chip, characterized in that: include: The RBCOT architecture buck converter according to any one of claims 1 to 8.
10. An electronic device, characterized in that: include: The chip as claimed in claim 9.