Asynchronous digital filter
By introducing asynchronous control modules and signal acquisition modules in the digital filter, each trigger is driven by an independent pulse signal to solve the problem of high dynamic power consumption of high -order digital filter, and reduces power consumption.
Patent Information
- Application Number
- CN202411406885.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-09
- Publication Date
- 2025-01-28
AI Technical Summary
Because the high-order digital filter relies on a unified clock signal driving, some DFF is triggered unnecessary, increasing the dynamic power consumption of the digital filter.
Design an asynchronous digital filter, which uses the asynchronous control module to generate an independent pulse signal of each first control unit to drive the corresponding first trigger to avoid unnecessary trigger.
The design of the asynchronous control module and signal collection module avoids unnecessary trigger activation, and reduces the dynamic power consumption of digital filter.
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Figure CN119382668A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to an asynchronous digital filter. Background Art
[0002] Digital filter is a widely used tool in signal processing, which can effectively enhance the quality of signal and reduce noise interference.
[0003] In the related art, a high-order digital filter needs to be composed of a large number of D flip-flops (D Flip-Flop, DFF), and these DFFs need to be driven by the same clock signal to ensure their working timing. However, each flip of the clock signal will cause some DFFs to be triggered unnecessarily, thereby increasing the dynamic power consumption of the digital filter. Summary of the invention
[0004] In order to overcome the problems existing in the related art, the present disclosure provides an asynchronous digital filter.
[0005] According to a first aspect of an embodiment of the present disclosure, there is provided an asynchronous digital filter, comprising:
[0006] An asynchronous control module, comprising a plurality of first control units connected in sequence, wherein two adjacent first control units interact with each other through handshake signals, so that each first control unit can generate an independent pulse signal;
[0007] A signal acquisition module, comprising a plurality of first triggers connected in sequence, wherein the plurality of first triggers correspond to the plurality of first control units one by one, and each first trigger is used to acquire a digital signal input to the first trigger according to a pulse signal generated by the corresponding first control unit; wherein the digital signal input to the first trigger of the plurality of first triggers is a target digital signal to be filtered, and in two adjacent first triggers, the digital signal input to the latter first trigger is a digital signal acquired by the former first trigger;
[0008] The logic operation module is used to perform weighted summation on the digital signals collected by the multiple first triggers to obtain a filtering result of the target digital signal.
[0009] In some embodiments, the asynchronous digital filter further comprises:
[0010] The result collection module is connected to the logic operation module and is used to collect the output result of the logic operation module after the logic operation module performs the weighted sum operation each time.
[0011] In some embodiments, the result collection module includes:
[0012] A second control unit, used for generating an independent pulse signal;
[0013] The second trigger is used to collect the output result of the logic operation module according to the pulse signal generated by the second control unit.
[0014] In some embodiments, the second control unit is connected to the last first control unit among the plurality of first control units through a delay unit, and interacts with the last first control unit through a handshake signal;
[0015] The delay unit is used to delay the handshake signal output by the last first control unit for a target time length and then input the delay signal into the second control unit.
[0016] In some embodiments, the target duration is greater than the time taken by the logic operation module to perform the weighted sum operation.
[0017] In some embodiments, a multiplexer is further provided between the result acquisition module and the logic operation module;
[0018] The first input end of the multiplexer is connected to the logic operation module, the second input end of the multiplexer is connected to the last first trigger among the multiple first triggers, and the output end of the multiplexer is connected to the result acquisition module.
[0019] In some embodiments, the logic operation module includes:
[0020] A shifter, used for calculating the product of the digital signal collected by the first trigger and the corresponding weight coefficient;
[0021] The adder is used to add the product results corresponding to each first trigger to obtain the filtering result. In some embodiments, when the weight coefficient corresponding to the digital signal is N, the shifter is used to shift the digital signal left by log2(N) bits; wherein N is an integer power of 2.
[0022] In some embodiments, the asynchronous digital filter further comprises:
[0023] The enable input terminal is respectively connected to the enable terminal of each first trigger of the plurality of first triggers, and is used to control the opening and closing of the asynchronous digital filter.
[0024] In some embodiments, the first control unit is a Click unit.
[0025] The technical solution provided by the embodiments of the present disclosure may have the following beneficial effects:
[0026] The asynchronous digital filter provided by the embodiment of the present disclosure includes: an asynchronous control module, a signal acquisition module and a logic operation module. Among them, the asynchronous control signal includes a plurality of first control units connected in sequence, and two adjacent first control units interact through handshake signals so that each first control unit can generate an independent pulse signal. The signal acquisition module includes a plurality of first triggers connected in sequence, and the plurality of first triggers correspond to the plurality of first control units one by one, and each first trigger is used to collect the digital signal input to the first trigger according to the pulse signal generated by the corresponding first control unit. The logic operation module can perform weighted summation of the digital signals collected by the plurality of first triggers to obtain a filtering result. In the embodiment of the present disclosure, since each first trigger is driven by an independent pulse signal generated by the corresponding first control unit, and does not rely on a unified clock signal drive, it is possible to avoid the first trigger from being triggered unnecessarily, thereby reducing the dynamic power consumption of the digital filter. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 A schematic structural diagram of an asynchronous digital filter in an embodiment of the present disclosure is shown.
[0028] Figure 2 A schematic structural diagram of a Click unit in an embodiment of the present disclosure is shown.
[0029] Figure 3 A schematic diagram showing the connection relationship of the result acquisition module in an embodiment of the present disclosure is shown. DETAILED DESCRIPTION
[0030] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.
[0031] The terms used in this disclosure are for the purpose of describing specific embodiments only and are not intended to limit the disclosure. The singular forms of "a", "said" and "the" used in this disclosure and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.
[0032] Furthermore, the terms “first”, “second”, etc. are merely used for distinguishing descriptions and should not be understood as indicating or implying relative importance.
[0033] Figure 1A schematic diagram of the structure of an asynchronous digital filter in an embodiment of the present disclosure is shown. Figure 1 As shown, the asynchronous digital filter includes: an asynchronous control module 100 , a signal acquisition module 200 and a logic operation module 300 .
[0034] The asynchronous control module 100 includes: a plurality of first control units 110 connected in sequence. Two adjacent first control units 110 interact with each other through handshake signals, so that each first control unit 110 can generate an independent pulse signal.
[0035] The signal acquisition module 200 includes: a plurality of first triggers 210 connected in sequence, and the plurality of first triggers 210 correspond one to one with the plurality of first control units 110. Each first trigger 210 is used to collect a digital signal input to the first trigger 210 according to a pulse signal generated by the corresponding first control unit 110. The digital signal input to the first first trigger 210 among the plurality of first triggers 210 is the target digital signal to be filtered, and in two adjacent first triggers 210, the digital signal input to the latter first trigger 210 is the digital signal collected by the former first trigger 210.
[0036] The logic operation module 300 is used to perform weighted summation on the digital signals collected by the multiple first triggers 210 to obtain a filtering result of the target digital signal.
[0037] In the embodiment of the present disclosure, a pulse signal generated by the first control unit, rather than a clock signal, is used to drive the first trigger, and each first trigger is driven by a different first control unit. Since the multiple first control units interact through handshake signals, the generated pulse signals are asynchronous, so asynchronous control of multiple first triggers can be achieved. That is, among multiple first control units, only after the first control unit of the previous stage generates a pulse signal, the first control unit of the next stage will generate a pulse signal. Accordingly, for multiple first triggers, only after the first trigger of the previous stage is triggered, the first trigger of the next stage may be triggered, thereby avoiding power consumption caused by unnecessary triggering of the first trigger.
[0038] In some embodiments, the first control unit 110 may be a Click unit, and multiple Click units interact with each other using a two-phase handshake protocol.
[0039] For example, please refer to Figure 2 , Figure 2 FIG. 2 is a schematic diagram showing the structure of a Click unit in an embodiment of the present disclosure. Figure 2 As shown, the Click unit can be composed of an XOR gate, an XOR gate, an AND gate, an inverter, a buffer, and a DFF.
[0040] Exemplarily, there are five signal interaction terminals in the Click unit. Among them, the input request terminal and the output response terminal are handshake signal receiving terminals, the input request terminal is used to receive the handshake signal sent by the previous level Click unit, and the output response terminal is used to receive the handshake signal returned by the next level Click unit. The output request terminal and the input response terminal are handshake signal sending terminals, the output request terminal is used to send the handshake signal to the next level Click unit, and the input response terminal is used to return the handshake signal to the previous level Click unit. The fire terminal is a pulse signal output terminal, and the buffer in the Click unit can be used to control the pulse signal width output by the fire terminal.
[0041] The input request terminal is connected to the input terminal and Figure 2 The input response terminal is connected to the input terminal and Figure 2 The output of the DFF on the left is connected to the input of the XOR gate and Figure 2 The input end of the DFF on the right side of the middle, and an inverter is also provided between the output response end and the input end of the DFF on the right side. The output request end is connected to the input end and Figure 2 The output of the DFF on the right side of the middle. The output of the XOR gate and the XNOR gate are connected to the input of the AND gate, and the output of the AND gate is connected to the fire terminal and the clock control terminals of the left and right DFFs through a buffer.
[0042] Those skilled in the art will appreciate that the Click unit can be implemented using any structure, not limited to Figure 2 The circuit structure is shown.
[0043] Exemplarily, in two adjacent Click units, the output request end of the previous Click unit is connected to the input request end of the next Click unit, and the output response end of the previous Click unit is connected to the input response end of the next Click unit. And in a plurality of Click units connected in sequence, the input request end of the first Click unit is used to input a request signal, wherein the number of flips of the request signal corresponds to the amount of data to be filtered. In other words, only when a request signal corresponding to the digital signal to be filtered is received, the asynchronous control module is in working state, and each Click unit can output a pulse signal through the fire end.
[0044] When the request signal input by the input request end is reversed, the fire end can generate a pulse signal, and the signals of the input response end and the output request end are also reversed.
[0045] At this time, if the signal at the output response end is not reversed, the fire end will not continue to generate a pulse signal even if the signal at the input request end is reversed again. In other words, after a pulse signal is generated at the fire end of the Click unit, the fire end can only reverse according to the signal at the input request end and generate a pulse signal again after the signal received at the output response end is reversed.
[0046] Exemplarily, in two adjacent Click units, the output request end of the previous Click unit can be connected to the input request end of the next Click unit through a delay unit (e.g., a buffer), and the delay unit can be used to control the pulse signal period output by the fire end.
[0047] For ease of understanding, the following will combine Figure 2 The Click unit structure shown is used to illustrate the process of generating the pulse signal.
[0048] In the initial state, the input request end, output response end, output request end, input response end and fire end in the Click unit are all in low-level state. Subsequently, the input request end receives a high-level signal, and the output of the XOR gate becomes a high-level signal. Since both input ends of the XOR gate are in low-level state, the output of the XOR gate is also a high-level signal. When both input ends of the AND gate are high-level signals, the AND gate can output a high-level signal, which is output by the fire end after passing through the buffer, thereby turning the signal output by the fire end into a high-level signal, thereby generating a pulse. At the same time, the output of the buffer is also connected to the clock control ends of the two DFFs respectively, thereby updating the states of the input response end and the output request end through the DFF, so that the Click unit at this level can shake hands with the Click unit at the previous level and the Click unit at the next level respectively.
[0049] Combination of the above Figure 2 The asynchronous control module in the embodiment of the present disclosure has been described. Figure 1 , the signal acquisition module in the embodiment of the present disclosure is explained.
[0050] In some embodiments, the first trigger 210 in the signal acquisition module 200 may be a DFF. The clock control terminal of each DFF is respectively connected to the pulse signal output terminal (i.e., Figure 2 The output end of each DFF is connected to the logic operation module 300. In two adjacent DFFs, the output end of the previous DFF is connected to the input end of the next DFF.
[0051] Exemplarily, after being triggered by a pulse signal, the DFF can collect digital signals input to the input end of the DFF, and input the collected digital signals to the logic operation module 300 for weighted summation operation, and at the same time input the collected digital signals to the next level DFF of the DFF.
[0052] For example, in Figure 1 In the example, DFF 01 can collect the digital signal fir_in input to DFF 01 according to the pulse signal generated by Click 01, and input the collected digital signal fir_in_d1 to the logic operation module 300 and DFF 02 at the same time.
[0053] In some embodiments, the asynchronous digital filter further includes an enable input terminal, namely Figure 1 The enable input terminal is connected to the enable terminal of each first trigger 210 respectively, and is used to control the opening and closing of the asynchronous digital filter.
[0054] Exemplarily, when the enable input terminal outputs a low-level signal, each of the first triggers 210 can be in a closed state, thereby turning off the asynchronous digital filter. When the enable input terminal outputs a high-level signal, each of the first triggers 210 can be in an open state, thereby turning on the asynchronous digital filter. Thus, the asynchronous digital filter switch in the embodiment of the present disclosure is controllable, and the asynchronous digital filter can be controlled to be closed in an idle state to achieve the purpose of saving power consumption.
[0055] Please continue to refer to Figure 1 , the following will combine Figure 1 The logic operation module in the embodiment of the present disclosure is described in detail.
[0056] In some embodiments, the logic operation module 300 may include a shifter 310 and an adder 320 .
[0057] The shifter 310 is used to calculate the product of the digital signal collected by the first trigger 210 and the corresponding weight coefficient. The adder 320 is used to add the product results corresponding to each first trigger 210 to obtain a filtering result.
[0058] Exemplarily, when the weight coefficient corresponding to the digital signal is N, the shifter 310 is used to left-shift the digital signal by log2(N) bits, so as to implement a multiplication operation through the shifter 310. Wherein, N is an integer power of 2.
[0059] For example, in Figure 1, the weight coefficients of fir_in_d1 and fir_in_d5 are 1, the weight coefficients of fir_in_d2 and fir_in_d4 are 2, and the weight coefficient of fir_in_d3 is 4, that is, the final output result of the logic operation module 300 is fir_in_d1+fir_in_d2×2+fir_in_d3×4+fir_in_d4×2+fir_in_d5.
[0060] At this time, the output results of fir_in_d2 and fir_in_d4 can be connected to independent shifters 310 capable of shifting left by one bit, and the output result of fir_in_d3 can be connected to a shifter 310 capable of shifting left by two bits, and then the output ends of the shifters 310 are connected to the input ends of the adder 320. Since the weight coefficients of fir_in_d1 and fir_in_d5 are 1, the output results of fir_in_d1 and fir_in_d5 can be directly input to the adder 320 without passing through the shifter 310.
[0061] Therefore, the embodiment of the present disclosure can reduce the scale of the integrated circuit and further reduce the power consumption of the digital filter by providing the shifter 310 to replace the multiplier to implement the multiplication operation.
[0062] Please refer again Figure 1 In some embodiments, the asynchronous digital filter further includes a result acquisition module 400. The result acquisition module 400 may be connected to the logic operation module 300, and is used to acquire the output result of the logic operation module 300 after the logic operation module 300 performs the weighted sum operation each time.
[0063] By setting the result acquisition module 400, accurate filtering results can be captured from the output results of the logic operation module 300, thereby achieving filtering of the transition state signal generated during the filtering process.
[0064] In some embodiments, the result acquisition module 400 includes a second control unit 410 and a second trigger 420. The second control unit 410 is used to generate an independent pulse signal. The second trigger 420 is used to collect the output result of the logic operation module 300 according to the pulse signal generated by the second control unit 410.
[0065] For example, please refer to Figure 3 , Figure 3 FIG. 4 is a schematic diagram showing the connection relationship of the result collection module 400 in the embodiment of the present disclosure. Figure 3 As shown, the second control unit 410 may be a Click unit with the same structure as the first control unit 110. The second control unit 410 (i.e. Figure 1Click 06 in FIG. 1) is connected to the last first control unit 110 (ie, the last first control unit 110) of the plurality of first control units 110 through a delay unit 120 (eg, a buffer). Figure 1 Click 05 in the figure) is connected and interacts with the last first control unit 110 through a handshake signal. The second trigger 420 can be a DFF, whose clock control terminal is connected to the pulse signal output terminal of the second control unit 410, and is used to collect the weighted summation operation result output by the logic operation module 300.
[0066] Exemplarily, the delay unit 120 is used to delay the handshake signal output by the last first control unit 110 in the asynchronous control module 100 for a target time and then input it into the second control unit 410. Figure 3 In the embodiment, the delay unit 120 can be arranged between the output request terminal of Click 05 and the input request terminal of Click 06.
[0067] By setting the delay unit 120, the timing relationship between the asynchronous control module 100 and the result acquisition module 400 can be adjusted, thereby ensuring that the result acquisition module 400 acquires the filtering result of the digital signal rather than the transition state result.
[0068] In some embodiments, the target duration is greater than the time taken by the logic operation module 300 to perform the weighted sum operation, so as to ensure that when the second control unit 410 sends a pulse signal to the second trigger 420 to trigger the second trigger 420 to collect the output result of the logic operation module 300, the logic operation module 300 has completed the weighted sum operation.
[0069] Please continue to refer to Figure 1 In some embodiments, a multiplexer 500 is further provided between the result acquisition module 400 and the logic operation module 300. A first input end of the multiplexer 500 is connected to the logic operation module 300, a second input end of the multiplexer 500 is connected to the last first trigger 210 among the plurality of first triggers 210, and an output end of the multiplexer 500 is connected to the result acquisition module 400.
[0070] For example, in Figure 1 In the embodiment, the first input end of the multiplexer 500 is connected to the adder 320 , the second input end of the multiplexer 500 is connected to the output end of the DFF 05 , and the output end of the multiplexer 500 is connected to the input end of the DFF 06 in the result collection module 400 .
[0071] Exemplarily, the asynchronous digital filter further includes a signal filtering terminal ( Figure 1When the signal filtering terminal is at a high level, the asynchronous digital filter can output a stable filtering result through the result acquisition module 400, and when the signal filtering terminal is at a low level, the asynchronous digital filter will output an unfiltered original digital signal.
[0072] By setting the multiplexer 500 , the output of the asynchronous digital filter can be switched between the original signal and the filtered signal, thereby expanding the application scenarios of the asynchronous digital filter.
[0073] The embodiments of the present disclosure are described in detail above in conjunction with the accompanying drawings; however, the present disclosure is not limited to the specific details in the above embodiments. Within the technical concept of the present disclosure, a variety of simple modifications can be made to the technical solution of the present disclosure, and these simple modifications all fall within the protection scope of the present disclosure.
[0074] In addition, various embodiments of the present disclosure may be arbitrarily combined, and as long as they do not violate the concept of the present disclosure, they should also be regarded as the contents disclosed by the present disclosure.
Claims
1. An asynchronous digital filter, characterized in that: include: An asynchronous control module, comprising a plurality of first control units connected in sequence, wherein two adjacent first control units interact with each other through handshake signals, so that each first control unit can generate an independent pulse signal; A signal acquisition module, comprising a plurality of first triggers connected in sequence, wherein the plurality of first triggers correspond one-to-one to the plurality of first control units, and each first trigger is used to acquire a digital signal input to the first trigger according to a pulse signal generated by the corresponding first control unit; wherein the digital signal input to the first trigger of the plurality of first triggers is a target digital signal to be filtered, and in two adjacent first triggers, the digital signal input to the latter first trigger is a digital signal acquired by the former first trigger; The logic operation module is used to perform weighted summation on the digital signals collected by the multiple first triggers to obtain a filtering result of the target digital signal.
2. The asynchronous digital filter according to claim 1, characterized in that: The asynchronous digital filter further comprises: The result collection module is connected to the logic operation module and is used to collect the output result of the logic operation module after the logic operation module performs the weighted sum operation each time.
3. The asynchronous digital filter according to claim 2, characterized in that: The result collection module comprises: A second control unit, used for generating an independent pulse signal; The second trigger is used to collect the output result of the logic operation module according to the pulse signal generated by the second control unit.
4. The asynchronous digital filter according to claim 3, characterized in that: The second control unit is connected to the last first control unit among the plurality of first control units through the delay unit, and interacts with the last first control unit through a handshake signal; The delay unit is used to delay the handshake signal output by the last first control unit by a target time length and then input the delay signal into the second control unit.
5. The asynchronous digital filter according to claim 4, characterized in that: The target duration is greater than the time taken by the logic operation module to perform the weighted sum operation.
6. The asynchronous digital filter according to claim 2, characterized in that: A multiplexer is also provided between the result acquisition module and the logic operation module; The first input end of the multiplexer is connected to the logic operation module, the second input end of the multiplexer is connected to the last first trigger among the multiple first triggers, and the output end of the multiplexer is connected to the result acquisition module.
7. The asynchronous digital filter according to claim 1, characterized in that: The logic operation module comprises: A shifter, used for calculating the product of the digital signal collected by the first trigger and the corresponding weight coefficient; The adder is used to add the product results corresponding to each first trigger to obtain the filtering result.
8. The asynchronous digital filter according to claim 7, characterized in that: When the weight coefficient corresponding to the digital signal is N, the shifter is used to left-shift the digital signal by log2(N) bits; wherein N is an integer power of 2.
9. The asynchronous digital filter according to claim 1, characterized in that: The asynchronous digital filter further comprises: The enable input terminal is respectively connected to the enable terminal of each first trigger of the plurality of first triggers, and is used to control the opening and closing of the asynchronous digital filter.
10. The asynchronous digital filter according to claim 1, characterized in that: The first control unit is a Click unit.