Clock frequency division circuit

Abstract

The invention discloses a clock frequency division circuit. The clock frequency division circuit includes a counter logic circuit, a target clock clearing circuit and a logic control circuit; the counter logic circuit is used to count the frequency division ratio by one according to the rising edge of the internal clock signal to determine the first count value; the first count value is stored as the second count value according to the falling edge of the internal clock signal, and the frequency division cycle start signal is output when the first count value is equal to 0; the target clock clearing circuit is used to perform a logic operation on the frequency division ratio and the duty cycle according to the rising edge of the internal clock signal within the frequency division cycle to form a control signal of the duty cycle within the frequency division cycle; the logic control circuit is used to form a target clock signal according to the frequency division ratio, the first count value, the second count value and the control signal. The frequency and duty cycle adjustment range of the clock frequency division circuit can be increased, and the performance of the clock frequency division circuit is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of digital circuits, and in particular to a clock frequency division circuit. Background Art

[0002] A clock divider (referred to as a divider) is an electronic device used to divide an input clock signal into an output signal of a lower frequency, and is widely used in digital circuits and communication systems. In the prior art, the frequency and duty cycle of the clock signal output by the clock divider are limited, and cannot meet the current demand for clock dividers. Summary of the invention

[0003] The present invention provides a clock frequency dividing circuit to increase the adjustable range of the frequency dividing ratio of a clock signal output by the clock frequency dividing circuit, and can adjust the duty cycle of the output clock signal, thereby improving the performance of the clock frequency dividing circuit.

[0004] In a first aspect, an embodiment of the present invention provides a clock frequency division circuit, including a counter logic circuit, a target clock clearing circuit and a logic control circuit;

[0005] The input end of the counter logic circuit is used to input the internal clock signal and the division ratio of the target clock signal, and the input end of the target clock clear circuit is used to input the internal clock signal, the division ratio and the duty cycle of the target clock signal; the logic control circuit is connected to the output end of the counter logic circuit and the output of the target clock clear circuit; the counter logic circuit is used to count the division ratio by one according to the rising edge of the internal clock signal to determine a first count value; store the first count value as a second count value according to the falling edge of the internal clock signal, and output a division cycle start signal when the first count value is equal to 0; the target clock clear circuit is used to perform a logical operation on the division ratio and the duty cycle according to the rising edge of the internal clock signal within the division cycle to form a control signal of the duty cycle within the division cycle; the logic control circuit is used to form the target clock signal according to the division ratio, the first count value, the second count value and the control signal.

[0006] Optionally, the counter logic circuit includes a first register, a second register, a first subtractor, a first selector, a first judgment unit and a second selector;

[0007] The enable terminal of the first register is used to input the internal clock signal, and the enable terminal of the second register is used to input the inverted signal of the internal clock signal; the input terminal of the first register is connected to the output terminal of the first selector, the output terminal of the first register is connected to the input terminal of the second register, the input terminal of the first subtractor and the input terminal of the first judgment unit, the output terminal of the first subtractor is connected to the first input terminal of the first selector, the second input terminal of the first selector is used to input the frequency division ratio, the control terminal of the first selector is connected to the output terminal of the second selector, the output terminal of the first judgment unit is connected to the control terminal of the second selector, the first input terminal of the second selector is used to input the frequency division ratio, The first register is used to determine the first count value according to the rising edge of the internal clock signal; the second register is used to store the first count value as the second count value according to the falling edge of the internal clock signal; the first subtractor is used to decrement the first count value by one, the first judgment unit is used to judge whether the first count value is 0, and when the first count value is 0, the second selector is controlled to select the second input end and the output end of the second selector to output the logic 1 as the frequency division cycle start signal; the first selector is used to select the second input end and the output end of the first selector according to the frequency division cycle start signal.

[0008] Optionally, the target clock clearing circuit includes a divider, a second subtractor, a first adder, a second judgment unit and a third selector;

[0009] The input end of the divider and the input end of the second judgment unit are used to input the duty cycle, the output end of the divider is connected to the second input end of the second subtractor, the first input end of the second subtractor is used to input the frequency division ratio, the output end of the second subtractor is connected to the first input end of the first adder, and the second input end of the first adder is used to input the logic 1; the first input end of the third selector is used to input the logic 0, and the second input end of the third selector is used to input the logic 1; the divider is used to right-shift the value of the duty cycle to form a first value, the second subtractor is used to difference the frequency division ratio and the first value to form a first odd control signal of the duty cycle, the first adder is used to add 1 to the first odd control signal to form an even control signal of the duty cycle, and the second judgment unit is used to control the third selector to output the logic 1 as the second odd control signal of the duty cycle when the duty cycle is 1.

[0010] Optionally, the target clock clearing circuit further includes a frequency division ratio register and a duty cycle register;

[0011] The input end of the frequency division ratio register is used to input the frequency division ratio, the first control end of the frequency division ratio register is used to input the internal clock signal, the second control end of the frequency division ratio register is used to input the frequency division period start signal, the output end of the frequency division ratio register is connected to the first input end of the second subtractor, and the frequency division ratio register is used to store the frequency division ratio within the frequency division period;

[0012] The input end of the duty cycle register is used to input the duty cycle, the first control end of the duty cycle register is used to input the internal clock signal, the second control end of the duty cycle register is used to input the frequency division period start signal, the output end of the duty cycle register is connected to the input end of the divider and the input end of the second judgment unit, and the duty cycle register is used to store the duty cycle within the frequency division period.

[0013] Optionally, the frequency division ratio register includes a fourth selector and a third register; the second input end of the fourth selector is used to input the frequency division ratio, the control end of the fourth selector is used to input the frequency division period start signal, the output end of the fourth selector is connected to the input end of the third register, the enable end of the third register is used to input the internal clock signal, and the output end of the third register is connected to the first input end of the fourth selector and the first input end of the second subtractor; the fourth selector is used to select the second input end and the output end of the fourth selector according to the frequency division period start signal, and the third register is used to store the frequency division ratio according to the rising edge of the internal clock signal within the frequency division period;

[0014] The duty cycle register includes a fifth selector and a fourth register; the second input end of the fifth selector is used to input the duty cycle, the control end of the fifth selector is used to input the division cycle start signal, the output end of the fifth selector is connected to the input end of the fourth register, the enable end of the fourth register is used to input the internal clock signal, and the output end of the fourth register is connected to the first input end of the fifth selector, the input end of the divider and the input end of the second judgment unit; the fifth selector is used to select the second input end and the output end of the fifth selector according to the division cycle start signal, and the fourth register is used to store the duty cycle according to the rising edge of the internal clock signal within the division cycle.

[0015] Optionally, the logic control circuit includes a reset unit, a rising edge logic control unit, a falling edge logic control unit and an OR logic unit;

[0016] The enable terminal of the reset unit is used to input the inverted signal of the internal clock signal, the input terminal of the reset unit is used to input the reset signal, the second count value, the frequency division ratio and the second odd control signal, and the reset unit is used to output a reset control signal according to the rising edge of the inverted signal of the internal clock signal and the reset signal when the duty cycle is equal to 1;

[0017] The control end of the rising edge logic control unit is connected to the output end of the reset unit, the enable end of the rising edge logic control unit is used to input the internal clock signal, the input end of the rising edge logic control unit is used to input the first count value, the frequency division cycle start signal, the frequency division ratio and the even control signal, the rising edge logic control unit is used to output the logic 1 according to the internal clock signal and the frequency division cycle start signal when the frequency division ratio is not equal to 0, and output the logic 0 when the first count value is equal to the even control signal, and is also used to reset the internal clock signal according to the reset control signal;

[0018] The enable terminal of the falling edge logic control unit is used to input the inverted signal of the internal clock signal, the input terminal of the falling edge logic control unit is used to input the second count value, the frequency division ratio, the duty cycle, the first odd control signal and the second odd control signal, the falling edge logic control unit is used to output the logic 1 according to the inverted signal of the internal clock signal when the duty cycle is odd and not equal to 1, the frequency division ratio is not equal to 0, and the second count value is equal to the frequency division ratio, and output the logic 0 when the second count value is equal to the first odd control signal and the duty cycle is odd;

[0019] The output end of the rising edge logic control unit is connected to the first input end of the OR logic unit, the output end of the falling edge logic control unit is connected to the second input end of the OR logic unit, and the output end of the OR logic unit serves as the output end of the clock frequency division circuit; the OR logic unit is used to perform an OR logic operation on the logic value output by the rising edge logic control unit and the logic value output by the falling edge logic control unit to form the target clock signal.

[0020] Optionally, the reset unit includes a sixth selector, a fifth register, a first inverter and a first AND gate;

[0021] The control end of the sixth selector is used to input the second count value, the division ratio and the second odd control signal, the first input end of the sixth selector is used to input the logic 0, the second input end of the sixth selector is used to input the logic 1, and the sixth selector is used to select the second input end and the output end of the sixth selector when the second count value is equal to the division ratio and the second odd control signal is logic 1; the output end of the sixth selector is connected to the input end of the fifth register, the enable end of the fifth register is used to input the inverted signal of the internal clock signal, the output end of the fifth register is connected to the input end of the first inverter, the output end of the first inverter is connected to the first input end of the first AND gate, the second input end of the first AND gate is used to input the reset signal, and the output end of the first AND gate serves as the output end of the reset unit.

[0022] Optionally, the rising edge logic control unit includes a seventh selector, an eighth selector and a sixth register;

[0023] The first input end of the seventh selector is connected to the output end of the sixth register and serves as the output end of the rising edge logic control unit, the second input end of the seventh selector is used to input the logic 0, the control end of the seventh selector is used to input the first count value and the even control signal, the output end of the seventh selector is connected to the first input end of the eighth selector, the second input end of the eighth selector is used to input the logic 1, the control end of the eighth selector is used to input the frequency division cycle start signal and the frequency division ratio, the output end of the eighth selector is connected to the input end of the sixth register, the enable end of the sixth register is used to input the internal clock signal, and the control end of the sixth register is connected to the output end of the reset unit; the seventh selector is used to select the second input end and output end of the seventh selector when the first count value is equal to the even control signal, and the eighth selector is used to select the second input end and output end of the eighth selector when the frequency division ratio is not equal to 0 and has the frequency division cycle start signal.

[0024] Optionally, the falling edge logic control unit includes a ninth selector, a tenth selector and a seventh register;

[0025] The first input end of the ninth selector is connected to the output end of the seventh register and serves as the output end of the falling edge logic control unit. The second input end of the ninth selector is used to input the logic 0. The control end of the ninth selector is used to input the second count value, the duty cycle and the first odd control signal. The output end of the ninth selector is connected to the first input end of the tenth selector. The second input end of the tenth selector is used to input the logic 1. The control end of the tenth selector is used to input the second count value, the frequency division ratio, the duty cycle and the second odd control signal. The output end of the tenth selector is connected to the input end of the seventh register. The enable end of the seventh register is used to input the inverted signal of the internal clock signal. The ninth selector is used to output the logic 0 when the second count value is equal to the first odd control signal and the duty cycle is an odd number. The tenth selector is used to output the logic 1 when the second count value is equal to the frequency division ratio, the frequency division ratio is not equal to 0, and the duty cycle is an odd number and is not equal to 1.

[0026] Optionally, the clock frequency dividing circuit further includes an internal clock signal generating circuit; the internal clock signal generating circuit includes an eleventh selector, a twelfth selector, an eighth register, an enable output unit and a second inverter;

[0027] The first input end of the eleventh selector and the first input end of the twelfth selector are connected to the output end of the eighth register, the second input end of the eleventh selector and the second input end of the twelfth selector are used to input the frequency division enable signal, the control end of the eleventh selector and the control end of the twelfth selector are used to input the frequency division cycle start signal, the output end of the eleventh selector is connected to the input end of the eighth register, the enable end of the eighth register and the input end of the enable output unit are used to input the initial clock signal, the output end of the twelfth selector is connected to the enable end of the enable output unit, the output end of the enable output unit is connected to the input end of the second inverter, the eleventh selector and the twelfth selector are used to select the second input end and the output end when the frequency division cycle start signal is valid, the enable output unit is used to output the initial clock signal as the internal clock signal according to the frequency division ratio, and the output end of the second inverter is used to output the inverted signal of the internal clock signal.

[0028] The technical solution of the embodiment of the present invention is to count the division ratio by one according to the rising edge of the internal clock signal through the counter logic circuit, so that the first count value can represent the starting position of the cycle of the internal clock signal, and the second count value can represent the half-cycle position of the internal clock signal. At the same time, the division cycle start signal can ensure the end position of the division cycle or the starting position of the next division cycle; then the target clock clearing circuit determines the number of high-level half-cycles and the number of low-level half-cycles of the internal clock signal required by the target clock signal according to the division ratio and the duty cycle, and uses them as control signals; the logic control circuit adjusts the half-cycle output state of each internal clock signal in the division cycle according to the control signal to form the target clock signal, so that the clock division circuit can not only adjust the frequency of the target clock signal according to the division ratio of any integer, but also adjust the duty cycle of the target clock signal according to any duty cycle, so that the target clock signal with any frequency and any duty cycle can be output, thereby increasing the adjustability of the target clock signal and improving the performance of the clock division circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic structural diagram of a clock frequency division circuit provided by an embodiment of the present invention.

[0030] Figure 2 A timing diagram of an internal clock signal and a target clock signal provided in an embodiment of the present invention.

[0031] Figure 3 Another timing diagram of an internal clock signal and a target clock signal provided by an embodiment of the present invention.

[0032] Figure 4 Another timing diagram of an internal clock signal and a target clock signal provided by an embodiment of the present invention.

[0033] Figure 5 Another timing diagram of an internal clock signal and a target clock signal provided by an embodiment of the present invention.

[0034] Figure 6 A schematic diagram of the structure of a counter logic circuit provided by an embodiment of the present invention.

[0035] Figure 7 A schematic diagram of the structure of a target clock clearing circuit provided by an embodiment of the present invention.

[0036] Figure 8 A schematic diagram of the structure of a logic control circuit provided by an embodiment of the present invention.

[0037] Fig. 9 A schematic structural diagram of an internal clock signal generating circuit provided by an embodiment of the present invention.

[0038] Fig.10 A schematic diagram of the structure of an auxiliary logic circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0039] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0040] Figure 1 A schematic diagram of the structure of a clock frequency division circuit provided by an embodiment of the present invention. Figure 1 As shown, the clock frequency division circuit includes a counter logic circuit 110, a target clock clearing circuit 120 and a logic control circuit 130; the input end of the counter logic circuit 110 is used to input the internal clock signal clki and the frequency division ratio ndiv of the target clock signal, and the input end of the target clock clearing circuit 120 is used to input the internal clock signal clki, the frequency division ratio ndiv and the duty cycle nedge of the target clock signal; the logic control circuit 130 is connected to the output end of the counter logic circuit 110 and the output of the target clock clearing circuit 120; the counter logic circuit 110 is used to adjust the frequency division ratio ndi according to the rising edge of the internal clock signal clki v performs a minus-one count to determine the first count value cnt1, stores the first count value cnt1 as the second count value cnt2 according to the falling edge of the internal clock signal clki, and outputs the frequency division cycle start signal zero when the first count value cnt1 is equal to 0; the target clock clearing circuit 120 is used to perform a logical operation on the frequency division ratio ndiv and the duty cycle nedge according to the rising edge of the internal clock signal clki within the frequency division cycle to form a control signal of the duty cycle within the frequency division cycle; the logic control circuit 130 is used to form the target clock signal clko according to the frequency division ratio ndiv, the first count value cnt1, the second count value cnt2 and the control signal.

[0041] Specifically, the internal clock signal clki can be a clock signal input by the clock frequency division circuit in a frequency division cycle when the clock frequency division circuit is enabled, that is, the initial clock signal. The frequency of the internal clock signal clki can be the same as the frequency of the initial clock signal input by the clock frequency division circuit. The frequency division ratio ndiv is the ratio of the frequency of the internal clock signal clki to the frequency of the clock signal output by the clock frequency division circuit, that is, the frequency of the target clock signal clko, minus 1. Among them, the frequency division cycle is the cycle of the target clock signal clko. When the frequency division ratio ndiv is greater than 0, there are multiple cycles of the internal clock signal clki in one frequency division cycle. Exemplarily, when the frequency division ratio ndiv is 1, the ratio of the frequency of the internal clock signal clki to the frequency of the target clock signal clko is 1+1=2, that is, the frequency of the internal clock signal clki is twice the frequency of the target clock signal clko, and there are 2 internal clock signals clki in each frequency division cycle. When the frequency division ratio ndiv is 2, the ratio of the frequency of the internal clock signal clki to the frequency of the target clock signal clko is 2+1=3, that is, the frequency of the internal clock signal clki is three times the frequency of the target clock signal clko, and there are 3 internal clock signals clki in each frequency division cycle. The duty cycle nedge is the ratio of the high level period of the target clock signal clko to the half period of the internal clock signal clki in one frequency division cycle. Exemplarily, when the frequency division ratio ndiv is 2 and the duty cycle nedge is 1, there are 3 internal clock signals clki in each frequency division cycle, and the ratio of the high level period of the target clock signal clko to the half period of the internal clock signal clki is 1, that is, the duty cycle of the target clock signal clko is 1 / 6.

[0042] At the beginning of the frequency division cycle, the counter logic circuit 110 can count the frequency division ratio ndiv down by one according to the rising edge of the internal clock signal clki, so that the change range of the first count value cnt1 is the frequency division ratio ndiv to 0, and the change condition of the first count value cnt1 is the rising edge of the internal clock signal clki, that is, the first count value cnt1 changes at the rising edge of the internal clock signal clki, so that the change of the first count value cnt1 can represent the cycle start position of the internal clock signal clki, that is, the first count value cnt1 is reduced by one, and an internal clock signal clki is output within the frequency division cycle. At the same time, the counter logic circuit 110 can store the first count value cnt1 as the second count value cnt2 at the falling edge of the internal clock signal clki, so that the second count value cnt2 changes at the falling edge of the internal clock signal clki, and the change of the second count value cnt2 can represent the half-cycle start position of the internal clock signal clki. When the first count value cnt1 is equal to 0, the output of the internal clock signal clki within the frequency division cycle ends, that is, one frequency division cycle ends and the next frequency division cycle begins. At this time, the counter logic circuit 110 can output a frequency division cycle start signal zero, which is used to indicate the end position of the frequency division cycle or the start position of the next frequency division cycle.

[0043] After determining the frequency division ratio ndiv and the duty cycle nedge, the number of internal clock signals clki in each frequency division cycle can be determined according to the frequency division ratio ndiv, that is, the number of rising edges and the number of falling edges of the internal clock signal clki in each frequency division cycle can be determined. The rising edge is the starting position of the internal clock signal clki, and the falling edge is the half-cycle position of the internal clock signal clki. At the same time, the time of outputting a high level in the target clock signal clko can be determined according to the duty cycle nedge, that is, the high and low state of the level corresponding to the half-cycle of each internal clock signal clki in the frequency division cycle can be determined. Then, the target clock clearing circuit 120 can determine the number of high levels of each internal clock signal clki outputting a half-cycle on the falling edge and the number of high levels of each internal clock signal clki outputting a half-cycle on the rising edge in the frequency division cycle according to the frequency division ratio ndiv and the duty cycle nedge, and form a control signal so that the control signal can characterize the half-cycle output state of each internal clock signal clki in the frequency division cycle. Then the logic control circuit 130 adjusts the half-cycle output state of each internal clock signal clki within the frequency division period according to the control signal to form the target clock signal clko, so that the clock frequency division circuit can not only adjust the frequency of the target clock signal clko according to the frequency division ratio ndiv of any integer, but also adjust the duty cycle of the target clock signal clko according to any duty cycle nedge, so that the target clock signal clko with any frequency and any duty cycle can be output, thereby increasing the adjustability of the target clock signal clko and improving the performance of the clock frequency division circuit. For example, Figure 2 A timing diagram of an internal clock signal and a target clock signal provided by an embodiment of the present invention. Figure 2 As shown, when the division ratio ndiv is 1 and the duty cycle nedge is 1, the frequency of the internal clock signal clki is twice the frequency of the target clock signal clko, and the duty cycle nedge is half a cycle of the internal clock signal clki, that is, the duty cycle of the target clock signal clko is 1 / 4. Figure 3 Another timing diagram of an internal clock signal and a target clock signal provided by an embodiment of the present invention. Figure 3 As shown, when the division ratio ndiv is 1 and the duty cycle nedge is 3, the frequency of the internal clock signal clki is twice the frequency of the target clock signal clko, and the duty cycle nedge is three half cycles of the internal clock signal clki, that is, the duty cycle of the target clock signal clko is 3 / 4. Figure 4 Another timing diagram of an internal clock signal and a target clock signal provided by an embodiment of the present invention. Figure 4As shown, when the division ratio ndiv is 2 and the duty cycle nedge is 1, the frequency of the internal clock signal clki is three times the frequency of the target clock signal clko, and the duty cycle nedge is half a cycle of the internal clock signal clki, that is, the duty cycle of the target clock signal clko is 1 / 6. Figure 5 Another timing diagram of an internal clock signal and a target clock signal provided by an embodiment of the present invention. Figure 5 As shown, when the division ratio ndiv is 2 and the duty cycle nedge is 5, the frequency of the internal clock signal clki is three times the frequency of the target clock signal clko, and the duty cycle nedge is five half cycles of the internal clock signal clki, that is, the duty cycle of the target clock signal clko is 5 / 6.

[0044] The technical solution of this embodiment is to count the division ratio by one less than the rising edge of the internal clock signal through the counter logic circuit, so that the first count value can represent the starting position of the cycle of the internal clock signal, and the second count value can represent the half-cycle position of the internal clock signal. At the same time, the division cycle start signal can ensure the end position of the division cycle or the starting position of the next division cycle; then the target clock clearing circuit determines the number of high-level half-cycles and low-level half-cycles of the internal clock signal required by the target clock signal according to the division ratio and the duty cycle, and uses them as control signals; the logic control circuit adjusts the half-cycle output state of each internal clock signal in the division cycle according to the control signal to form the target clock signal, so that the clock division circuit can not only adjust the frequency of the target clock signal according to the division ratio of any integer, but also adjust the duty cycle of the target clock signal according to any duty cycle, so that the target clock signal with any frequency and any duty cycle can be output, thereby increasing the adjustability of the target clock signal and improving the performance of the clock division circuit.

[0045] Figure 6 A schematic diagram of the structure of a counter logic circuit provided by an embodiment of the present invention. Figure 6As shown, the counter logic circuit includes a first register DR1, a second register DR2, a first subtractor SUB1, a first selector CH1, a first judgment unit P1 and a second selector CH2; the enable end EN1 of the first register DR1 is used to input the internal clock signal clki, and the enable end EN2 of the second register DR2 is used to input the inverted signal clkin of the internal clock signal; the input end of the first register DR1 is connected to the output end of the first selector CH1, the output end of the first register DR1 is connected to the input end of the second register DR2, the input end of the first subtractor SUB1 and the input end of the first judgment unit P1, the output end of the first subtractor SUB1 is connected to the first input end of the first selector CH1, the second input end of the first selector CH1 is used to input the frequency division ratio ndiv, the control end of the first selector CH1 is connected to the output end of the second selector CH2, the first judgment unit P1 The output end is connected to the control end of the second selector CH2, the first input end of the second selector CH2 is used to input logic 0, and the second input end of the second selector CH2 is used to input logic 1; the first register DR1 is used to determine the first count value cnt1 according to the rising edge of the internal clock signal clki; the second register DR2 is used to store the first count value cnt1 as the second count value cnt2 according to the falling edge of the internal clock signal clki; the first subtractor SUB1 is used to subtract one from the first count value cnt1, the first judgment unit P1 is used to judge whether the first count value cnt1 is 0, and when the first count value cnt1 is 0, control the second selector CH2 to select the second input end and output end of the second selector CH2, so as to output logic 1 as the frequency division cycle start signal zero; the first selector CH1 is used to select the second input end and output end of the first selector CH1 according to the frequency division cycle start signal zero.

[0046] Specifically, the number of bits of the first register DR1 and the number of bits of the second register DR2 can be set according to the range of the frequency division ratio, so that the number of bits of the first register DR1 and the number of bits of the second register DR2 meet the requirements of the frequency division ratio. Exemplarily, when the maximum frequency division ratio of the clock frequency division circuit is 15, the number of bits of the first register DR1 and the number of bits of the second register DR2 can be 4 bits, so that the number of bits of the first register DR1 and the second register DR2 can store values ​​of 0-15. In the initial case, the number of bits of the first register DR1 and the value of the second register DR2 can be 0, that is, the first count value cnt1 is 0. At this time, the first judgment unit P1 selects the second input end and the output end of the second selector CH2 according to the first count value cnt1, so that the second selector CH2 outputs the frequency division cycle start signal zero of logic 1. The first selector CH1 selects the second input end and the output end according to the frequency division cycle start signal zero, so that the first selector CH1 outputs the frequency division ratio ndiv to the first register DR1. Among them, the frequency division ratio ndiv is not equal to 0. The first register DR1 outputs the frequency division ratio ndiv as the first count value cnt1 at the rising edge of the internal clock signal clki. The second register DR2 outputs the frequency division ratio ndiv as the second count value cnt2 at the rising edge of the inverted signal clkin of the internal clock signal, that is, the second register DR2 outputs the frequency division ratio ndiv as the second count value cnt2 at the falling edge of the internal clock signal clki. At the same time, the first judgment unit P1 judges that the first count value cnt1 is not equal to 0, so that the second selector CH2 selects the first input terminal and the output terminal, so that the second selector CH2 outputs logic 0. The first selector CH1 selects the first input terminal and the output terminal of the first selector CH1 according to the logic 0 output by the second selector CH2. The first subtractor SUB1 performs a subtraction operation on the frequency division ratio ndiv and outputs ndiv-1 to the first input terminal of the first selector CH1. At this time, the first selector CH1 outputs ndiv-1 to the first register DR1. Then repeat the above process until the input terminal of the first register DR1 is 0. Thus, the frequency division ratio can be sequentially reduced by one and output to the first register DR1 through the first selector CH1, so that the first register DR1 can sequentially reduce the frequency division ratio by one at the rising edge of the internal clock signal, and the second register DR2 can sequentially reduce the frequency division ratio by one at the falling edge of the internal clock signal. At the same time, the second selector CH2 can output logic 1 as the frequency division cycle start signal zero at the end position of the previous frequency division cycle, that is, the start position of the next frequency division cycle.

[0047] Figure 7 A schematic diagram of the structure of a target clock clearing circuit provided by an embodiment of the present invention. Figure 7As shown, the target clock clearing circuit includes a divider DIV, a second subtractor SUB2, a first adder ADD1, a second judgment unit P2 and a third selector CH3; the input end of the divider DIV and the input end of the second judgment unit P2 are used to input the duty cycle nedge, the output end of the divider DIV is connected to the second input end of the second subtractor SUB2, the first input end of the second subtractor SUB2 is used to input the frequency division ratio ndiv, the output end of the second subtractor SUB2 is connected to the first input end of the first adder ADD1, and the second input end of the first adder ADD1 is used to input logic 1; the first input end of the third selector CH3 The input end is used to input logic 0, and the second input end of the third selector CH3 is used to input logic 1; the divider DIV is used to right-shift the value of the duty cycle nedge to form a first value, the second subtractor SUB2 is used to difference the division ratio ndiv and the first value to form a first odd control signal clkneg of the duty cycle, the first adder ADD1 is used to add 1 to the first odd control signal clkneg to form an even control signal clkpos of the duty cycle, and the second judgment unit P2 is used to control the third selector CH3 to output logic 1 as the second odd control signal nedgeeq1 of the duty cycle when the duty cycle is 1.

[0048] Specifically, the current duty cycle nedge can be input to the input end of the divider DIV, and the current duty cycle nedge is divided by 2, so that the first value output by the divider DIV is the value of the binary value of the duty cycle nedge shifted right by one position. Exemplarily, when the duty cycle is 5, the binary value is 101, and after the divider DIV performs the division by 2 operation, the first value output is 10, that is, 2. The second subtractor SUB2 makes a difference between the division ratio ndiv and the first value to determine the value of the first odd control signal clkneg, which is used to characterize the number of low-level half-cycles of the internal clock signal required within the high-level cycle of the target clock signal clko, which is the division ratio ndiv starting to count down by one to the first value. When the duty cycle is an odd number and is not equal to 1, the logic control circuit 130 can control the low-level half cycle of the internal clock signal to output a high level according to the second count value cnt2 and the frequency division ratio ndiv, and can control the low-level half cycle of the internal clock signal to output a low level when the second count value cnt2 drops to the first odd control signal clkneg, so that when the duty cycle nedge is an odd number, the low-level half cycle of the internal clock signal can be controlled to output a high level as needed, thereby realizing the duty cycle adjustment of the target clock signal clko. The first adder ADD1 adds 1 to the first odd control signal clkneg to form an even control signal clkpos of the duty cycle, which is used to characterize the number of high-level half cycles of the internal clock signal required in the high-level cycle of the target clock signal clko, which is the frequency division ratio ndiv starting from minus one to the first value plus 1. At this time, the logic control circuit 130 can control the internal clock signal to output a high level in the high-level half cycle according to the frequency division cycle start signal and the frequency division ratio ndiv, and can control the high-level half cycle of the internal clock signal to output a low level when the first count value cnt1 drops to the even control signal clkpos. Therefore, the output number of the high-level half cycle of the internal clock signal can be controlled according to the need of the duty cycle nedge, so as to achieve the duty cycle adjustment of the target clock signal clko. In addition, when the frequency division ratio is greater than 0 and the duty cycle nedge is 1, the second judgment unit P2 can control the third selector CH3 to output the second odd control signal nedgeeq1. The logic control circuit 130 can reset the high-level half cycle of the internal clock signal according to the second odd control signal nedgeeq1, so that the high level can be output in the high-level half cycle of the first internal clock signal. After meeting the duty cycle requirement of the target clock signal clko, the high-level half cycle of other internal clock signals is controlled to output a low level, so as to achieve the minimum duty cycle control of the target clock signal clko.

[0049] Continue to refer Figure 7The target clock clearing circuit also includes a frequency division ratio register 121 and a duty cycle register 122; the input end of the frequency division ratio register 121 is used to input the frequency division ratio ndiv, the first control end of the frequency division ratio register 121 is used to input the internal clock signal clki, the second control end of the frequency division ratio register 121 is used to input the frequency division cycle start signal zero, the output end of the frequency division ratio register 121 is connected to the first input end of the second subtractor SUB2, and the frequency division ratio register 121 is used to store the frequency division ratio ndiv within the frequency division cycle; the input end of the duty cycle register 122 is used to input the duty cycle nedge, the first control end of the duty cycle register 122 is used to input the internal clock signal clki, the second control end of the duty cycle register 122 is used to input the frequency division cycle start signal zero, the output end of the duty cycle register 122 is connected to the input end of the divider DIV and the input end of the second judgment unit P2, and the duty cycle register 122 is used to store the duty cycle nedge within the frequency division cycle.

[0050] Specifically, when the frequency division cycle start signal zero is input, the next frequency division cycle begins. At this time, the frequency division ratio register 121 can update the frequency division ratio ndiv and latch the frequency division ratio ndiv during the frequency division cycle, so that other structures in the target clock clearing circuit can form corresponding control signals according to the frequency division ratio ndiv. Similarly, the duty cycle register 122 can update the duty cycle nedge at the beginning of the next frequency division cycle and latch the duty cycle nedge during the frequency division cycle, so that other structures in the target clock clearing circuit can form corresponding control signals according to the duty cycle nedge. In this way, the required target clock signal clko can be output, and at the same time, the frequency division ratio ndiv and the duty cycle nedge can be avoided from being modified during the frequency division cycle, and the changes in the frequency division ratio ndiv and / or the duty cycle nedge during the frequency division cycle can be avoided from causing abnormal clock signals.

[0051] Continue to refer Figure 7The frequency division ratio register 121 includes a fourth selector CH4 and a third register DR3; the second input terminal of the fourth selector CH4 is used to input the frequency division ratio ndiv, the control terminal of the fourth selector CH4 is used to input the frequency division cycle start signal zero, the output terminal of the fourth selector CH4 is connected to the input terminal of the third register DR3, the enable terminal EN3 of the third register DR3 is used to input the internal clock signal clki, and the output terminal of the third register DR3 is connected to the first input terminal of the fourth selector CH4 and the first input terminal of the second subtractor SUB2; the fourth selector CH4 is used to select the second input terminal and the output terminal of the fourth selector CH4 according to the frequency division cycle start signal zero, and the third register DR3 is used to store the frequency division ratio ndiv according to the rising edge of the internal clock signal clki within the frequency division cycle; the duty cycle register The register 122 includes a fifth selector CH5 and a fourth register DR4; the second input terminal of the fifth selector CH5 is used to input the duty cycle negde, the control terminal of the fifth selector CH5 is used to input the frequency division cycle start signal zero, the output terminal of the fifth selector CH5 is connected to the input terminal of the fourth register DR4, the enable terminal EN4 of the fourth register DR4 is used to input the internal clock signal clki, and the output terminal of the fourth register DR4 is connected to the first input terminal of the fifth selector CH5, the input terminal of the divider DIV and the input terminal of the second judgment unit P2; the fifth selector CH5 is used to select the second input terminal and the output terminal of the fifth selector CH5 according to the frequency division cycle start signal zero, and the fourth register DR4 is used to store the duty cycle negde according to the rising edge of the internal clock signal clki within the frequency division cycle.

[0052] Specifically, when the frequency division cycle start signal zero is input, the next frequency division cycle begins, the fourth selector CH4 selects the second input terminal and the output terminal, the fourth selector CH4 outputs the current frequency division ratio ndiv to the third register DR3, and the third register DR3 stores the frequency division ratio ndiv according to the rising edge of the internal clock signal clki. At the same time, the fifth selector CH5 selects the second input terminal and the output terminal, the fifth selector CH5 outputs the current duty cycle negde to the fourth register DR4, and the fourth register DR4 stores the duty cycle negde according to the rising edge of the internal clock signal clki. During the frequency division cycle, the fourth selector CH4 selects the first input terminal and the output terminal, the first input terminal of the fourth selector CH4 inputs the frequency division ratio ndiv output by the third register DR3, and at this time, the fourth selector CH4 still outputs the current frequency division ratio ndiv to the third register DR3, so as to realize the latching of the frequency division ratio ndiv. Similarly, the fifth selector CH5 selects the first input terminal and the output terminal, and the first input terminal of the fifth selector CH5 inputs the duty cycle negde output by the fourth register DR4. At this time, the fifth selector CH5 still outputs the current duty cycle negde to the fourth register DR4 to achieve latching of the duty cycle negde.

[0053] Figure 8 Schematic diagram of a logic control circuit provided by an embodiment of the present invention. Figure 8As shown, the logic control circuit includes a reset unit 131, a rising edge logic control unit 132, a falling edge logic control unit 133 and an OR logic unit 134; the enable end of the reset unit 131 is used to input the inverted signal clkin of the internal clock signal, the input end of the reset unit 131 is used to input the reset signal rst, the second count value cnt2, the frequency division ratio ndiv and the second odd control signal nedgeeq1, the reset unit 131 is used to output the reset control signal clkrstn according to the rising edge of the inverted signal clkin of the internal clock signal and the reset signal rst when the duty cycle nedge is equal to 1; the rising edge logic The control end of the control unit 132 is connected to the output end of the reset unit 131, the enable end of the rising edge logic control unit 132 is used to input the internal clock signal clki, the input end of the rising edge logic control unit 132 is used to input the first count value cnt1, the frequency division cycle start signal zero, the frequency division ratio ndiv and the even control signal clkpos, the rising edge logic control unit 132 is used to output logic 1 according to the internal clock signal clki and the frequency division cycle start signal zero when the frequency division ratio ndiv is not equal to 0, and output logic 0 when the first count value cnt1 is equal to the even control signal clkpos, and is also used to output logic 0 according to the reset control The control signal clkrstn resets the internal clock signal clki; the enable end of the falling edge logic control unit 133 is used to input the inverted signal clkin of the internal clock signal, and the input end of the falling edge logic control unit 133 is used to input the second count value cnt2, the frequency division ratio ndiv, the duty cycle nedge, the first odd control signal clkneg and the second odd control signal nedgeeq1. The falling edge logic control unit 133 is used to control the inverted signal clkrstn according to the internal clock signal when the duty cycle nedge is odd and not equal to 1, the frequency division ratio ndiv is not equal to 0, and the second count value cnt2 is equal to the frequency division ratio ndiv. The signal clkin outputs logic 1, and outputs logic 0 when the second count value cnt2 is equal to the first odd control signal clkneg and the duty cycle nedge is an odd number; the output end of the rising edge logic control unit 132 is connected to the first input end of the OR logic unit 134, the output end of the falling edge logic control unit 133 is connected to the second input end of the OR logic unit 134, and the output end of the OR logic unit 134 serves as the output end of the clock frequency division circuit; the OR logic unit 134 is used to perform an OR logic operation on the logic value output by the rising edge logic control unit 132 and the logic value output by the falling edge logic control unit 133 to form a target clock signal clko.

[0054] Specifically, when the frequency division cycle start signal zero is input, the next frequency division cycle starts. If the frequency division ratio ndiv is not equal to 0, the rising edge logic control unit 132 can output logic 1 according to the rising edge of the internal clock signal clki, so that the or logic unit 134 outputs logic 1, that is, the logic control circuit can output a high-level clock signal in the high-level half cycle of the internal clock signal. When the first count value cnt1 is reduced by one to the even control signal clkpos, the rising edge logic control unit 132 can output logic 0 according to the rising edge of the internal clock signal clki, and the falling edge logic control unit 133 outputs logic 0 when the duty cycle nedge is an even number, so that the or logic unit 134 outputs logic 0, that is, the logic control circuit outputs a low-level clock signal in the high-level half cycle of the internal clock signal clki. When the duty cycle nedge is equal to 1, the reset unit 131 can output the reset control signal clkrstn to the rising edge logic control unit 132 according to the reset signal rst when the second count value cnt2 is equal to the division ratio ndiv, so that the rising edge logic control unit 132 outputs logic 0, and at the same time, the falling edge logic control unit 133 outputs logic 0 when the duty cycle nedge is 1, so that the or logic unit 134 outputs logic 0, that is, the logic control circuit resets the internal clock signal at the falling edge of an internal clock signal within the division period, so that the high-level clock signal of the target clock signal clko has only a high-level half-cycle clock signal of the internal clock signal, so that the duty cycle nedge of the target clock signal clko can be achieved to be 1. When the division ratio ndiv is not equal to 0 and the duty cycle nedge is an odd number greater than 1, the falling edge logic control unit 133 outputs logic 1 according to the falling edge of the internal clock signal clki when the second count value cnt2 is equal to the division ratio ndiv, so that the OR logic unit 134 outputs logic 1, that is, the logic control circuit starts to output a high-level clock signal at the falling edge of the first internal clock signal within the division period, so that the logic control circuit can output a high-level clock signal in the low-level half cycle of the internal clock signal, so that the duty cycle of the target clock signal clko can be arbitrarily adjusted according to the half cycle of the internal clock signal. When the second count value cnt2 is reduced by one to the first odd control signal clkneg, the falling edge logic control unit 133 can output logic 0 according to the falling edge of the internal clock signal clki, and at the same time, the rising edge logic control unit 132 outputs logic 0 when the duty cycle nedge is an odd number, so that the OR logic unit 134 outputs logic 0, that is, the logic control circuit outputs a low-level clock signal in the low-level half-cycle of the internal clock signal clki, so that the falling edge logic control unit 133 can control the low-level half-cycle of the internal clock signal clki to output a corresponding number of high-level half-cycles according to the requirement of the duty cycle nedge, thereby realizing the duty cycle control of the target clock signal clko.The OR logic unit 134 may be an OR gate, which is used to implement a logical OR operation of the logic value output by the rising edge logic control unit 132 and the logic value output by the falling edge logic control unit 133 .

[0055] Continue to refer Figure 8 The reset unit 131 includes a sixth selector CH6, a fifth register DR5, a first inverter F1 and a first AND gate AND1; the control end of the sixth selector CH6 is used to input the second count value cnt2, the frequency division ratio ndiv and the second odd control signal nedgeeq1, the first input end of the sixth selector CH6 is used to input logic 0, the second input end of the sixth selector CH6 is used to input logic 1, the sixth selector CH6 is used to select the second input end and the output end of the sixth selector CH6 when the second count value cnt2 is equal to the frequency division ratio ndiv and the second odd control signal nedgeeq1 is logic 1; the output end of the sixth selector CH6 is connected to the input end of the fifth register DR5, the enable end EN5 of the fifth register DR5 is used to input the inverted signal clkin of the internal clock signal, the output end of the fifth register DR5 is connected to the input end of the first inverter F1, the output end of the first inverter F1 is connected to the first input end of the first AND gate AND1, the second input end of the first AND gate AND1 is used to input the reset signal rst, and the output end of the first AND gate AND1 serves as the output end of the reset unit 131.

[0056] Specifically, when the division ratio ndiv is equal to 1 and the second count value cnt2 is equal to the division ratio ndiv, the sixth selector CH6 selects the second input terminal and the output terminal, the sixth selector CH6 outputs logic 1 to the fifth register DR5, and the fifth register DR5 outputs logic 1 to the first inverter F1 at the falling edge of the internal clock signal clki. The first inverter F1 inverts the logic 1 to form a logic 0 and then outputs it to the first input terminal of the first AND gate AND1. At this time, the first AND gate AND1 directly outputs a reset control signal clkrstn with a logic of 0 according to the logic 0 to reset the rising edge logic control unit 132, so that the rising edge logic control unit 132 outputs logic 0. When the division ratio ndiv is not equal to 1 and / or the second count value cnt2 is not equal to the division ratio ndiv, the sixth selector CH6 selects the first input terminal and the output terminal, the sixth selector CH6 outputs logic 0 to the fifth register DR5, the fifth register DR5 outputs logic 0 to the first inverter F1 at the falling edge of the internal clock signal clki, the first inverter F1 inverts the logic 0 to form a logic 1 and then outputs it to the first input terminal of the first AND gate AND1, at this time the reset control signal clkrstn output by the first AND gate AND1 is consistent with the reset signal rst, so that the rising edge logic control unit 132 can be reset according to the reset signal rst.

[0057] Continue to refer Figure 8 The rising edge logic control unit 132 includes a seventh selector CH7, an eighth selector CH8 and a sixth register DR6; the first input end of the seventh selector CH7 is connected to the output end of the sixth register DR6 and serves as the output end of the rising edge logic control unit 132, the second input end of the seventh selector CH7 is used to input logic 0, the control end of the seventh selector CH7 is used to input the first count value cnt1 and the even control signal clkpos, the output end of the seventh selector CH7 is connected to the first input end of the eighth selector CH8, the second input end of the eighth selector CH8 is used to input logic 1, and the control end of the eighth selector CH8 is used to input The frequency division cycle start signal zero and the frequency division ratio ndiv, the output end of the eighth selector CH8 is connected to the input end of the sixth register DR6, the enable end EN6 of the sixth register DR6 is used to input the internal clock signal clki, and the control end of the sixth register DR6 is connected to the output end of the reset unit 131; the seventh selector CH7 is used to select the second input end and output end of CH7 of the seventh selector when the first count value cnt1 is equal to the even control signal clkpos, and the eighth selector CH8 is used to select the second input end and output end of the eighth selector CH8 when the frequency division ratio ndiv is not equal to 0 and has the frequency division cycle start signal zero.

[0058] Specifically, when the frequency division cycle start signal zero is input, the next frequency division cycle starts. If the frequency division ratio ndiv is not equal to 0, the eighth selector CH8 selects the second input terminal and the output terminal, and the eighth selector CH8 outputs logic 1 to the sixth register DR6. The sixth register DR6 outputs logic 1 at the rising edge of the internal clock signal clki, so that the or logic unit 134 outputs logic 1, that is, the logic control circuit can output a high-level clock signal in the high-level half cycle of the internal clock signal. Then the eighth selector CH8 selects the first input terminal and the output terminal. Before the first count value cnt1 is reduced by one to the even control signal clkpos, the seventh selector CH7 selects the first input terminal and the output terminal, and the seventh selector CH7 outputs the logic 1 output by the sixth register DR6, so that the eighth selector CH8 continuously outputs logic 1, realizes the latching of logic 1, and enables the logic control circuit to output the number of high-level clock signals required by the frequency division ratio ndiv in the high-level half cycle of the internal clock signal. Then the first count value cnt1 is reduced by one to the even control signal clkpos, at which time the seventh selector CH7 selects the second input terminal and the output terminal, the seventh selector CH7 outputs logic 0 to the first input terminal of the eighth selector CH8, the eighth selector CH8 outputs logic 0 to the sixth register DR6, and the sixth register DR6 outputs logic 0 at the rising edge of the internal clock signal clki. At the same time, the falling edge logic control unit 133 outputs logic 0 when the duty cycle nedge is an even number, so that the OR logic unit 134 outputs logic 0, that is, the logic control circuit outputs a low-level clock signal in the high-level half cycle of the internal clock signal clki, so that the logic control circuit outputs the required number of high-level clock signals in the high-level half cycle.

[0059] Continue to refer Figure 8The falling edge logic control unit 133 includes a ninth selector CH9, a tenth selector CH10 and a seventh register DR7; the first input end of the ninth selector CH9 is connected to the output end of the seventh register DR7 and serves as the output end of the falling edge logic control unit 133, the second input end of the ninth selector CH9 is used to input logic 0, the control end of the ninth selector CH9 is used to input the second count value cnt2, the duty cycle nedge and the first odd control signal clkneg, the output end of the ninth selector CH9 is connected to the first input end of the tenth selector CH10, the second input end of the tenth selector CH10 is used to input logic 1, and the control end of the tenth selector CH10 is used to input logic 1. When the second count value cnt2, the division ratio ndiv, the duty cycle nedge and the second odd control signal nedgeeq1 are input, the output end of the tenth selector CH10 is connected to the input end of the seventh register DR7, and the enable end EN7 of the seventh register DR7 is used to input the inverted signal clkin of the internal clock signal; the ninth selector CH9 is used to output logic 0 when the second count value cnt2 is equal to the first odd control signal clkneg and the duty cycle nedge is odd, and the tenth selector CH10 is used to output logic 1 when the second count value cnt2 is equal to the division ratio ndiv, the division ratio ndiv is not equal to 0, and the duty cycle nedge is odd and not equal to 1.

[0060] Specifically, when the frequency division ratio ndiv is not equal to 0 and the duty cycle nedge is an odd number and not equal to 1, the logic control circuit needs to control at least one internal clock signal to output a high-level clock signal in the low-level half cycle. At this time, the second count value cnt2 can be equal to the frequency division ratio ndiv, that is, at the falling edge of the first internal clock signal in the frequency division period, the tenth selector CH10 can be controlled to select the second input terminal and the output terminal, and the tenth selector CH10 outputs logic 1 to the seventh register DR7. The seventh register DR7 outputs logic 1 at the falling edge of the internal clock signal clki, so that the OR logic unit 134 outputs logic 1, that is, the logic control circuit can output a high-level clock signal in the low-level half cycle of the internal clock signal. Then the tenth selector CH10 selects the first input terminal and the output terminal. Before the second count value cnt2 is reduced by one to the first odd control signal clkneg, the ninth selector CH9 selects the first input terminal and the output terminal, and the ninth selector CH9 outputs the logic 1 output by the seventh register DR7, so that the tenth selector CH10 continuously outputs the logic 1, and the latching of the logic 1 is realized, so that the logic control circuit can output the number of high-level clock signals required by the frequency division ratio ndiv in the low-level half cycle of the internal clock signal. Then the second count value cnt2 is reduced by one to the first odd control signal clkneg, at which time the ninth selector CH9 selects the second input terminal and the output terminal, and the ninth selector CH9 outputs the logic 0 to the first input terminal of the tenth selector CH10, and the tenth selector CH10 outputs the logic 0 to the seventh register DR7, and the seventh register DR7 outputs the logic 0 at the falling edge of the internal clock signal clki. At the same time, the rising edge logic control unit 132 outputs logic 0 when the duty cycle nedge is an odd number, so that the OR logic unit 134 outputs logic 0, that is, the logic control circuit outputs a low-level clock signal in the low-level half cycle of the internal clock signal clki, so that the logic control circuit outputs the required number of high-level clock signals in the low-level half cycle.

[0061] The clock frequency division circuit provided in the embodiment of the present invention further includes an internal clock signal generating circuit. Fig. 9 Schematic diagram of the structure of an internal clock signal generating circuit provided by an embodiment of the present invention. Fig. 9As shown, the internal clock signal generating circuit includes an eleventh selector CH11, a twelfth selector CH12, an eighth register DR8, an enable output unit CG and a second inverter F2; the first input end of the eleventh selector CH11 and the first input end of the twelfth selector CH12 are connected to the output end of the eighth register DR8, the second input end of the eleventh selector CH11 and the second input end of the twelfth selector CH12 are used to input a frequency division enable signal diven, the control end of the eleventh selector CH11 and the control end of the twelfth selector CH12 are used to input a frequency division cycle start signal zero, the output end of the eleventh selector CH11 is connected to the eighth register DR8 The enable terminal EN8 of the eighth register DR8 and the input terminal of the enable output unit CG are used to input the initial clock signal clk, the output terminal of the twelfth selector CH12 is connected to the enable terminal of the enable output unit CG, the output terminal of the enable output unit CG is connected to the input terminal of the second inverter F2, the eleventh selector CH11 and the twelfth selector CH12 are used to select the second input terminal and the output terminal when the division cycle start signal zero is valid, the enable output unit CG is used to output the initial clock signal clk as the internal clock signal clki according to the division ratio ndiv, and the output terminal of the second inverter F2 is used to output the inverted signal clkin of the internal clock signal.

[0062] Specifically, the internal clock signal generating circuit can generate an internal clock signal clki and an inverted signal clkin of the internal clock signal according to the initial clock signal clk. Specifically, the frequency division enable signal diven is used to control the state of the clock frequency division circuit. When the frequency division enable signal diven is logic 1, the clock frequency division circuit is in an enabled state and can output the target clock signal clko according to the frequency division ratio ndiv and the duty cycle nedge. When the frequency division enable signal diven is logic 0, the clock frequency division circuit is in a non-operating state. When the frequency division cycle start signal zero is input, the next frequency division cycle begins. The eleventh selector CH11 and the twelfth selector CH12 both select the second input terminal and the output terminal, and the eleventh selector CH11 outputs the frequency division enable signal diven. When the frequency division enable signal diven is logic 1, the eighth register DR8 can output logic 1 to the first input terminal of the eleventh selector CH11 and the first input terminal of the twelfth selector CH12 at the rising edge of the initial clock signal clk. At this time, the twelfth selector CH12 outputs the frequency division enable signal diven, and the enable output unit CG outputs the initial clock signal clk as the internal clock signal clki according to the frequency division enable signal diven. At the same time, the second inverter F2 inverts the internal clock signal clki to form the inverted signal clkin of the internal clock signal. During the frequency division period, the eleventh selector CH11 and the twelfth selector CH12 both select the first input terminal and the output terminal, and the eleventh selector CH11 and the twelfth selector CH12 both output the logic 1 output by the eighth register DR8 to achieve the latching of the logic 1, so that the enable output unit CG continues to output the internal clock signal clki during the frequency division period, and the second inverter F2 continues to output the inverted signal clkin of the internal clock signal. When the frequency division enable signal diven is logic 0, the eighth register DR8 can output logic 0 to the first input terminal of the eleventh selector CH11 and the first input terminal of the twelfth selector CH12 at the rising edge of the initial clock signal clk. At this time, the twelfth selector CH12 outputs the division enable signal diven, and the enable output unit CG cannot output the initial clock signal clk according to the division enable signal diven. At the same time, the second inverter F2 cannot output the inverted signal clkin of the internal clock signal, so that the clock division circuit cannot work normally.

[0063] When the frequency division enable signal diven is updated, the next frequency division cycle starts when the frequency division cycle start signal zero is input. The eleventh selector CH11 and the twelfth selector CH12 both select the second input terminal and the output terminal, and can synchronously update the frequency division enable signal diven, so that the clock frequency division circuit can work under the updated frequency division enable signal diven.

[0064] In some embodiments, the clock frequency dividing circuit may further include an auxiliary logic circuit. Fig.10 A schematic diagram of the structure of an auxiliary logic circuit provided by an embodiment of the present invention. Fig.10 As shown, the auxiliary logic circuit includes a second AND gate AND2, a third AND gate AND3, a third inverter F3 and a ninth register DR9. The first input end of the second AND gate AND2 and the input end of the third inverter F3 are used to input the frequency division enable signal diven, the second input end of the second AND gate AND2 and the second input end of the third AND gate AND3 are used to input the frequency division cycle start signal zero, the output end of the third inverter F3 is connected to the first input end of the third AND gate AND3, the output end of the third AND gate AND3 is connected to the input end of the ninth register DR9, and the enable end EN9 of the ninth register DR9 is used to input the internal clock signal clki. The output end of the second AND gate AND2 is used to output the clock cycle signal sync, which is used to output logic 1 when the frequency division cycle start signal zero is equal to 1 and the frequency division enable signal diven is equal to 1, and can be used for synchronization of the clock domain of the internal clock signal clki. The output end of the ninth register DR9 is used to output the stop signal stop, which is used to characterize the working state of the clock frequency division circuit. When the frequency division enable signal diven is 0 and the frequency division cycle start signal zero is equal to 1, the stop signal stop is set, indicating that the clock frequency division circuit is in a stopped state.

[0065] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A clock frequency division circuit, characterized in that: including a counter logic circuit, a target clock clearing circuit and a logic control circuit; The input end of the counter logic circuit is used to input the internal clock signal and the frequency division ratio of the target clock signal, and the input end of the target clock clearing circuit is used to input the internal clock signal, the frequency division ratio and the duty cycle of the target clock signal; The input end of the logic control circuit is connected to the output end of the counter logic circuit and the output end of the target clock clearing circuit; the counter logic circuit is used to count the frequency division ratio by one according to the rising edge of the internal clock signal to determine a first count value; to count the frequency division ratio by one according to the falling edge of the internal clock signal to determine a second count value, and to output a frequency division cycle start signal when the first count value is equal to 0; the target clock clearing circuit is used to perform a logical operation on the frequency division ratio and the duty cycle according to the rising edge of the internal clock signal within the frequency division cycle to form a control signal of the duty cycle within the frequency division cycle; The logic control circuit is used to form the target clock signal according to the frequency division ratio, the first count value, the second count value and the control signal; the frequency division period is the period of the target clock signal; The counter logic circuit includes a first register, a second register, a first subtractor, a first selector, a first judgment unit and a second selector; The enable terminal of the first register is used to input the internal clock signal, and the enable terminal of the second register is used to input the inverted signal of the internal clock signal; the input terminal of the first register is connected to the output terminal of the first selector, the output terminal of the first register is connected to the input terminal of the second register, the input terminal of the first subtractor and the input terminal of the first judgment unit, the output terminal of the first subtractor is connected to the first input terminal of the first selector, the second input terminal of the first selector is used to input the frequency division ratio, the control terminal of the first selector is connected to the output terminal of the second selector, the output terminal of the first judgment unit is connected to the control terminal of the second selector, the first input terminal of the second selector is used to input logic 0, and the second input terminal of the second selector is used to input logic 1; The first register is used to determine the first count value according to the rising edge of the internal clock signal; The second register is used to store the first count value as the second count value according to the falling edge of the internal clock signal; the first subtractor is used to subtract one from the first count value, the first judgment unit is used to judge whether the first count value is 0, and control the second selector to select the second input terminal and output terminal of the second selector when the first count value is 0, so as to output the logic 1 as the division cycle start signal; the first selector is used to select the second input terminal and output terminal of the first selector according to the division cycle start signal.

2. The clock frequency division circuit according to claim 1, characterized in that: The target clock clearing circuit includes a divider, a second subtractor, a first adder, a second judgment unit and a third selector; The input end of the divider and the input end of the second judgment unit are used to input the duty cycle, the output end of the divider is connected to the second input end of the second subtractor, the first input end of the second subtractor is used to input the frequency division ratio, the output end of the second subtractor is connected to the first input end of the first adder, and the second input end of the first adder is used to input logic 1; the first input end of the third selector is used to input logic 0, and the second input end of the third selector is used to input the logic 1; The divider is used to right-shift the value of the duty cycle to form a first value, the second subtractor is used to subtract the frequency division ratio and the first value to form a first odd control signal of the duty cycle, the first adder is used to add 1 to the first odd control signal to form an even control signal of the duty cycle, and the second judgment unit is used to control the third selector to output the logic 1 as the second odd control signal of the duty cycle when the duty cycle is 1.

3. The clock frequency division circuit according to claim 2, characterized in that: The target clock clearing circuit also includes a frequency division ratio register and a duty cycle register; The input end of the frequency division ratio register is used to input the frequency division ratio, the first control end of the frequency division ratio register is used to input the internal clock signal, the second control end of the frequency division ratio register is used to input the frequency division period start signal, the output end of the frequency division ratio register is connected to the first input end of the second subtractor, and the frequency division ratio register is used to store the frequency division ratio within the frequency division period; The input end of the duty cycle register is used to input the duty cycle, the first control end of the duty cycle register is used to input the internal clock signal, the second control end of the duty cycle register is used to input the frequency division period start signal, the output end of the duty cycle register is connected to the input end of the divider and the input end of the second judgment unit, and the duty cycle register is used to store the duty cycle within the frequency division period.

4. The clock frequency division circuit according to claim 3, characterized in that: The frequency division ratio register comprises a fourth selector and a third register; the second input end of the fourth selector is used to input the frequency division ratio, the control end of the fourth selector is used to input the frequency division period start signal, the output end of the fourth selector is connected to the input end of the third register, the enable end of the third register is used to input the internal clock signal, and the output end of the third register is connected to the first input end of the fourth selector and the first input end of the second subtractor; the fourth selector is used to select the second input end and the output end of the fourth selector according to the frequency division period start signal, and the third register is used to store the frequency division ratio according to the rising edge of the internal clock signal within the frequency division period; The duty cycle register includes a fifth selector and a fourth register; the second input end of the fifth selector is used to input the duty cycle, the control end of the fifth selector is used to input the frequency division cycle start signal, the output end of the fifth selector is connected to the input end of the fourth register, the enable end of the fourth register is used to input the internal clock signal, and the output end of the fourth register is connected to the first input end of the fifth selector, the input end of the divider and the input end of the second judgment unit; The fifth selector is used to select the second input terminal and the output terminal of the fifth selector according to the frequency division cycle start signal, and the fourth register is used to store the duty cycle according to the rising edge of the internal clock signal within the frequency division cycle.

5. The clock frequency division circuit according to any one of claims 2 to 4, characterized in that: The logic control circuit includes a reset unit, a rising edge logic control unit, a falling edge logic control unit and an OR logic unit; The enable terminal of the reset unit is used to input the inverted signal of the internal clock signal, the input terminal of the reset unit is used to input the reset signal, the second count value, the frequency division ratio and the second odd control signal, and the reset unit is used to output a reset control signal according to the rising edge of the inverted signal of the internal clock signal and the reset signal when the duty cycle is equal to 1; The control end of the rising edge logic control unit is connected to the output end of the reset unit, the enable end of the rising edge logic control unit is used to input the internal clock signal, the input end of the rising edge logic control unit is used to input the first count value, the frequency division cycle start signal, the frequency division ratio and the even control signal, the rising edge logic control unit is used to output the logic 1 according to the internal clock signal and the frequency division cycle start signal when the frequency division ratio is not equal to 0, and output the logic 0 when the first count value is equal to the even control signal, and is also used to reset the internal clock signal according to the reset control signal; The enable terminal of the falling edge logic control unit is used to input the inverted signal of the internal clock signal, the input terminal of the falling edge logic control unit is used to input the second count value, the frequency division ratio, the duty cycle, the first odd control signal and the second odd control signal, the falling edge logic control unit is used to output the logic 1 according to the inverted signal of the internal clock signal when the duty cycle is odd and not equal to 1, the frequency division ratio is not equal to 0, and the second count value is equal to the frequency division ratio, and output the logic 0 when the second count value is equal to the first odd control signal and the duty cycle is odd; The output end of the rising edge logic control unit is connected to the first input end of the OR logic unit, the output end of the falling edge logic control unit is connected to the second input end of the OR logic unit, and the output end of the OR logic unit serves as the output end of the clock frequency division circuit; the OR logic unit is used to perform an OR logic operation on the logic value output by the rising edge logic control unit and the logic value output by the falling edge logic control unit to form the target clock signal.

6. The clock frequency division circuit according to claim 5, characterized in that: The reset unit includes a sixth selector, a fifth register, a first inverter and a first AND gate; The control end of the sixth selector is used to input the second count value, the division ratio and the second odd control signal, the first input end of the sixth selector is used to input the logic 0, the second input end of the sixth selector is used to input the logic 1, and the sixth selector is used to select the second input end and the output end of the sixth selector when the second count value is equal to the division ratio and the second odd control signal is logic 1; the output end of the sixth selector is connected to the input end of the fifth register, the enable end of the fifth register is used to input the inverted signal of the internal clock signal, the output end of the fifth register is connected to the input end of the first inverter, the output end of the first inverter is connected to the first input end of the first AND gate, the second input end of the first AND gate is used to input the reset signal, and the output end of the first AND gate serves as the output end of the reset unit.

7. The clock frequency division circuit according to claim 5, characterized in that: The rising edge logic control unit includes a seventh selector, an eighth selector and a sixth register; The first input end of the seventh selector is connected to the output end of the sixth register and serves as the output end of the rising edge logic control unit, the second input end of the seventh selector is used to input the logic 0, the control end of the seventh selector is used to input the first count value and the even control signal, the output end of the seventh selector is connected to the first input end of the eighth selector, the second input end of the eighth selector is used to input the logic 1, the control end of the eighth selector is used to input the frequency division cycle start signal and the frequency division ratio, the output end of the eighth selector is connected to the input end of the sixth register, the enable end of the sixth register is used to input the internal clock signal, and the control end of the sixth register is connected to the output end of the reset unit; the seventh selector is used to select the second input end and output end of the seventh selector when the first count value is equal to the even control signal, and the eighth selector is used to select the second input end and output end of the eighth selector when the frequency division ratio is not equal to 0 and has the frequency division cycle start signal.

8. The clock frequency division circuit according to claim 5, characterized in that: The falling edge logic control unit includes a ninth selector, a tenth selector and a seventh register; The first input end of the ninth selector is connected to the output end of the seventh register and serves as the output end of the falling edge logic control unit, the second input end of the ninth selector is used to input the logic 0, the control end of the ninth selector is used to input the second count value, the duty cycle and the first odd control signal, the output end of the ninth selector is connected to the first input end of the tenth selector, the second input end of the tenth selector is used to input the logic 1, the control end of the tenth selector is used to input the second count value, the frequency division ratio, the duty cycle and the second odd control signal, the output end of the tenth selector is connected to the input end of the seventh register, and the enable end of the seventh register is used to input the inverted signal of the internal clock signal; The ninth selector is used to output the logic 0 when the second count value is equal to the first odd control signal and the duty cycle is an odd number, and the tenth selector is used to output the logic 1 when the second count value is equal to the division ratio, the division ratio is not equal to 0, and the duty cycle is an odd number and not equal to 1.

9. The clock frequency division circuit according to claim 1, characterized in that: It also includes an internal clock signal generating circuit; the internal clock signal generating circuit includes an eleventh selector, a twelfth selector, an eighth register, an enable output unit and a second inverter; The first input end of the eleventh selector and the first input end of the twelfth selector are connected to the output end of the eighth register, the second input end of the eleventh selector and the second input end of the twelfth selector are used to input the frequency division enable signal, the control end of the eleventh selector and the control end of the twelfth selector are used to input the frequency division cycle start signal, the output end of the eleventh selector is connected to the input end of the eighth register, the enable end of the eighth register and the input end of the enable output unit are used to input the initial clock signal, the output end of the twelfth selector is connected to the enable end of the enable output unit, the output end of the enable output unit is connected to the input end of the second inverter, the eleventh selector and the twelfth selector are used to select the second input end and the output end when the frequency division cycle start signal is valid, the enable output unit is used to output the initial clock signal as the internal clock signal according to the frequency division ratio, and the output end of the second inverter is used to output the inverted signal of the internal clock signal.

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