Gate drive circuit and power conversion device

Abstract

In this gate drive circuit, first and second gate drive ICs each have: an INA terminal and an INB terminal to which PWM signals are input; a gate output terminal for outputting a gate drive signal; and an OSFB terminal for outputting a feedback signal of the gate drive signal. The first and second gate drive ICs are configured so as to output the gate drive signal of an ON state when inputs to the INA terminal and the INB terminal are ON and OFF, respectively. In the first gate drive IC, the INA terminal and the INB terminal receive a first PWM signal and a second PWM signal, respectively. In the second gate drive IC, the INA terminal and the INB terminal receive the second PWM signal and the first PWM signal, respectively. A first diode has the cathode side that is connected to the INB terminal of the second gate drive IC and the anode side that is connected to the OSFB terminal of the first gate drive IC. A second diode has the cathode side that is connected to the INB terminal of the first gate drive IC and the anode side that is connected to the OSFB terminal of the second gate drive IC.

Description

[Technical Field]

[0001] The present invention relates to a gate drive circuit and a power conversion device. [Background technology]

[0002] Typically, an inverter that drives a three-phase AC motor is equipped with six switching elements for the three-phase upper and lower arms, and there are also gate driver circuits for each of the six arms to drive each switching element. The three-phase AC current that drives the motor is generated by controlling the ON / OFF of the upper and lower arm switching elements using gate drive signals from the gate driver circuit. In this process, a dead time is provided in which the upper and lower arm switching elements are turned OFF to prevent upper and lower short circuits, such as when the upper and lower arms are turned ON simultaneously or when one arm is turned ON while the gate of the other arm is in the OFF transition. Generally, there are two known methods for ensuring dead time: using software and using hardware. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent No. 4442348 Summary of the Invention [Problem to be solved by the invention]

[0004] However, when dead time is secured by software, there are cases where the dead time is temporarily lost due to software malfunctions, etc. Also, securing dead time by hardware requires a large-scale circuit, which is disadvantageous in terms of cost and implementation area compared to software-based methods. Furthermore, there is also the issue that optimization is difficult because the OFF transition time changes depending on the amount of current flowing through the switching element. [Means for solving the problem]

[0005] A gate drive circuit according to an aspect of the present invention includes a first gate drive IC that drives the gate of a first switching element of an upper arm, a second gate drive IC that drives the gate of a second switching element of a lower arm that is connected in series to the first switching element, first, second, third and fourth resistor elements, and first and second diodes, wherein each of the first and second gate drive ICs has an INA terminal and an INB terminal to which a PWM signal is input, a gate output terminal that outputs a gate drive signal, and an OSFB terminal that outputs a feedback signal of the gate drive signal, and is configured to output an ON state gate drive signal when the PWM signal of the INA terminal is ON and the PWM signal of the INB terminal is OFF, and the first gate drive IC outputs the PWM signal A first PWM signal for the first switching element is input to the INA terminal via the first resistor element, and a second PWM signal for the second switching element is input to the INB terminal via the second resistor element. In the second gate drive IC, the second PWM signal is input to the INA terminal via the third resistor element, and the first PWM signal is input to the INB terminal via the fourth resistor element. The first diode has a cathode connected to the INB terminal of the second gate drive IC and an anode connected to the OSFB terminal of the first gate drive IC. The second diode has a cathode connected to the INB terminal of the first gate drive IC and an anode connected to the OSFB terminal of the second gate drive IC. [Effects of the Invention]

[0006] According to the present invention, it is possible to prevent short circuits between the upper and lower electrodes due to insufficient dead time. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram illustrating an example of a gate drive circuit according to an embodiment. [Figure 2] FIG. 2 is a diagram showing logic symbols and logic tables for gate driving. [Figure 3] FIG. 3 is a diagram showing an example of a timing chart from the gate of the upper arm being turned OFF to the gate of the lower arm being turned ON in a conventional case. [Figure 4] FIG. 4 is a timing chart showing a case where the dead time DT is set shorter than Ton+Toff. [Figure 5] FIG. 5 is a timing chart according to this embodiment. [Figure 6] FIG. 6 is a diagram illustrating the synchronous rectification control. [Figure 7] FIG. 7 is a timing chart for when synchronous rectification control is performed. [Figure 8] FIG. 8 is a diagram illustrating the change in the fall time of the gate voltage depending on the magnitude of the current flowing through the switching element. [Figure 9] FIG. 9 is a diagram showing the first modification. [Figure 10] FIG. 10 is a diagram showing a second modification. [Figure 11] FIG. 11 is a diagram illustrating the voltage of the INB terminal during pull-down control. [Figure 12] FIG. 12 is a diagram illustrating the voltage of the INA terminal during pull-down control. [Figure 13] FIG. 13 is a diagram illustrating an example of a power conversion device that supplies a three-phase alternating current. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, an embodiment of a semiconductor device according to the present invention will be described with reference to the drawings. The following description and drawings are examples for explaining the present invention, and appropriate omissions and simplifications have been made for clarity of explanation. Furthermore, in the following description, identical or similar elements and processes are given the same reference numerals, and duplicate explanations may be omitted. Note that the content described below merely shows an example of an embodiment of the present invention, and the present invention is not limited to the following embodiment, and can be implemented in various other forms.

[0009] Fig. 1 is a diagram showing an example of a gate drive circuit 1 according to the present embodiment. For example, as shown in Fig. 13, a power conversion device 200 that supplies three-phase AC current to a three-phase AC motor M includes an inverter 201 having six switching elements S1 to S6 that constitute upper and lower phase arms. Fig. 1 shows a gate drive circuit for switching elements S1 and S2 that constitute the upper and lower arms for one phase of the inverter 201 shown in Fig. 13.

[0010] The power conversion device 200 includes an inverter 201, a control circuit 202, and a gate drive circuit 203. The control circuit 202 includes a CPU and generates a PWM signal for supplying three-phase AC current based on the magnetic pole position of the rotor of the motor M detected by a magnetic pole position sensor 301 and the motor current value detected by a current sensor 302. The PWM signal generated by the control circuit 202 is input to a gate drive circuit 203 provided with gate drive ICs. The gate drive circuit 203 is provided with six gate drive ICs corresponding to the six switching elements S1 to S6. The gate drive circuit 203 generates gate drive signals for driving each of the switching elements S1 to S6 of the inverter 201 based on the PWM signal and outputs the gate drive signals to each of the switching elements S1 to S6. As a result, DC power from the high-voltage battery 300 is converted into AC power and supplied to the motor M.

[0011] FIG. 1 illustrates switching elements S1 and S2 constituting the upper and lower arms of one phase, and the portion of the gate drive circuit 203 in FIG. 13 corresponding to the switching elements S1 and S2 is illustrated as a gate drive circuit 1. This gate drive circuit 1 includes two gate drive ICs 10A and 10B. The gate of switching element S1 is driven by gate drive IC 10A, and the gate of switching element S2 is driven by gate drive IC 10B. Power semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) using SiC, GaN, or the like are used for the switching elements S1 and S2. Freewheeling diodes D1 and D2 are connected in parallel to each switching element S1 and S2 in the direction opposite to the current flow direction when the element is switched on. MOSFETs have a body diode (parasitic diode) inside the element, and the body diode is used as the freewheeling diodes D1 and D2.

[0012] The gate driver ICs 10A and 10B are equipped with an insulated communication circuit between the low-voltage circuit and the high-voltage circuit. The upper-arm gate driver IC 10A controls the gate of the high-voltage side switching element S1 in response to an upper-arm PWM signal (PWM-H signal) input from the low-voltage side CPU. The lower-arm gate driver IC 10B controls the gate of the low-voltage side switching element S2 in response to a lower-arm PWM signal (PWM-L signal) input from the CPU.

[0013] Gate driver ICs 10A and 10B have the same configuration and are equipped with two types of PWM signal input terminals. One is the INA terminal 101, which sets the gate voltage to High in response to a High PWM signal and turns the gate ON. The other is the INB terminal, which turns the gate ON in response to a Low PWM signal. The input PWM signal, gate drive logic symbols, and logic table are shown in Figure 2.

[0014] The gate driver ICs 10A and 10B have output terminals such as a gate output terminal (GATE terminal) 103 and a gate monitor terminal (MON terminal) 104. The gate output terminal 103 is an output terminal for a gate drive signal that controls the gate voltage, and can be a single terminal, but is usually configured with two or more terminals to change the ON and OFF speeds. The gate monitor terminal 104 is a terminal that monitors the gate voltage, and may also serve as the gate output terminal 103.

[0015] A CPU (not shown) outputs a PWM signal (hereinafter referred to as a PWM-H signal) that controls gate drive for the upper arm and a PWM signal (hereinafter referred to as a PWM-L signal) that controls gate drive for the lower arm, and inputs these signals to INA terminals 101 of gate drive ICs 10A, 10B in the upper and lower arms. The PWM-H signal is also input to INB terminal 102 of gate drive IC 10B in the lower arm, and the PWM-L signal is also input to INB terminal 102 of gate drive IC 10A in the upper arm. The PWM signal input to INA terminal 101 of the paired gate drive IC is input to INB terminal 102 in this way to prevent switching elements S1, S2 of the upper and lower arms from being turned ON simultaneously, causing a short circuit between the upper and lower arms.

[0016] The gate driver ICs 10A and 10B also have a gate state feedback terminal 105 (hereinafter referred to as an OSFB terminal) that outputs the gate state as feedback to the low-voltage side. The OSFB terminal 105 outputs a high signal when the gate voltage exceeds a predetermined threshold, and outputs a low signal when the gate voltage is below the predetermined threshold.

[0017] 1, in this embodiment, the output signal from the OSFB terminal 105 of the gate driver IC 10A of the upper arm is input to the INB terminal 102 of the gate driver IC 10B on the opposite arm. Similarly, the output signal from the OSFB terminal 105 of the gate driver IC 10B of the lower arm is input to the INB terminal 102 of the gate driver IC 10A on the opposite arm. This makes it possible to suppress gate drive on the opposite arm while one of the gates is turning off, preventing upper and lower short circuits and shortening dead time.

[0018] As described above, the OSFB signal output from the OSFB terminal 105 goes high when the gate voltage exceeds a predetermined threshold, and conversely, goes low when the gate voltage falls below the predetermined threshold. Therefore, the high and low levels of the PWM signal input to the INA terminal 101 and the high and low levels of the OSFB signal output from the OSFB terminal 105 are not instantaneously synchronized. Therefore, considering a situation in which the OSFB signal (hereinafter referred to as the OSFB-L signal) of the gate driver IC 10B is low and the PWM-L signal input to the INB terminal 102 of the gate driver IC 10A is high, the low level of the OSFB-L signal prevents the INB terminal 102 of the gate driver IC 10A from going high.

[0019] Therefore, in order to prevent the effect of preventing the top and bottom from being turned on simultaneously by the INB terminal 102 from being impaired, the OSFB terminal 105 of the gate driver IC 10B is connected to the INB terminal 102 of the gate driver IC 10A via a diode 20B that is arranged so that the OSFB terminal side of the gate driver IC 10B serves as the anode, as shown in Figure 1. Similarly, the OSFB terminal 105 of the gate driver IC 10A is connected to the INB terminal 102 of the gate driver IC 10B via a diode 20A that is arranged so that the OSFB terminal side of the gate driver IC 10A serves as the anode.

[0020] Also, if we consider a situation where the OSFB-H signal is High and the PWM-H signal is Low, there will be a conflict between the High and Low signals, and the INA terminal 101 of the gate driver IC 10A will not go Low. To avoid this conflict, a resistor R1 is placed on the PWM signal input line of the INA terminal 101 of each of the gate driver ICs 10A and 10B, and a resistor R2 is placed on the PWM signal input line of the INB terminal 102 of each of the gate driver ICs 10A and 10B.

[0021] FIG. 3 shows an example of a timing chart from when the gate of the upper arm is turned OFF to when the gate of the lower arm is turned ON in a conventional configuration, i.e., when the OSFB signal is not input to the INB terminal 102 of the paired arm and resistors R1 and R2 are not provided, as in this embodiment. A dead time DT is provided to prevent short circuits between the upper and lower arms. The dead time DT indicates the time during which neither the PWM-H signal nor the PWM-L signal input to the INA terminals 101 of the upper and lower arms is high. FIG. 3 shows a scene in which the PWM-H signal is switched from high to low and the PWM-L signal is switched from low to high.

[0022] When the PWM-H signal switches from high to low, the gate voltage Vg-H of the upper arm switching element S1 begins to drop. Even after the gate voltage Vg-H starts to drop, the current IH flowing through the switching element S1 is maintained for a while, and when the gate voltage Vg-H drops to a certain voltage, the current IH becomes zero. The time from when the gate voltage Vg-H starts to drop until the current IH becomes zero is called the turn-off time (Toff).

[0023] When the PWM-H signal goes low and the dead time DT has elapsed, the PWM-L signal, which is the PWM signal for the lower arm, goes high. The time from when the PWM-L signal goes high until the current IL starts to flow through the lower arm switching element S2 is called the turn-on time (Ton). Vg-L is the gate voltage of the lower arm switching element S2. Normally, the dead time DT is set so that DT > (Ton + Toff) to prevent short circuits between the upper and lower arms. The dead time DT is usually set by software on the CPU side.

[0024] FIG. 4 shows a timing chart for when the dead time DT is set shorter than Ton+Toff. FIG. 4 also shows the INA-H signal, INA-L signal, and INB-L signal. The INA-H signal and INB-L signal have the same waveform as the PWM-H signal, and the INA-L signal has the same waveform as the PWM-L signal. When the PWM-H signal switches from high to low, the INB-L signal of the lower arm also switches low. If the PWM-L signal then switches from low to high before the turn-off time Toff of the upper arm elapses, the INA-L signal of the lower arm also switches from low to high. The INA-L terminal 101 and the INB-L terminal 102 are set to (high, low), and the GATE terminal 103 of the lower arm switches to high, increasing the gate voltage Vg-L. Thus, even if the gate driver IC includes the INB terminal 102, a short circuit between the upper and lower arms occurs during the period T1 when the dead time DT is shorter than Ton+Toff.

[0025] On the other hand, the configuration shown in FIG. 1 can prevent upper and lower short circuits due to insufficient dead time. FIG. 5 is a timing chart of this embodiment when the dead time DT set by the PWM-H signal and PWM-L signal is the same as that shown in FIG. 4. FIG. 5 also shows the OSFB-H signal of the upper arm. When the PWM-H signal of the upper arm switches from high to low, the gate voltage Vg-H drops. However, the OSFB-H signal remains high as long as the gate voltage Vg-H is above a predetermined threshold. When the gate voltage Vg-H falls below the predetermined threshold, the OSFB-H signal changes from high to low.

[0026] In this embodiment, the output signal of the OSFB terminal 105 is input to the INB terminal 102 of the opposing arm, so even if the INA-H signal switches to Low and the INA-L signal switches to High, the signal input to the INB terminal 102 of the lower arm (the INB-L signal) is maintained at High. That is, while the OSFB-H signal is High, the INB-L signal is maintained at High, and gate driving of the lower arm does not start even if the INA-L signal is High. In this way, in this embodiment, a short-circuit prevention period DT1 longer than the set dead time DT is ensured, and even if the set dead time DT is insufficient, it is possible to prevent upper and lower short circuits.

[0027] When the upper arm gate voltage Vg-H falls below a predetermined threshold and the OSFB-H signal goes low, the INB-L signal also goes low, starting the gate drive operation of the lower arm. Then, the gate voltage Vg-L rises, and the lower arm switching element S2 turns on. In this way, in this embodiment, the short-circuit prevention period DT1 is created in accordance with the gate state. Therefore, even if the set dead time DT is DT=0, for example, the short-circuit prevention period DT1, which is essentially a dead time, is secured, and upper and lower short circuits can be prevented.

[0028] FIG. 6 is a diagram explaining synchronous rectification control, and is illustrated in a simplified manner for ease of understanding. When current flows through an inductive load L such as a motor, freewheeling diodes D1 and D2 are provided to keep the current flowing through the inductive load L. FIG. 6 shows a case where MOSFETs are used for the switching elements S1 and S2, and the parasitic diodes of the elements function as diodes D1 and D2. When the upper arm switching element S1 is ON and the lower arm switching element S2 is OFF, current flows in the direction shown by the solid arrow.

[0029] After a certain amount of current flows, turning off the switching element S1 on the upper arm causes a freewheeling current to flow via the diode D2 on the lower arm. If the switching elements S1 and S2 are IGBTs, the diodes D1 and D2 are provided separately. On the other hand, in the case of MOSFETs, SiC, or GaN, the diodes D1 and D2 of the switching elements S1 and S2 are parasitic diodes, and the freewheeling current flows via these parasitic diodes. MOSFETs (including SiC) and GaN HEMTs (High Electron Mobility Transistors) have reverse conduction when their gates are turned on. Therefore, if the switching element S2 is turned on during freewheeling, the freewheeling current flows through the switching element S2, which has lower loss than the diode D2. In other words, synchronous rectification allows freewheeling with low loss. On the other hand, since IGBTs do not have reverse conduction, the current still flows through the diode D2 even if the switching element S2 is turned on during freewheeling.

[0030] Figure 7 is a timing chart for synchronous rectification control, which adds the current I-Di flowing through diode D2 to the timing chart of Figure 3. Note that the current IL flowing through the FET is positive in the drain → source direction, and positive in the forward direction of diode D2. Traditionally, when performing synchronous rectification control, a dead time DT is set to prevent upper and lower short circuits. The longer the dead time DT, the longer the time T2 during which current I-Di flows during reflux. The reflux loss due to diode D2 is greater than the reflux loss due to FET conduction. Therefore, in order to reduce losses during reflux, it is necessary to shorten the dead time DT and shorten the time T2, which is the loss period due to diode D2.

[0031] Normally, the dead time DT is determined taking into account the rise time and fall time of the gate voltage Vg, but it is generally a fixed time. As explained in Figure 4, if the dead time DT is made too short, a short circuit will occur between the top and bottom, so there is a limit to how short the dead time DT can be. Also, the fall time of the gate voltage Vg varies depending on the current being conducted, and the smaller the current, the slower the gate fall tends to be. Therefore, the dead time is usually set to match the case when the current is small, which means that the reflux time during the dead time will be longer when the current is large.

[0032] Figure 8 is a diagram that explains how the gate voltage fall time changes depending on the magnitude of the current flowing through the switching elements S1 and S2. The dashed lines for the gate voltage Vg-H and current IH on the upper arm and the current IL on the lower arm indicate the case where the current flowing through the element is large. The fall time of the gate voltage Vg-H changes depending on the magnitude of the current flowing through the element. At the same time, the turn-off time of the current IH also fluctuates. When the current is large, both the fall time of the gate voltage and the turn-off time become shorter.

[0033] In Figure 8, T3 is the diode loss period due to diode D2 when the current is small, and T4 is the diode loss period when the current is large. If a constant dead time DT is set, the larger the current, the longer the diode loss period. Therefore, if the dead time DT is optimized for large currents, the possibility of an upper and lower short circuit occurring when a smaller current is conducted increases. Of course, it is possible to control the dead time DT each time using software on the CPU side according to the current magnitude, but this is not practical due to the software processing load and the considerable effort required for optimization. Furthermore, in the configuration described in Patent Document 1, it is difficult to control the dead time DT each time according to the current magnitude using a circuit.

[0034] On the other hand, in this embodiment, synchronous rectification can be performed in the optimum short-circuit prevention period DT1 (see FIG. 5) that is suited to the gate state. As a result, it is possible to prevent upper and lower short circuits while minimizing diode loss.

[0035] (Prevents upper and lower short circuits during soft shutdown) The gate driver ICs 10A and 10B are equipped with a soft turn-off or soft shutdown function as a protection function when an overcurrent is detected. In soft shutdown, the gate-off time is extended by slowing down the falling speed of the gate drive signal to prevent the switching elements from being destroyed by a surge caused by the gate being turned off. The inverter 201 shown in FIG. 13 may perform three-phase short-circuit control as a safety operation. When a fault state (overcurrent detection) is notified to the low-voltage side CPU or safety operation circuit, three-phase short-circuit control is performed on the opposite arm. For example, if an overcurrent is detected in the upper arm, three-phase short-circuit control is performed on the opposite lower arm. If voltage due to soft shutdown remains in the upper arm during this three-phase short-circuit control, an upper-lower short circuit will occur.

[0036] However, in the configuration of this embodiment, the output signal from OSFB terminal 105 is input to INB terminal 102 on the opposing arm side, so while the gate voltage of the arm during soft shutdown remains, the opposing arm will not turn on, as shown in Figure 5. Therefore, even in the case described above, it is possible to prevent the occurrence of an upper and lower short circuit.

[0037] (Variation 1) 9 is a diagram showing a first modification of the above-described embodiment. In the first modification, a capacitor C1 having one end grounded is connected between the INB terminal 102 of the gate driving IC 10A and the diode 20B, and a capacitor C2 having one end grounded is connected between the INB terminal 102 of the gate driving IC 10B and the diode 20A.

[0038] In the first modification, when the gate voltage of the upper arm rises and the output signal from the OSFB terminal 105 of the gate driver IC 10A goes high, the INB terminal 102 of the gate driver IC 10B of the lower arm goes high. Then, when the gate of the upper arm turns off and the OSFB terminal 105 of the gate driver IC 10A goes low, the function of capacitor C2 slows the rate at which the voltage at the INB terminal 102 of the gate driver IC 10B drops. As a result, the gate rise of the lower arm can be delayed for a certain period of time. For example, some gate driver ICs have a Miller clamp (a function to prevent false calls) that activates after the gate turns off. In such cases, providing capacitors C1 and C2 as described above delays the gate turn-on of the opposing arm, which allows more time for the Miller clamp to operate.

[0039] (Variation 2) Fig. 10 is a diagram showing Modification 2. In Fig. 10, a resistor R3 is further added to the configuration shown in Fig. 1. The resistor R3 is provided between the diode 20A and the INB terminal 102 of the gate driver IC 10B, and between the diode 20B and the INB terminal 102 of the gate driver IC 10A. The other configuration is the same as that of Fig. 1.

[0040] Normally, a PWM signal is driven to either a control voltage (VCC) or 0V by a push-pull output. As shown in Figure 11, the INA terminal 101 of the gate driver IC is equipped with a built-in pull-down resistor RPD so that it remains low even if it becomes open. On the other hand, the INB terminal 102 is equipped with a built-in pull-up resistor RUP because the logic is such that it is not driven when the INB terminal 102 is high. Note that resistors RPD and RUP are provided in both gate driver ICs 10A and 10B, but Figure 11 shows only the resistors RPD and RUP of the gate driver IC 10A.

[0041] In the safe operation circuit of the power conversion device, pull-up or pull-down may occur during safe operation. In the second modification, resistor R3 is provided so that the input signals to the INA terminal 101 and the INB terminal 102 have consistent values ​​even in such cases.

[0042] 11, when controlling by pull-down, that is, when the PWM-H signal of the upper arm is low (=0V), the INB-L signal must be lower than the low threshold value VTHL in order for the INB terminal 102 of the lower arm to also be in the low state. When a current flows from RPU to R2 to RPD in FIG. 11, resistor R2 must satisfy the following equation (1) in order for the potential of the INB terminal 102 of the gate driver IC 10B to be lower than VTHL. VCC × (R2+RPD) / (R2+RPD+RPU) <VTHL R2<(VTHL / (VCC-VTHL))×RPU-RPD …(1)

[0043] Furthermore, when the gate voltage Vg-H of the upper arm switching element S1 is high, the OSFB terminal 105 of the gate driver IC 10A is in a high (=5V) state. When the PWM-H signal is pulled down from this state and becomes low (=0V), the INA-H signal input to the INA terminal 101 must become lower than the low threshold value VTHL (see FIG. 12). VCC×RPD / (RPD+R2+R3×RPU / (R3+RPU)) <VTHL R2+R3×RPU / (R3+RPU)>((VCC-VTHL) / VTHL)×RPD …(2)

[0044] In variant 2, by further adding a resistor R3 and setting the values ​​of resistors R2 and R3 to satisfy equations (1) and (2), the INB-L signal and the INA-H signal can be made lower than the low threshold value VTHL.

[0045] For example, as a safety operation of the inverter 201 that drives the three-phase AC motor M shown in FIG. 13, there is three-phase short-circuit control by the control operation of the safety circuit on the CPU side. When a contactor (not shown) that opens and closes the connection between the inverter 201 and the high-voltage battery 300 is opened while the motor M is rotating, the high-voltage voltage in the inverter 201 rises due to the induced voltage of the motor M. At this time, the three-phase switching elements S1, S3, and S5 of the upper arm or the three-phase switching elements S2, S4, and S6 of the lower arm are turned on to create a three-phase short-circuit. In this case, the safety circuit pulls up the side that is turned on and pulls down the side that is not turned on. As a result, the induced voltage is converted into a current between the three-phase switching elements that are turned on and the motor M, preventing the high-voltage voltage in the inverter 201 from rising.

[0046] Furthermore, depending on the situation, there may be a safety control that transitions from a three-phase short circuit to a freewheel (FW) state in which all arms are turned off. When such safety control is performed, the PWM signal of the arm that is turned on is pulled down to low. However, in a configuration such as that shown in FIG. 11 in which the INB terminal 102 has a pull-up resistor RUP, as described above, the voltage of the INA terminal 101 does not fall below the low threshold value VTHL in the configuration shown in FIG. 1. To avoid such a problem, in the second modification, a resistor R3 is provided between the diodes 20A and 20B and each INB terminal 102.

[0047] According to the embodiment and the first and second modifications of the present invention described above, the following advantageous effects can be achieved.

[0048] 1, the gate drive circuit 1 includes a gate drive IC 10A that drives the gate of an upper-arm switching element S1, a gate drive IC 10B that drives the gate of a lower-arm switching element S2 connected in series to the switching element S1, two resistors R1, two resistors R2, and diodes 20A and 20B. Each of the gate drive ICs 10A and 10B has an INA terminal 101 and an INB terminal 102 to which a PWM signal is input, a gate output terminal 103 that outputs a gate drive signal, and an OSFB terminal 105 that outputs a feedback signal for the gate drive signal, and is configured to output an ON-state gate drive signal when the PWM signal at the INA terminal 101 is ON and the PWM signal at the INB terminal 102 is OFF. In the gate driver IC 10A, a PWM-H signal for switching element S1 is input to the INA terminal 101 via resistor R1, and a PWM-L signal for switching element S2 is input to the INB terminal 102 via resistor R2. In the gate driver IC 10B, a PWM-L signal is input to the INA terminal 101 via resistor R1, and a PWM-H signal is input to the INB terminal 102 via resistor R2. The cathode of diode 20A is connected to the INB terminal 102 of the gate driver IC 10B, and the anode is connected to the OSFB terminal 105 of the gate driver IC 10A. The cathode of diode 20B is connected to the INB terminal 102 of the gate driver IC 10A, and the anode is connected to the OSFB terminal 105 of the gate driver IC 10B.

[0049] As shown in Figure 1, the output signal from the OSFB terminal 105 of the gate driver IC 10A of the upper arm is input to the INB terminal 102 of the gate driver IC 10B on the opposite arm, and the output signal from the OSFB terminal 105 of the gate driver IC 10B of the lower arm is input to the INB terminal 102 of the gate driver IC 10A on the opposite arm. This makes it possible to suppress gate drive on the opposite arm while one of the gates is turning off, and prevents upper and lower short circuits even if the dead time DT set by the PWM signal is insufficient.

[0050] 1, the provision of diodes 20A and 20B prevents the low level of the OSFB-L signal from preventing the INB terminal 102 of gate driver IC 10A from going high when the OSFB-L signal of gate driver IC 10B is low and the PWM-L signal input to the INB terminal 102 of gate driver IC 10A is high. Furthermore, the provision of resistors R1 and R2 as shown in FIG. 1 prevents a situation in which the high level of the OSFB-H signal and the low level of the PWM-H signal compete with each other, preventing the INA terminal 101 of gate driver IC 10A from going low.

[0051] (C2) In (C1) above, a resistor R3 is further provided which is connected in series with the diodes 20A and 20B, as shown in Fig. 10. By providing the resistor R3 in this way, as described in Figs. 10 to 12, even when pull-down control is performed during safe operation, the INB-L signal and the INA-H signal can be controlled to be lower than the low threshold VTHL.

[0052] (C3) In (C1) above, field-effect transistors are used for the switching elements S1 and S2 shown in FIG. 1. In the case of MOSFETs (including SiC) and GaN HEMTs (High Electron Mobility Transistors), reverse conduction occurs when the gate is ON, so synchronous rectification can be performed by controlling the switching element S2 to ON during reflux. As shown in FIGS. 3 to 7, in this embodiment, synchronous rectification can be performed during the optimal short-circuit prevention period DT1 that is tailored to the gate state. As a result, it is possible to minimize diode loss while preventing upper and lower short circuits.

[0053] (C4) In the above (C3), the field effect transistor is a field effect transistor using silicon carbide or gallium nitride. Field effect transistors using these materials have a high forward voltage Vf of the parasitic body diode. Therefore, they are characterized by a greater loss reduction effect due to synchronous rectification.

[0054] (C5) In (C1) above, the gate driver ICs 10A and 10B have a soft shutdown function that slows down the falling speed of the gate driver signal to extend the gate-off time. In the above-described embodiment, as shown in FIG. 1, the output signal from the OSFB terminal 105 is input to the INB terminal 102 of the opposing arm. Therefore, as long as the gate voltage of the arm during soft shutdown remains, the opposing arm will not be turned on, as shown in FIG. 5. Therefore, even when a gate driver IC with a soft shutdown function is used, it is possible to prevent the occurrence of a short circuit between the upper and lower terminals during soft shutdown.

[0055] (C6) In (C1) above, as shown in FIG. 9, a capacitor element C1 with one end grounded is connected between the INB terminal 102 of the gate driver IC 10A and the diode 20B. Similarly, a capacitor element C2 with one end grounded is connected between the INB terminal 102 of the gate driver IC 10B and the diode 20A. For example, when the gate of the upper arm in FIG. 9 is turned OFF and the OSFB terminal 105 of the gate driver IC 10A goes low, the function of capacitor C2 can slow down the rate at which the voltage at the INB terminal 102 of the gate driver IC 10B drops. As a result, the gate rise of the lower arm can be delayed by a certain time.

[0056] (C7) As shown in Figures 1 and 13, a power conversion device includes a gate drive circuit 1 (203) described in any one of (C1) to (C6) above, a switching element S1 driven by a gate drive signal output by a gate drive IC 10A, a switching element S2 driven by a gate drive signal output by a gate drive IC 10B, and a control circuit 202 that outputs a PWM-H signal to the gate drive IC 10A and a PWM-L signal to the gate drive IC 10B.

[0057] 1, the gate drive IC provided in the gate drive circuit 203 inputs the output signal of the OSFB terminal 105 to the INB terminal 102 of the opposing arm. In three-phase short-circuit control during soft shutdown, while the gate voltage of the arm during soft shutdown remains, the opposing arm will not turn on as shown in FIG. 5, so that the occurrence of an upper and lower short circuit can be prevented.

[0058] In the above embodiment, the power conversion device 200 shown in FIG. 13 is described as an application example of the gate drive circuit 1, but the gate drive circuit 1 can be applied to various power conversion devices such as DC-DC converters.

[0059] The above-described embodiments and various modifications are merely examples, and the present invention is not limited to these details as long as the features of the invention are not impaired. Furthermore, although various embodiments and modifications have been described above, the present invention is not limited to these details. Other aspects conceivable within the scope of the technical idea of ​​the present invention are also included within the scope of the present invention. [Explanation of symbols]

[0060] 1...gate drive circuit, 10A, 10B...gate drive IC, 101...INA terminal, 102...INB terminal, 103...gate output terminal, 104...gate monitor terminal, 105...gate state feedback terminal (OSFB terminal), 200...power conversion device, 201...inverter, 202...control circuit, 203...gate drive circuit, C1, C2...capacitor, D1, D2...diode, M...motor, S1 to S6...switching elements

Claims

1. A gate drive circuit comprising: a first gate drive IC that drives a gate of a first switching element of an upper arm; a second gate drive IC that drives a gate of a second switching element of a lower arm that is connected in series to the first switching element; first, second, third and fourth resistance elements; and first and second diodes; Each of the first and second gate driver ICs comprises: INA and INB terminals to which PWM signals are input; a gate output terminal for outputting a gate drive signal; an OSFB terminal that outputs a feedback signal of the gate drive signal, and is configured to output an ON state gate drive signal when the PWM signal of the INA terminal is ON and the PWM signal of the INB terminal is OFF; In the first gate drive IC, as the PWM signals, a first PWM signal for the first switching element is input to the INA terminal via the first resistor element, and a second PWM signal for the second switching element is input to the INB terminal via the second resistor element; In the second gate driver IC, as the PWM signals, the second PWM signal is input to the INA terminal via the third resistor element, and the first PWM signal is input to the INB terminal via the fourth resistor element; the first diode has a cathode connected to the INB terminal of the second gate driver IC and an anode connected to the OSFB terminal of the first gate driver IC; a cathode side of the second diode connected to the INB terminal of the first gate driver IC and an anode side of the second diode connected to the OSFB terminal of the second gate driver IC;

2. 2. The gate drive circuit according to claim 1, a fifth resistor element connected in series with the first diode; a sixth resistive element connected in series with the second diode.

3. 2. The gate drive circuit according to claim 1, A gate drive circuit, wherein the first and second switching elements are field effect transistors.

4. 4. The gate drive circuit according to claim 3, The gate drive circuit, wherein the field effect transistor is a field effect transistor using silicon carbide or gallium nitride.

5. 2. The gate drive circuit according to claim 1, The first and second gate driver ICs have a soft shutdown function that slows down the falling speed of the gate driver signal to make the gate off time longer.

6. 2. The gate drive circuit according to claim 1, a first capacitor element having one end grounded is connected between the INB terminal of the first gate driver IC and the second diode; a second capacitor element having one end grounded is connected between the INB terminal of the second gate driver IC and the first diode;

7. A gate drive circuit according to any one of claims 1 to 6; the first switching element driven by a gate drive signal output from the first gate drive IC; the second switching element driven by a gate drive signal output from the second gate drive IC; a control circuit that outputs the first PWM signal to the first gate driver IC and outputs the second PWM signal to the second gate driver IC.

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