High-energy-efficiency incremental analog-to-digital converter based on high-order filter

Abstract

The invention discloses a high-energy-efficiency incremental analog-to-digital converter based on a high-order filter, which comprises an analog loop filter of a CIFF architecture and a high-order CoI decimation filter, and is characterized in that the analog loop filter comprises a first-stage integrator, a second-stage integrator, a passive summing circuit and a multi-bit quantizer which can be partially turned off; the high-order CoI decimation filter is realized by a multi-stage digital integrator formed by a full adder and a register. According to the invention, higher first-order integration is carried out on digital output of an analog loop filter based on a high-order decimation filter, a first-stage integrator is divided into four integrators which are connected in parallel, two integrators are turned off in the last 50% period of each conversion process, and another integrator is turned off in the last 25% period. The quantization error of the incremental analog-to-digital converter is reduced through the high-order decimation filter, and meanwhile, the power consumption is reduced by using the partial turn-off integrator, so that the energy efficiency of the analog-to-digital converter is integrally improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog-to-digital conversion, and in particular relates to a high-efficiency incremental analog-to-digital converter based on a high-order filter. Background Art

[0002] In recent years, with the continuous development of the concept of the Internet of Everything, smart sensors used in the field of the Internet of Things have become a topic of focus for researchers; Incremental Analog-to-Digital Converters (IADCs) are widely used in high-performance sensor systems due to their simple filter design, high precision, and low latency. However, for low-order and low-bit incremental analog-to-digital converters, achieving a high signal-to-quantization-noise ratio (SQNR) requires a long conversion cycle, which increases the number of times power-consuming circuit modules such as integrators work, making it difficult to reduce system power consumption.

[0003] Researchers have taken a series of measures to improve the energy efficiency of IADC. For example, the Chinese patent application with publication number CN114285414A proposed a scaling incremental analog-to-digital conversion method and converter, which adopts a scaling architecture to move the quantizer outside the loop, which is beneficial to the optimization and improvement of the system linearity and energy efficiency of IADC. However, the scaling operation introduces additional quantization errors, which requires more conversion cycles to quantize the signal. Extended counting technology is another effective means to reduce the quantization noise of IADC. For example, the Chinese patent application with publication number CN115549683A proposed a high-precision incremental zoom ADC architecture, the principle of which is to further quantize the quantization noise, but a high-gain amplifier is required in the circuit to prevent the leakage of quantization noise, which increases the difficulty of circuit design.

[0004] It can be seen that the improvement ideas of the existing work are all to improve the analog loop filter of the IADC, which increases the cost or design difficulty of the analog circuit. Summary of the invention

[0005] In view of the above, the present invention provides a high-efficiency incremental analog-to-digital converter based on a high-order filter, which utilizes the random distribution characteristics of quantization noise to improve the SQNR, and at the same time utilizes the nonlinear weight brought by the high-order filter to perform slice-by-slice shutdown of the integrator to optimize the power consumption of the IADC and improve the energy efficiency of the entire IADC.

[0006] A high-efficiency incremental analog-to-digital converter based on a high-order filter, comprising: An analog loop filter with a CIFF (Cascaded Integrators with Feedforward) architecture, which acts as a delta-sigma modulator to achieve analog-to-digital conversion of differential input signals and shaping of quantization noise; A high-order CoI (Cascade-of-Integrator) decimation filter is used to perform a higher-order decimation filter on the digital output of the delta-sigma modulator to obtain the final digital output result of the IADC and reduce the quantization error of the IADC.

[0007] Furthermore, the analog loop filter includes a clock generation module, a first-stage integrator that can be turned off in slices, a second-stage integrator, a passive summing circuit, and a multi-bit quantizer, wherein: The clock generation module is used to provide necessary switching clocks for the first-stage integrator, the second-stage integrator, the passive summing circuit and the multi-bit quantizer; The first-stage integrator is used to calculate the difference between the differential input signal and the output of the multi-bit quantizer, and then accumulate the difference with the output signal of the first-stage integrator in the previous cycle to obtain the output signal of the first-stage integrator in the current cycle; The second-stage integrator is used to accumulate the output signal of the first-stage integrator in the current cycle and the output signal of the second-stage integrator in the previous cycle to obtain the output signal of the second-stage integrator in the current cycle; The passive summing circuit is used to perform passive summing of the differential input signal, the output signal of the first-stage integrator in the current cycle, and the output signal of the second-stage integrator in the current cycle through charge redistribution of the capacitor; The multi-bit quantizer is used to quantize the summing result of the passive summing circuit to obtain the digital output of the delta-sigma modulator.

[0008] Furthermore, the first-stage integrator includes four parallel-connected integrators and a control logic module. The working states of the four integrators are enabled by the control logic module. Each integrator includes a sampling feedback capacitor C S1P and C S1N , Integral capacitor C INT1P and C INT1N , Amplifier AMP1 and switches S1~S1 using chopping technology 12 , where one end of S1 is connected to the positive phase input signal V IP And as the positive phase input terminal of the first stage integrator, the other end of S1 is connected to one end of S3, one end of S5 and C S1P One end of S2 is connected to the inverting input signal V IN And as the inverting input end of the first stage integrator, the other end of S2 is connected to one end of S4, one end of S6 and C S1NThe other end of S3 and the other end of S4 are connected to the inverting voltage reference source V refn , the other end of S5 and the other end of S6 are connected to the positive phase voltage reference source V refp , C S1P The other end is connected to one end of S7, one end of S9 and the positive input end of AMP1. S1N The other end of S8 and S 10 One end of S7 and the inverting input of AMP1 are connected, and the other end of S7 and the other end of S8 are connected to the common mode voltage V CM , the other end of S9 is connected to C INT1P One end is connected to S 10 The other end of the INT1N One end of C INT1P The other end is connected to the inverting output of AMP1 and S 11 One end of C INT1N The other end is connected to the positive phase output terminal of AMP1 and S 12 One end is connected to S 11 The other end of the first stage integrator is used as the positive phase output end, S 12 The other end serves as the inverting output end of the first-stage integrator.

[0009] Furthermore, within the switching clock φ1, the first-stage integrator performs sampling operation, S1, S2, S7, and S8 are closed, and V IP and V IN are sampled to C S1P and C S1N In the switching clock φ2, the first-stage integrator performs integration operation, and the output of the multi-bit quantizer controls the on / off of S3, S4, S5, and S6 after DWA (Data weighted averaging) digital logic operation, so that C S1P and C S1N Connect to V refp or V refn , feedback the quantization result of the previous cycle; then S9 and S 10 Closed, so that the residual of input and feedback is integrated to C INT1P and C INT1N superior.

[0010] Furthermore, the control logic module outputs an enable signal EN of a 4-bit digital code, and the 4-bit digital code corresponds to the working state of the four integrators. For each Nyquist conversion of the IADC, within the first 50% cycle, the enable signal EN output by the control logic module is 1111; within 50%~75% of the cycle, the enable signal EN output by the control logic module is 1100; within the last 25% of the cycle, the enable signal EN output by the control logic module is 1000; when the digital code is 1, the corresponding integrator performs related operations according to the switch clocks φ1 and φ2; when the digital code is 0, the corresponding integrator S1~S 12 All off.

[0011] Furthermore, the second stage integrator includes a sampling capacitor C S2P and C S2N , Integral capacitor C INT2P and C INT2N , amplifier AMP2 and switch S 13 ~S 18 , where C S2P One end of S 13 One end of the integrator is connected to the positive phase output of the first stage integrator and serves as the positive phase input of the second stage integrator. S2N One end of S 14 One end of the inverting output end of the first stage integrator is connected to the inverting input end of the second stage integrator. S2P The other end of S 15 One end, S 17 One end is connected to the positive input terminal of AMP2, C S2N The other end of S 16 One end, S 18 One end is connected to the inverting input of AMP2, S 13 The other end, S 14 The other end, S 15 The other end and S 16 The other end is connected to the common mode voltage V CM , S 17 The other end of the INT2P One end is connected to S 18 The other end of the INT2N One end of C INT2P The other end is connected to the inverting output of AMP2 and serves as the non-inverting output of the second-stage integrator. INT2N The other end is connected to the non-inverting output end of AMP2 and serves as the inverting output end of the second-stage integrator.

[0012] Furthermore, within the switching clock φ1, the second-stage integrator performs an integration operation, S 13 , S 14, S 17 , S 18 Closed, completed from C S2P and C S2N to C INT2P and C INT2N The second-stage integrator performs sampling operation within the switching clock φ2, S 11 , S 12 , S 15 , S 16 Close, and sample the integration result of the first-stage integrator to C S2P and C S2N superior.

[0013] Furthermore, the passive summing circuit includes a summing capacitor C F1P ~C F3P and C F1N ~C F3N , summing control switch S 19 ~S 34 , where S 19 One end of S is connected to the positive phase output end of the second stage integrator. 20 One end of S is connected to the inverting output end of the second stage integrator. 19 The other end of S 31 One end and C F3P One end is connected to S 20 The other end of S 32 One end and C F3N One end is connected to S 31 The other end of S 27 One end is connected to the common mode voltage V CM , S 32 The other end of S 28 One end is connected to the common mode voltage V CM , S 27 The other end of the F2P One end of the second stage integrator is connected to the non-inverting input end, S 28 The other end of the F2N One end of the inverting input terminal of the second stage integrator is connected to C F2P The other end of S 29 One end, S 33 One end, S 25 One end of C F3P The other end and C F1P One end of the passive summing circuit is connected to the positive phase output terminal, C F2N The other end of S 30 One end, S 34 One end, S 26 One end of C F3N The other end and CF1N One end of the passive summing circuit is connected to the inverting output terminal, S 29 The other end of S 33 The other end is connected to the common mode voltage V CM , S 30 The other end of S 34 The other end is connected to the common mode voltage V CM , S 25 The other end and S 26 The other end is connected to the common mode voltage V CM , C F1P The other end of S 23 One end and S 21 One end of C F1N The other end of S 24 One end and S 22 One end is connected to S 23 The other end and S 24 The other end is connected to the common mode voltage V CM , S 21 The other end is connected to the positive phase input signal V IP , S 22 The other end is connected to the inverting input signal V IN .

[0014] Furthermore, within the switching clock φ1, S 19 , S 20 , S 21 , S 22 , S 25 , S 26 , S 33 , S 34 Closed, the passive summing circuit samples the differential input signal to C F1P and C F1N The output signal of the second stage integrator is sampled to C F3P and C F3N On; at the switching clock φ ADD_2 Inside, S 29 and S 30 Closed, the passive summing circuit integrates the output signal of the first stage integrator to C F2P and C F2N On; at the switching clock φ ADD During the stage, S 23 , S 24 , S 27 , S 28 , S 31 , S 32 When closed, the passive summing circuit performs charge redistribution to complete the summation of the differential input signal, the first-stage integrator output signal, and the second-stage integrator output signal.

[0015] Furthermore, the high-order CoI extraction filter is composed of a three-stage digital integrator D INT1 ~D INT3 Each level of digital integrator is composed of a full adder and a register. INT1 The full adder adds the digital output of the delta-sigma modulator to the previous cycle D INT1 The output result is added as the current cycle D INT1 The output result is stored in the register; D INT2 The full adder in the previous cycle D INT1 The output result of the previous cycle D INT2 The output result is added as the current cycle D INT2 The output result is stored in the register; D INT3 The full adder in the previous cycle D INT2 The output result of the previous cycle D INT3 The output result is added as the current cycle D INT3 The output result (i.e. the final digital output result of IADC in the current cycle) is stored in the register.

[0016] Due to the periodic reset working mode of IADC, the design of its extraction filter can be implemented by CoI digital integrator. The present invention proposes an incremental analog-to-digital converter architecture based on a high-order filter, which effectively utilizes the characteristics of random distribution of quantization error. Starting from the idea of ​​filter design, the quantization error of the system is reduced and the SQNR is improved. At the same time, the present invention makes the first-stage integrator segmented and turnable, and combines it with dynamic power consumption reduction technology to optimize the power consumption of IADC while ensuring noise performance, thereby improving the energy efficiency of the entire IADC. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 The block diagram of the structure of the energy-efficient incremental analog-to-digital converter system based on a high-order filter of the present invention.

[0018] Figure 2 Schematic diagram of the structure of an analog loop filter circuit of a CIFF architecture in an embodiment of the present invention.

[0019] Figure 3 FIG. 4 is a schematic diagram of the working timing of the analog loop filter in an embodiment of the present invention.

[0020] Figure 4 The diagram is a circuit structure and control logic diagram of a first-stage integrator with segmented shutdown in an embodiment of the present invention.

[0021] Figure 5 Schematic diagram of the circuit structure of a high-order CoI extraction filter in an embodiment of the present invention.

[0022] Figure 6 FIG. 1 is a schematic diagram of an IADC output spectrum before and after a high-order decimation filter is applied under AC input according to an embodiment of the present invention.

[0023] Figure 7 Graph showing the IADC output spectrum before and after the partial shutdown technology is applied under AC input according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] In order to describe the present invention more specifically, the technical solution of the present invention is described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0025] like Figure 1 As shown, the incremental analog-to-digital converter based on the high-order decimation filter of the present invention includes an analog loop filter of a CIFF architecture and a high-order CoI decimation filter. The analog loop filter is composed of a two-stage integrator (the transfer function is , z represents the Z transform operator) completes the Δ-Σ modulation of the input signal U to obtain the digital output V, and the quantization error in the analog loop filter is E1; the high-order CoI extraction filter performs a third-order digital integration on V to obtain the final output D of the IADC OUT ; The reset of the analog loop filter and the high-order CoI extraction filter is controlled by the RST (reset) signal.

[0026] The analog loop filter of the CIFF architecture includes a partially switchable first-stage integrator INT1, a second-stage integrator INT2, a passive summing circuit and a 3-bit (BIT) quantizer. The circuit is implemented as follows: Figure 2 As shown, where: The first-stage integrator INT1 includes four parallel slice integrators 1-4 and a control logic module. The working states of the four slice integrators 1-4 are enabled by the control logic module. Each slice integrator includes a sampling feedback capacitor C S1P and C S1N , Integral capacitor C INT1P and C INT1N , Amplifier AMP1 and switches S1~S1 using chopping technology 12 , where one end of S1 is connected to the positive phase input signal V IP And as the positive phase input terminal of the first stage integrator, the other end of S1 is connected to one end of S3, one end of S5 and C S1P One end of S2 is connected to the inverting input signal V IN And as the inverting input end of the first stage integrator, the other end of S2 is connected to one end of S4, one end of S6 and C S1N The other end of S3 and the other end of S4 are connected to the inverting voltage reference source V refn, the other end of S5 and the other end of S6 are connected to the positive phase voltage reference source V refp , C S1P The other end is connected to one end of S7, one end of S9 and the positive input end of AMP1. S1N The other end of S8 and S 10 One end of S7 and the inverting input of AMP1 are connected, and the other end of S7 and the other end of S8 are connected to the common mode voltage V CM , the other end of S9 is connected to C INT1P One end is connected to S 10 The other end of the INT1N One end of C INT1P The other end is connected to the inverting output of AMP1 and S 11 One end of C INT1N The other end is connected to the positive phase output terminal of AMP1 and S 12 One end is connected to S 11 The other end of the first stage integrator is used as the positive phase output end, S 12 The other end serves as the inverting output end of the first-stage integrator.

[0027] The second stage integrator INT2 includes a sampling capacitor C S2P and C S2N , Integral capacitor C INT2P and C INT2N , amplifier AMP2 and switch S 13 ~S 18 , where C S2P One end of S 13 One end of the integrator is connected to the positive phase output of the first stage integrator and serves as the positive phase input of the second stage integrator. S2N One end of S 14 One end of the inverting output end of the first stage integrator is connected to the inverting input end of the second stage integrator. S2P The other end of S 15 One end, S 17 One end is connected to the positive input terminal of AMP2, C S2N The other end of S 16 One end, S 18 One end is connected to the inverting input of AMP2, S 13 The other end, S 14 The other end, S 15 The other end and S 16 The other end is connected to the common mode voltage V CM , S 17 The other end of the INT2P One end is connected to S 18 The other end of the INT2NOne end of C INT2P The other end is connected to the inverting output of AMP2 and serves as the non-inverting output of the second-stage integrator. INT2N The other end is connected to the non-inverting output end of AMP2 and serves as the inverting output end of the second-stage integrator.

[0028] The passive summing circuit includes a summing capacitor C F1P ~C F3P and C F1N ~C F3N , summing control switch S 19 ~S 34 , where S 19 One end of S is connected to the positive phase output end of the second stage integrator. 20 One end of S is connected to the inverting output end of the second stage integrator. 19 The other end of S 31 One end and C F3P One end is connected to S 20 The other end of S 32 One end and C F3N One end is connected to S 31 The other end of S 27 One end is connected to the common mode voltage V CM , S 32 The other end of S 28 One end is connected to the common mode voltage V CM , S 27 The other end of the F2P One end of the second stage integrator is connected to the non-inverting input end, S 28 The other end of the F2N One end of the inverting input terminal of the second stage integrator is connected to C F2P The other end of S 29 One end, S 33 One end, S 25 One end of C F3P The other end and C F1P One end of the passive summing circuit is connected to the positive phase output terminal, C F2N The other end of S 30 One end, S 34 One end, S 26 One end of C F3N The other end and C F1N One end of the passive summing circuit is connected to the inverting output terminal, S 29 The other end of S 33 The other end is connected to the common mode voltage V CM , S 30 The other end of S 34The other end is connected to the common mode voltage V CM , S 25 The other end and S 26 The other end is connected to the common mode voltage V CM , C F1P The other end of S 23 One end and S 21 One end of C F1N The other end of S 24 One end and S 22 One end is connected to S 23 The other end and S 24 The other end is connected to the common mode voltage V CM , S 21 The other end is connected to the positive phase input signal V IP , S 22 The other end is connected to the inverting input signal V IN .

[0029] like Figure 3 The figure shows the working sequence of the analog loop filter, including φ1, φ2, φ ADD ,φ ADD_2 Four clocks. In the φ1 stage, the first-stage integrator performs sampling operation, S1, S2, S7, and S8 are closed, and the input signal V IP 、V IN is sampled to C S1P and C S1N On; the second stage integrator performs integration operation, S 13 , S 14 , S 17 , S 18 Closed, completed from C S2P , C S2N to C INT2P , C INT2N The integral of the passive summation circuit S 21 , S 22 , S 25 , S 26 Closed, the input signal is sampled to C F1P and C F1N Up; S 19 , S 20 , S 33 , S 34 Close, and sample the output of the second stage integrator to C F3P and C F3N In the φ2 stage, the first-stage integrator performs integration operation, and S3, S4, S5, and S6 are controlled by the quantizer output after DWA digital logic operation, respectively for C S1P and C S1N The lower plate is connected to the reference source V refn、V refp , feedback the results of the previous cycle quantization; S9, S 10 Closed, the residual of input and feedback is integrated to C INT1P , C INT1N On; the second stage integrator performs sampling operation, S 11 , S 12 , S 15 , S 16 Close, sample the first-level integration result to C S2P , C S2N On. ADD_2 In the passive summing circuit, S 29 , S 30 Close, integrate the output of the first stage to C F2P and C F2N On. ADD During the stage, S 23 , S 24 , S 27 , S 28 , S 31 , S 32 When closed, the passive summing circuit performs charge redistribution to complete the summation of the input signal, the first-stage integrator, and the second-stage integrator.

[0030] like Figure 4 The figure shows the partial turn-off circuit implementation and timing of the first-stage integrator. The switches S1~S in the four identical integrators are shown in FIG. 12 The operation of the amplifier AMP1 is controlled by the φ1 and φ2 clocks as well as the enable signal EN<1:4>. When EN(i)=1 (i=1,2,3,4), each part of the integrator is controlled by the φ1 and φ2 clocks to realize the predetermined circuit functions and output the signal V OP1 and V ON1 When EN(i)=0, S1, S2, S7, and S8 are disconnected, and no sampling operation is performed; S3, S4, S5, and S6 are disconnected, and no sampling operation is performed from the reference source V refn 、V refp Feedback; S9, S 10 , S 11 , S 12 For each Nyquist conversion of the incremental ADC, all four integrators are turned on within the first 50% of the cycle, EN<1:4>=1111; 50%~75% of the cycle, EN<1:4>=1100; the last 25% of the cycle, EN<1:4>=1000.

[0031] like Figure 5 The circuit implementation of the third-order CoI extraction filter in this embodiment is shown as follows, including a three-stage digital integrator DINT1 ~D INT3 Each stage of digital integrator includes a full adder and a register. The inputs of the first stage full adder are the output V of the analog loop filter and the accumulated result of the previous cycle stored in the register; the two inputs of the second stage integrator are the accumulated results of the first and second stages in the previous cycle; the two inputs of the third stage integrator are the accumulated results of the second and third stages in the previous cycle, and the output of the third stage integrator is the final output D of IADC. OUT The reset signal RST is set high at the beginning of each Nyquist conversion to reset all registers; when the quantizer work of each conversion cycle is completed and the clock signal CLK arrives, the register storage refreshes the accumulated result of the current cycle.

[0032] The incremental analog-to-digital converter based on the high-order filter in this embodiment effectively improves the signal-to-noise ratio of the IADC. Figure 6 As shown in the figure, the IADC has a signal-to-noise-distortion ratio of 106.5dB after applying the high-order decimation filter, and only 100.5dB when the high-order decimation filter is not applied, and the effective number of bits is increased by 1. Figure 7 As shown in the figure, based on the application of a high-order decimation filter, the first-stage integrator is partially shut down. After the partial shut-down technology is applied, the SNDR is only reduced by 0.3dB, and the power consumption of the IADC is reduced to 75% of that when the partial shut-down technology is not used, which effectively improves the energy efficiency of the IADC.

[0033] The above description of the embodiments is to facilitate the understanding and application of the present invention by those skilled in the art. It is obvious that those skilled in the art can easily make various modifications to the above embodiments and apply the general principles described herein to other embodiments without creative work. Therefore, the present invention is not limited to the above embodiments, and improvements and modifications made by those skilled in the art based on the disclosure of the present invention should be within the scope of protection of the present invention.

Claims

1. A high-efficiency incremental analog-to-digital converter based on a high-order filter, characterized in that: include: The analog loop filter of the CIFF architecture acts as a delta-sigma modulator to achieve analog-to-digital conversion of the differential input signal and shaping of the quantization noise; The high-order CoI decimation filter is used to perform a high-order decimation filter on the digital output of the delta-sigma modulator to obtain the final digital output result of the IADC and reduce the quantization error of the IADC.

2. The high-efficiency incremental analog-to-digital converter based on a high-order filter according to claim 1, characterized in that: The analog loop filter comprises a clock generation module, a first-stage integrator with slice-turnoff capability, a second-stage integrator, a passive summing circuit and a multi-bit quantizer, wherein: The clock generation module is used to provide necessary switching clocks for the first-stage integrator, the second-stage integrator, the passive summing circuit and the multi-bit quantizer; The first-stage integrator is used to calculate the difference between the differential input signal and the output of the multi-bit quantizer, and then accumulate the difference with the output signal of the first-stage integrator in the previous cycle to obtain the output signal of the first-stage integrator in the current cycle; The second-stage integrator is used to accumulate the output signal of the first-stage integrator in the current cycle and the output signal of the second-stage integrator in the previous cycle to obtain the output signal of the second-stage integrator in the current cycle; The passive summing circuit is used to perform passive summing of the differential input signal, the output signal of the first-stage integrator in the current cycle, and the output signal of the second-stage integrator in the current cycle through charge redistribution of the capacitor; The multi-bit quantizer is used to quantize the summing result of the passive summing circuit to obtain the digital output of the delta-sigma modulator.

3. The high-efficiency incremental analog-to-digital converter based on a high-order filter according to claim 2, characterized in that: The first-stage integrator includes four parallel integrators and a control logic module. The working state of the four integrators is enabled by the control logic module. Each integrator includes a sampling feedback capacitor C S1P and C S1N , Integral capacitor C INT1P and C INT1N , Amplifier AMP1 and switches S1~S1 using chopping technology 12 , where one end of S1 is connected to the positive phase input signal V IP And as the positive phase input terminal of the first stage integrator, the other end of S1 is connected to one end of S3, one end of S5 and C S1P One end of S2 is connected to the inverting input signal V IN And as the inverting input end of the first stage integrator, the other end of S2 is connected to one end of S4, one end of S6 and C S1N The other end of S3 and the other end of S4 are connected to the inverting voltage reference source V refn , the other end of S5 and the other end of S6 are connected to the positive phase voltage reference source V refp , C S1P The other end is connected to one end of S7, one end of S9 and the positive input end of AMP1. S1N The other end of S8 and S 10 One end of S7 and the inverting input of AMP1 are connected, and the other end of S7 and the other end of S8 are connected to the common mode voltage V CM , the other end of S9 is connected to C INT1P One end is connected to S 10 The other end of the INT1N One end of C INT1P The other end is connected to the inverting output of AMP1 and S 11 One end of C INT1N The other end is connected to the positive phase output terminal of AMP1 and S 12 One end is connected to S 11 The other end of the first stage integrator is used as the positive phase output end, S 12 The other end serves as the inverting output end of the first-stage integrator.

4. The high-efficiency incremental analog-to-digital converter based on a high-order filter according to claim 3, characterized in that: In the switching clock φ1, the first-stage integrator performs sampling operation, S1, S2, S7, S8 are closed, and V IP and V IN are sampled to C S1P and C S1N In the switching clock φ2, the first-stage integrator performs integration operation, and the output of the multi-bit quantizer controls the on / off of S3, S4, S5, and S6 after the DWA digital logic operation, so that C S1P and C S1N Connect to V refp or V refn , feedback the quantization result of the previous cycle; then S9 and S 10 Closed, so that the residual of input and feedback is integrated to C INT1P and C INT1N superior.

5. The high-efficiency incremental analog-to-digital converter based on a high-order filter according to claim 4, characterized in that: The control logic module outputs an enable signal EN of a 4-bit digital code, and the 4-bit digital code corresponds to the working state of the four integrators. For each Nyquist conversion of the IADC, within the first 50% cycle, the enable signal EN output by the control logic module is 1111; within 50% to 75% of the cycle, the enable signal EN output by the control logic module is 1100; within the last 25% of the cycle, the enable signal EN output by the control logic module is 1000; when the digital code is 1, the corresponding integrator performs related operations according to the switch clocks φ1 and φ2; When the digital code is 0, the corresponding integrator S1~S 12 All off.

6. The high-efficiency incremental analog-to-digital converter based on a high-order filter according to claim 2, characterized in that: The second stage integrator includes a sampling capacitor C S2P and C S2N , Integral capacitor C INT2P and C INT2N , amplifier AMP2 and switch S 13 ~S 18 , where C S2P One end of S 13 One end of the integrator is connected to the positive phase output of the first stage integrator and serves as the positive phase input of the second stage integrator. S2N One end of S 14 One end of the inverting output end of the first stage integrator is connected to the inverting input end of the second stage integrator. S2P The other end of S 15 One end, S 17 One end is connected to the positive input terminal of AMP2, C S2N The other end of S 16 One end, S 18 One end is connected to the inverting input of AMP2, S 13 The other end, S 14 The other end, S 15 The other end and S 16 The other end is connected to the common mode voltage V CM , S 17 The other end of the INT2P One end is connected to S 18 The other end of the INT2N One end of C INT2P The other end is connected to the inverting output of AMP2 and serves as the non-inverting output of the second-stage integrator. INT2N The other end is connected to the non-inverting output end of AMP2 and serves as the inverting output end of the second-stage integrator.

7. The high-efficiency incremental analog-to-digital converter based on a high-order filter according to claim 6, characterized in that: Within the switching clock φ1, the second-stage integrator performs integration operation, S 13 , S 14 , S 17 , S 18 Closed, completed from C S2P and C S2N to C INT2P and C INT2N The second-stage integrator performs sampling operation within the switching clock φ2, S 11 , S 12 , S 15 , S 16 Close, and sample the integration result of the first-stage integrator to C S2P and C S2N superior.

8. The high-efficiency incremental analog-to-digital converter based on a high-order filter according to claim 3, characterized in that: The passive summing circuit includes a summing capacitor C F1P ~C F3P and C F1N ~C F3N , summing control switch S 19 ~S 34 , where S 19 One end of S is connected to the positive phase output end of the second stage integrator. 20 One end of S is connected to the inverting output end of the second stage integrator. 19 The other end of S 31 One end and C F3P One end is connected to S 20 The other end of S 32 One end and C F3N One end is connected to S 31 The other end of S 27 One end is connected to the common mode voltage V CM , S 32 The other end of S 28 One end is connected to the common mode voltage V CM , S 27 The other end of the F2P One end of the second stage integrator is connected to the non-inverting input end, S 28 The other end of the F2N One end of the inverting input terminal of the second stage integrator is connected to C F2P The other end of S 29 One end, S 33 One end, S 25 One end of C F3P The other end and C F1P One end of the passive summing circuit is connected to the positive phase output terminal, C F2N The other end of S 30 One end, S 34 One end, S 26 One end of C F3N The other end and C F1N One end of the passive summing circuit is connected to the inverting output terminal, S 29 The other end of S 33 The other end is connected to the common mode voltage V CM , S 30 The other end of S 34 The other end is connected to the common mode voltage V CM , S 25 The other end and S 26 The other end is connected to the common mode voltage V CM , C F1P The other end of S 23 One end and S 21 One end of C F1N The other end of S 24 One end and S 22 One end is connected to S 23 The other end and S 24 The other end is connected to the common mode voltage V CM , S 21 The other end is connected to the positive phase input signal V IP , S 22 The other end is connected to the inverting input signal V IN .

9. The high-efficiency incremental analog-to-digital converter based on a high-order filter according to claim 8, characterized in that: Within the switching clock φ1, S 19 , S 20 , S 21 , S 22 , S 25 , S 26 , S 33 , S 34 Closed, the passive summing circuit samples the differential input signal to C F1P and C F1N The output signal of the second stage integrator is sampled to C F3P and C F3N On; at the switching clock φ ADD_2 Inside, S 29 and S 30 Closed, the passive summing circuit integrates the output signal of the first stage integrator to C F2P and C F2N On; at the switching clock φ ADD During the stage, S 23 , S 24 , S 27 , S 28 , S 31 , S 32 When closed, the passive summing circuit performs charge redistribution to complete the summation of the differential input signal, the first-stage integrator output signal, and the second-stage integrator output signal.

10. The high-efficiency incremental analog-to-digital converter based on a high-order filter according to claim 1, characterized in that: The high-order CoI extraction filter consists of a three-stage digital integrator D INT1 ~D INT3 Each level of digital integrator is composed of a full adder and a register. INT1 The full adder adds the digital output of the delta-sigma modulator to the previous cycle D INT1 The output result is added as the current cycle D INT1 The output result is stored in the register; D INT2 The full adder in the previous cycle D INT1 The output result of the previous cycle D INT2 The output result is added as the current cycle D INT2 The output result is stored in the register; D INT3 The full adder in the previous cycle D INT2 The output result of the previous cycle D INT3 The output result is added as the current cycle D INT3 The output result is stored in the register.

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