Analog-to-digital conversion

Abstract

The invention relates to a successive approximation register analog-to-digital converter. An example successive approximation register analog-to-digital converter includes a first sample and hold circuit that samples an analog signal at a first point in time and generates a first input voltage; a second sample and hold circuit sampling the analog signal at a second point in time and generating a second input voltage; and a first analog-to-digital converter. The first analog-to-digital converter performs a feed-forward equalization function by receiving a first input voltage and a second input voltage, sampling the first input voltage and the second input voltage, and outputting a multi-bit digital signal based on a sampling result of the first input voltage and a sampling result of the second input voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2023-0097451 filed in the Korean Intellectual Property Office on July 26, 2023, the disclosure of which is incorporated herein by reference in its entirety. Background Art

[0003] Nowadays, various types of electronic devices are being used. Electronic devices can perform various functions. In order to perform unique operations, electronic devices can operate alone or can operate while communicating with any other electronic devices. As the amount of data exchanged between electronic devices increases, communication circuits capable of sending and receiving signals at high speed are adopted. Electronic devices are connected through communication channels, and the communication channels transmit and receive signals between electronic devices.

[0004] However, due to various factors such as skin effect and dielectric loss, high-frequency components of signals transmitted through a communication channel may be weakened, resulting in a decrease in the quality of the signal transmitted at a high speed.

[0005] To solve the quality degradation problem, equalizers such as a continuous time linear equalizer (CTLE), a decision feedback equalizer (DFE), and a feedforward equalizer may be employed. In particular, generally, since a feedforward equalizer processes inputs of many bits, the area and power consumption of a chip increase. Summary of the invention

[0006] The present disclosure relates to analog-to-digital converters, including successive approximation register analog-to-digital converters that perform the functionality of a feed-forward equalizer without a separate feed-forward equalizer.

[0007] In general, according to some aspects, a successive approximation register analog-to-digital converter that performs a successive approximation operation includes: a first sampling and holding circuit that samples an analog signal at a first time point and generates a first input voltage; a second sampling and holding circuit that samples the analog signal at a second time point and generates a second input voltage; and a first analog-to-digital converter that includes a first plurality of capacitors for sampling the first input voltage and a second plurality of capacitors for sampling the second input voltage. The first analog-to-digital converter samples the first input voltage by using at least some of the first plurality of capacitors, and samples the second input voltage by using at least some of the second plurality of capacitors, and the first analog-to-digital converter outputs a multi-bit digital signal based on the sum of a first charge corresponding to the sampling result of the first input voltage and a second charge corresponding to the sampling result of the second input voltage.

[0008] In general, according to some aspects, a successive approximation register analog-to-digital converter includes: a first sampling and holding circuit that generates a first input voltage by sampling an analog signal; a second sampling and holding circuit that generates a second input voltage by sampling the analog signal after the first input voltage is sampled; a first analog-to-digital converter that includes a first tap and a second tap, each of which includes a plurality of switched capacitors; and a second analog-to-digital converter that includes a third tap and a fourth tap, each of which includes a plurality of switched capacitors. The first tap samples the first input voltage at a first time point, the second tap samples the second input voltage at a second time point, the third tap samples the second input voltage at a second time point, and the first analog-to-digital converter outputs a first multi-bit digital signal based on the sum of a first charge corresponding to the sampling result of the first tap and a second charge corresponding to the sampling result of the second tap.

[0009] Generally, according to some aspects, an operation method of a successive approximation register analog-to-digital converter includes: generating a first input voltage by sampling an analog signal at a first time point using a first sampling and holding circuit; generating a second input voltage by sampling the analog signal at a second time point using a second sampling and holding circuit; sampling the first input voltage by using a first tap of the first analog-to-digital converter, sampling the second input voltage by using a second tap of the first analog-to-digital converter, sampling the second input voltage by using a third tap of the second analog-to-digital converter, and outputting a first multi-bit digital signal based on the sampling result of the first tap and the sampling result of the second tap. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0011] Figure 1 A configuration of an example of an electronic system including an equalizer is shown.

[0012] Figure 2 and Figure 3 It is shown by Figure 1 An example conceptual diagram of distortion of a signal transmitted through a communication channel.

[0013] Figure 4 It is shown Figure 1 An example block diagram of a configuration of a first device.

[0014] Figure 5 It is shown Figure 4 An example block diagram of a SAR-ADC configuration.

[0015] Figure 6 It is shown Figure 5 An example timing diagram of the operation of a sample and hold circuit.

[0016] Figure 7 It is shown Figure 5 An example circuit diagram of a C-DAC configuration.

[0017] Figure 8 It is shown Figure 7 An example flow chart of the operation of a SAR-ADC.

[0018] Fig. 9 It is shown Figure 7 Example circuit diagram of the operation of each state of the C-DAC.

[0019] Fig.10 is an example diagram showing how a SAR logic circuit generates a switch control signal.

[0020] Fig.11 It is shown Figure 7 Example circuit diagram of the operation of each state of the C-DAC.

[0021] Fig.12 It is shown Figure 7 Example circuit diagram of the operation of each state of the C-DAC.

[0022] Fig.13 It is shown Figure 7 Example circuit diagram of the operation of each state of the C-DAC.

[0023] Fig.14 is a diagram showing an example of feed-forward equalization (FFE) performed by a SAR-ADC.

[0024] Fig.15 is a flow chart showing an example of the operation of a SAR-ADC.

[0025] Fig.16 A configuration of an example of an electronic system including an equalizer is shown.

[0026] Fig.17 A configuration of an example of a system including an equalizer is shown. DETAILED DESCRIPTION

[0027] Hereinafter, embodiments of the present disclosure will be described in detail and clearly so that a person having ordinary skill in the art can easily perform the present disclosure.

[0028] In the detailed description, components described with reference to terms such as "part", "unit", "module", "block", etc. and functional blocks shown in the drawings will be implemented in software, hardware, or a combination thereof. For example, software may be machine code, firmware, embedded code, and application software. For example, hardware may include circuits, electronic circuits, processors, computers, integrated circuits, integrated circuit cores, pressure sensors, inertial sensors, micro-electromechanical systems (MEMS), passive components, or a combination thereof.

[0029] Figure 1 is a block diagram showing a configuration of an example of an electronic system 1000 including an equalizer.

[0030] The electronic system 1000 includes a first device 1100 and a second device 1300. In some implementations, each of the devices 1100 and 1300 is implemented with one of various electronic devices such as a smart phone, a wearable device, a memory device, a desktop computer, a laptop computer, a video game console, a home appliance, and a medical device.

[0031] However, the present disclosure is not limited thereto. In some embodiments, the electronic system 1000 may be implemented with a single device. In the above implementations, each of the devices 1100 and 1300 may be a component included in a single device and may be implemented with a circuit, module, chip, and / or package-level entity. The terms "system" and "device" are provided for better understanding and are not intended to limit the present disclosure.

[0032] Devices 1100 and 1300 may communicate with each other and may exchange data / signals through a communication channel 1200. Communication channel 1200 may include a conductive material for transmitting data / signals. For example, communication channel 1200 may be implemented with a trace pattern on a printed circuit board (PCB), a conductive line of a cable, a metal pin / pad of a connector, etc.

[0033] The first device 1100 may include a receiver 1110, an equalizer 1130, and a digital signal processor (DSP) 1150. Although not illustrated in the drawings, the first device 1100 may also include a functional circuit. The functional circuit may operate to provide a unique function of the first device 1100. For example, the functional circuit may include various components such as a processor (such as a central processing unit (CPU) or an application processor (AP)), a memory, an image sensor, and a display. The second device 1300 may include a transmitter 1310 and an equalizer 1330.

[0034] Devices 1100 and 1300 may be implemented with independent (or separate) components or devices. Therefore, when viewed from the perspective of the second device 1300, the first device 1100 may be an external device, and when viewed from the perspective of the first device 1100, the second device 1300 may be an external device.

[0035] The receiver 1110 may receive a signal through the communication channel 1200, and may provide the received signal to the equalizer 1130. The receiver 1110 may include an electrostatic discharge circuit for protecting the first device 1100 from a sudden voltage change (eg, static electricity).

[0036] The equalizer 1130 may generate a signal S4 by performing equalization on a signal received from the receiver 1110. The equalizer 1130 may provide the signal S4 to the DSP 1150. The equalizer 1130 may also be referred to as a "RX equalizer."

[0037] The equalizer 1330 may receive the signal S1 and may perform equalization. For example, the signal S1 may be a signal received from outside the second device 1300, may be a signal stored in the second device 1300, or may be a signal processed by the second device 1300. The equalizer 1330 may provide the equalized signal to the transmitter 1310. The equalizer 1330 may also be referred to as a “TX equalizer”. The transmitter 1310 may provide a signal to the first device 1100 through the communication channel 1200.

[0038] In the above manner, each of the devices 1100 and 1300 can transmit / receive signals through the communication channel 1200. When the communication speed between the devices 1100 and 1300 increases (for example, when communication is performed at a higher frequency or with a larger bandwidth), the devices 1100 and 1300 can exchange a large amount of data during a unit time.

[0039] However, due to various factors such as skin effect and dielectric loss, the communication channel 1200 may show a low-pass frequency response characteristic. Therefore, in high-speed operation, the bandwidth of the communication channel 1200 may be limited and may therefore be less than the bandwidth of the signal. In this case, the high-frequency component of the signal transmitted through the communication channel 1200 may be weakened, resulting in inter-symbol interference in the time domain. As a result, as the speed of transmitting the signal becomes higher, the distortion of the signal may become more serious, and the quality of the signal may become worse. In this article, a symbol may refer to one or more bits of data, each bit having a specific logical value.

[0040] To compensate for the unexpected distortion of the signal, the equalizers 1130 and 1330 may perform equalization on the signal. Specifically, the configuration and operation of the equalizer 1130 of the present disclosure, which processes the signal received from the receiver 1110, will be described in detail with reference to the following drawings.

[0041] Figure 2 and Figure 3 It is shown by Figure 1 1200. It will be appreciated that the signal transmitted through the communication channel 1200 is distorted similar to the process described below.

[0042] For better understanding, in the following description, it is assumed that the electronic system 1000 processes a signal in a four-level pulse amplitude modulation (PAM-4) manner. However, it can be understood that the implementation can be changed or modified to process any other manner of signal (e.g., PAM-8, PAM-16 or NRZ (non-return to zero)).

[0043] Signal S2 has Figure 2 The waveform shown. In this document, the horizontal direction of the waveform is associated with time, and the vertical direction of the waveform is associated with a signal level (eg, a voltage level).

[0044] The waveform of the signal S2 shows that the signal S2 is generated to sequentially have signal levels corresponding to logic "0", logic "1", and logic "0". When the signal S2 is transmitted from the transmitter 1310 to the first device 1100 through the communication channel 1200, the signal S2 is distorted due to the characteristics of the communication channel 1200. For example, the waveform of the signal S3 output from the receiver 1110 after the signal S2 is input to the first device 1100 is different from the waveform of the signal S2.

[0045] Signal S2 has Figure 3 The waveform of signal S2 shows that signal S2 is generated to sequentially have signal levels corresponding to logic "0", logic "1", logic "1", and logic "0". When signal S2 is transmitted from transmitter 1310 to first device 1100 through communication channel 1200, each symbol corresponding to logic "1" is distorted due to the characteristics of communication channel 1200 and corresponds to signals S3a and S3b, respectively.

[0046] Signals S3a and S3b may affect each other in the time domain (i.e., may experience inter-symbol interference); in this case, signal S3 may be distorted. For example, the waveform of signal S3 output from receiver 1110 after signal S2 is input to first device 1300 may be different from the waveform of signal S2.

[0047] As described above, when a signal is transmitted / received through the communication channel 1200, the waveform of the signal may be distorted unintentionally. For this reason, incorrect data may be exchanged between the devices 1100 and 1300, and unexpected errors may occur in the operation of the devices 1100 and 1300. This may mean that the electronic system 1000 becomes unstable. Equalizers 1130 and 1330 may be used to compensate for the distortion of the signal.

[0048] Figure 4 It is shown Figure 1 An example block diagram of a configuration of a first device 1100 is shown.

[0049] The first device 1100 includes an equalizer 1130 and a DSP 1150. The equalizer 1130 includes a continuous time linear equalizer (CTLE) 1131, a successive approximation register analog-to-digital converter (SAR-ADC) 1132, a phase interpolator 1133, and a clock distributor 1134. The DSP 1150 includes a decision feedback equalizer (DFE) 1151.

[0050] The CTLE 1131 may receive an input signal through the communication channel 1200 and may remove unnecessary frequency components of the input signal. The CTLE 1131 may operate as a high-pass filter for the purpose of compensating for the low-pass frequency response characteristics. That is, the CTLE 1131 may reduce low-frequency distortion caused in the communication channel 1200.

[0051] In some embodiments, the CTLE 1131 may be implemented with a passive CTLE or an active CTLE. For example, when the CTLE 1131 is implemented with a passive CTLE, the CTLE 1131 may include passive elements, such as at least one resistor and at least one capacitor. For example, when the CTLE 1131 is implemented with an active CTLE, in addition to the resistor, the CTLE 1131 may also include active elements, such as a transistor. However, the present disclosure is not limited thereto. For example, the CTLE 1131 may be implemented with various elements for compensating for the low-pass frequency response characteristics of the communication channel 1200.

[0052] The SAR-ADC 1132 may be configured to generate a digital signal S4 by quantizing the signal S3 in a binary search manner. The SAR-ADC 1132 may include a plurality of sample and hold circuits 1141 and a plurality of ADCs 1145 in order to efficiently process signals received at a high speed.

[0053] For the purpose of performing time interleaving, the sampling and holding circuit 1141 can sample and hold the signal S3a at a given timing. For example, the sampling and holding circuit 1141 can sample and hold the signal S3a at different time points. After sampling and holding the signal S3a, each sampling and holding circuit can provide a sampled value to the corresponding ADC. ADC1145 can receive the sampled value from the sampling and holding circuit 1141, and can generate a signal S4 by quantizing the sampled value based on a binary search method.

[0054] In some embodiments, the first device 1100 of the present disclosure may not generally include a separate feed-forward equalizer (FFE) disposed outside the SAR-ADC (or inside the DSP). On the contrary, each of the ADC 1145 may be configured to perform the function of the FFE. To this end, each of the ADC 1145 may include a plurality of taps, each of which includes a plurality of capacitors, and the plurality of taps may sample the input voltage (i.e., the output of the sample and hold circuit 1141) at different time points. In this case, at least some of the capacitors of each tap may be implemented as participating in the sampling, and the weight applied to the sampling performed by each tap may be set differently for each tap. Each of the ADC 1145 may sum the sampling results to which the weights are applied, and the summed sampling results may have a higher resolution than the resolution of the sampling performed by one tap (i.e., the FFE coefficient). Each of the ADC 1145 may output a digital signal (i.e., S4) based on the summation result.

[0055] According to the above configuration and operation, in analog-to-digital conversion, since the mutual influence of signals received at different time points is taken into account, the same effect as that of performing FFE in the SAR-ADC 1132 can be achieved. That is, even if FFE is not separately provided outside the SAR-ADC 1132, since the same effect as that of FFE provided in the SAR-ADC 1132 is achieved, the circuit size can be reduced, and power consumption can also be reduced. The SAR-ADC 1132 of the present disclosure will be described in detail with reference to the following drawings.

[0056] The phase interpolator 1133 may generate clocks of different phases based on the clock CLK. The clock distributor 1134 may receive clocks of different phases from the phase interpolator 1133, and may distribute clocks required for the operation of the sampling and holding circuit 1141 and the ADC 1145. Meanwhile, although not shown in the drawings, in order to obtain a clock having an appropriate frequency required for the operation of the phase interpolator 1133, the equalizer 1130 may further include a frequency divider for dividing the clock CLK.

[0057] The DFE 1151 may apply a weight to each of the previous symbol, the current symbol, and the next symbol for the purpose of removing inter-symbol interference from the signal S4.

[0058] at the same time, Figure 4 The illustrated implementation is provided as an example. In some implementations, the equalizer 1130 may not include the CTLE 1131 and / or the DFE 1151. Although not shown in the drawings, the DSP 1150 may also include a clock and data recovery (CDR) circuit that recovers clock and data from the signal S4 output from the equalizer 1130.

[0059] Figure 5 It is shown Figure 4 An example block diagram of a configuration of the SAR-ADC 1132 is shown.

[0060] SAR-ADC 1132 includes sample and hold circuits 1141-1 to 1141-m and ADCs 1145-1 to 1145-m. Each of ADCs 1145-1 to 1145-m includes a capacitive digital-to-analog converter (C-DACs), a successive approximation register (SAR) logic circuit, and a comparator (COMP). In some implementations, the first ADC 1145-1 includes a first C-DAC 1146-1, a first comparator 1147-1, and a first SAR logic circuit 1148-1. The remaining ADCs 1145-2 to 1145-m have a configuration similar to that of the first ADC 1145-1.

[0061] refer to Figure 5 , the sampling and holding circuits 1141-1 to 1141-m can sample the signal S3a based on the clocks CLK1 to CLKm having different phases. As a result, the sampling and holding circuits 1141-1 to 1141-m can sequentially latch the signal S3a at the enable timing of the clocks CLK1 to CLKm, and can sequentially generate sampling values ​​SV1 to SVm. The sampling and holding circuits 1141-1 to 1141-m can hold the sampling values ​​SV1 to SVm. The sampling and holding circuits 1141-1 to 1141-m can sequentially output the sampling values ​​SV1 to SVm, and the sampling values ​​SV1 to SVm can be respectively input to the ADCs 1145-1 to 1145-m as input voltages.

[0062] Each of the ADCs 1145-1 to 1145-m can convert an analog signal into a digital signal based on a sampling value (i.e., one of the sampling values ​​SV1 to SVm). Alternatively, each of the ADCs 1145-1 to 1145-m can perform analog-to-digital conversion based on a plurality of sampling values ​​(i.e., at least two of the sampling values ​​SV1 to SVm), and can simultaneously perform the function of a feed-forward equalizer (FFE).

[0063] In some embodiments, the first C-DAC 1146-1 may include a plurality of taps, each of which includes a plurality of capacitors. The taps of the first C-DAC 1146-1 may respectively sample input voltages sampled by the sampling and holding circuit at different time points. For example, the first tap of the first ADC 1145-1 may perform sampling based on the input voltage received from the first sampling and holding circuit 1141-1. The second tap of the first ADC 1145-1 may perform sampling based on the input voltage received from the second sampling and holding circuit 1141-2.

[0064] In some embodiments, sampling of the input voltage may be performed by at least some of the capacitors of the first C-DAC 1146-1. To this end, the first SAR logic circuit 1148-1 may individually control switches of the capacitors connected to the first C-DAC 1146-1. In some embodiments, the first SAR logic circuit 1148-1 may generate a control signal by using a digital value (i.e., the output of the first SAR logic circuit 1148-1) in a previously performed successive approximation operation, which allows at least some of the capacitors of the first C-DAC 1146-1 to participate in the sampling. Therefore, some of the capacitors of the first C-DAC 1146-1 may participate in the sampling.

[0065] In some embodiments, the sum of the capacitances of the capacitors participating in sampling among the capacitors of the first tap of the first C-DAC 1146-1 may be different from the sum of the capacitances of the capacitors participating in sampling among the capacitors of the second tap of the first C-DAC 1146-1. For example, the difference in the sums may be semantically considered as different weights (i.e., FFE coefficients) being applied to sampling operations of different taps. However, the present disclosure is not limited thereto. In some embodiments, the sums of the capacitances may be equal to each other.

[0066] The first SAR logic circuit 1148-1 can control the tap of the first C-DAC 1146-1 so that charge sharing occurs. The total amount of shared charge can correspond to the sum of the values ​​obtained by multiplying the voltage input at different time points with the weight. That is, the total amount of shared charge can correspond to the result value obtained by the execution of the FFE filter, and the coefficient of the FFE filter can indicate the sum of the capacitances of the capacitors participating in the sampling among the capacitors of each C-DAC. In other words, the operation of performing charge sharing after the tap sampling of the input voltage sampled at different time points by the sampling and holding circuit can be substantially the same as the operation of performing feedforward equalization.

[0067] The first comparator 1147-1 may compare a voltage corresponding to the amount of charge accumulated at each tap with a reference voltage, and may sequentially output digital values ​​corresponding to the taps respectively as comparison results. A voltage corresponding to the amount of charge accumulated at all taps may be input to a first terminal of the first comparator 1147-1, and a reference voltage may be input to a second terminal of the first comparator 1147-1. The reference voltage input to the first comparator 1147-1 may be a ground voltage (reference voltage). Figure 6 ), but the present disclosure is not limited thereto.

[0068] The first SAR logic circuit 1148-1 may generate a multi-bit digital signal S4 by performing a successive approximation operation based on the digital value received from the first comparator 1147-1. The value of the digital signal S4 may be stored in a register included inside (or outside) the first SAR logic circuit 1148-1. The first SAR logic circuit 1148-1 may output the digital signal S4 to an external device (e.g., Figure 4 The DSP 1150 of the embodiment may control the first C-DAC 1146-1 based on the digital signal S4 so that at least some of the tapped capacitors of the first C-DAC 1146-1 participate in sampling.

[0069] As described above, since analog-to-digital conversion is performed by using the above-mentioned manner of applying different weights to input voltages provided at different time points, the FFE function of removing distortion due to inter-symbol interference can be performed by the first ADC 1145-1. In addition, in order to more effectively remove the distortion due to inter-symbol interference, the first ADC 1145-1 can further use the third sampling value SV3. In some embodiments, the first ADC 1145-1 can also use the fourth sampling value SV4.

[0070] Figure 6 It is shown Figure 5 An example timing diagram of the operation of the sample and hold circuit 1141.

[0071] For better understanding, it is assumed that "m" is 10, and it is assumed that the frequency of the clock (eg, CLK1) output from the clock distributor 1134 is half the frequency of the clock CLK, as shown in FIG. Figure 6 In this case, the clock CLK1 may be input to the sampling and holding circuits 1141-1, 1141-5, and 1141-9, the clock CLK2 may be input to the sampling and holding circuits 1141-2, 1141-6, and 1141-10, the clock CLK3 may be input to the sampling and holding circuits 1141-3 and 1141-7, and the clock CLK4 may be input to the sampling and holding circuits 1141-4 and 1141-8.

[0072] At the first time point t1, the first sampling and holding circuit 1141-1 can sample the signal S3a to generate a first sampling value SV1. As described above, at the second time point t2, the second sampling and holding circuit 1141-2 can sample the signal S3a to generate a second sampling value SV2; at the third time point t3, the third sampling and holding circuit 1141-3 can sample the signal S3a to generate a third sampling value SV3; and at the fourth time point t4, the fourth sampling and holding circuit 1141-4 can sample the signal S3a to generate a fourth sampling value SV4. Figure 6 An example in which the first sample value SV1 is output after the fourth time point t4 is shown in FIG. This can be understood as outputting the first sample value SV1 after the sampling operation and the holding operation.

[0073] Figure 7 It is shown Figure 5 1 is an example circuit diagram of a configuration of a C-DAC. A circuit diagram of a first C-DAC 1146-1 is shown as an example, and the remaining C-DACs 1146-2 to 1146-m also have the same structure as the first C-DAC 1146-1. For better understanding, the first comparator 1147-1 and the first SAR logic circuit 1148-1 are shown together.

[0074] The first C-DAC 1146-1 may include a plurality of taps, and each tap of the first C-DAC 1146-1 may include a plurality of capacitors and a plurality of switches. In some embodiments, the first C-DAC 1146-1 may include taps TAB1 to TAB4, and the first tap TAB1 may include capacitors C11 to C16 and switches SW11 to SW16. As shown, a capacitor (e.g., C11) and a switch (e.g., SW11) corresponding to the capacitor may be connected in series, which is referred to as a "switched capacitor". The expression "controlling a switched capacitor" may mean controlling a switch (e.g., SW11) connected to a capacitor (e.g., C11). In some embodiments, the number of taps is not limited to the above examples, and the number of switched capacitors included in each tap is not limited to the above examples.

[0075] Meanwhile, the number of capacitors of each tap may be associated with the number of bits of output data of the ADC (i.e., the resolution of the ADC). In some embodiments, the condition "Ci+1=2×Ci and C11=C12" (i is an integer between 12 and 15) may be established between the capacitances of capacitors C11 to C16, and Figure 7 The capacitors C11 to C16 can be implemented to sample 5-bit data. This can be considered that the first tap TAB1 has a resolution corresponding to a 5-bit FFE coefficient. For example, when the capacitance of the capacitor C11 is 1pF, the capacitances of the capacitors C12 to C16 can be 1pF, 2pF, 4pF, 8pF, and 16pF, respectively.

[0076] In addition, the number of taps connected to the first input terminal of the first comparator 1147-1 may be associated with the number of bits of the result of the successive approximation operation (ie, S4). Figure 7 As shown, when four taps are connected to the first input terminal of the first comparator 1147-1, the value of the digital signal S4 can consist of 7 bits.

[0077] The switch SW10 may be connected between the first tap TAB1 and the first comparator 1147-1, and the switch SW17 may be connected between the first tap TAB1 and the ground terminal. The switch SW10 may participate in charge sharing with the remaining taps TAB2 to TAB4, and the switch SW17 may participate in sampling.

[0078] The switches SW11 to SW16 and the switches SW10 and SW17 can be individually controlled by the switch control signal CTRL_SW generated by the first SAR logic circuit 1148-1. Each of the capacitors C11 to C16 can be selectively connected to one of the first input voltage SV1, the reference voltage Vref, and the ground voltage through the corresponding switch in the switches SW11 to SW16. The first tap TAB1 can be connected to the ground terminal through the switch SW17, or can be connected to the first input terminal of the first comparator 1147-1 through the switch SW10.

[0079] The first comparator 1147-1 can compare the voltage corresponding to the amount of charge accumulated at the taps TAB1 to TAB4, and can output digital values ​​sequentially. The first input terminal of the first comparator 1147-1 can be selectively connected to the taps TAB1 to TAB4 through switches SW10, SW20, SW30 and SW40, and the second input terminal of the first comparator 1147-1 can be connected to a reference voltage. For example, the reference voltage can be a ground voltage, but the present disclosure is not limited thereto. For example, the reference voltage can be a positive voltage or a negative voltage.

[0080] The first SAR logic circuit 1148-1 can perform a successive approximation operation based on the digital value received from the first comparator 1147-1, and can output a multi-bit digital signal S4. The first SAR logic circuit 1148-1 can generate a switch control signal CTRL_SW based on the digital value (i.e., S4) generated in the previous successive approximation operation. Since the switches SW11 to SW16 of the first tap TAB1 are controlled by the switch control signal CTRL_SW, some of the capacitors C11 to C16 can participate in sampling the first input voltage SV1.

[0081] The operation of the remaining taps TAB2 to TAB4 may be similar to the above-described operation associated with the first tap TAB1. However, according to the present disclosure, in order to Figure 4 ), the switch control timing of the taps TAB1 to TAB4 may be different. For example, after the first input voltage SV1 is sampled by using the first tap TAB1, the second input voltage SV2 may be sampled by using the second tap TAB2. As described above, after the second input voltage SV2 is sampled, the input voltages SV3 and SV4 may be sampled sequentially.

[0082] Figure 8 It is shown Figure 7 An example flow chart of the operation of a SAR-ADC. Fig. 9 , Fig.11 , Fig.12 and Fig.13It is shown Figure 7 An example circuit diagram of the operation of the C-DAC with corresponding states. Fig.10 FIG. 1 is an example diagram showing how a SAR logic circuit generates a switch control signal. Figures 8 to 13 The operation of a SAC-ADC performing feed-forward equalization is described.

[0083] refer to Figure 8 and Fig. 9 , the first tap TAB1 is from a sample and hold circuit (e.g., Figure 5 One of the first taps 1145-1 to 1145-m) receives a sampled value as an input voltage (S110). In some implementations, first, the first tap TAB1 receives a first input voltage (ie, a first sampled value SV1) from the first sampling and holding circuit 1141-1.

[0084] Next, the first input voltage SV1 is sampled by using at least some of the capacitors of the first tap TAB1. The first SAR logic circuit 1148-1 controls the switches SW11 to SW16 so that at least some of the capacitors C11 to C16 participate in the sampling. For example, the first SAR logic circuit 1148-1 generates a switch control signal CTRL_SW for individually controlling the switches SW11 to SW16.

[0085] In some embodiments, reference Fig. 9 and 10 , in order to select the capacitors involved in sampling, the first SAR logic circuit 1148-1 may utilize the digital value generated in the previous successive approximation operation (i.e., S4). For example, when each tap has a resolution corresponding to a 5-bit FFE coefficient, and when the first C-DAC 1146-1 includes Fig. 9 When the four taps are shown, the digital value S4 output from the first SAR logic circuit 1148-1 may consist of 7 bits. Here, the first SAR logic circuit 1148-1 may generate a switch control signal CTRL_SW for individually controlling the switches SW11 to SW16 based on the 7-bit digital value S4.

[0086] In some embodiments, the first SAR logic circuit 1148-1 may select at least some of the 7 bits of the digital value S4 to generate a 6-bit switch control signal CTRL_SW. For example, the most significant bit MSB of the switch control signal CTRL_SW may be used as a signal for controlling the switch SW16, and the least significant bit LSB of the switch control signal CTRL_SW may be used as a signal for controlling the switch SW1. For example, a bit value "1" may correspond to a value for turning on the switch SW16, and a bit value "0" may correspond to a value for turning off the switch SW11, but is not limited thereto.

[0087] In some implementations, the first SAR logic circuit 1148-1 may combine seven bits of the digital value S4 to generate a 6-bit switch control signal CTRL_SW. In this case, various combinations may be used to generate the 6-bit switch control signal CTRL_SW.

[0088] Some of the switches SW11 to SW16 may be selectively controlled so that the first input voltage SV1 is input to the first electrodes of the capacitors C11 to C16 corresponding to the selectively controlled switches. Fig. 9 An example in which the first input voltage SV1 is input to the first electrodes of the capacitors C13, C15, and C16 and the ground voltage is input to the first electrodes of the capacitors C11, C12, and C14 is shown.

[0089] By using the switch control signal CTRL_SW, the first SAR logic circuit 1148-1 may turn off the switch SW10 and may turn on the switch SW17. As a result, the second electrodes of the capacitors C11 to C16 may be connected to the ground terminal and may be electrically disconnected from the first input terminal of the first comparator 1147-1.

[0090] In some embodiments, when the voltage level of the first input voltage SV1 is Vin, the voltage level of the first node N1 may be Vin, and the voltage level of the second node N2 may be 0 V. Herein, the second node N2, which is a node commonly connected to the second ends of the capacitors C11 to C16 and connected to the first input terminal of the first comparator 1147-1, may be referred to as a "common node." The voltage difference of the opposite ends of each of the capacitors C13, C15, and C16 may be maintained at Vin until the switches SW10 to SW17 are individually controlled.

[0091] refer to Figure 8 and Fig.11 , the common node N2 is floated (S130). To this end, the first SAR logic circuit 1148-1 controls the switches SW13, SW15, and SW16 based on the switch control signal CTRL_SW, so that the first electrodes of the capacitors C13, C15, and C16 are connected to the ground terminal. At the same time, the first SAR logic circuit 1148-1 turns off the switch SW17 by using the switch control signal CTRL_SW.

[0092] According to the above switching operation, in the state where the voltage difference of the opposite ends of each of the capacitors C13, C15 and C16 is maintained at Vin, the voltage level of the first electrode of the capacitors C13, C15 and C16 can be reduced to 0V. This may mean that the law of conservation of charge is applied as it is. Because the difference between the voltage level of the node N3 and the voltage level of the second node N2 should maintain Vin, the voltage level of the second node N2 can be reduced from 0V to -Vin. That is, information about the sampling performed by the capacitors C13, C15 and C16 can be stored in the form of charge at the common node N2.

[0093] Meanwhile, for the convenience of description, the above floating operation is described as being similar to the reference Fig. 9 However, in a broad sense, the floating operation can be understood as a part of the sampling operation performed by some capacitors of the first tap TAB1.

[0094] return Figure 8 , in operation S140, receiving (S110), sampling (S120), and floating (S130) of the sampled value are repeatedly performed by at least one of the remaining taps TAB2 to TAB4.

[0095] For example, the second tap TAB2 can receive the second input voltage SV2 from the second sampling and holding circuit 1141-2. Fig. 9 In the above description given, the second tap TAB2 can receive the second input voltage SV2, can perform a sampling operation on the second input voltage SV2, and can be used in conjunction with the reference voltage SV2. Fig.11 Herein, the difference between the time point at which the first tap TAB1 receives the first input voltage SV1 and the time point at which the second tap TAB2 receives the second input voltage SV2 may correspond to the sampling period of the sampling and holding circuits 1141-1 to 1141-m (refer to Figure 5 ).

[0096] After sampling and floating of the second tap TAB2 are completed, the third tap TAB3 may perform sampling and floating based on the input voltage (ie, the third input voltage SV3 ), and then the fourth tap TAB4 may perform sampling and floating based on the fourth input voltage SV4 .

[0097] According to the operation S140 of repeated sampling and floating, the second tap TAB2 receives and samples the second input voltage SV2 delayed by up to the sampling period (i.e., T) relative to the first input voltage SV1. Next, the third tap TAB3 receives and samples the third input voltage SV3 delayed by up to the sampling period (i.e., T) relative to the second input voltage SV2, and the fourth tap TAB4 receives and samples the fourth input voltage SV4 delayed by up to the sampling period (i.e., T) relative to the third input voltage SV3.

[0098] In some embodiments, in the operation S140 of repeated sampling and floating, weights of the same value may be applied to the taps TAB1 to TAB4. In this case, the weights stored in Fig.10 The 6-bit value in the register of can be used to generate the switch control signal CTRL_SW without modification, and the taps TAB1 to TAB4 can have the same FFE coefficient. However, in some embodiments, in the operation S140 of repeated sampling and floating, weights of different values ​​can be applied to the taps TAB1 to TAB4. In this case, the 7-bit digital value (i.e., S4) can be selected to be the same as the one stored in the register. Fig.10 The 6-bit value in the register of , and at least some of the taps TAB1 to TAB4 may have the same FFE coefficient. Figure 8 and Fig.12 , charge redistribution can be performed between taps TAB1 to TAB4. The switches SW10, SW20, SW30 and SW40 connecting taps TAB1 to TAB4 with the first comparator 1147-1 can be turned on by switch control signal CTRL_SW. In this way, charge redistribution can be performed at nodes N2, N4, N6 and N8, and nodes N2, N4, N6 and N8 can have the same potential. In this article, the total amount of charge accumulated at nodes N2, N4, N6 and N8 for charge redistribution can be considered as the sum of the values ​​obtained by multiplying input voltage (that is, SV1, SV2, SV3 and SV4) and related weights. Because input voltage (that is, SV1, SV2, SV3 and SV4) corresponds to the data signals received at different timings, respectively, the total amount of shared charge can indicate the result of performing feed-forward equalization.

[0099] Although the switch SW30 and the node N6 are not shown in the drawings, the switch SW30 may be understood as a switch of the third tap TAB3 corresponding to the switch SW10 of the first tap TAB1. In addition, the node N6 may be understood as a node of the third tap TAB3 corresponding to the node N2 of the first tap TAB1.

[0100] refer to Figure 8 and Fig.13, the decision is performed by the first comparator 1147-1 (S160). For example, when performing the successive approximation operation, the first SAR logic circuit 1148-1 allows the switches SW11 to SW16 to be sequentially opened or closed by using the switch control signal CTRL_SW generated by the finite state machine FSM.

[0101] In detail, the switching of switches SW16, SW26, SW36, and SW46 may be performed to determine the most significant bit MSB of data corresponding to the charge accumulated at the first C-DAC1146-1. Depending on the switching of switches SW16, SW26, SW36, and SW46, capacitors C16, C26, C36, and C46 may be connected to a terminal to which a reference voltage Vref is applied. As a result, the potential of the second node N2 (or N4, N6, or N8) may be changed from -Vin to a voltage represented by the following equation.

[0102]

[0103] The first comparator 1147-1 can compare the voltage (ie, the voltage represented by the above equation) and the ground voltage to determine the MSB. For example, when the comparison result is greater than "0", the MSB can be determined as "1"; when the comparison result is less than "0", the MSB can be determined as "0".

[0104] In order to determine the center significant bit CSB and the least significant bit LSB, the same operation as above may be performed on the remaining switches. For example, in a state where the capacitor of each tap is connected to the ground terminal, the switches SW11, SW21, SW31, and SW41 may be controlled to be connected to the terminal to which the reference voltage Vref is applied, and the first comparator 1147-1 may compare the changed voltage of the second node N2 with the ground voltage to determine the LSB.

[0105] The first comparator 1147 - 1 may sequentially output comparison results to the first SAR logic circuit 1148 - 1 , and the first SAR logic circuit 1148 - 1 may output a multi-bit digital signal S4 based on the comparison results of the first comparator 1147 - 1 .

[0106] Fig.14 is a diagram showing an example of feed-forward equalization (FFE) performed by a SAR-ADC.

[0107] Fig.14 The SAR-ADC 1132 with reference Figure 4 and Figure 5 However, to simplify the description, Fig.14SAR-ADC 1132 including five sample and hold circuits 1141 - 1 to 1141 - 5 and five C-DACs 1146 - 1 to 1146 - 5 is shown in FIG.

[0108] At any time point before time point T1 (for example, Figure 6 At time point t1), the sampling and holding circuits 1141-1 to 1141-5 can perform sampling and holding on the signal S3a. As a result, each of the sampling and holding circuits 1141-1 to 1141-5 can obtain a desired value by sampling the signal S3a at a given timing. For example, the first sampling and holding circuit 1141-1 can obtain a first sampling value SV1. As described above, the sampling and holding circuits 1141-2 to 1141-5 can obtain sampling values ​​SV2, SV3, SV4, and SV5, respectively, by performing sampling at time points T2 to T5 (refer to Figure 6 ).

[0109] At time point T1, the first tap TAB1 of the first C-DAC 1146-1 may receive the first sample value SV1 as an input voltage, and may perform sampling and floating based on the first input voltage SV1. The sampling and holding may be performed with reference to Figures 9 to 11 In sampling and floating, the FFE coefficient of the first tap TAB1 can be applied to the sampled charge by controlling the switch so that at least some of the capacitors of the first tap TAB1 participate in sampling. As a sampling result, a charge whose amount corresponds to the first input voltage SV1 can be obtained.

[0110] At time point T2, the first C-DAC 1146-1 may receive the second sampling value SV2 as an input voltage, and may perform sampling and floating based on the second input voltage SV2. In addition, the second C-DAC 1146-2 may receive the second input voltage SV2 as an input voltage, and may perform sampling and floating based on the second input voltage SV2. As a result of the sampling, a charge whose amount corresponds to the second input voltage SV2 may be stored at each of the second tap TAB2 of the first C-DAC 1146-1 and the first tap TAB1 of the second C-DAC 1146-2.

[0111] At time point T3, each of the first to third C-DAC ADCs 1146-1 to 1146-3 may receive the third sample value SV3 as an input voltage, and may perform sampling and floating based on the third input voltage SV3. As a result of the sampling, a charge whose amount corresponds to the third input voltage SV3 may be stored at each of the third tap TAB3 of the first C-DAC 1146-1, the second tap TAB2 of the second C-DAC 1146-2, and the first tap TAB1 of the third C-DAC 1146-3.

[0112] At time point T4, the first C-DAC 1146-1 to the fourth C-DAC 1146-4 may receive the fourth sampling value SV4 as an input voltage, and may perform sampling and floating based on the fourth input voltage SV4. As a result of the sampling, a charge whose amount corresponds to the fourth input voltage SV4 may be stored at each of the fourth tap TAB4 of the first C-DAC 1146-1, the third tap TAB3 of the second C-DAC 1146-2, the second tap TAB2 of the third C-DAC 1146-3, and the first tap TAB1 of the fourth C-DAC 1146-4.

[0113] After storing charges corresponding to signals sampled and held at different time points at four taps of the first C-DAC 1146-1, at time point T5, the first C-DAC 1146-1 may perform charge sharing and decision. Fig.12 and Fig.13 Charge sharing and decision are performed in the same manner as described. The first C-DAC 1146-1 may output the determined bit as a digital value.

[0114] Thereafter, the first to fourth C-DACs 1146 - 1 to 1146 - 4 may sequentially perform sampling, charge sharing, decision, etc., and may sequentially output determined digital values.

[0115] Fig.15 is a flow chart showing an example of the operation of a SAR-ADC.

[0116] and Figure 8 The implementation methods are different. Fig.15 In the embodiment, the FFE functions of multiple ADCs are performed in parallel. In order to implement the SAR-ADC with FFE function of the present disclosure, at least two sampling and holding circuits and an ADC including at least two taps are required, so reference will be made to simplify Figure 5 The configuration implemented by the structure is used to describe the operation of the SAR-ADC.

[0117] refer to Figure 5and Fig.15 , in operation S210, a first input voltage SV1 may be generated by sampling an analog signal S3a using a first sample and hold circuit 1141-1.

[0118] In operation S220, the second input voltage SV2 may be generated by sampling the analog signal S3a using the second sample and hold circuit 1141-2. The time point at which the second input voltage SV2 is sampled may be different from the time point at which the first input voltage SV1 is sampled.

[0119] In operation S230, a third input voltage SV3 may be generated by sampling the analog signal S3a using the third sample and hold circuit 1141-3. The time point of sampling the third input voltage SV3 may be different from the time point of sampling the first input voltage SV1 and the time point of sampling the second input voltage SV2.

[0120] In operation S240, the first input voltage SV1 may be sampled by using the first tap TAB1 of the first ADC 1145-1. The first tap TAB1 may have an FFE coefficient corresponding to the capacitor involved in the sampling. Thereafter, in operation S250, the second input voltage SV2 may be sampled by using the second tap TAB2 of the first ADC 1145-1. In the first ADC 1145-1, each of the first tap TAB1 and the second tap TAB2 may have an FFE coefficient corresponding to the capacitor involved in the sampling.

[0121] In operation S260, the first ADC 1145-1 can output a first multi-bit digital signal based on the sampling result of the first tap TAB1 and the sampling result of the second tap TAB2. For example, in the first ADC 1145-1, charge redistribution can be performed by allowing the output signal of the first tap TAB1 and the output signal of the second tap TAB2 to be short-circuited. In this article, the total amount of charge stored at the first C-DAC 1146-1 of the first ADC 1145-1 corresponds to the sum of the input voltage SV1 of the first tap TAB1 by which the weight is multiplied and the input voltage SV2 of the second tap TAB2 by which the weight is multiplied. This can correspond to the result value obtained after FFE filtering.

[0122] Meanwhile, operations S240 to S260 performed by the first ADC 1145-1 may be performed in parallel in the second ADC 1145-2. For example, the second input voltage SV2 may be sampled (S270) by using the first tap TAB1 of the second ADC 1145-2, and the third input voltage SV3 may be sampled (S280) by using the second tap TAB2 of the second ADC 1145-2.

[0123] Afterwards, in operation S290, the second ADC 1145-2 can output a second multi-bit digital signal based on the sampling result of the first tap TAB1 and the sampling result of the second tap TAB2. For example, in the second ADC 1145-2, charge redistribution can be performed by allowing the output signal of the first tap TAB1 and the output signal of the second tap TAB2 to be short-circuited. In this article, the total amount of charge stored at the second C-DAC 1146-2 of the second ADC 1145-2 corresponds to the sum of the input voltage SV2 of the first tap TAB1 by which the weight is multiplied and the input voltage SV3 of the second tap TAB2 by which the weight is multiplied. This can correspond to the result value obtained after FFE filtering.

[0124] In some embodiments, the first multi-bit digital signal may be a digital signal corresponding to the first input voltage SV1, which is determined in consideration of interference with the second input voltage SV2. In addition, the second multi-bit digital signal may be a digital signal corresponding to the second input voltage SV2, which is determined in consideration of interference with the third input voltage SV3. That is, the first multi-bit digital signal and the second multi-bit digital signal may be signals from which inter-symbol interference is removed (i.e., they undergo feedforward equalization).

[0125] Fig.16 is a block diagram showing a configuration of an example of an electronic system 2000 including an equalizer.

[0126] The electronic system 2000 includes a first device 2100 and a second device 2300. In some implementations, each of the devices 2100 and 2300 is implemented with one of various electronic devices such as a smart phone, a wearable device, a desktop computer, a laptop computer, and a tablet computer.

[0127] The first device 2100 and the second device 2300 exchange signals through the channels 2210 and 2230. For example, the first device 2100 receives a signal from the second device 2300 through the first communication channel 2210 and transmits a signal to the second device 2300 through the second communication channel 2230.

[0128] The first device 2100 includes a receiver 2110, a transmit equalizer 2120, a receive equalizer 2130, a transmitter 2140, a DSP 2150, a serializer / deserializer (SER / DES) 2160, a CDR circuit 2170, and a functional circuit 2180. The second device 2300 includes a receiver 2310, a transmit equalizer 2320, a receive equalizer 2330, a transmitter 2340, a DSP 2350, a SER / DES 2360, a CDR circuit 2370, and a functional circuit 2380.

[0129] The receivers 2110 and 2310, the receiving equalizers 2130 and 2330, the DSPs 2150 and 2350, the CDR circuits 2170 and 2370, and the functional circuits 2180 and 2380 may be connected to the reference circuits. Figures 1 to 14 The components described correspond to the

[0130] The SER / DES 2360 may serialize the data generated according to the operation of the functional circuit 2380. The SER / DES 2360 may provide a signal S1 corresponding to the serialized data to the transmission equalizer 2320. The transmission equalizer 2320 may generate a signal S2 by performing pre-equalization on the signal S1. The transmitter 2340 may transmit the signal S2 to the first device 2100 through the first communication channel 2210.

[0131] The receiving equalizer 2130 may include performing a reference Figures 1 to 14 The SAR-ADC receiving the FFE function of the equalizer 2130 may output a multi-bit digital signal S4, and the DSP 2150 may perform additional equalization on the signal S4 by using the DFE. The DSP 2150 may output a signal S5 as a result of the equalization.

[0132] The SER / DES 2160 may deserialize the data received from the DSP 2150. The SER / DES 2160 may provide the deserialized data to the functional circuit 2180. The functional circuit 2180 may also operate according to the provided data.

[0133] As described above, the SER / DES 2160 may serialize the data generated according to the operation of the functional circuit 2180, and may provide the signal S6 to the transmission equalizer 2120. The transmission equalizer 2120 may generate the signal S7 by performing pre-equalization on the signal S6. The transmitter 2140 may transmit the signal S7 to the second device 2300 through the second communication channel 2230.

[0134] The receiver 2310 may provide a signal S8 to the receiving equalizer 2330 based on the signal received through the second communication channel 2230. The receiving equalizer 2330 including the SAR-ADC performing the FFE function of the present disclosure may generate a signal S9 by performing equalization on the signal S8. The CDR circuit 2370 may recover the clock and data from the signal S9. The DSP 2350 may provide the clock and data recovered by the CDR circuit 2370 to the SER / DES 2360.

[0135] SER / DES 2360 may deserialize the provided data. SER / DES 2360 may provide the deserialized data to functional circuit 2380. Functional circuit 2380 may also operate based on the provided data.

[0136] Fig.17 is a diagram of an example of a system 3000 including an equalizer.

[0137] The system 3000 includes a main processor 3100, a memory (e.g., 3200a and 3200b), and a storage device (e.g., 3300a and 3300b). In addition, the system 3000 includes at least one of an image capture device 3410, a user input device 3420, a sensor 3430, a communication device 3440, a display 3450, a speaker 3460, a power supply device 3470, and a connection interface 3480.

[0138] The main processor 3100 may control all operations of the system 3000, and more specifically, operations of other components in the system 3000. The main processor 3100 may be implemented as a general-purpose processor, a dedicated processor, or an application processor.

[0139] The main processor 3100 may include at least one CPU core 3110, and also include a controller 3120 configured to control memories 3200a and 3200b and / or storage devices 3300a and 3300b. In some embodiments, the main processor 3100 may also include an accelerator 3130, which is a dedicated circuit for high-speed data operations such as artificial intelligence (AI) data operations. The accelerator 3130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and may be implemented as a chip physically separated from other components of the main processor 3100.

[0140] Memories 3200a and 3200b may be used as main memory devices of the system 3000. Although each of the memories 3200a and 3200b may include volatile memory, such as static random access memory (SRAM) and / or dynamic RAM (DRAM), each of the memories 3200a and 3200b may include nonvolatile memory, such as flash memory, phase change RAM (PRAM) and / or resistive RAM (RRAM). The memories 3200a and 3200b may be implemented in the same package as the main processor 3100.

[0141] The storage devices 3300a and 3300b may be used as non-volatile storage devices configured to store data regardless of whether power is supplied thereto, and have a larger storage capacity than the memories 3200a and 3200b. The storage devices 3300a and 3300b may include storage controllers (STRG CTRL) 3310a and 3310b, respectively, and NVM (non-volatile memory) 3320a and 3320b configured to store data via the control of the storage controllers 3310a and 3310b. Although the NVM 3320a and 3320b may include a flash memory having a two-dimensional (2D) structure or a three-dimensional (3D) V-NAND structure, the NVM 3320a and 3320b may include other types of NVMs, such as PRAM and / or RRAM.

[0142] The storage devices 3300a and 3300b may be physically separated from the main processor 3100 and included in the system 3000 or implemented in the same package as the main processor 3100. In addition, the storage devices 3300a and 3300b may have various types of solid-state devices (SSDs) or memory cards, and may be removably combined with other components of the system 3000 through an interface such as a connection interface 3480 to be described below. The storage devices 3300a and 3300b may be devices to which a standard protocol is applied, such as universal flash storage (UFS), embedded multimedia card (eMMC), or non-volatile memory express (NVMe), but are not limited thereto.

[0143] The image capture device 3410 can capture still images or moving images. The image capture device 3410 may include a camera, a camcorder, and / or a webcam.

[0144] The user input device 3420 may receive various types of data input by a user of the system 3000 and include a touch pad, a keypad, a keyboard, a mouse, and / or a microphone.

[0145] The sensor 3430 may detect various types of physical quantities that may be obtained from the outside of the system 3000 and convert the detected physical quantities into electrical signals. The sensor 3430 may include a temperature sensor, a pressure sensor, an illumination sensor, a position sensor, an acceleration sensor, a biosensor, and / or a gyro sensor.

[0146] The communication device 3440 may transmit and receive signals between other devices outside the system 3000 according to various communication protocols. The communication device 3440 may include an antenna, a transceiver, and / or a modem.

[0147] Display 3450 and speaker 3460 may be used as output devices configured to output visual information and auditory information, respectively, to a user of system 3000 .

[0148] The power supply device 3470 may appropriately convert power supplied from a battery embedded in the system 3000 and / or an external power source, and supply the converted power to each component of the system 3000 .

[0149] The connection interface 3480 may provide a connection between the system 3000 and an external device that is connected to the system 3000 and can transmit and receive data to and from the system 3000. The connection interface 3480 may be implemented by using various interface schemes, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCIe), NVMe, IEEE 1394, Universal Serial Bus (USB) interface, Secure Digital (SD) card interface, MultiMediaCard (MMC) interface, eMMC interface, UFS interface, embedded UFS (eUFS) interface, and Compact Flash (CF) card interface.

[0150] In particular, the connection interface 3480 may include a physical layer for connecting with an external device, and the physical layer may include a SAR-ADC that performs the FFE function of the present disclosure.

[0151] According to the present disclosure, a successive approximation register analog-to-digital converter can be provided, which performs the function of a feedforward equalizer without a separate feedforward equalizer.

[0152] Therefore, since a separate feed-forward equalizer provided at the digital stage is generally not required, the chip size and power consumption can be reduced.

[0153] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of any invention or the scope that may be claimed, but as descriptions of features that may be specific to a particular implementation of a particular invention. Certain features described in this specification in the context of independent implementations can also be implemented in combination in a single implementation. On the contrary, the various features described in the context of a single implementation can also be implemented in multiple implementations individually or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations and even initially claimed as such, one or more features from the claimed combination may be deleted from the combination in some cases, and the claimed combination may be directed to a sub-combination or a variation of the sub-combination.

[0154] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A successive approximation register analog-to-digital converter, configured to perform a successive approximation operation, the successive approximation register analog-to-digital converter comprising: A first sample and hold circuit configured to sample the analog signal at a first time point and generate a first input voltage; a second sampling and holding circuit configured to sample the analog signal at a second time point and generate a second input voltage; as well as a first analog-to-digital converter comprising a first plurality of capacitors configured to sample a first input voltage and a second plurality of capacitors configured to sample a second input voltage, wherein the first analog-to-digital converter is configured to sample a first input voltage using at least some of the first plurality of capacitors and to sample a second input voltage using at least some of the second plurality of capacitors, and The first analog-to-digital converter is configured to output a first multi-bit digital signal based on a sum of a first charge and a second charge, the first charge corresponding to a sampling result of the first input voltage and the second charge corresponding to a sampling result of the second input voltage.

2. The successive approximation register analog-to-digital converter according to claim 1, comprising: a third sample and hold circuit configured to sample the analog signal and generate a third input voltage; as well as a second analog-to-digital converter comprising a third plurality of capacitors configured to sample a third input voltage, wherein the second analog-to-digital converter is configured to sample a third input voltage using at least some of the third plurality of capacitors, and The second analog-to-digital converter is configured to output a second multi-bit digital signal based on the sum of the second charge and the third charge, and the third charge corresponds to the sampling result of the third input voltage.

3. The successive approximation register analog-to-digital converter according to claim 1, wherein: The first analog-to-digital converter comprises: a first capacitive digital-to-analog converter comprising a first plurality of capacitors and a second plurality of capacitors; a comparator configured to compare the output of the first capacitive digital-to-analog converter with a first reference voltage and sequentially output a plurality of comparison results; and The first SAR logic circuit is configured to output a first multi-bit digital signal based on the plurality of comparison results.

4. The successive approximation register analog-to-digital converter according to claim 1, wherein: A first plurality of electrodes of the first plurality of capacitors are connected to the first node and a first plurality of electrodes of the second plurality of capacitors are connected to the second node, and Wherein, the first analog-to-digital converter comprises: a first plurality of switches respectively connected to a second plurality of electrodes of the first plurality of capacitors; a second plurality of switches respectively connected to a second plurality of electrodes of a second plurality of capacitors; a first comparator configured to compare voltages of the first node and the second node with a first reference voltage and sequentially output a plurality of comparison results; and The first SAR logic circuit is configured to output a first multi-bit digital signal based on the plurality of comparison results.

5. The successive approximation register analog-to-digital converter according to claim 4, wherein: The first successive approximation register logic circuit is configured to generate switch control signals that control the first and second pluralities of switches based on a multi-bit digital signal generated in a previously performed successive approximation operation.

6. The successive approximation register analog-to-digital converter according to claim 4, wherein: The first analog-to-digital converter comprises: a third plurality of switches configured to connect the first node to the first input terminal of the first comparator or to a ground terminal; and a fourth plurality of switches configured to connect the second node to the first input terminal of the first comparator or to a ground terminal, wherein the first SAR logic circuit is configured to generate switch control signals for controlling the first plurality of switches, the second plurality of switches, the third plurality of switches, and the fourth plurality of switches, wherein, under the control of the switch control signal, the first node is connected to the ground terminal and disconnected from the first input terminal of the first comparator, and Wherein, under the control of the switch control signal, at least some of the first plurality of capacitors are connected to the terminal to which the first input voltage is input.

7. The successive approximation register analog-to-digital converter according to claim 6, wherein: Under the control of the switch control signal, the first node is connected to the ground terminal and disconnected from the first input terminal of the first comparator, and Wherein, under the control of the switch control signal, at least some of the first plurality of capacitors are connected to the ground terminal.

8. The successive approximation register analog-to-digital converter according to claim 7, wherein: Under the control of the switch control signal, the second node is connected to the ground terminal and disconnected from the first input terminal of the first comparator, and Wherein, under the control of the switch control signal, at least some of the second plurality of capacitors are connected to the terminal to which the second input voltage is input.

9. The successive approximation register analog-to-digital converter according to claim 8, wherein: Under the control of the switch control signal, the second node is connected to the ground terminal and disconnected from the first input terminal of the first comparator, and Wherein, under the control of the switch control signal, at least some of the second plurality of capacitors are connected to the ground terminal.

10. The successive approximation register analog-to-digital converter according to claim 9, wherein: Under the control of the switch control signal, the first node and the second node are disconnected from the ground terminal and connected to the first input terminal of the first comparator.

11. The successive approximation register analog-to-digital converter according to claim 10, wherein: Under control of the switch control signal, a first capacitor selected from the first plurality of capacitors and a second capacitor selected from the second plurality of capacitors and corresponding to the first capacitor are connected to a terminal to which a second reference voltage is input, and The first comparator is configured to output a digital value based on voltage changes of the first node and the second node.

12. The successive approximation register analog-to-digital converter according to claim 11, wherein: The first analog-to-digital converter is configured to output a first multi-bit digital signal based on a successive approximation operation.

13. A successive approximation register analog-to-digital converter, comprising: a first sample and hold circuit configured to sample the analog signal to generate a first input voltage; a second sample and hold circuit configured to sample the analog signal to generate a second input voltage after the first input voltage is sampled; A first analog-to-digital converter including a first tap and a second tap, each of the first tap and the second tap including a plurality of switched capacitors; as well as a second analog-to-digital converter, a third tap and a fourth tap, each of the third tap and the fourth tap comprising a plurality of switched capacitors, The first tap is configured to sample the first input voltage at a first time point, The second tap is configured to sample the second input voltage at a second time point, The third tap is configured to sample the second input voltage at a second time point, and The first analog-to-digital converter is configured to output a first multi-bit digital signal based on a sum of a first charge and a second charge, the first charge corresponding to a sampling result of the first tap and the second charge corresponding to a sampling result of the second tap.

14. The successive approximation register analog-to-digital converter according to claim 13, comprising: a third sample and hold circuit configured to sample the analog signal to generate a third input voltage, The fourth tap is configured to sample the third input voltage at a third time point.

15. The successive approximation register analog-to-digital converter according to claim 14, wherein: The second analog-to-digital converter is configured to output a second multi-bit digital signal based on a sum of a third charge and a fourth charge, the third charge corresponding to a sampling result of the third tap and the fourth charge corresponding to a sampling result of the fourth tap.

16. The successive approximation register analog-to-digital converter according to claim 13, wherein: At least some of the plurality of switched capacitors of the first tap are configured to perform sampling of the first input voltage at a first point in time, and At least some of the plurality of switched capacitors of the second tap are configured to perform sampling of the second input voltage at a second time point.

17. The successive approximation register analog-to-digital converter according to claim 16, wherein: The first analog-to-digital converter is configured to generate a switching control signal that controls a plurality of switching capacitors of a first tap and a plurality of switching capacitors of a second tap based on a multi-bit digital signal generated in a previously performed successive approximation operation.

18. A method for operating a successive approximation register analog-to-digital converter, the method comprising: generating a first input voltage by sampling an analog signal at a first point in time using a first sample and hold circuit; generating a second input voltage by sampling the analog signal at a second time point using a second sample and hold circuit; sampling a first input voltage by using a first tap of a first analog-to-digital converter; sampling a second input voltage by using a second tap of the first analog-to-digital converter; sampling the second input voltage by using a third tap of the second analog-to-digital converter; as well as A first multi-bit digital signal is output based on the sampling result of the first tap and the sampling result of the second tap.

19. The method according to claim 18, comprising: generating a third input voltage by sampling the analog signal at a third time point using a third sample and hold circuit; sampling a third input voltage by using a fourth tap of the second analog-to-digital converter; as well as A second multi-bit digital signal is output based on the sampling result of the third tap and the sampling result of the fourth tap.

20. The method according to claim 19, wherein: Each of the first tap, the second tap, the third tap, and the fourth tap includes a plurality of switched capacitors, and Wherein, a plurality of switched capacitors are controlled based on a first multi-bit digital signal or a second multi-bit digital signal generated in a previously performed successive approximation operation.

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