Checker decoder circuit
By introducing school -testing circuits and weight correction circuits in the verification sub -decoder, the problem of the circuit area and time delay of traditional decoders when the code type becomes larger, and achieve efficient error correction.
Patent Information
- Application Number
- CN202311095142.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-07-26
- Filing Date
- 2023-08-29
- Publication Date
- 2025-01-28
AI Technical Summary
When the codeword becomes larger, the circuit area is large and the error checking time delay is large, making it difficult to achieve efficient error correction.
Designed a verification sub -decoder, including school testing circuit and weight correction circuit, to correct the error in the message level by calculating the school test and correcting the mask Essence
This design has achieved efficient correct corrections of large -size characters by reducing the area of the circuit and reducing power consumption, and improving the performance of the codeware.
Smart Images
Figure CN119382719A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a syndrome decoder circuit for performing syndrome decoding. Background Art
[0002] A conventional syndrome decoder will receive a codeword containing message bits and parity bits and then generate syndrome bits. The syndrome bits are essentially a pattern of errors from which the erroneous bits can be identified. In a typical scheme, if all syndrome bits are consistent with what is expected, then there are no errors in the codeword.
[0003] However, for conventional ECC syndrome decoders, as the number of message bits increases, the number of parity bits may also increase. As codewords become larger, conventional syndrome decoding schemes may become less practical because the circuit area may become considerable and the time delay due to error checking may be considerable. Therefore, a different decoding circuit that requires fewer inputs is needed to save circuit area and reduce power consumption. Summary of the invention
[0004] The present invention provides a syndrome decoder, the syndrome decoder comprising: a syndrome calculation circuit configured to receive K-bit message bits and P-bit parity bits to calculate S-bit syndrome bits; an X-bit weight correction circuit configured to receive a first number of multiple groups of S-bit syndrome bits and a first number of K-bit message bits to generate a first group of correction masks for the first number of K-bit message bits; and an X-1-bit weight correction circuit configured to receive a second number of multiple groups of S-bit syndrome bits and a second number of K-bit message bits to generate a second group of correction masks for the second number of K-bit message bits, wherein K, P and S are integers greater than 0, the first number of K-bit message bits includes the most significant bit of the K-bit message bits, and the first group of correction masks and the second group of correction masks are generated simultaneously, wherein the first number is not equal to the second number.
[0005] The present invention further provides a syndrome decoder, the syndrome decoder comprising: a syndrome calculation circuit configured to receive K-bit message bits and P-bit parity bits to calculate S-bit syndrome bits; an X-bit weight correction circuit configured to receive a first number of syndrome bits of multiple groups of S-bits and a first number of K-bit message bits to generate an X-1-bit enable signal and generate a first set of correction masks for the first number of K-bit message bits; and an X-1-bit weight correction circuit configured to receive a second number of syndrome bits of multiple groups of S-bits, a second number of K-bit message bits and an X-1-bit enable signal to generate an X-2-bit enable signal and generate a second set of correction masks for the second number of K-bit message bits, wherein K, P and S are integers greater than 0, the first number of K-bit message bits includes the most significant bit of the K-bit message bits, and the second number is less than the first number. BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Figure 1 A block diagram showing a syndrome encoder circuit and a syndrome decoder circuit according to an exemplary embodiment of the present invention;
[0007] Figure 2 The implementation of the syndrome matching circuit and the data correction circuit according to the exemplary embodiment of the present invention is shown;
[0008] Figure 3 A hardware diagram showing an X-bit weight correction circuit according to a first exemplary embodiment of the present invention;
[0009] Figure 4 An X-bit weight correction circuit according to a second exemplary embodiment of the present invention is shown;
[0010] Figure 5 A hardware diagram showing an X-bit weight correction circuit according to a second exemplary embodiment of the present invention;
[0011] Figure 6 A memory device having a syndrome encoder circuit according to an exemplary embodiment of the present invention is shown. DETAILED DESCRIPTION
[0012] Figure 1 A block diagram of a syndrome encoder circuit 101 and a syndrome decoder circuit 102 is shown. The syndrome encoder circuit 101 may include, but is not limited to, an encoding algorithm circuit 111 that receives K bits of original message bits (where D[0] is the least significant bit and D[K-1] is the most significant bit) to generate parity bits P0, P1, ..., Pp-1, etc. based on a known generator algorithm. The K bits of original message bits and the parity bits may be transmitted as a codeword via a transmitter. The codeword may include the K bits of original message bits and the P bits of parity bits appended to the end of the K bits of original message bits.
[0013] When the syndrome decoder circuit 102 receives the codeword, the codeword is decoded using the parity bits to recover the original message bits by correcting errors that may exist in the codeword. In detail, after the decoder receives the codeword, the codeword is generally received as a codeword containing K bits of message bits (e.g., Din[0], Din[1], ... Din[K-1]) and P bits of parity bits (e.g., P0, P1, ..., Pp-1, etc.). Assuming that no errors occurred during transmission, the K bits of message bits and the P bits of parity bits of the received codeword match the transmitted codeword with the original message bits (e.g., D[0], D[1], ... D[K-1]) and parity bits (e.g., P0, P1, ..., Pp-1, etc.).
[0014] The syndrome decoder circuit 102 may include a syndrome calculation circuit 121, a syndrome matching circuit 122, and a data correction circuit 123. Assuming that the number of S syndrome bits is equal to the number of P parity bits, the syndrome calculation circuit 121 calculates S syndrome bits (S0, S1, S2, ..., S1) from K message bits and P parity bits of the received codeword. S-1 After calculating the S-bit syndrome bits, the syndrome matching circuit 122 will receive the S-bit syndrome bits to detect one or more bit errors. Based on the S-bit syndrome bits, the syndrome matching circuit 122 will determine a set of correction masks (including multiple correction masks, such as Figure 2 The correction mask [0] ... correction mask [K-2], correction mask [K-1] shown in the figure, wherein each correction mask corresponds to each of the K-bit message bits. Each correction mask will indicate whether each of the corresponding K-bit message bits contains an error.
[0015] The data correction circuit 123 receives the result from the set of correction masks and the K message bits (e.g., Din[0], Din[1] ... Din[K-1]) from the check sub-matching circuit 122 to correct one of the message bits whose corresponding correction mask has indicated a bit error (if such a bit error exists). Figure 1 In the example, assuming that the first correction mask 131 corresponding to Din[0] indicates that there is no error and the second correction mask 132 corresponding to Din[1] indicates that there is an error, the data correction circuit 123 will flip the binary value of Din[1] to correct Din[1]. Subsequently, the data correction circuit 123 will output K bits of output message bits (e.g., Dout[0], Dout[1]...Dout[K-1]) that should be similar to the original message bits.
[0016] Figure 2A simple implementation of the syndrome matching circuit 122 and the data correction circuit 123 is shown in FIG. The syndrome matching circuit 122 will include a first plurality of logic gates 201, and each of the first plurality of logic gates 201 will receive all S syndrome bits. This means that all S syndrome bits (e.g., S0, S1, ... S S-1 ) will be input to each of the first plurality of logic gates 201 of the syndrome matching circuit 122. The purpose of the syndrome matching circuit 122 is to output a set of correction masks, where each correction mask indicates whether its corresponding bit contains an error. For K bits of message bits (e.g., Din[0], Din[1] ... Din[K-2], Din[K-1]), there will be K bits of correction masks (e.g., correction mask[0], correction mask[1] ... correction mask[K-2], correction mask[K-1]), where Din[0] corresponds to correction mask[0], Din[1] corresponds to correction mask[1], and so on. The data correction circuit 123 may include a second plurality of logic gates 202, which are designed to flip one of the input message bits in response to the correction mask corresponding to the one of the input message bits having indicated an error. By reducing the number of inputs to each of the logic gates of the syndrome matching circuit 122 , the implementation of the syndrome matching circuit 122 and the data correction circuit 123 may be further improved.
[0017] The present invention provides an embodiment that does not require all S-bit syndrome bits to be input into a logic gate (e.g., 201) to compare it with each of the K-bit input message bits. In this way, the area required for circuit layout can be reduced, and the power consumption required for calculation can be reduced. Figure 3In, for this exemplary embodiment, the circuit may include an X-bit weight correction circuit, an X-1-bit weight correction circuit, an X-2-bit weight correction circuit, and so on. All of the above weight correction circuits will perform weight correction at the same time. Assuming X=4 as an example, the 4-bit weight correction circuit may include a first plurality of AND gates 301 corresponding to a portion of the syndrome matching circuit 122 and a plurality of XOR gates 312 corresponding to a portion of the data correction circuit 123, and each of the first plurality of AND gates 301 will receive a first number of syndrome bits 304. When there is no error in the message bits Din[KM] to Din[K-1], the binary value of the first number of syndrome bits 304 is 0 or 1, and it is expected that not all are 1. The number of the first number of syndrome bits 304 is 4 bits. This means that generally speaking, each of the first plurality of AND gates 301 will receive a 4-bit input. For example, 4-bit syndrome bits whose values can be 1 can be selected from the S-bit syndrome bits to define the 4-bit syndrome bits 304. Each of the first plurality of AND gates 301 will also output a corresponding correction mask from correction mask [KM] to correction mask [K-1] to correct the corresponding bit in the input message bit. When there is no error in the message bits Din[KM] to Din[K-1], each of the first plurality of AND gates 301 is expected to output a binary value of 0 as the value of the correction mask [KM] and [K-1] in the first set of correction masks.
[0018] like Figure 3 As shown, in the first plurality of AND gates 301, AND gate 311 will receive 4 binary value inputs and thus output a correction mask [K-1]. If the correction mask [K-1] is 0, it means that Din[K-1], which happens to be the most significant bit, does not have any error. However, assuming that the correction mask [K-1] is 1, the correction mask [K-1] will flip the value of Din[K-1]. An XOR gate 312, which is part of the data correction circuit 123, will receive the correction mask [K-1] and Din[K-1]. According to the truth table of any typical XOR gate that receives a first input and a second input, a value of 1 for the first input will flip the value of the second input. This means that whenever the value of the correction mask [K-1] is 1, the XOR gate 312 will generate Dout[K-1] by flipping the binary value of Din[K-1]. The same principle also applies to Figure 3 All XOR gates in .
[0019] In addition, the X-1 bit weight correction circuit may include a second plurality of AND gates 302 corresponding to a portion of the syndrome matching circuit 122, each of the second plurality of AND gates 302 will receive a second number of syndrome bits 305, the second number of syndrome bits 305 may be 6, 7 or 8 syndrome bits, and when there is no error in the message bits Din[KN] to Din[KM-1], the binary value of the second number of syndrome bits 305 is expected to be 0 or 1. For each of the second plurality of AND gates 302, three of the input bits will not be inverted, while the remaining input bits will be inverted. Each of the second plurality of AND gates 302 may have input bits that are inverted as different groups. The exact design of the inversion may vary depending on the specific decoding algorithm utilized. However, similar to the first plurality of AND gates 301, the purpose of the second plurality of AND gates 302 is also to generate a correction mask with a binary value of 1 whenever the corresponding input bit has an error. Furthermore, when there is no error in the message bits Din[KN] to Din[KM-1], the second plurality of AND gates 302 are expected to output a binary value of 0 as the values of the correction masks [KN] and [KM-1] in the second set of correction masks.
[0020] In addition, the X-2 bit weight correction circuit may include a third plurality of AND gates 303 corresponding to a portion of the syndrome matching circuit 122, each of the third plurality of AND gates 303 will receive a third number of syndrome bits 306, the third number of syndrome bits 306 may be all of the S bits of syndrome bits, and when there is no error in the message bits Din[0] to Din[KN-1], the binary value of the third number of syndrome bits 306 is expected to be 0 or 1. For each of the third plurality of AND gates 303, two of the input bits will not be inverted, while the remaining input bits will be inverted. Each of the third AND gates 303 may have input bits that are inverted as different groups. The exact design of the inversion may vary depending on the specific decoding algorithm used. However, similar to the first plurality of AND gates 301 and the second plurality of AND gates 302, the purpose of the third plurality of AND gates 303 is also to generate a correction mask with a binary value of 1 whenever the corresponding input bit has an error. Furthermore, when there is no error in the message bits Din[0] to Din[KN-1], the third plurality of AND gates 303 are expected to output a binary value of 0 as the values of the correction masks [0] and [KN-1] in the third set of correction masks.
[0021] According to another exemplary embodiment, instead of performing all weight correction calculations simultaneously, the weight correction calculations may be performed in several stages. Figure 4 An embodiment of a syndrome matching circuit 122 and a data correction circuit 123 based on a continuous bit weight correction circuit is shown. The circuit has Y stages (Y is 3, for example), including an X-bit weight correction circuit, an X-1-bit weight correction circuit, and an X-2-bit weight correction circuit.
[0022] refer to Figure 4 , the X-bit weight correction circuit 401 is configured to receive a first number of syndrome bits 404 and a first continuous number 411 of a plurality of continuous bits in the K-bit message bits Din[0] to Din[K-1] (e.g., including message bits Din[KM] to Din[K-1]) to generate an enable signal 451 for the X-1-bit weight correction circuit and a first set of correction masks 412. Assuming X=4, the 4-bit weight correction circuit 401 will receive the first number of bits of 4 to correct the first continuous number 411 in the K-bit message bits Din[0] to Din[K-1]. Assuming K=128, the message bits will have 128 bits. Assuming that the number of bits of the first continuous number 411 is 16, the 4-bit weight correction circuit 401 will correct the first 16 bits in the message bits, and the first bit of the 16 bits is the most significant bit. Assuming no bit error is detected, the X-bit weight correction circuit 401 will output an enable signal 451 of logic 0 to enable the X−1-bit weight correction circuit 402 and output a first set of correction masks 412 corresponding to the first consecutive numbers 411 .
[0023] Next, the X-1-bit weight correction circuit 402 will be configured to receive a second number of syndrome bits 405, a second consecutive number 421 of a plurality of consecutive bits of the K-bit message bits Din[0] to Din[K-1] (e.g., including message bits Din[KN] to Din[KM-1]), and an enable signal 451 to generate an enable signal 452 for the X-2-bit weight correction circuit and a second set of correction masks 422. The second consecutive number 421 is a number that immediately follows the first consecutive number 411 and does not overlap with the first consecutive number 411. The X-1-bit weight correction circuit 402 is configured to correct one of the bits within the second consecutive number 421. Assuming that no bit error is detected, the X-1-bit weight correction circuit 402 will output an enable signal 452 of logic 0 to enable the X-2-bit weight correction circuit 403 and output a second set of correction masks 422 corresponding to the second consecutive number 421.
[0024] Next, the X-2 bit weight correction circuit 403 is configured to receive a third number of syndrome bits 406 and a third consecutive number 431 of a plurality of consecutive bits of the K-bit message bits Din[0] to Din[K-1] (e.g., including message bits Din[K-0] to Din[KN-1]) and an enable signal 452 to generate a third group of correction masks 432, wherein the third consecutive number 431 of the K-bit message bits Din[0] to Din[K-1] may include the least significant bit of the K-bit message bits. The third number of the S-bit syndrome bits may be X-2 bits (e.g., 2 bits). The third consecutive number 431 is a number immediately following the second consecutive number 421 and does not overlap with the second consecutive number 421. The X-2 bit weight correction circuit 403 is configured to correct one of the bits within the third consecutive number 431. Subsequently, the X-2 bit weight correction circuit 403 will output a third group of correction masks 432 corresponding to the third consecutive number 431.
[0025] In addition, the X-bit weight correction circuit 401 is configured to correct a corresponding one of the first consecutive numbers 411 of the K-bit message bits, and in response to one of the correction masks in the first set of correction masks 412 being detected, the enable signal 451 is triggered to change the logic level (change to logic 1) to disable the X-1-bit weight correction circuit 402. On the other hand, in response to the enable signal 451 of logic 0 having enabled the X-1-bit weight correction circuit 402, the X-1-bit weight correction circuit 402 will be configured to correct a corresponding one of the second consecutive numbers 421 of the K-bit message bits, and in response to one of the correction masks in the second set of correction masks 422 being detected, the X-2-bit enable signal 452 is triggered to change the logic level (change to logic 1) to disable the X-2-bit weight correction circuit 403. Similarly, in response to the X-2-bit weight correction circuit enable signal 452 having enabled the X-2-bit weight correction circuit 403, the X-2-bit weight correction circuit 403 will be configured to correct a corresponding one of the third consecutive numbers 431 of K-bit message bits.
[0026] exist Figure 5 This is described in more detail in Figure 4 The circuit shown. Figure 5 A possible implementation of an X-bit weight correction circuit 501 (ie, 401), an X-1-bit weight correction circuit 502 (ie, 402), and an X-2-bit weight correction circuit 503 (ie, 403) is shown. For the X-bit weight correction circuit 501, the structure is the same as Figure 3 Similarly, where AND gate 521 corresponds to AND gate 311 and XOR gate 522 corresponds to XOR gate 312, each of AND gates 521 will receive the first number of syndrome bits 591, so the principle operation is not repeated.
[0027] The X-1 bit weight correction circuit 502 includes a plurality of NAND gates 531, and each of the NAND gates will receive the second number of syndrome bits 592, and for each of the inputs of the X-1 bit weight correction circuit 502, there is a NOR gate 532 located between the NAND gate 531 and the XOR gate 533. The purpose of the NOR gate 532 is to receive the W4_ERR signal 511, which disables the X-1 bit weight correction circuit 502 in response to the X-bit weight correction circuit 501 having detected an error. The W4_ERR signal 511 is the same as the signal previously described in the embodiment of the present invention. Figure 4 The W4_ERR signal 511 is the same as the enable signal 451 of the X-1 bit weight correction circuit described in . The W4_ERR signal 511 is output from the first OR gate 594, which receives all the correction masks from the correction mask [KM], the correction mask [K-2], and the correction mask [K-1]. This means that if any of the correction masks has a binary value of 1, the W4_ERR signal 511 also has a binary value of 1, which will invalidate the effect of the correction mask and cause the output of the NOR gate 532 to be 0.
[0028] The X-2 bit weight correction circuit 503 includes a plurality of NAND gates 541 and each of the NAND gates will receive a third number of syndrome bits 593. For each of the X-2 bit weight syndrome bit inputs, there is a NOR gate 542 located between the NAND gate 541 and the XOR gate 543. The purpose of the NOR gate 542 is to receive the W4_ERR signal 511 and the W3_ERR signal 512, which are respectively responsive to the X-bit weight correction circuit 501 and the X-1 bit weight correction circuit 502 having detected an error to disable the X-2 bit weight correction circuit 503. The W3_ERR signal 512 is the same as the W4_ERR signal 511 and the W3_ERR signal 512 previously described. Figure 4 The W3_ERR signal 512 is the same as the enable signal 452 of the X-2 bit weight correction circuit described in . The W3_ERR signal 512 is output from the second OR gate 596, and the second OR gate 596 receives all correction masks from the correction mask [KN], the correction mask [KM-2], and the correction mask [KM-1]. This means that if any of the correction masks has a binary value of 1, the W3_ERR signal 512 also has a binary value of 1, which will invalidate the effect of the correction mask and cause the output of the NOR gate 542 to be 0. This means that if the X-bit weight correction circuit 501 or the X-1 bit weight correction circuit 502 has detected an error, the X-2 bit weight correction circuit 503 will not correct any bit errors.
[0029] The present invention provides a Figure 6600 is shown with a syndrome decoder circuit 602. For a typical memory device (e.g., 600), the syndrome decoder circuit (e.g., 602) may be implemented as part of a memory controller 601. However, the syndrome decoder circuit may also be implemented as a component in other parts of a memory device or a component in any other electronic device where bit errors need to be corrected. The memory device 600 may include, but is not limited to, a memory controller 601 electrically connected to a memory bank 604 and an input / output (I / O) interface 603. The I / O interface 603 is configured to receive data that may be in the form of a received codeword for storage and is configured to transmit data that has been stored in the memory bank 604. The memory bank 604 is configured to store data in a non-volatile manner. The memory controller 601 is configured to control the I / O interface 603 and the memory bank 604 and includes a syndrome decoder circuit 602. The details of the syndrome decoder circuit 602 have been described and therefore need not be repeated.
[0030] In summary, the present invention is applicable to any memory device having a decoder that requires less circuit area and is capable of correcting errors with reduced power consumption.
Claims
1. A syndrome decoder circuit, comprising: The syndrome calculation circuit is configured to receive K message bits and P parity bits to calculate S syndrome bits, an X-bit weight correction circuit configured to receive a first number of the S-bit syndrome bits and a first number of the K-bit message bits to generate a first set of correction masks for the first number of the K-bit message bits, and an X-1-bit weight correction circuit configured to receive a second number of the S-bit syndrome bits and a second number of the K-bit message bits to generate a second set of correction masks for the second number of the K-bit message bits, wherein K, P and S are integers greater than 0, the first number of the K-bit message bits includes the most significant bit of the K-bit message bits, and the first set of correction masks and the second set of correction masks are generated simultaneously, Wherein the first number is not equal to the second number.
2. The syndrome decoder circuit according to claim 1, further comprising: an X-2 bit weight correction circuit configured to receive a third number of the plurality of groups of the S bits of syndrome bits and a third number of the K bits of message bits to generate a third group of correction masks for the third number of the K bits of message bits, wherein the third number of the K bits of message bits includes the least significant bit of the K bits of message bits and the third group of correction masks is generated simultaneously with the first group of correction masks and the second group of correction masks, Wherein the third number is not equal to the second number.
3. The syndrome decoder circuit of claim 1 , wherein the X-bit weight correction circuit comprises a first plurality of AND gates, each of the first plurality of AND gates being configured to receive a first number of syndrome bits of the S-bit syndrome bits and output a corresponding correction mask in the first set of correction masks, the first set of correction masks comprising a plurality of correction masks each corresponding to a bit in the first number of the K-bit message bits, The binary values of the first number of syndrome bits are 0 or 1, and the first number of syndrome bits are 4 syndrome bits selected from the S syndrome bits whose values can be 1.
4. The syndrome decoder circuit of claim 1 , wherein the X-1 bit weight correction circuit comprises a second plurality of AND gates, each of the second plurality of AND gates being configured to receive a second number of syndrome bits of the S bits and output a corresponding correction mask in the second set of correction masks, wherein the plurality of correction masks included in the second set of correction masks each correspond to a bit in the second number of the K bits of message bits, wherein X-1 inputs of each of the second plurality of AND gates do not have inverters, while the remaining inputs of each of the second plurality of AND gates have inverters, and the binary value of the second number of syndrome bits is 0 or 1.
5. The syndrome decoder circuit of claim 2 , wherein the X-2 bit weight correction circuit comprises a third plurality of AND gates, each of the third plurality of AND gates being configured to receive a third number of syndrome bits of the S bits of syndrome bits and output a corresponding correction mask in the third set of correction masks, wherein the plurality of correction masks included in the third set of correction masks each correspond to a bit in the third number of the K bits of message bits, wherein X-2 inputs of each of the third plurality of AND gates do not have inverters, while the remaining inputs of each of the third plurality of AND gates have inverters, and the binary value of the third number of syndrome bits is 0 or 1.
6. The syndrome decoder circuit of claim 1 , wherein each of the first set of correction masks is output to an XOR gate configured to flip a corresponding one of the first digits of the K-bit message bits in response to a corresponding one of the first set of correction masks indicating an error, and each of the second set of correction masks is output to an XOR gate configured to flip a corresponding one of the second digits of the K-bit message bits in response to a corresponding one of the second set of correction masks indicating an error.
7. The syndrome decoder circuit of claim 2, wherein X is 4, the first number of the S syndrome bits is 4, the second number of the S syndrome bits is 6, 7, or 8, and the third number of the S syndrome bits is 8.
8. A syndrome decoder circuit, comprising: The syndrome calculation circuit is configured to receive K message bits and P parity bits to calculate S syndrome bits, an X-bit weight correction circuit configured to receive a first number of the S-bit syndrome bits and a first number of the K-bit message bits to generate an X-1-bit enable signal and generate a first set of correction masks for the first number of the K-bit message bits, and An X-1-bit weight correction circuit is configured to receive a second number of multiple groups of the S-bit syndrome bits, a second number of the K-bit message bits and the X-1-bit enable signal to generate an X-2-bit enable signal and generate a second set of correction masks for the second number of the K-bit message bits, wherein K, P and S are integers greater than 0, the first number of the K-bit message bits includes the most significant bit of the K-bit message bits, and the second number is less than the first number.
9. The syndrome decoder circuit of claim 8, further comprising: An X-2 bit weight correction circuit is configured to receive multiple groups of a third number of the S bits of syndrome bits and a third number of the K bits of message bits to generate a third group of correction masks for the third number of the K bits of message bits, wherein the third number of the K bits of message bits includes the least significant bit of the K bits of message bits and the third number of the S bits of syndrome bits is less than the second number of the S bits of syndrome bits.
10. The syndrome decoder circuit of claim 9, wherein the X-bit weight correction circuit is configured to correct a corresponding one of the first digits of the K-bit message bits, and in response to one correction mask in the first set of correction masks being detected, triggering the X-1-bit enable signal to transition a logic level to disable the X-1-bit weight correction circuit.
11. The syndrome decoder circuit according to claim 10, wherein in response to the X-1-bit enable signal having enabled the X-1-bit weight correction circuit, the X-1-bit weight correction circuit is configured to correct a corresponding one of the second digits of the K-bit message bits, and in response to one correction mask in the second set of correction masks having been detected, the X-2-bit enable signal is triggered to change the logic level to disable the X-2-bit weight correction circuit.
12. The syndrome decoder circuit of claim 11 , wherein in response to the X-2-bit enable signal having enabled the X-2-bit weight correction circuit, the X-2-bit weight correction circuit is configured to correct a corresponding one of the third digits of the K-bit message bits.
13. The syndrome decoder circuit of claim 8 , wherein the X-bit weight correction circuit comprises a first plurality of AND gates, each of the first plurality of AND gates being configured to receive a first number of syndrome bits of the S bits of syndrome bits and output a corresponding correction mask in the first set of correction masks, the first set of correction masks comprising a plurality of correction masks each corresponding to a bit in the first number of the K bits of message bits.
14. The syndrome decoder circuit of claim 13 , wherein the X-1 bit weight correction circuit comprises a second plurality of AND gates, each of the second plurality of AND gates being configured to receive a second number of syndrome bits of the S bits and output a corresponding correction mask in the second set of correction masks, the plurality of correction masks included in the second set of correction masks each corresponding to a bit in the second number of the K bits of message bits.
15. The syndrome decoder circuit of claim 9, wherein the X-2 bit weight correction circuit comprises a third plurality of AND gates, each of the third plurality of AND gates being configured to receive a third number of syndrome bits of the S bits and output a corresponding correction mask in the third set of correction masks, the plurality of correction masks included in the third set of correction masks each corresponding to a bit in the third number of the K bits of message bits.
16. The syndrome decoder circuit of claim 8, wherein each of the first set of correction masks is output to an XOR gate configured to flip a corresponding one of the first digits of the K bits of message bits in response to a corresponding one of the first set of correction masks indicating an error.
17. The syndrome decoder circuit of claim 16 , wherein each of the second set of correction masks is output to an XOR gate configured to flip a corresponding one of the second digits of the K bits of message bits in response to a corresponding one of the second set of correction masks indicating an error and in response to the X-1 bit enable signal having enabled the X-1 bit weight correction circuit.
18. The syndrome decoder circuit of claim 9, wherein each of the third set of correction masks is output to an XOR gate configured to flip a corresponding one of the third digits of the K bits of message bits in response to a corresponding one of the third set of correction masks indicating an error and in response to the X-1 bit enable signal having enabled the X-1 bit weight correction circuit and the X-2 bit enable signal having enabled the X-2 bit weight correction circuit.
19. The syndrome decoder circuit of claim 8, wherein the first set of correction masks are all output to a first OR gate that generates the X-1 bit enable signal, and the second set of correction masks are all output to a second OR gate that generates the X-2 bit enable signal.