Message forwarding circuit

Abstract

The invention relates to a message forwarding circuit, which comprises a data packet receiving circuit, a memory, a write-in control circuit, a write data control circuit, an identifier generation circuit, a read-out control circuit and a data packet sending circuit: the data packet receiving circuit is used for receiving a data packet of a message and identifying the type of the data packet; the write-in control circuit is used for responding to the received data packet type provided by the data packet receiving circuit, generating an address for the memory and providing the address for the memory; the identifier generation circuit generates identifier information of the message according to the received one or more data packets; the write data control circuit provides the received data packet for the memory; the read-out control circuit reads out a data packet from the memory and provides the data packet to the data packet sending circuit; and the data packet transmitting circuit transmits the received data packet.

Description

Technical Field

[0001] The present application generally relates to the field of data processing technology. More specifically, the present application relates to a method and circuit for message forwarding. Background Art

[0002] A message refers to a data unit that can be exchanged and transmitted between different hardware devices, buses and / or interfaces. During the process of exchanging and transmitting messages, the messages need to be forwarded, and during the process of forwarding the messages, the messages need to be cached.

[0003] Figure 1 A message format is shown. A message 10 includes a series of data packets, such as data packets P1-1, P1-2, P1-3... and even P1-m, where m represents the length of message 10, that is, the number of data packets in message 10. The first data packet P1-1 has a SOP (Start Of Packet) to indicate the beginning of message 10, and the last data packet has an EOP (End Of Packet) to indicate the end of message 10. The storage method of messages in the cache generally adopts FIFO (First In First Out). The first-in-first-out feature of the FIFO memory can be used to ensure the order of the message content.

[0004] Figure 2 The process of storing a message in a FIFO memory is shown, wherein each square represents a storage unit of the memory, a square without pattern filling represents a blank storage unit, and a square with pattern filling represents a storage unit in which a data packet is stored; and from top to bottom, the storage unit address increases in sequence. P1-1, P1-2, P1-3, P1-4 represent consecutive data packets in the first message, P2-1, P2-2 represent consecutive data packets in the second message; T1, T2, T3, T4, Tx represent several time periods. In addition, in the specification, storing a message or a data packet of a message into a memory is also referred to as writing a message or a data packet of a message into a memory. As an example, when storing a data packet of a message, it is stored in the form of storing one data packet at a time. It should also be noted that, as in the following text, the second message is the next message of the first message; that is, the order of the first message and the second message referred to in the specification is different from the order of the first message and the second message in the claims. Please refer to the attached drawings to understand the contents of the specification.

[0005] In the T1 time period, the data packet P1-1 is stored in the first storage unit 101 of the FIFO memory. In the T2 time period, the data packet P1-2 is stored in the second storage unit 102 of the FIFO memory. The second storage unit 102 is located after the first storage unit 101. For example, the address of the second storage unit 102 is equal to the address of the first storage unit 101 plus one. In the T3 time period, the data packet P1-3 is stored in the third storage unit 103 of the FIFO memory. The address of the third storage unit 103 is equal to the address of the second storage unit 102 plus one. In the T4 time period, the data packet P1-4 is stored in the fourth storage unit 104 of the FIFO memory. The address of the fourth storage unit 104 is equal to the address of the third storage unit 103 plus one. By storing each data packet of the message in this way, in a certain time period Tx, all data packets of the first message and the first two data packets P2-1 and P2-2 of the second message are stored.

[0006] Based on the FIFO principle, during the message reading process, the reading is performed in a first-in-first-out manner. For the first message, data packet P1-1 is read first, then data packet P1-2, then data packet P1-3, and so on, until all data packets of the first message stored in the FIFO memory are read, and for the second message, the messages are read in the order of P2-1 and P2-2. It can be seen that the data packets stored first are read out first, and the data packets stored later are read out later.

[0007] In addition, some information in a message can only be obtained after all the data packets in the message are received or in the middle. For example, the HASH value of the message or the length of the message data can only be calculated after all the data packets in the message are received. The destination address information is set in the middle data packet of the message (for example Figure 1 The data packet between P1-1 and P1-m can be called the middle data packet of message 10), which can only be obtained when the middle data packet of the message is obtained. Usually, after the data packet of the message is stored, this information is stored at the end of the message or stored separately.

[0008] Figure 3 The above situation is shown. The data entry format of the message is: data segment A-information C-data segment B; the data exit format of the message is: data segment A-information C-data segment B-information C+information D, wherein information C can be the above-mentioned destination address information, and information D can be message length information, or message summary information and other information used to indicate message characteristics (wherein, message length information and message summary information can be calculated after the message is received); for the subsequent units that process the message, information C and information D are useful information of the message, and the subsequent units can decide the corresponding processing methods based on these useful information. Figure 3The defect of the method shown is that when reading a message, the last data packet must be read to obtain the length, address, summary and other information of the corresponding message. In other words, only by reading the entire message can the useful information of a message be obtained, and this useful information is very important for the subsequent processing. It can be seen that in the above method, the subsequent stage cannot obtain the useful information of the message in the first time, which is not conducive to further processing.

[0009] In order to solve the above problems, Figure 4 A message access method based on dual FIFO mode is shown, in which a data FIFO and an information FIFO are set, the data FIFO is used to store the data of the message, and the information FIFO is used to store the useful information of the message.

[0010] like Figure 4 As shown, during the message reception process, according to Figure 2 Each data packet is stored in the memory in sequence. For example, the first message and the second message are stored in the data FIFO in sequence, and the second message is the next message of the first message. The first message includes data packets P1-1, P1-2...P1-m, and the second message includes data packets P2-1, P2-2...P2-n, where n represents the length of the second message, that is, the number of data packets of the second message. The data packet P1-1 of the first message is stored in the first storage unit 301, and the data packet P1-2 of the first message is stored in the second storage unit 302, and so on. The last data packet P1-m of the first message is stored in the mth storage unit 30m; the data packet P2-1 of the second message is stored in the m+1th storage unit 401, and the data packet P2-2 of the second message is stored in the m+2th storage unit 402, and so on. The last data packet P1-n of the second message is stored in the m+nth storage unit 40n. During the process of writing the first message, for example, when the first message is received or stored, the information extracted from the first message or the calculated summary and other information (collectively referred to as identification information P1-info) is stored in the first storage unit 41 corresponding to the information FIFO; during the process of writing the second message, for example, when the second message is received or stored, the information extracted from the second message or the calculated summary and other information (collectively referred to as identification information P2-info) is stored in the second storage unit 42 corresponding to the information FIFO; wherein the second storage unit 42 of the information FIFO is the next storage unit of the first storage unit 41 of the information FIFO.

[0011] like Figure 4As shown, when reading data, the message information can be first taken out from the information FIFO, and then the corresponding message can be taken out from the data FIFO. For example, the P1-info of the first message is first read out from the information FIFO, output to the next stage, and then the data packet of the first message is read out from the data FIFO and output. After the data packet of the first message is read, the P2-info of the second message is first read out from the information FIFO, output to the next stage, and then the data packet of the second message is read out from the data FIFO and output.

[0012] according to Figure 4 As shown, the above dual FIFO mode can solve the problem that the useful information of the message cannot be provided to the subsequent stage in the first time. However, the dual FIFO mode also has some defects, including: first, it is necessary to control the write and read operations of the two FIFOs, and it is also necessary to ensure the synchronization between the two FIFOs, which consumes certain resources; second, the depth of the information FIFO is difficult to select. If it is too large, it will be wasteful, and if it is too small, it may cause overflow. Summary of the invention

[0013] In order to solve the problems existing in the message forwarding in the above-mentioned prior art, the present application reserves a reserved storage unit for each message in the data packet storage process, stores useful information in the reserved storage unit, and stores the data packets in the message in the storage unit after the reserved storage unit in sequence. When reading the message from the memory, the data in the storage unit is read in sequence according to the storage address from small to large, so that the useful information in the reserved storage unit and the data packets stored in the subsequent storage units are read in sequence. The scheme of the present application can not only realize the first-time notification of the subsequent stage, but also avoid the disadvantages of using dual FIFO. Compared with the dual FIFO mode, the present application does not require information FIFO, and does not need to consider the depth of the information FIFO. The storage space utilization rate is high, and only the storage (i.e., writing) process needs to be controlled. The reading control can be implemented according to conventional technology, and the demand for control resources is relatively small. In summary, the present application provides an efficient message forwarding solution that can replace the dual FIFO mode.

[0014] According to a first aspect of the present application, a method for forwarding a first message according to the first aspect of the present application is provided, wherein the message includes at least one data packet, including: receiving a data packet in a first message, storing the data packet in a storage unit after a reserved storage unit, wherein the reserved storage unit is the first storage unit in the memory, or the next storage unit of the storage unit corresponding to the last data packet of a second message, and the second message is the previous message of the first message; when the first data packet of the first message starts to be stored, or when the storage of all data packets of the second message is completed, the address of the reserved storage unit is also determined; in response to receiving all data packets of the first message, the identification information used to indicate the first message is stored in the reserved storage unit.

[0015] According to the first method for forwarding a message in the first aspect of the present application, a second method for forwarding a message in the first aspect of the present application is provided, wherein the identification information includes length information of the message and / or summary information of the message.

[0016] According to the first or second method for forwarding messages according to the first aspect of the present application, a third method for forwarding messages according to the first aspect of the present application is provided, which also includes: when all data packets of the first message are stored, or when the first data packet of the third message starts to be stored, updating the address of the reserved storage unit; the third message is the next message of the first message.

[0017] According to one of the first to third methods of forwarding messages according to the first aspect of the present application, a fourth method of forwarding messages according to the first aspect of the present application is provided to determine the address of the reserved storage unit, including: determining that the address of the reserved storage unit is the storage unit address corresponding to the last data packet of the second message plus one.

[0018] According to one of the first to fourth methods of forwarding messages according to the first aspect of the present application, a fifth method of forwarding messages according to the first aspect of the present application is provided. If the data packet carries a header identifier, the header identifier is deleted, and the data packet after the header identifier is deleted is stored in the next storage unit of the reserved storage unit.

[0019] According to one of the first to fifth methods of forwarding messages according to the first aspect of the present application, a sixth method of forwarding messages according to the first aspect of the present application is provided. If the data packet only carries a tail identifier, the data packet is stored in the next storage unit of the storage unit corresponding to the previous data packet.

[0020] According to one of the first to sixth methods of forwarding messages according to the first aspect of the present application, a seventh method of forwarding messages according to the first aspect of the present application is provided. If the data packet does not carry a header identifier and a tail identifier, the data packet is stored in the next storage unit of the storage unit corresponding to the previous data packet.

[0021] According to one of the first to seventh methods of forwarding messages according to the first aspect of the present application, an eighth method of forwarding messages according to the first aspect of the present application is provided. If the data packet carries a header identifier and a tail identifier, the header identifier is deleted, and the data packet after the header identifier is deleted is stored in the next storage unit of the reserved storage unit.

[0022] According to one of the first to eighth methods of forwarding messages according to the first aspect of the present application, a ninth method of forwarding messages according to the first aspect of the present application is provided, which also includes: storing the header identifier carried by the first data packet of the first message together with the identifier information in the reserved storage unit.

[0023] According to one of the third to ninth methods of forwarding messages according to the first aspect of the present application, a tenth method of forwarding messages according to the first aspect of the present application is provided, which also includes: generating a synchronization signal in response to updating the address of the reserved storage unit; and reading a data packet of the first message from the memory in response to the synchronization signal.

[0024] In the tenth method for forwarding a message according to the first aspect of the present application, an eleventh method for forwarding a message according to the first aspect of the present application is provided, wherein the method of reading a data packet of a first message from a memory in response to the synchronization signal comprises: reading and outputting the data packets in the storage units in sequence starting from a reserved storage unit in at least one storage unit corresponding to the first message according to the synchronization signal.

[0025] According to the eleventh method for forwarding a message according to the first aspect of the present application, a twelfth method for forwarding a message according to the first aspect of the present application is provided, further comprising: after all data packets of a message are read, sending a corresponding read completion notification.

[0026] In the twelfth method for forwarding a message according to the first aspect of the present application, a thirteenth method for forwarding a message according to the first aspect of the present application is provided, which also includes: while reading the data packet of the first message according to the synchronization signal, also storing the data packet corresponding to the third message according to the updated address of the reserved storage unit.

[0027] According to a second aspect of the present application, a first circuit for forwarding messages according to the second aspect of the present application is provided, wherein the message includes at least one data packet, and the circuit includes: a memory including multiple storage units; an identification generation circuit for generating identification information of the message; a storage control circuit for: receiving a data packet in a first message, and storing the data packet in a storage unit after a reserved storage unit, wherein the reserved storage unit is the first storage unit in the memory, or the next storage unit of the storage unit corresponding to the last data packet of a second message, and the second message is the previous message of the first message; when the first data packet of the first message starts to be stored, or when the storage of all data packets of the second message is completed, the address of the reserved storage unit is also determined; in response to receiving all data packets of the first message, the identification information used to indicate the first message is stored in the reserved storage unit.

[0028] According to the first circuit for forwarding messages according to the second aspect of the present application, a second circuit for forwarding messages according to the second aspect of the present application is provided, wherein the storage control circuit includes a write control circuit and a write data control circuit; the write control circuit is used to determine the storage address of each data packet; and the write data control circuit is used to provide the data packet to the memory.

[0029] According to the first or second circuit for forwarding messages according to the second aspect of the present application, a third circuit for forwarding messages according to the second aspect of the present application is provided, and the identification information includes length information of the message and / or summary information of the message.

[0030] According to one of the first to third circuits for forwarding messages according to the second aspect of the present application, a fourth circuit for forwarding messages according to the second aspect of the present application is provided, and the write control circuit is also used to: update the address of the reserved storage unit when all data packets of the first message are stored, or when the first data packet of the third message starts to be stored, and the third message is the next message of the first message.

[0031] According to one of the first to fourth circuits for forwarding messages according to the second aspect of the present application, a fifth circuit for forwarding messages according to the second aspect of the present application is provided, and the write control circuit is also used to: determine that the address of the reserved storage unit is the storage unit address corresponding to the last data packet of the second message plus one.

[0032] According to one of the first to fifth circuits for forwarding messages according to the second aspect of the present application, a sixth circuit for forwarding messages according to the second aspect of the present application is provided, and the write data control circuit is also used to: if the data packet carries a header identifier, delete the header identifier, and store the data packet after deleting the header identifier into the next storage unit of the reserved storage unit.

[0033] According to one of the first to sixth circuits for forwarding messages according to the second aspect of the present application, a seventh circuit for forwarding messages according to the second aspect of the present application is provided, and the write data control circuit is also used to: if the data packet only carries a tail identifier, then the data packet is stored in the next storage unit of the storage unit corresponding to the previous data packet.

[0034] According to one of the first to seventh circuits for forwarding messages according to the second aspect of the present application, an eighth circuit for forwarding messages according to the second aspect of the present application is provided, and the write data control circuit is also used to: if the data packet does not carry a header identifier and a tail identifier, then store the data packet in the next storage unit of the storage unit corresponding to the previous data packet.

[0035] According to one of the first to eighth circuits for forwarding messages according to the second aspect of the present application, a ninth circuit for forwarding messages according to the second aspect of the present application is provided, and the write data control circuit is also used to: if the data packet carries a header identifier and a tail identifier, delete the header identifier, and store the data packet after the header identifier is deleted into the next storage unit of the reserved storage unit.

[0036] According to one of the first to ninth circuits for forwarding messages according to the second aspect of the present application, a tenth circuit for forwarding messages according to the second aspect of the present application is provided, and the write data control circuit is also used to: store the header identifier carried by the first data packet of the first message together with the identification information in a reserved storage unit.

[0037] According to one of the fourth to tenth circuits for forwarding messages according to the second aspect of the present application, there is provided an eleventh circuit for forwarding messages according to the second aspect of the present application, which also includes: a read-out control circuit, used to determine the storage address of the data to be read, read the data according to the storage address, and generate a data packet, wherein the read-out control circuit determines the storage address of the data to be read by incrementing the storage address of the data that generated the previous data packet.

[0038] According to the eleventh circuit for forwarding messages according to the second aspect of the present application, there is provided a twelfth circuit for forwarding messages according to the second aspect of the present application, wherein the write control circuit sends a synchronization signal to the read control circuit in response to updating the address of the reserved storage unit; the read control circuit, in response to the synchronization signal, starts reading data according to the storage address and generates a data packet, and increments the storage address to read data and generate the next data packet until all data packets of the message are generated.

[0039] According to the twelfth circuit for forwarding messages according to the second aspect of the present application, there is provided a thirteenth circuit for forwarding messages according to the second aspect of the present application, and the read-out control circuit is further used to: read and output the data packets in the storage units in sequence starting from the reserved storage units in at least one storage unit corresponding to the first message according to the synchronization signal.

[0040] According to the thirteenth circuit for forwarding messages according to the second aspect of the present application, there is provided a fourteenth circuit for forwarding messages according to the second aspect of the present application, and the read-out control circuit is further used to: after all data packets of a message are read, send a corresponding read completion notification.

[0041] According to the fourteenth circuit for forwarding messages according to the second aspect of the present application, there is provided a fifteenth circuit for forwarding messages according to the second aspect of the present application, further comprising: while the read control circuit reads the data packet of the first message according to the synchronization signal, the write data control circuit stores the data packet corresponding to the third message according to the updated address of the reserved storage unit.

[0042] According to the thirteenth circuit for forwarding messages of the second aspect of the present application, there is provided a sixteenth circuit for forwarding messages of the second aspect of the present application, wherein the read control circuit also has an input connected to a data output enable signal; and the write control circuit also has an output connected to a data write enable signal.

[0043] According to one of the first to sixteenth circuits for forwarding messages according to the second aspect of the present application, there is provided a seventeenth circuit for forwarding messages according to the second aspect of the present application, wherein the memory includes a memory for caching.

[0044] According to a third aspect of the present application, a first circuit for forwarding a message according to the third aspect of the present application is provided, wherein the message includes at least one data packet, and the circuit includes a data packet receiving circuit, a memory, a write control circuit, a write data control circuit, an identification generating circuit, a read control circuit, and a data packet sending circuit: a data packet receiving circuit, for receiving a data packet of a message, identifying a data packet type, and providing the received data packet to the write data control circuit and the identification generating circuit, and providing the identified data packet type to the write control circuit and the write data control circuit; a write control circuit, in response to receiving a data packet type provided by the data packet receiving circuit, generating an address for the memory and providing it to the memory; a write data control circuit providing the received data packet to the memory; writing the data packet received from the write data control circuit to the memory according to the address for the memory received from the write control circuit; the identification generating circuit generating identification information of the message according to one or more received data packets; the read control circuit reading a data packet from the memory and providing it to the data packet sending circuit; the data packet sending circuit sending the received data packet.

[0045] According to the first circuit for forwarding messages according to the third aspect of the present application, a second circuit for forwarding messages according to the third aspect of the present application is provided, and the types of data packets include the start data packet of the message, the end data packet of the message and other data packets of the message.

[0046] According to the first or second circuit for forwarding messages according to the third aspect of the present application, a third circuit for forwarding messages according to the third aspect of the present application is provided. If the received data packet is the starting data packet of a message, the write control circuit increments the last data packet address of the previous message to generate an address for the memory; if the received data packet is other data packets of a message or the ending data packet of a message, the write control circuit updates the address for the memory in an incremental manner.

[0047] According to the second circuit for forwarding messages according to the third aspect of the present application, a fourth circuit for forwarding messages according to the third aspect of the present application is provided. If the received data packet is the end data packet of the message, after the end data packet of the message is written into the memory, the write control circuit suspends receiving data packets from the data packet receiving circuit, caches the address for the memory, and also uses the last data packet address of the previous message as the address for the memory, and instructs the identification generation circuit to provide the identification information of the generated message to the write data control circuit; the write data control circuit provides the identification information of the message obtained from the identification generation circuit to the memory.

[0048] According to the third circuit for forwarding messages according to the third aspect of the present application, a fifth circuit for forwarding messages according to the third aspect of the present application is provided. After the identification information of the message is written into the memory, the write control circuit also increments the cached address for the memory, and updates the last data packet address of the previous message with the incremented cached address for the memory.

[0049] According to the fourth circuit for forwarding messages according to the third aspect of the present application, a sixth circuit for forwarding messages according to the third aspect of the present application is provided, after the identification information of the message is written into the memory, the write control circuit also synchronizes the updated last data packet address of the previous message to the read control circuit; the read control circuit reads the data packet from the memory according to the read address, and in response to the data packet being read out from the memory, increments the read address as a new read address; if the read address is equal to the last data packet address of the previous message received from the write control circuit, the read control circuit pauses reading the data packet from the memory.

[0050] According to a fourth aspect of the present application, a storage device according to the fourth aspect of the present application is provided, comprising one of the circuits for forwarding messages according to the second aspect of the present application.

[0051] According to a fifth aspect of the present application, a storage device according to the fifth aspect of the present application is provided, comprising one of the circuits for forwarding messages according to the second aspect of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0053] Figure 1 Schematic diagram of message structure;

[0054] Figure 2 It is a schematic diagram of a message storage method in the prior art;

[0055] Figure 3 It is a schematic diagram of the data input and data output formats in the prior art;

[0056] Figure 4 It is a schematic diagram of the message reading and writing method in the dual FIFO mode;

[0057] Figure 5A A schematic diagram of a first message storage process according to an embodiment of the present application;

[0058] Figure 5BThis is a schematic diagram of a first message storage process in another application scenario;

[0059] Fig. 6A A schematic diagram of a second message storage process according to an embodiment of the present application;

[0060] Figure 6B It is a schematic diagram of a second message storage process in another application scenario;

[0061] Figure 7 A flow chart of a method for forwarding a message according to an embodiment of the present application;

[0062] Figure 8 A flowchart of another method for forwarding a message according to an embodiment of the present application;

[0063] Fig. 9 A schematic diagram of a reading and writing method according to an embodiment of the present application;

[0064] Fig.10 A schematic diagram of the data input and data output formats according to an embodiment of the present application;

[0065] Fig.11 A schematic diagram of a circuit for forwarding a message according to an embodiment of the present application;

[0066] Fig.12 is another circuit schematic diagram for forwarding messages according to an embodiment of the present application;

[0067] Fig.13 A schematic diagram of a data packet storage process according to an embodiment of the present application;

[0068] Fig.14 A schematic diagram of the parallel processing of writing and reading messages;

[0069] Fig.15 A schematic diagram of the structure of a storage device according to an embodiment of the present application. DETAILED DESCRIPTION

[0070] Figure 5A , Figure 5B The process of writing the first message into the memory according to an embodiment of the present application is shown. Fig. 6A , Figure 6B The process of writing the second message into the memory according to an embodiment of the present application is demonstrated.

[0071] like Figure 5AAs shown, as an example, a continuous storage space in the memory includes a first storage unit 501, a second storage unit 502, a third storage unit 503, a fourth storage unit 504, ... In the storage space, the addresses of adjacent storage units are continuous, and starting from the first storage unit 501, the addresses of subsequent storage units increase in sequence. For example, the address of the first storage unit 501 is 0x3A, the address of the second storage unit 502 is 0x3B, the address of the third storage unit 503 is 0x3C, and so on. For another example, the address corresponding to the first storage unit 501 is 0x31~0x33, the address corresponding to the second storage unit 502 is 0x34~0x36, the address corresponding to the third storage unit 501 is 0x37~0x39, and the address corresponding to the fourth storage unit 504 is 0x3A~0x3C. In other words, a storage unit can occupy one address space or multiple address spaces. In one embodiment, the first storage unit 501 can be the first storage unit of the memory, and the first storage unit 501 is used as a reserved storage unit.

[0072] In the T1 time period, the first data packet P1-1 of the first message is received, and the storage unit corresponding to P1-1 is determined according to the reserved storage unit, that is, P1-1 is stored in the next storage unit of the reserved storage unit (the second storage unit 502), and P1-1 is written into the second storage unit 502.

[0073] In the T2 time period, the second data packet P1-2 of the first message is received, and P1-2 is stored in the next storage unit of the storage unit corresponding to P1-1, that is, the second data packet P1-2 is written into the third storage unit 503. Similarly, in the T3 time period, the third data packet P1-3 of the first message is received, and P1-3 is stored in the next storage unit of the storage unit corresponding to P1-2, that is, the third data packet P1-3 is written into the fourth storage unit 504. And so on, all data packets of the first message are stored. In the Tm time period, the last data packet P1-m of the first message is stored; and the identification information P1-info of the first message is stored in the first storage unit 501, thereby completing the entire writing process of the first message.

[0074] Figure 5B Another application scenario is shown. Figure 5A The only difference is that after the storage of the last data packet P1-m is completed in the Tm time period, the identification information P1-info of the first message is stored in the first storage unit 501 in the next time period Tm+1 of the Tm time period, thereby completing the entire writing process of the first message. It can be seen that the storage process of the identification information can share a time period with the storage of the last data packet, or it can have its own exclusive time period.

[0075] Fig. 6A The second message writing process according to the embodiment of the present application is shown. The second message is the next message of the first message, combined with Figure 5A , T1' represents a time period after the Tm time period; or combined Figure 5B , T1' represents a time period after the Tm+1 time period. Storage unit 601 is the next storage unit of the storage unit corresponding to the last data packet P1-m of the first message. Starting from storage unit 601, the following are storage unit 602, storage unit 603, storage unit 604, etc. As an example, after the last data packet P1-m of the first message is stored, the reserved storage unit address is updated according to the storage unit address corresponding to the last data packet P1-m. The updating method is: the next storage unit of the storage unit corresponding to the last data packet P1-m is used as the reserved storage unit of the second message, that is, the storage unit 601 is used as the reserved storage unit of the second message.

[0076] In the time period T1′, the first data packet P2-1 of the second message is received, the next storage unit 602 of the reserved storage unit 601 is used as the storage unit of the data packet P2-1, and P2-1 is written into the storage unit 602 after the storage unit 601.

[0077] During the time period T2′, the second data packet P2-2 of the second message is received, the next storage unit 603 of the storage unit 602 corresponding to P2-1 is used as the storage unit of the data packet P2-2, and P2-2 is written into the storage unit 603.

[0078] In the T3' time period, the third data packet P2-3 of the second message is received, and the next storage unit 604 of the storage unit 603 corresponding to P2-2 is used as the storage unit of the data packet P2-3, and the third data packet P2-3 of the second message is written into the storage unit 604. And so on, all the data packets of the second message are stored. In the Tn' time period, the last data packet P2-n of the second message is stored, and the identification information P2-info of the second message is stored into the storage unit 601, thereby completing the entire writing process of the second message.

[0079] Figure 6B Another application scenario is shown. Fig. 6A The only difference is that after the storage of the last data packet P2-n is completed in the Tn' time period, the identification information P2-info of the second message is stored in the reserved storage unit 601 of the second message in the next time period Tn'+1 of the Tn' time period, thereby completing the entire second message writing process.

[0080] It should be noted that the size of the reserved storage unit (501, 601) may be equal to or different from the size of the subsequent storage unit. For example, the reserved storage unit 501 may occupy multiple address spaces, while the subsequent storage units (such as storage unit 502, storage unit 503, etc.) occupy one address space. In actual application scenarios, the size of the reserved storage unit can be determined according to the amount of information required to be stored in the reserved storage unit.

[0081] Figure 7 The method flow of forwarding a message according to an embodiment of the present application is shown. The message forwarding method includes: storing a data packet in a storage unit after a reserved storage unit; when a message starts to be stored, also determining the address of the reserved storage unit; in response to receiving all data packets of a message, storing identification information for indicating the message in the reserved storage unit.

[0082] As an example, Figure 7 As shown, the message forwarding method includes: firstly, executing step S101, receiving a data packet of a message. In one embodiment, each message includes at least one data packet.

[0083] Then, step S102 is executed to determine the type of the current data packet received, that is, to determine which data packet of the message the current data packet received is, such as the first data packet (i.e., the start data packet, such as P1-1, P2-1), the last data packet (i.e., the end data packet, such as P1-m, P2-n), or the intermediate data packet between the first data packet and the last data packet (i.e., other data packets). As an example, it is possible to determine which data packet of the message the data packet belongs to by determining whether the data packet carries a header identifier SOP or an end identifier EOP.

[0084] If the current data packet received is the start data packet of the message, it means that the data packets in the message start to be stored, and step S103 is executed to determine the address of the reserved storage unit corresponding to the message. Step S103 includes two cases: one case, the reserved storage unit is the first storage unit in the memory (for example Figure 5A In another case, the reserved storage unit is the next storage unit of the storage unit corresponding to the last data packet of the previous message (for example Fig. 6A The storage unit 601 shown is the next storage unit of the storage unit corresponding to the last data packet P1-m of the first message).

[0085] Then, step S104 is executed to store the start data packet in the next storage unit of the reserved storage unit, for example Figure 5A As shown, the start data packet P1 - 1 of the first message is stored in the storage unit 502 after the reserved storage unit 501 .

[0086] If the current data packet received is an intermediate data packet or an end data packet of the message, that is, the current data packet received does not include a start data packet of the message, then step S105 is executed to store the current data packet in the next storage unit of the storage unit corresponding to the previous data packet. Figure 5A For example, the second data packet P1-2 of the first message is stored in the next storage unit 503 of the storage unit 502 corresponding to the starting data packet P1-1 of the first message; for another example, the data packet P1-3 is stored in the next storage unit 504 of the storage unit 503 corresponding to the data packet P1-2.

[0087] Then, step S106 is executed to determine whether all the data packets of the message have been received. If all the data packets have been received, step S107 is executed to store the identification information of the corresponding message in the reserved storage unit determined in step 103. Then, the next data packet of the message (or the first data packet of the next message) is received, and steps S101 to S107 are executed cyclically.

[0088] Figure 8 The method flow of forwarding a message according to another embodiment of the present application is shown. The message forwarding method of this embodiment includes: storing a data packet in a storage unit after a reserved storage unit; when all data packets of a message are stored, further determining the address of the reserved storage unit; in response to receiving all data packets of a message, storing identification information for indicating the message in the reserved storage unit.

[0089] Figure 8 In the illustrated embodiment, step S201 is first performed to receive a data packet of a message.

[0090] Then execute step S202 to determine the type of the current data packet received, that is, determine whether the current data packet received is the first data packet of the message (i.e., the start data packet), the last data packet (i.e., the end data packet), or an intermediate data packet between the first data packet and the last data packet (i.e., other data packets).

[0091] If the current data packet received is the start data packet of the message, step S203 is executed to store the start data packet in the next storage unit of the reserved storage unit, for example Figure 5A As shown, the starting data packet P1-1 of the first message is stored in the storage unit 502 after the reserved storage unit 501; at this time, the corresponding reserved storage unit 501 has been determined. For example, the reserved storage unit is the first storage unit in the memory or the storage unit determined after all data packets of the previous message are stored.

[0092] If the currently received data packet is an intermediate data packet or the last data packet of the message, that is, the currently received data packet is not the start data packet, step S204 is executed to store the currently received data packet in the next storage unit of the storage unit corresponding to the previous data packet.

[0093] Then, step S205 is executed to determine whether all data packets of a message have been received. If all data packets have been received, step S206 is executed to store the identification information of the corresponding message in the previously determined reserved storage unit, for example Fig. 6A In the process, the identification information P2-info of the second message is stored in the reserved storage unit 601.

[0094] Then, step S207 is executed. Since all the data packets of a message have been received, or all the data of a message have been stored, the address of the reserved storage unit corresponding to the next message can be determined. Figure 5A , 6A In the storage process of the first message, the corresponding reserved storage unit is the storage unit 501. When all the data packets of the first message are received, it is necessary to determine the address of the next reserved storage unit 601. After the address of the next reserved storage unit is determined, the next data packet of the message (or the first data packet of the next message) continues to be received, and steps S201 to S207 are executed cyclically.

[0095] Figure 7 and Figure 8 In the embodiments shown, the only difference is whether the address of the reserved storage unit is determined when a message starts to be stored or after a message is stored. When a message starts to be stored, the address of the reserved storage unit corresponding to the current message is determined; and after a message is stored, the address of the reserved storage unit corresponding to the next message is determined.

[0096] In the above embodiment, the identification information may be information extracted from the middle of the message (such as Figure 3 The information C) shown may also be summary information (such as a hash value) calculated for the entire message, or the length information of the entire message, or a combination of the above-mentioned information, which is not limited in the present application.

[0097] In the above embodiment, if a message contains at least two data packets, the header mark (SOP) is located at the first data packet of the message, and the tail mark (EOP) is located at the end data packet of the message, i.e., the last data packet. In some cases, if a message has only one data packet, the data packet carries both the header mark and the tail mark. In addition, for different data packets in the same message, different processing is performed during storage, for example: if the data packet carries the header mark, the header mark is deleted, and the data packet after deleting the header mark is stored in the next storage unit of the reserved storage unit, for example, after deleting the header mark in the data packet P1-1, the data packet is stored in the storage unit 502. If the data packet carries only the tail mark, the data packet is stored in the next storage unit of the storage unit corresponding to the previous data packet. If the data packet does not carry the header mark and the tail mark (indicating that the data packet is an intermediate data packet), the data packet is stored in the next storage unit of the storage unit corresponding to the previous data packet. If the data packet carries a header identifier and a tail identifier, the header identifier is deleted, and the data packet after the header identifier is deleted is stored in the next storage unit of the reserved storage unit.

[0098] In addition, after all the data packets in a message are stored, the header identifier can be stored in the reserved storage unit together with the above identifier information. The above processing method does not process the data packets containing the tail identifier, and they are directly stored in the corresponding storage unit. In other embodiments, because the message length information can be put into the identifier information, the length of the message can be known when reading the message, so the tail position of the message can be calculated; therefore, for the data packets containing the tail identifier, the tail identifier can also be deleted and stored.

[0099] The above embodiment describes the process of writing a message. The technical solution of the present application will be described below in conjunction with the process of reading a message.

[0100] Fig. 9 The diagram shows the comparison of the writing process and reading process of the message. The left side shows the writing process, with arrows showing the order of writing data packets in the memory; the right side shows the reading process, with arrows showing the order of reading data packets in the memory. Please refer to Figures 5 and 6 for understanding Fig. 9 content.

[0101] When the first data packet P1-1 of the first message is received, the first data packet P1-1 is stored in the storage unit 502; when the second data packet P1-2 of the first message is received, the write address jumps to the storage unit 503, and the second data packet P1-2 is stored in the storage unit 503; when the third data packet P1-3 of the first message is received, the write address jumps to the storage unit 504... until the last data packet P1-m of the first message is stored, the write address jumps to the storage unit 501, and the identification information P1-info of the first message is written to the storage unit 501. Then, continue to receive data packets of the next message (the second message). When the first data packet P2-1 of the second message is received, the write address jumps to the storage unit 602, and the data packet P2-1 is stored in the storage unit 602; when the second data packet P2-2 of the second message is received, the data packet P2-2 is stored in the storage unit 603; when the third data packet P2-3 of the second message is received, the write address jumps to the storage unit 604... until the last data packet P1-n of the second message is stored, the write address jumps to the storage unit 601, and the identification information P1-info of the second message is written to the storage unit 601.

[0102] According to the above description, when starting to write a message, the write address will skip the address of the current reserved storage unit, and the next storage unit of the reserved storage unit will start to write data in sequence. When all the data packets of a message are written, the write address will jump back to the current reserved storage unit. When the storage of the previous message is completed or the next message starts to be stored, the address of the current reserved storage unit is updated to obtain a new reserved storage unit, and the write address jumps to the next storage unit of the new reserved storage unit. That is to say, in the storage process of a message, the operation of updating the address of the reserved storage unit is only once, that is, when the storage of the previous message is completed, or when the first data packet of the message starts to be stored. For example, the reserved storage unit is updated by adding one to the storage address corresponding to the last data packet of the previous message (for example, the storage address corresponding to the last data packet P1-m of the first message is added by one, that is, the address of the storage unit 601 is obtained). In the process of storing a message data packet, the address of the corresponding reserved storage unit of the message is unchanged.

[0103] like Fig. 9As shown, when reading out the message, the data is always read out from the memory in sequence in the manner of increasing the read address of the storage unit address. As an example, when reading the first message stored in the memory, the identification information of the first message stored in the storage unit 501 is first read, and then the first data packet of the first message stored in the storage unit 502 is read, and then the second data packet of the first message stored in the storage unit 503 and the third data packet of the first message stored in the storage unit 504 are read in sequence... until the last data packet of the first message stored in the storage unit P1-m is read, and the reading of the first message is completed. When reading the second message stored in the memory, the reading is performed in the same manner as the reading of the first message, that is, the identification information of the second message stored in the storage unit 601 is first read, and then the first data packet of the second message stored in the storage unit 602 is read, and then the second data packet of the second message stored in the storage unit 603 and the third data packet of the second message stored in the storage unit 604 are read in sequence... until the last data packet of the second message stored in the storage unit P2-n is read, and the reading of the second message is completed.

[0104] according to Fig. 9 It can be seen from the description that according to the method of the embodiment of the present application, in the process of forwarding messages, when writing data, the memory no longer writes data in the way that the memory stores data of the "first in, first out" type (storage unit addresses are written in order from small to large). Instead, the data packets in a message are stored in order after the storage unit where the identification information is stored, and then the identification information is stored in the storage unit with the smallest storage address among all the storage units corresponding to a message. When reading out data information, the data is read in the order of the storage unit address from small to large. For example, when reading the data of the first message, the data stored in the storage units P1-1, P1-2 and P1-3 are read in sequence.

[0105] Fig.10 The data input format and data output format according to the embodiment of the present application are shown. Fig.10 As shown, the data entry format of the message is: data segment A-information C-data segment B; information C is the useful information of the message and is located in the middle of the message. The data exit format of the message is: identification information-data segment A-information C-data segment B. Fig.10 contrast Figure 3 It can be seen that after the processing of the embodiment of the present application, the identification information is placed at the front of the message when the message is output. When the data is read out, the identification information is sent out first, and the subsequent stage can obtain the identification information at the first time. For example, the identification information may contain key information such as the destination address of the message, which is convenient for the subsequent stage to know in advance and perform corresponding processing.

[0106] The message forwarding method of the present application is described in detail above, and the circuit structure for implementing the above method will be described in detail below.

[0107] Fig.11 A circuit for message forwarding according to an embodiment of the present application is shown. Figure 7 or Figure 8 In one embodiment, a circuit for forwarding a message includes a memory, an identification generating circuit, and a storage control circuit. The memory includes a plurality of storage units. The identification generating circuit is used to generate identification information of the message. The storage control circuit is used to implement Figure 7 or Figure 8 The method flow, for example, mainly includes: receiving a data packet and storing the data packet in a memory, determining an address of a reserved storage unit, and storing identification information in the reserved storage unit.

[0108] In an application scenario, the storage control circuit can be implemented by the division of labor between the write control circuit and the write data control circuit. For example, the write control circuit is used to determine the storage address of each data packet; the write data control circuit is used to provide the data packet to the memory. It should be noted that the above-mentioned various circuit units can be a CPU or a hardware circuit independent of the CPU. If it is a CPU, the corresponding functions are implemented by writing software; if it is a hardware circuit independent of the CPU, such a hardware circuit can be generated by hardware description language and corresponding processes.

[0109] Fig.12 A circuit for forwarding a message according to another embodiment of the present application is shown. Fig.12 As shown, the circuit includes a data packet receiving circuit, a memory, a write control circuit, a write data control circuit, an identification generation circuit, a read control circuit and a data packet sending circuit. Fig.11 Similarly, the various circuit units mentioned above may be a CPU or a hardware circuit independent of the CPU.

[0110] The memory is used to cache messages, for example, it can be a buffer, including multiple storage units. The data packet receiving circuit is used to receive data packets of the message, identify the data packet type, and provide the received data packet to the write data control circuit and the identifier generation circuit, and provide the identified data packet type to the write control circuit and the write data control circuit. This process is represented as process (1). For example, the data packet type includes the start data packet of the message, the end data packet of the message, and other data packets of the message (for the classification and processing of data packet types, please refer to Figure 7 and Figure 8The data packet receiving circuit determines the data packet type according to the header mark (SOP) and the tail mark (EOP) in the data packet. For example, the data packet with the header mark (SOP) is the start data packet, the data packet with the tail mark (EOP) is the end data packet, the data packet without the header mark (SOP) and the tail mark (EOP) is other data packets, and the data packet with both the header mark (SOP) and the tail mark (EOP) can be classified as the start data packet.

[0111] The write control circuit generates an address for the memory, i.e., a write address, in response to the data packet type provided by the data packet receiving circuit, and provides it to the memory. This process is represented as process (2). The identification generation circuit generates identification information of the message based on one or more received data packets. The identification generation circuit can provide the generated identification information to the write control circuit. This process is represented as process (3-1). In one embodiment, the write data control circuit can provide the received end data packet and other data packets directly to the memory, and delete the header identification (SOP) of the start data packet and provide it to the memory; moreover, the write data control circuit also receives the identification information generated by the identification generation circuit, and provides the identification information and the header identification (SOP) to the memory (for storage in a reserved storage unit).

[0112] In addition, the memory also writes the data packet received from the write data control circuit into the memory according to the address for the memory received from the write control circuit, that is, the memory writes the data packet received from the write data control circuit into the memory according to the write address.

[0113] The read control circuit is used to determine the storage address of the data to be read, that is, the read address, read the data according to the read address, and generate a data packet. The read control circuit determines the read address of the data to be read by incrementing the read address of the data that generated the previous data packet, which is represented as process (4). In one application scenario, the read address can be incremented sequentially, for example, each time the read is performed, the read address is incremented by 1 (or 2, or 3, which can be determined according to the size of the address space occupied by the storage unit); in another application scenario, the read address can also be incremented in a jump manner according to a predetermined rule, for example, the read address is incremented by 1 at the first jump, and the read address is incremented by 2 at the second jump... Return Fig.12 , the read address is sent to the data packet sending circuit, which is represented as process (8). The data packet sending circuit reads the data packet from the corresponding storage unit of the memory according to the instruction of the read address, which is represented as process (5). The data packet sending circuit sends the received data packet.

[0114] In addition, after writing the identification information of the message into the memory, the write control circuit will also generate a synchronization signal and send it to the read control circuit. That is, after a message is stored, the write control circuit sends a synchronization signal to the read control circuit. This process is represented as process (6). As an example, Fig. 9 After the storage of the first message is completed, a synchronization signal is sent to the read control circuit to instruct the read control circuit to read the first message.

[0115] After all the data packets of a message are read, the read control circuit sends a corresponding read completion notification, which is represented as process (7). The purpose of process (7) is to inform the write control circuit that a message has been read, so that the write control circuit can instruct the memory to store the new message into the storage space occupied by the message. For example, Fig. 9 After the first message is read out, the read control circuit sends a notification to the write control circuit. If the storage space of the memory is full, the write control circuit can instruct the memory to store the newly received data into the storage unit 501, the storage unit 502, etc. to overwrite the first message. As another implementation, after receiving the notification, the write control circuit can also instruct the memory to release the storage space of the first message.

[0116] The read control circuit also has a data output enable signal connected to its input for receiving an external command, which is used to instruct to read and output a message data packet from the memory, and this process is represented as process (9). The write control circuit also has a data write enable signal connected to its output for indicating that the external can send a message to the data packet receiving circuit, and this process is represented as process (10).

[0117] The main function of the write control circuit is to determine the address used for the memory, that is, the write address. The write control circuit will be described below from the perspective of address generation (including pseudo code expressed in computer language). Fig.13 The figure shows the process of storage address changes during message storage. The write address is a variable, denoted by wr; la is the address of the current reserved storage unit, also a variable; D0, D1, D1+1, D1+2 are the storage addresses of the corresponding storage units; it involves messages 1, 2, and 3 stored in sequence, and message 1, message 2, and message 3 are separated by dotted lines; (a) represents the storage process of the first data packet of message 2, (b) represents the storage process of the middle data packet and the end data packet of message 2, (c) represents the storage process of the identification information corresponding to message 2, (d) represents the process of calculating and updating the reserved storage unit address to prepare for the storage of message 3, and (e) represents the storage process of the first data packet of message 3.

[0118] In (a), when all data packets of message 1 are stored or the first data packet of message 2 is received, the address of the reserved storage unit corresponding to message 2 is calculated as la. Since la represents the address of the current reserved storage unit, la points to the address D0 of the next storage unit corresponding to the last data packet of message 1, that is, la=D0, and la remains unchanged during the storage process of other data packets of message 2. When the first data packet of message 2 is received, the address wr of the storage unit storing the first data packet is calculated according to the address of the reserved storage unit corresponding to message 2. For example, the address is wr=la+1=D0+1, that is, the first data packet is stored in the next storage unit of the reserved storage unit.

[0119] In (b), if the middle data packet of message 2 is received, the storage unit address corresponding to the current data packet is calculated according to the storage unit address corresponding to the previous data packet. For example, if the storage unit address of the previous data packet is wr=D0+n, the current storage unit address is wr=D0+n+1. When the end data packet is received, the storage unit address wr corresponding to the current data packet (end data packet) is calculated according to the storage unit address corresponding to the previous data packet. As an example, let wr=D1=the storage unit address corresponding to the previous data packet+1. At the same time, the storage unit address corresponding to the current data packet is cached, that is, D1 is cached. At the same time, the indicator generation circuit is instructed to provide the generated identification information to the write data control circuit.

[0120] In (c), after all data packets of message 2 are stored, the identification information of message 2 needs to be stored. Specifically, the identification information is stored in a reserved storage unit, and the address of the storage unit storing the identification information is the address of the reserved storage unit, that is, wr=la=D0. At this time, the write data control circuit provides the identification information of the message obtained from the identification generation circuit to the memory, and stores it in the storage unit with address D0 in the memory. In (c), dark filling is used to indicate that the identification information is stored in the memory.

[0121] In (d), after writing the identification information of message 2 into the memory, the write control circuit also increments the cache address D1 to obtain D1+1, and uses the incremented cache address D1+1 to update the current reserved storage unit address, and uses it as the next message reserved storage unit address, that is, the reserved storage unit address corresponding to message 3 is D1+1, that is, at this time la=D1+1.

[0122] In (e), when writing the first data packet of message 3, the current storage unit address will point to the address of the next storage unit of the current reserved storage unit, that is, wr=la+1, and the current la=D1+1, so the current wr=D1+2. It can be seen that process (e) is similar to process (a), and at this time the write control circuit will increment the address of the current reserved storage unit to generate an address.

[0123] Combination Fig.12 After writing the identification information of the message into the memory, the write control circuit also synchronizes the address of the last data packet of the previous message (after a message is stored (including the identification information), the address of the last data packet of the previous message will also be updated) to the read control circuit. For example, after the storage of message 2 is completed, the address D1 of the last data packet of message 2 is synchronized to the read control circuit. The read control circuit reads the data packet from the memory according to the read address, and increments the read address as a new read address in response to the data packet being read from the memory; if the read address is equal to the last data packet address of the previous message received from the write control circuit (such as D1), it indicates that the last data packet of message 2 has been read, and message 3 is still in the storage process at this time, so the read control circuit pauses reading the data packet from the memory to wait for the write control circuit to write all of message 3 into the memory. Moreover, the read control circuit is also used to send a corresponding read completion notification after all data packets of a message are read, for example, Fig.13 If message 1 has been read out, the write control circuit can instruct the memory to store the new message into the storage space occupied by message 1 or release the storage space of message 1.

[0124] The above circuit is described from the perspective of memory address generation and change. It should also be noted that the memory writing and reading processes are performed in parallel.

[0125] Fig.14 The parallel processing of message writing and reading is shown. Among them, if the storage of message 1 is completed or the reserved storage unit address is updated, a synchronization signal can be sent to the read control circuit. At this time, the read control circuit starts to read the data packet of message 1 according to the synchronization signal. At the same time, the write control circuit continues to write message 2. It can be seen that the reading of message 1 and the writing of message 2 are carried out in parallel. The synchronization process between the writing and reading operations is mainly used to ensure that a message can be read only after it is stored, and that after a message is read, the storage space occupied by it can be occupied or released by a new message. For example Fig.12 As described in processes (6) and (7).

[0126] According to another aspect of the present application, an embodiment of the present application further provides a storage device, which can be as follows: Fig.15The storage device shown, the storage device 102 includes an interface 103, a control component 104, one or more NVM chips 105 and a DRAM (Dynamic Random Access Memory) 110. The storage device includes the circuit for forwarding messages described in the above embodiment, for example, it can be used to process message forwarding between various circuit units inside the storage device. The above NVM chip 105 includes common storage media such as NAND flash memory. The above interface 103 is used to exchange data with the host (external electronic device). The above control component 104 is used to control data transmission between the interface 103, the NVM chip 105 and the DRAM 110, and is also used for storage management, host logical address to flash physical address mapping, erase leveling, bad block management, etc. The control component 104 can be implemented in a variety of ways such as software, hardware, firmware or a combination thereof. For example, the circuit for message forwarding in the above embodiment can be arranged in the control component 104.

[0127] According to another aspect of the present application, an embodiment of the present application further provides an electronic device, the electronic device comprising a processor and a storage device, the storage device being the storage device mentioned in the above storage device embodiment. Since the above has been introduced in detail, it will not be repeated here.

[0128] It should be noted that, for the purpose of simplicity, the present application describes some methods and embodiments thereof as a series of actions and combinations thereof, but those skilled in the art will appreciate that the scheme of the present application is not limited by the order of the actions described. Therefore, based on the disclosure or teaching of the present application, those skilled in the art will appreciate that some of the steps therein may be performed in other orders or simultaneously. Further, those skilled in the art will appreciate that the embodiments described in the present application may be regarded as optional embodiments, i.e., the actions or modules involved therein are not necessarily necessary for the implementation of one or some schemes of the present application. In addition, depending on the different schemes, the present application also has different emphases on the description of some embodiments. In view of this, those skilled in the art will appreciate that the parts that are not described in detail in a certain embodiment of the present application may also refer to the relevant descriptions of other embodiments.

[0129] In terms of specific implementation, based on the disclosure and teachings of this application, those skilled in the art can understand that several embodiments disclosed in this application can also be implemented by other methods not disclosed herein. For example, with respect to the various units in the electronic device or device embodiments described above, this article splits them on the basis of considering the logical functions, and there may be other splitting methods in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features or functions in the units or components can be selectively disabled. In terms of the connection relationship between different units or components, the connection discussed in the above text in conjunction with the accompanying drawings can be a direct or indirect coupling between units or components. In some scenarios, the aforementioned direct or indirect coupling involves a communication connection using an interface, wherein the communication interface can support electrical, optical, acoustic, magnetic or other forms of signal transmission.

[0130] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they are aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application. Obviously, those skilled in the art may make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A circuit for forwarding a message, the message comprising a plurality of data packets, characterized in that: The circuit includes a data packet receiving circuit, a memory, a write control circuit, a write data control circuit, an identification generating circuit, a read control circuit and a data packet sending circuit: The memory includes a plurality of storage units; The data packet receiving circuit is used to receive a data packet of a message, identify a data packet type, and provide the received data packet to the write data control circuit and the identifier generating circuit, and provide the identified data packet type to the write control circuit and the write data control circuit; The write control circuit generates an address for the memory in response to receiving the data packet type provided by the data packet receiving circuit, and provides the address to the memory; wherein, if the received data packet is the end data packet of a message, the address for the memory is cached, the last data packet address of the previous message is also used as the address for the memory, and the identification generation circuit is instructed to provide the identification information of the generated message to the write data control circuit; After writing the identification information of the message into the memory, the write control circuit also increments the cached address for the memory, and updates the last data packet address of the previous message with the incremented cached address for the memory; If the received data packet is the start data packet of a message, the write control circuit increments the address of the last data packet of the previous message to generate an address for the memory; If the received data packet is another data packet of the message, the write control circuit updates the address for the memory in an incremental manner; The identification generating circuit generates identification information of the message according to the received one or more data packets; The write data control circuit provides the received data packet to the memory; wherein the write data control circuit deletes the header identifier of the start data packet and provides it to the memory, and directly provides the end data packet and other data packets to the memory; writing a data packet received from a write data control circuit to the memory according to an address for the memory received from a write control circuit; The read control circuit reads a data packet from the memory and provides the data packet to the data packet sending circuit; The data packet sending circuit sends out the received data packet.

2. The circuit according to claim 1, characterized in that The write data control circuit provides the identification information of the message obtained from the identification generation circuit to the memory.

3. The circuit according to claim 1 or 2, characterized in that: If the received data packet is the end data packet of the message, after writing the end data packet of the message into the memory, the write control circuit also suspends receiving data packets from the data packet receiving circuit.

4. The circuit according to any one of claims 1 to 3, characterized in that: After the identification information of the message is written into the memory, the write control circuit further generates a synchronization signal and sends it to the read control circuit, indicating that the read control circuit can read the message.

5. The circuit according to any one of claims 1 to 4, characterized in that: The read control circuit reads a data packet from the memory according to a read address, and in response to the data packet being read from the memory, increments the read address to serve as a new read address.

6. The circuit according to any one of claims 1 to 5, characterized in that: After writing the identification information of the message into the memory, the write control circuit also synchronizes the last data packet address of the updated previous message to the read control circuit; If the read address is equal to the last data packet address of the last message received from the write control circuit, the read control circuit suspends reading data packets from the memory.

7. The circuit according to any one of claims 1 to 6, characterized in that: After all data packets of a message are read, the read control circuit sends a read completion notification to the write control circuit, informing the write control circuit that the message has been read.

8. The circuit according to any one of claims 1 to 7, characterized in that: The write control circuit determines the address of the reserved storage unit when the first data packet of the first message starts to be stored, or when all data packets of the second message are stored, wherein the second message is the previous message of the first message, and the reserved storage unit address is the address of the next storage unit of the storage unit corresponding to the last data packet of the second message.

9. The circuit according to claim 8, characterized in that The read control circuit reads the second message, while the write control circuit writes the first message.

10. A method for forwarding a message, wherein the message includes a plurality of data packets, characterized in that: include: Receive a data packet in a first message, and store the data packets of the first message in order in a storage unit after a reserved storage unit, wherein the reserved storage unit is the first storage unit in the memory, or the next storage unit of the storage unit corresponding to the last data packet of the second message, and the second message is the previous message of the first message; wherein, If the data packet is the start data packet of a message, the header identifier is deleted, and the data packet after the header identifier is deleted is stored in the next storage unit of the reserved storage unit; If the data packet is the end data packet of a message or another data packet, the data packet is stored in a storage unit next to the storage unit corresponding to the previous data packet; When the first data packet of the first message starts to be stored, or when all data packets of the second message are stored, the address of the reserved storage unit is also determined; In response to receiving all data packets of the first message, storing identification information indicating the first message in the reserved storage unit; The data packets are read in the order of storage unit addresses from small to large.

Images