Large area gap filling using volume expansion

Abstract

An exemplary method of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within a processing region of a semiconductor processing chamber. The substrate may define one or more features along the substrate. A method may include depositing a silicon-containing material on a substrate. The silicon-containing material may extend within one or more features along the substrate. The method may include providing an oxygen-containing precursor. The method may include annealing a silicon-containing material with an oxygen-containing precursor. The annealing may cause the silicon-containing material to expand within the one or more features. The method may include repeating one or more operations to iteratively fill one or more features on the substrate.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to U.S. Patent Application No. 17 / 737,340, filed on May 5, 2022, entitled “Large Area Gap Fill Using Volumetric Expansions,” the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present technology relates to methods and components for semiconductor processing. More particularly, the present technology relates to systems and methods for depositing silicon-containing materials with reduced void or seam formation. Background Art

[0003] Integrated circuits are made possible by processes that produce intricately patterned layers of material on a substrate surface. Producing patterned materials on a substrate requires controlled methods of forming and removing materials. As device dimensions continue to decrease, features within integrated circuits may become smaller and aspect ratios of structures may increase, and maintaining the dimensions of these structures during processing operations may be challenging. Some processes may result in holes or gaps in the material that may have unwanted or undesirable effects in further processing. As device dimensions continue to increase, developing materials that can control the formation of holes or gaps may become more difficult.

[0004] Therefore, there is a need for improved systems and methods that can be used to produce high quality devices and structures. The present technology addresses these and other needs. Summary of the invention

[0005] An exemplary method of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The substrate may define one or more features along the substrate. The method may include depositing a silicon-containing material on the substrate. The silicon-containing material may extend within one or more features along the substrate. The method may include providing an oxygen-containing precursor. The method may include annealing the silicon-containing material with the oxygen-containing precursor. Annealing may cause the silicon-containing material to expand within the one or more features. The method may include repeating one or more of the operations to iteratively fill one or more features on the substrate.

[0006] In some embodiments, one or more features along the substrate may be characterized by a tapered sidewall. The silicon-containing material deposited on the substrate may define gaps or holes before being annealed by the oxygen-containing precursor. While the silicon-containing material is deposited on the substrate, the temperature within the semiconductor processing chamber may be maintained at greater than or about 300° C. While the silicon-containing material is deposited on the substrate, the pressure within the semiconductor processing chamber may be maintained at greater than or about 100 Torr. The silicon-containing material is annealed at a temperature greater than or about 600° C. The annealing may be performed for a period of time greater than or about 30 minutes.

[0007] Some embodiments of the present technology may include semiconductor processing methods. The method may include providing a first silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The substrate may define one or more features along the substrate. The method may include forming a plasma of the first silicon-containing precursor. The method may include depositing a first silicon-containing material on the substrate. The first silicon-containing material may extend within one or more features along the substrate. The method may include providing a second silicon-containing precursor. The method may include depositing a second silicon-containing material on the first silicon-containing material. The second silicon-containing material may extend within one or more features along the substrate. The method may include providing an oxygen-containing precursor. The method may include annealing the second silicon-containing material with the oxygen-containing precursor. The annealing may cause the second silicon-containing material to expand within the one or more features.

[0008] In some embodiments, the first silicon-containing precursor may be or include tetraethoxysilane. The second silicon-containing precursor may be or include disilane. Depositing the second silicon-containing material may be performed in a semiconductor processing chamber separate from the semiconductor processing chamber in which the first silicon-containing material is deposited. Annealing the second silicon-containing material may increase the thickness of the second silicon-containing material by greater than or about 50%. While depositing the second silicon-containing material on the substrate, the temperature may be maintained at greater than or about 300° C. Depositing the second silicon-containing material on the first silicon-containing material may be performed as a plasma-free operation. The oxygen-containing precursor may be or include steam. Annealing the second silicon-containing material may be performed at a temperature greater than or about 600° C.

[0009] Some embodiments of the present technology may include semiconductor processing methods. The method may include forming a plasma of a first silicon-containing precursor. The method may include depositing a first silicon-containing material on a substrate defining one or more features along the substrate. The first silicon-containing material may extend within the one or more features along the substrate. The method may include providing a second silicon-containing precursor. The method may include depositing a second silicon-containing material on the first silicon-containing material. The second silicon-containing material may extend within the one or more features along the substrate. The method may include providing an oxygen-containing precursor. The method may include forming a plasma of the oxygen-containing precursor. The method may include treating the second silicon-containing material with plasma effluents of the oxygen-containing precursor. The plasma effluents of the oxygen-containing precursor may expand the second silicon-containing material on the substrate.

[0010] In some embodiments, forming the plasma of the oxygen-containing precursor may be performed at a temperature greater than or about 450° C. The plasma of the oxygen-containing precursor may be generated at a plasma power greater than or about 800 W. The oxygen-containing precursor may be or include nitrous oxide, diatomic oxygen, or a combination of both. The first silicon-containing precursor may be or include tetraethoxysilane. The second silicon-containing precursor may be or include disilane. Treating the second silicon-containing material with the plasma effluent of the oxygen-containing precursor may reduce gaps or pores defined in the second silicon-containing material.

[0011] The present technology may provide numerous benefits over conventional systems and techniques. For example, embodiments of the present technology may reduce hole or gap sizes applicable to multiple substrate features. Additionally, the present technology may produce silicon-containing films for gap-fill applications, as well as any other applications where deposited films characterized by reduced hole or gap sizes may be beneficial. These and other embodiments and their many advantages and features are described in more detail in conjunction with the following description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remainder of the specification and the accompanying drawings.

[0013] Figure 1 A schematic cross-sectional view of an exemplary plasma system is shown in accordance with some embodiments of the present technology.

[0014] Figure 2 Operations in a semiconductor processing method according to some embodiments of the present technology are illustrated.

[0015] Figure 3A-Figure 3F Exemplary schematic cross-sectional structures are shown in which material layers are included and created according to some embodiments of the present technology.

[0016] Figure 4 Operations in a semiconductor processing method according to some embodiments of the present technology are illustrated.

[0017] Figure 5A-5D Exemplary schematic cross-sectional structures are shown in which material layers are included and created according to some embodiments of the present technology.

[0018] Several of the drawings are included as schematic diagrams. It should be understood that the drawings are for illustrative purposes only and should not be considered to be to scale unless specifically noted to be to scale. Furthermore, as schematic diagrams, the drawings are provided to aid understanding and may not include all aspects or information compared to actual representations and may include exaggerated material for illustrative purposes.

[0019] In the drawings, similar components and / or features may have the same reference numeral. In addition, various components of the same type may be distinguished by following the reference numeral with a letter that distinguishes between similar components. If only the first reference numeral is used in the specification, such description may apply to any of the similar components having the same first reference numeral, regardless of the letter. DETAILED DESCRIPTION

[0020] As device dimensions continue to shrink, the thickness and size of many material layers may be reduced to scale the device. The size of features across semiconductor structures may be reduced, and the aspect ratio of the features may be increased. As the aspect ratio of features increases, the chemical vapor deposition process may create holes or gaps within the features due to pinching off near the top of the feature before the feature is fully filled.

[0021] Conventional techniques, such as operations associated with 3D NAND, have been focused on producing films to fill high aspect ratio features in underlying structures that control hole or gap formation. Deposition of silicon-containing materials on underlying structures containing high aspect ratio trenches may be incomplete because many silicon-containing film depositions produce conformal films. The filling operation may result in feature sealing near the top of the feature before filling within the feature, which may produce holes in the filling material or gaps in the middle of the feature, which may extend to the top of the structure. In some production where polishing operations may be performed subsequently, removal may result in exposure of holes or gaps, which may provide access within the feature. Once exposed to the atmosphere, this may allow oxidation of the material, as well as the incorporation of slurry or other materials along the holes or gaps. Therefore, many conventional techniques are limited in their ability to prevent structural defects in the final device.

[0022] The present technology overcomes these problems by annealing the film on the underlying structure to reduce the presence or size of any holes or gaps in the film. By annealing the film with an oxygen-containing precursor, the present technology can change the film on the underlying structure to expand a portion of the film to reduce any holes or gaps in the film, which enables the subsequent deposition of silicon-containing materials to gradually fill the features while minimizing the formation of holes or gaps. By filling features or high aspect ratio structures with silicon-containing materials with reduced or eliminated holes or gaps, the present technology can prevent problems in any subsequent integration processing and / or defects in the final device. Although the remainder of this article will conventionally identify specific deposition processes utilizing the disclosed technology and will describe a type of semiconductor processing chamber, it will be readily understood that the described process can be performed in any number of semiconductor processing chambers. Therefore, the present technology should not be considered to be limited to use with these specific deposition processes or chambers. Before describing the method of semiconductor processing according to the present technology, the present disclosure will discuss a possible chamber that can be used to perform processing according to an embodiment of the present technology.

[0023] Figure 1 A cross-sectional view of an exemplary semiconductor processing chamber 100 according to some embodiments of the present technology is shown. The figure may show an overview of a system that incorporates one or more aspects of the present technology and / or may be specifically configured to perform one or more operations according to embodiments of the present technology. Additional details of the chamber 100 or the method performed may be further described below. According to some embodiments of the present technology, the chamber 100 may be used to form a film layer, although it should be understood that the method may be similarly performed in any chamber where film formation may occur. The semiconductor processing chamber 100 may include a chamber body 102, a substrate support 104 disposed inside the chamber body 102, and a lid assembly 106 coupled to the chamber body 102 and enclosing the substrate support 104 in a processing space 120. The substrate 103 may be provided to the processing space 120 through an opening 126, which may be conventionally sealed for processing using a slit valve or door. During processing, the substrate 103 may be placed on a surface 105 of the substrate support 104. As indicated by arrow 145, the substrate support 104 may be rotated along an axis 147, wherein the shaft 144 of the substrate support 104 may be located at the axis 147. Alternatively, the substrate support 104 may be lifted for rotation as desired during a deposition process.

[0024] The plasma profile modulator 111 may be disposed in the semiconductor processing chamber 100 to control the plasma distribution on the substrate 103 disposed on the substrate support 104. The plasma profile modulator 111 may include a first electrode 108, which may be disposed adjacent to the chamber body 102 and may separate the chamber body 102 from other components of the lid assembly 106. The first electrode 108 may be part of the lid assembly 106, or may be a separate sidewall electrode. The first electrode 108 may be a ring or annular member, and may be a ring electrode. The first electrode 108 may be a continuous ring around the circumference of the semiconductor processing chamber 100 surrounding the processing space 120, or may be discontinuous at selected locations as desired. The first electrode 108 may also be a perforated electrode, such as a perforated ring or mesh electrode, or may be a plate-like electrode, such as, for example, a secondary gas distributor.

[0025] One or more isolators 110a, 110b, which may be dielectric materials such as ceramics or metal oxides, e.g., aluminum oxide and / or aluminum nitride, may contact the first electrode 108 and electrically and thermally separate the first electrode 108 from the gas distributor 112 and the chamber body 102. The gas distributor 112 may define an aperture 118 for distributing process precursors into the processing volume 120. The gas distributor 112 may be coupled to a first power source 142, such as an RF generator, an RF power supply, a DC power supply, a pulsed DC power supply, a pulsed RF power supply, or any other power source that may be coupled to the semiconductor processing chamber 100. In some embodiments, the first power source 142 may be an RF power supply.

[0026] The gas distributor 112 may be a conductive gas distributor or a non-conductive gas distributor. The gas distributor 112 may also be formed of conductive and non-conductive elements. For example, the body of the gas distributor 112 may be conductive, while the panel of the gas distributor 112 may be non-conductive. The gas distributor 112 may be formed of conductive and non-conductive elements. Figure 1 The first power source 142 is shown to provide power, or in some embodiments, the gas distributor 112 may be grounded.

[0027] The first electrode 108 may be coupled to a first tuning circuit 128, which may control a ground path for the semiconductor processing chamber 100. The first tuning circuit 128 may include a first electronic sensor 130 and a first electronic controller 134. The first electronic controller 134 may be or include a variable capacitor or other circuit element. The first tuning circuit 128 may be or include one or more inductors 132. The first tuning circuit 128 may be any circuit that achieves a variable or controllable impedance under plasma conditions present in the processing space 120 during processing. In some embodiments shown, the first tuning circuit 128 may include a first branch and a second branch coupled in parallel between ground and the first electronic sensor 130. The first branch may include a first inductor 132A. The second branch may include a second inductor 132B coupled in series with the first electronic controller 134. The second inductor 132B may be disposed between the first electronic controller 134 and a node connecting both the first branch and the second branch to the first electronic sensor 130. The first electronic sensor 130 may be a voltage or current sensor and may be coupled to a first electronic controller 134 , which may provide a degree of closed-loop control of the plasma conditions within the processing volume 120 .

[0028] The second electrode 122 may be coupled to the substrate support 104. The second electrode 122 may be embedded within the substrate support 104 or coupled to the surface 105 of the substrate support 104. The second electrode 122 may be a plate, a perforated plate, a mesh, a wire mesh, or any other distributed arrangement of conductive elements. The second electrode 122 may be a tuning electrode and may be coupled to a second tuning circuit 136 through a conduit 146, such as a cable having a selected resistance of, for example, 50 ohms, disposed in the shaft 144 of the substrate support 104. The second tuning circuit 136 may have a second electronic sensor 138 and a second electronic controller 140, which may be a second variable capacitor. The second electronic sensor 138 may be a voltage or current sensor and may be coupled to the second electronic controller 140 to provide further control of the plasma conditions in the processing volume 120.

[0029] The third electrode 124, which may be a bias electrode and / or an electrostatic adsorption electrode, may be coupled to the substrate support 104. The third electrode may be coupled to a second power source 150 via a filter 148, which may be an impedance matching circuit. The second power source 150 may be a DC power source, a pulsed DC power source, an RF bias power source, a pulsed RF power source, or a bias power source, or a combination of these or other power sources. In some embodiments, the second power source 150 may be an RF bias power source. The substrate support 104 may also include one or more heating elements configured to heat the substrate to a processing temperature, which may be between about 25° C. and about 800° C. or higher.

[0030] Figure 1 The lid assembly 106 and substrate support 104 can be used with any processing chamber for performing plasma or thermal processing. In operation, the semiconductor processing chamber 100 can provide real-time control of plasma conditions in the processing space 120. The substrate 103 can be placed on the substrate support 104, and the processing gas can be flowed through the lid assembly 106 using the inlet 114 according to any desired flow plan. The gas can exit the semiconductor processing chamber 100 through the outlet 152. Electrical power can be coupled to the gas distributor 112 to establish a plasma in the processing space 120. In some embodiments, the substrate can be subjected to an electrical bias using the third electrode 124.

[0031] When the plasma in the processing space 120 is ignited, a potential difference can be established between the plasma and the first electrode 108. A potential difference can also be established between the plasma and the second electrode 122. The electronic controllers 134, 140 can then be used to adjust the flow characteristics of the ground path represented by the two tuning circuits 128 and 136. The set point can be transmitted to the first tuning circuit 128 and the second tuning circuit 136 to provide independent control of the deposition rate and plasma density uniformity from the center to the edge. In an embodiment where both electronic controllers can be variable capacitors, the electronic sensors can adjust the variable capacitors to independently maximize the deposition rate and minimize the thickness non-uniformity.

[0032] Each of the tuning circuits 128, 136 may have a variable impedance that can be adjusted using the corresponding electronic controller 134, 140. In the case where the electronic controllers 134, 140 are variable capacitors, the capacitance range of each variable capacitor and the inductance of the first inductor 132A and the second inductor 132B may be selected to provide an impedance range. This range may depend on the frequency and voltage characteristics of the plasma, which may have a minimum value within the capacitance range of each variable capacitor. Therefore, when the capacitance of the first electronic controller 134 is at a minimum or maximum, the impedance of the first tuning circuit 128 may be high, resulting in a plasma shape with minimal aerial or lateral coverage on the substrate support 104. When the capacitance of the first electronic controller 134 approaches a value that minimizes the impedance of the first tuning circuit 128, the aerial coverage of the plasma may grow to a maximum, effectively covering the entire working area of ​​the substrate support 104. When the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape may shrink from the chamber wall and the aerial coverage of the substrate support 104 may decrease. The second electronic controller 140 may have a similar effect, as the capacitance of the second electronic controller 140 may be varied to increase and decrease the aerial coverage of the plasma on the substrate support 104 .

[0033] The electronic sensors 130, 138 can be used to tune the respective circuits 128, 136 in a closed loop. Depending on the type of sensor used, a set point for current or voltage can be installed in each sensor, and the sensors can be provided with control software that determines the adjustment to each respective electronic controller 134, 140 to minimize deviations from the set point. Thus, the plasma shape can be selected and dynamically controlled during processing. It should be understood that although the above discussion is based on electronic controllers 134, 140 that can be variable capacitors, any electronic component with an adjustable characteristic can be used to provide an adjustable impedance for the tuning circuits 128 and 136.

[0034] Figure 2 Exemplary operations in a processing method 200 according to some embodiments of the present technology are shown. The method 200 may be performed in a variety of processing chambers, including the semiconductor processing chamber 100 described above, as well as any other chamber in which operations may be performed, including non-plasma chambers. The method 200 may include one or more operations prior to the start of the method 200, including front-end processing, deposition, etching, polishing, cleaning, or any other operation that may be performed prior to the operation. The method 200 may include a plurality of optional operations, which may or may not be specifically associated with some embodiments of the method according to embodiments of the present technology. For example, many operations are described to provide a broader scope of the processing performed, but are not critical to the technology, or may be performed by alternative methods as further discussed below. The method 200 may describe Figure 3A-Figure 3F The operations schematically shown in FIG. 2 will be described in conjunction with the operations of method 200. It should be understood that the drawings illustrate only partial schematics, and that the substrate may include any number of additional materials and features having the various properties and aspects shown.

[0035] The method 200 may or may not involve developing the semiconductor structure into a selective operation of a particular manufacturing operation. It should be understood that the method 200 may be performed on any number of semiconductor structures or substrates 305, such as Figure 3A As shown, an exemplary structure 300 includes one or more silicon-containing materials on which one or more silicon-containing materials may be formed. Figure 3AAs shown, substrate 305 may be processed to form one or more features 315, which may be recessed, such as trenches, holes, or any other structure in semiconductor processing. Substrate 305 may be any number of materials, such as a base wafer or substrate 305 made of silicon or silicon-containing materials, other substrate 305 materials, and one or more materials that may be formed on substrate 305 during semiconductor processing. For example, in some embodiments, substrate 305 may be processed to include one or more materials or structures for semiconductor processing. Substrate 305 may be or include a dielectric material, such as an oxide or nitride of any number of materials. In an embodiment, one or more layers of material 310 may be deposited on substrate 305. In an embodiment, one or more layers of material 310 may be or include a silicon-containing material. The silicon-containing material may be or include silicon, including amorphous silicon, doped silicon, silicon oxide, silicon nitride, or silicon carbide.

[0036] As shown, one or more features 315 may be defined by one or more layers of material 310 and / or substrate 305, such as grooves, holes, or other recessed features. Features 315 may be characterized by tapered sidewalls. In embodiments, features 315 may be characterized by a diameter or width at the top of feature 315 being greater than a diameter or width at the bottom of feature 315. The aspect ratio of feature 315, or the ratio of the depth of the feature relative to the width or diameter of the feature formed, may be greater than or about 1:1, and may be greater than or about 2:1, greater than or about 3:1, greater than or about 4:1, greater than or about 5:1, greater than or about 6:1, greater than or about 7:1, greater than or about 8:1, greater than or about 9:1, greater than or about 10:1, or greater. Although only one feature 315 is shown, it should be understood that exemplary structures may have any number of features 315 defined along the structure according to embodiments of the present technology.

[0037] At operation 205, method 200 may include providing a silicon-containing precursor to a processing area of ​​a semiconductor processing chamber. The silicon-containing precursor may be provided to the same processing area of ​​the semiconductor processing chamber to perform operations before the method 200 begins. The silicon-containing precursor that may be used in method 200 may be or include any number of silicon-containing precursors. For example, the silicon-containing precursor may be or include silane (SiH4), disilane (Si2H6), silicon tetrachloride (SiCl4), tetraethoxysilane (TEOS), or any other precursor capable of forming, for example, silicon oxide (SiO), silicon nitride (SiN), or silicon carbide (SiC) materials. In some embodiments, along with the silicon-containing precursor, one or more additional precursors may be delivered, such as a hydrogen-containing precursor and one or more carrier gases or inert gases, such as argon or helium. Although higher-order silanes may be used in embodiments of the present technology, and they may produce an increased flow of deposited material, the increased hydrogen content in the just-deposited material may result in degassing in subsequent operations.

[0038] At operation 210 and as Figure 3B As shown, method 200 may include depositing a silicon-containing material 320a on substrate 305 and one or more layers of material 310 (if present). The silicon-containing precursor may contact substrate 305 and one or more layers of material 310 (if present). Figure 3B As shown, when exposed, silicon-containing material 320a may extend along any and / or all exposed surfaces along substrate 305 along with any other incorporated materials, such as one or more layers of material 310. During operation 225, growth may occur within feature 315 from the sidewalls defining feature 315 inwardly.

[0039] Depositing the silicon-containing material 320a on the substrate 305 at operation 215 can be performed as a plasma-free operation. By performing operation 215 without plasma, the deposition of the silicon-containing material 320a can be highly conformal. In an embodiment, the deposition of the silicon-containing material 320a can be characterized by a conformality of greater than or about 80%, greater than or about 85%, greater than or about 90%, greater than or about 95%, or greater. This high level of conformality can be beneficial during expansion of the silicon-containing material 320a in a subsequent anneal, as further described below, because the silicon-containing material 320a can expand at all depths of the feature 315.

[0040] As the feature 315 begins to close or fill with silicon-containing material 320a, a hole 330 and / or a gap 335 may be formed in the silicon-containing material 320a. The hole 330 may refer to the portion of the feature 315 between the silicon-containing material 320a deposited at the bottom and top of the feature 315. The hole 330 may be formed due to the accumulation or "breadloafing" of the silicon-containing material 320a deposited at the top of the feature 315. The gap 335 may refer to a gap or groove extending into the silicon-containing material 320a at or near the bottom of the feature 315. Although illustrated as a uniform opening in the figure, it should be understood that the features of the hole 330 and / or gap 335 structures may be additionally characterized by a variety of shapes, which may include top wide, bottom wide, and more amorphous shapes, as will be readily understood by those skilled in the art. At longer deposition times, the amount of deposition on top of feature 315 may begin to completely close feature 315, such that voids 330 or gaps 335 are formed and covered by silicon-containing material 320a. At even longer periods of time, voids 330 or gaps 335 may no longer be filled by silicon-containing material 320a. The present technique may be combined with one or more annealing processes to expand silicon-containing material 320a to reduce or eliminate any voids 330 and / or gaps 335.

[0041] During the above deposition, the semiconductor processing chamber, pedestal, or substrate 305 can be maintained at various temperatures at which film deposition can be performed. In some embodiments, the temperature of the semiconductor processing chamber, pedestal, or substrate 305 can be maintained at less than or about 700° C., less than or about 650° C., less than or about 600° C., less than or about 550° C., less than or about 500° C., or lower. In embodiments, the temperature of the semiconductor processing chamber, pedestal, or substrate 305 can be maintained at greater than or about 300° C., greater than or about 350° C., greater than or about 400° C., greater than or about 450° C., greater than or about 500° C., or higher, which can promote thermal decomposition of the precursor, thereby allowing plasma-free deposition to be performed.

[0042] Also during the above deposition, the semiconductor processing chamber may be maintained at various pressures at which deposition may be performed. For example, when depositing the silicon-containing material 320a, the pressure within the semiconductor processing chamber may be maintained at greater than or about 100 Torr, and may be maintained at greater than or about 150 Torr, greater than or about 200 Torr, greater than or about 250 Torr, greater than or about 300 Torr, greater than or about 350 Torr, greater than or about 400 Torr, or higher. Similarly, when depositing the silicon-containing material 320a, the pressure within the semiconductor processing chamber may be maintained at less than or about 500 Torr, and may be maintained at less than or about 450 Torr, less than or about 400 Torr, less than or about 350 Torr, less than or about 300 Torr, less than or about 250 Torr, less than or about 200 Torr, or lower.

[0043] At operation 215, after depositing the silicon-containing material 320a, the method 200 may include providing an oxygen-containing precursor. In some embodiments, the method 200 may include stopping the flow of the silicon-containing precursor before operation 215. Stopping the flow of the silicon-containing precursor may stop the deposition, thereby allowing the deposited film to be processed, such as annealing. The oxygen-containing precursor may be provided to the same processing area of ​​the semiconductor processing chamber to deposit the silicon-containing material 320a, and may continue from the (multiple) deposition operations described above. In other embodiments, the structure 300 may be moved to a different chamber before operation 215. The oxygen-containing precursor that can be used for the method 200 may be or include any number of oxygen-containing precursors. For example, the oxygen-containing precursor may be or include nitrous oxide (N2O), water (H2O), diatomic oxygen (O2), ozone (O3), a combination of one or more of these, or any other oxygen-containing material.

[0044] In some embodiments, the method 200 may include forming a plasma of an oxygen-containing precursor in operation 220. The plasma power may affect the depth of oxygen penetration, may reduce the temperature required to expand the silicon-containing material 320a, and / or may increase the amount of hole 330 and / or gap 335 removal that may occur. Thus, in some embodiments, the plasma power applied when generating the plasma of the oxygen-containing precursor may be greater than or about 800 W, greater than or about 850 W, greater than or about 900 W, greater than or about 1000 W, or higher. However, at higher plasma powers, bombardment may increase and may result in sputtering and / or etching of the silicon-containing material 320a, and thus, in some embodiments, the plasma power may be less than or about 1500 W, less than or about 1400 W, less than or about 1300 W, less than or about 1200 W, less than or about 1000 W, or lower. When forming a plasma containing an oxygen precursor, the temperature within the semiconductor processing chamber may be maintained at greater than or about 450° C., and may be maintained at greater than or about 500° C., greater than or about 550° C., greater than or about 600° C., or higher. When forming a plasma containing an oxygen precursor, the temperature may be maintained at less than or about 650° C., and may be maintained at less than or about 600° C., less than or about 550° C., less than or about 500° C., or lower. In embodiments where a plasma containing an oxygen precursor is formed, the oxygen-containing precursor may include one or both of N2O and O2.

[0045] At operation 225 and as Figure 3C As shown, method 200 may include annealing silicon-containing material 320a with an oxygen-containing precursor or plasma effluents of an oxygen-containing precursor. As previously described, when depositing silicon-containing material 320a, holes 330 and / or gaps 335 may form in silicon-containing material 320a due to increased sidewall deposition that may close inwardly and seal feature 315 before completely filling feature 315. In order to reduce or remove these holes 330 or gaps 335, the present technology may expand silicon-containing material 320a by annealing the film. Due to the incorporation of oxygen into silicon-containing material 320a, the oxygen-containing precursor or plasma effluents of an oxygen-containing precursor may cause silicon-containing material 320a to expand inwardly from the sidewalls of feature 315 when formed.

[0046] Annealing may cause the silicon-containing material 320a to expand within one or more features 315. As the silicon-containing material 320a expands within the features 315, the material may expand in all directions of the features 315 and reduce any unfilled spaces between the silicon-containing material 320a deposited on the sidewalls of the features 315. Without being bound by any particular theory, during annealing, the silicon-containing material 320a may expand inwardly and may coalesce across the features 315 during expansion and annealing. Thus, treating the silicon-containing material 320a with an oxygen-containing precursor, such as with plasma effluent of an oxygen-containing precursor, may reduce any voids 330 or gaps 335 defined in the silicon-containing material 320a.

[0047] During operation 225, the temperature may be increased compared to the temperature used during the previous deposition operation. When annealing the silicon-containing material 320a, the temperature within the semiconductor processing chamber in which the annealing may be performed may be maintained at greater than or about 600°C, and may be maintained at greater than or about 650°C, greater than or about 700°C, greater than or about 750°C, greater than or about 800°C, greater than or about 850°C, greater than or about 900°C, or higher. However, at higher temperatures, one or more layers of the substrate 305 and / or material 310 (if present) may also be affected by the annealing. For example, in embodiments using a substrate 305 that is or includes silicon, the substrate 305 may also begin to oxidize. Thus, when annealing the silicon-containing material 320a, the temperature within the semiconductor processing chamber may be maintained at less than or about 1000°C, and may be maintained at less than or about 950°C, less than or about 900°C, less than or about 850°C, less than or about 800°C, less than or about 750°C, less than or about 700°C, or less. In embodiments where the silicon-containing material 320a is treated with plasma effluents containing an oxygen-containing precursor, the temperature at which the annealing and expansion of the silicon-containing material 320a is performed may be below the temperature of thermally induced oxidation. In such embodiments, when annealing the silicon-containing material 320a, the temperature within the semiconductor processing chamber may be maintained at less than or about 600°C, and may be maintained at less than or about 575°C, less than or about 550°C, or less.

[0048] At operation 225, the silicon-containing material 320a is annealed with the oxygen-containing precursor, or the plasma effluent of the oxygen-containing precursor (if present), and can be continued for a sufficient time to expand the silicon-containing material 320a in the feature 315 by a desired amount. The time may depend on various factors, including, but not limited to, the depth of the feature 315, the aspect ratio of the feature 315, and / or the thickness of the silicon-containing material 320a. In some embodiments, the annealing can be performed for a time period greater than or about 30 minutes, and can be greater than or about 45 minutes, greater than or about 60 minutes, greater than or about 75 minutes, greater than or about 90 minutes, greater than or about 105 minutes, greater than or about 120 minutes, greater than or about 150 minutes, greater than or about 180 minutes, greater than or about 210 minutes, greater than or about 240 minutes, or longer. At longer time periods, treating the silicon-containing material 320a with the oxygen-containing precursor or the plasma effluent of the oxygen-containing precursor (if present) can result in increased expansion of the silicon-containing material 320a. Thus, in some embodiments, processing may be performed for less than or about 180 minutes, less than or about 150 minutes, less than or about 120 minutes, or less.

[0049] During operation 225, the thickness of the silicon-containing material 320a may increase depending on how long the silicon-containing material 320a is annealed. This may be due, at least in part, to the incorporation of oxygen into the film and the conversion of the silicon film into a silicon oxide film. Under a shorter annealing process, the increased thickness of the silicon-containing material 320a may be smaller. Under a longer annealing process, the increased thickness of the silicon-containing material 320a may be greater. In an embodiment, annealing the silicon-containing material 320a may increase the thickness of the silicon-containing material 320a by greater than or about 50%, and may increase the thickness of the silicon-containing material 320a by greater than or about 60%, greater than or about 70%, greater than or about 80%, greater than or about 90%, greater than or about 100%, greater than or about 110%, or more. Annealing the silicon-containing material 320a may increase the thickness of the silicon-containing material 320a by less than or about 120%, and may increase the thickness of the silicon-containing material 320a by less than or about 110%, less than or about 100%, or less.

[0050] like Figure 3D-Figure 3E As shown, to fill feature 315 while reducing or eliminating voids 330 and / or gaps 335, method 200 may include sequentially depositing silicon-containing materials, such as additional silicon-containing material 320b, and then annealing additional silicon-containing material 320b with an oxygen-containing precursor. After annealing, additional silicon-containing material 320b may combine and conform to previously annealed silicon-containing material 320a to form combined silicon-containing material 320c. This process may be repeated for any number of cycles. Figure 3FAs shown, when the deposition and annealing of the silicon-containing material are cycled, during each deposition and annealing sequence, one or more features 315 can be iteratively filled higher in the bottom-up gap fill, such as toward the top of the feature 315. As previously described, annealing the silicon-containing material 320b with an oxygen-containing precursor or plasma effluents of an oxygen-containing precursor can cause the silicon-containing material 320b to expand. By repeatedly depositing and annealing the silicon-containing material, the material can expand and the voids 330 and / or gaps 335 can be reduced or completely eliminated.

[0051] The number of iterations of sequentially depositing and annealing the film may depend on a variety of factors, including, but not limited to, the depth of feature 315, the aspect ratio of feature 315, the amount of silicon-containing material deposited, and / or the presence of voids 330 and / or gaps 335 in the silicon-containing material. In some embodiments, method 200 of depositing and annealing the silicon-containing material may be repeated at least twice, and may include depositing and annealing the silicon-containing material at least three times, at least four times, at least five times, at least six times, at least seven times, or more times.

[0052] In embodiments where silicon-containing material 320 is repeatedly deposited in feature 315 and subsequently annealed, earlier films may expand more than later films. This may be due to the smaller film thickness subsequently deposited in feature 315 to control expansion. Additionally, as previously described, one or more features 315 along substrate 305 may be characterized by tapered sidewalls. Due to the previously described conformal deposition, the sidewall profile may challenge gap filling with eliminated voids 330 and / or seams 335. However, the present technology may be able to overcome any number of topography and / or feature geometries to produce reduced void space or no void fill.

[0053] Some embodiments of the present technology may also provide non-cyclic filling, which may improve throughput. Figure 4 Exemplary operations in a processing method 400 according to some embodiments of the present technology are shown. The method 400 may be performed in a variety of processing chambers, including the semiconductor processing chamber 100 described above, as well as any other chamber in which operations may be performed, including non-plasma chambers. The method 400 may include any aspects, materials, or features of the method 200 described above. The method 400 may include a plurality of optional operations, which may or may not be specifically associated with some embodiments of the method according to embodiments of the present technology. For example, many operations are described to provide a broader scope of the processing performed, but are not critical to the technology, or may be performed by alternative methods as further discussed below. The method 400 may describe Figure 5A-5D The operations schematically illustrated in FIG. 4 will be described in conjunction with the operations of method 400. It should be understood that the drawings illustrate only partial schematics, and that the substrate may include any number of additional materials and features having the various properties and aspects shown.

[0054] The method 400 may or may not involve selective operations to develop the semiconductor structure into a particular manufacturing operation. It should be understood that the method 400 may be performed on any number of semiconductor structures or substrates 505, such as Figure 5A 3. As shown, an exemplary structure 500 including one or more silicon-containing materials may be formed thereon. Substrate 505 may have any aspect, quality, or characteristic described with respect to substrate 305. Substrate 505 may also have features 515 similar to features 315 described with respect to substrate 305.

[0055] In an embodiment, a first silicon-containing material may be deposited before depositing a silicon-containing material that may undergo volume expansion. For example, a first silicon oxide material may be formed within a feature to a first thickness, and then silicon oxide may be formed as described above, which may provide a final fill operation that may produce a reduced or void-free fill. At operation 405, method 400 may include providing a first silicon-containing precursor to a processing region of a semiconductor processing chamber, such as semiconductor processing chamber 100, in which substrate 505 may be accommodated. In some embodiments, an oxygen-containing precursor may be provided with the silicon-containing precursor. The semiconductor processing chamber may be a chamber that is the same as or different from a chamber in which a pre-processing or earlier processing operation may be performed. The first silicon-containing precursor may be or include any silicon-containing precursor previously discussed with respect to operation 205 of method 200, as well as any oxygen-containing precursor discussed above. In some embodiments, a precursor containing silicon and oxygen may be used as the first silicon-containing precursor, and may be or include, for example, TEOS.

[0056] At operation 410, method 400 may include forming a plasma of a first silicon-containing precursor, which may also include forming a plasma of an oxygen-containing precursor or other deposition precursors (if included). Plasma power may affect the depth of silicon penetration, the degree of bond redirection, and / or the amount of void 530 and / or gap 535 formation that may subsequently occur. Thus, in some embodiments, the plasma power applied when generating a plasma of a silicon-containing precursor (such as the first plasma power applied in method 400) may be less than or about 2000 W, and may be less than or about 1500 W, less than or about 1250 W, less than or about 1000 W, less than or about 750 W, less than or about 500 W, less than or about 250 W, or less. However, at lower plasma powers, the plasma effluent of the silicon-containing precursor may not easily reach the full depth of feature 515, and therefore, in some embodiments, the plasma power can be greater than or about 250 W, greater than or about 500 W, greater than or about 750 W, greater than or about 1000 W, or more.

[0057] At operation 415 and as Figure 5BAs shown, method 400 may include depositing a first silicon-containing material 517 on substrate 505 and / or one or more layers of material 510. In some embodiments, as a non-limiting example, the deposited film may be a film sought for gap filling, such as silicon oxide. The plasma effluent of the first silicon-containing precursor may contact substrate 505, and one or more layers of material 510 (if present). Figure 5B As shown, when exposed, first silicon-containing material 520 may extend along any and / or all exposed surfaces along substrate 505 along with any other incorporated materials, such as one or more layers of material 510. During operation 415, growth may occur inwardly within feature 515 from the sidewalls defining feature 515. First silicon-containing material 517 may be silicon or a silicon-containing film, and in some embodiments, the first silicon-containing material may be a silicon and oxygen-containing film.

[0058] The deposition of the first silicon-containing material 517 can be substantially conformal, and thus, growth can occur inwardly from the sidewalls defining the feature 515 into the feature 515, wherein the growth rate inwardly from the sidewalls can be less than or equal to the growth rate at the bottom and top of the feature 515. The amount of deposition can vary based on the amount of time that the deposition of the first silicon-containing material 517 is performed. Although the amount of deposition can vary, during the deposition of operation 415, a greater amount of the first silicon-containing material 517 can be deposited at the bottom of the feature 515 than at the top of the feature 515. Furthermore, in some embodiments, a greater amount of the first silicon-containing material 517 can be deposited at the bottom and / or top of the feature 515 than at the sidewalls defining the feature 515.

[0059] The deposition of the first silicon-containing material may be performed to fill the feature by an amount to reduce or limit iterations of deposition of the second silicon-containing material. For example, in some embodiments, the first silicon-containing material may be deposited to fill greater than or about 10% of the width or diameter of the filled feature, and may be deposited to fill greater than or about 15%, greater than or about 20%, greater than or about 25%, greater than or about 30%, greater than or about 35%, greater than or about 40%, greater than or about 45%, greater than or about 50%, greater than or about 55%, greater than or about 60%, greater than or about 65%, greater than or about 70%, greater than or about 75%, greater than or about 80%, or more. However, as the amount of deposition increases, the likelihood of voids being formed by pinching off may increase. Thus, to help maintain access to the feature, the first silicon-containing material may be deposited to fill less than or about 85% of the width or diameter of the feature being filled, and may be deposited to fill less than or about 80%, less than or about 75%, less than or about 70%, less than or about 65%, less than or about 60%, less than or about 55%, less than or about 50%, or less.

[0060] At operation 420, method 400 may include providing a second silicon-containing precursor to a processing region of a second semiconductor processing chamber. Prior to operation 420, structure 500 may be moved to a different semiconductor processing chamber. In other embodiments, the second silicon-containing precursor may be provided to the same processing region of the semiconductor processing chamber to deposit the first silicon-containing material 517, and the deposition operation may continue as described above. In embodiments, the first silicon-containing precursor may be or include TEOS, as previously described, and the second silicon-containing precursor may be or include Si2H6, although any silicon-containing material as previously described may be used in embodiments of the present technology. At operation 425 and as described above, the first silicon-containing precursor may be provided to the same processing region of the semiconductor processing chamber to deposit the first silicon-containing material 517. Figure 5C As shown, method 400 may include depositing a second silicon-containing material 520 on substrate 505, one or more layers of material 510 (if present), and / or first silicon-containing material 517. The second silicon-containing precursor may contact substrate 505, one or more layers of material 510 (if present), and / or first silicon-containing material 517. Figure 5C As shown, when exposed, the second silicon-containing material 520 can extend along any and / or all exposed surfaces along the substrate 505 along with any other incorporated materials (such as one or more layers of material 510 and / or the first silicon-containing material 517). The second silicon-containing precursor and the second silicon-containing material 520 can share any qualities, properties, or characteristics with the silicon-containing material 320 previously described with respect to the method 200.

[0061] Although operation 415 may include plasma enhanced deposition, depositing the second silicon-containing material 525 on the substrate 505 or on the first silicon-containing material 517 at operation 425 may be performed as a plasma-free operation. By performing operation 425 without plasma, the deposition of the second silicon-containing material 520 may be highly conformal. In an embodiment, the deposition of the second silicon-containing material 520 may be characterized by a conformality of greater than or about 80%, greater than or about 85%, greater than or about 90%, greater than or about 95%, or greater. This high level of conformality may be beneficial during expansion of the second silicon-containing material 520 in a subsequent anneal, as further described below, because the second silicon-containing material 520 may expand at all depths of the feature 515. Similar to method 200, as the feature 515 begins to close or fill with the silicon-containing material 520, a hole 530 and / or a gap 535 may be formed in the silicon-containing material 520.

[0062] During the above deposition, the semiconductor processing chamber, pedestal, or substrate 505 can be maintained at a temperature as described above with respect to method 200. Similarly, the semiconductor processing chamber can be maintained at a pressure as described above with respect to method 200. Based on the amount of the first silicon-containing material deposited in the feature, the second silicon-containing material can be deposited to provide a single expansion operation, although multiple cycles can be performed as previously described. For example, after depositing the first silicon-containing material to any thickness related to the feature size as discussed above, the second silicon-containing material can be deposited to less than, greater than, or about 50% of the remaining width or diameter of the feature to be filled.

[0063] At operation 430, after depositing the silicon-containing material 520, the method 400 may include providing an oxygen-containing precursor to a second processing region of the second semiconductor processing chamber to process the silicon-containing material 520. In some embodiments, the method 400 may include forming a plasma of the oxygen-containing precursor at operation 435. At operation 440 and as Figure 5D As shown, method 400 may include annealing silicon-containing material 520 with an oxygen-containing precursor or plasma effluent of an oxygen-containing precursor. Processing silicon-containing material 520 may be similar to and share any features of operations 215-225 as described above with respect to method 200.

[0064] In embodiments where the silicon-containing material is deposited and annealed only once, some voids 530 and / or seams 535 may remain in feature 515 based on the degree of expansion of the entire feature and the amount of material deposited. However, in such embodiments, the presence of voids 530 and / or seams 535 may still be reduced compared to conventional techniques.

[0065] In the foregoing description, for the purpose of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that certain embodiments may be practiced without some of these details or with other details.

[0066] Several embodiments have been disclosed, and those skilled in the art will recognize that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the embodiments. In addition, in order to avoid unnecessarily confusing the present technology, many well-known processes and elements are not described. Therefore, the above description should not be considered to limit the scope of the present technology.

[0067] Where a range of values ​​is provided, it is understood that, unless the context clearly indicates otherwise, each intermediate value between the upper and lower limits of this range, to the smallest fraction of the unit of the lower limit, is also explicitly disclosed. Any narrower range between any described value or undescribed intermediate value within the described range and any other described or intermediate value within the described range is contemplated. The upper and lower limits of these smaller ranges may be independently included in or excluded from the range, and each range in which one of the limits is included, neither is included, or both are included in the smaller range is also contemplated in the present technology, for any explicitly excluded limits within the described range. Where the range includes one or both of the limits, ranges excluding one or both of those included limits are also contemplated.

[0068] As used herein and in the appended claims, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, reference to "a silicon-containing precursor" includes a plurality of such precursors, and reference to "the silicon-containing material" includes one or more materials and equivalents thereof known to those skilled in the art, and so forth.

[0069] Furthermore, when used in this specification and the following claims, the words “comprise(s)”, “comprising”, “contain(s)”, “containing”, “include(s)”, and “including” are intended to specify the presence of described features, integers, components, or operations, but they do not preclude the presence or addition of one or more other features, integers, components, operations, actions, or groups.

Claims

1. A semiconductor processing method, comprising: i) providing a silicon-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is disposed within the processing region of the semiconductor processing chamber, and wherein the substrate defines one or more features along the substrate; ii) depositing a silicon-containing material on the substrate, wherein the silicon-containing material extends within the one or more features along the substrate; iii) providing an oxygen-containing precursor; iv) annealing the silicon-containing material with the oxygen-containing precursor, wherein the annealing causes the silicon-containing material to expand within the one or more features; as well as Operations i to iv are repeated to iteratively fill the one or more features on the substrate.

2. The semiconductor processing method according to claim 1, wherein: The one or more features along the substrate are characterized by tapered sidewalls.

3. The semiconductor processing method according to claim 1, wherein: The silicon-containing material deposited on the substrate defines gaps or pores prior to annealing by the oxygen-containing precursor.

4. The semiconductor processing method according to claim 1, wherein: The temperature within the semiconductor processing chamber is maintained at greater than or about 300° C. while depositing the silicon-containing material on the substrate.

5. The semiconductor processing method according to claim 1, wherein: The pressure within the semiconductor processing chamber is maintained at greater than or about 100 Torr while the silicon-containing material is deposited on the substrate.

6. The semiconductor processing method according to claim 1, wherein: The silicon-containing material is annealed at a temperature greater than or about 600°C.

7. The semiconductor processing method according to claim 1, wherein: The annealing is performed for a period of time greater than or about 30 minutes.

8. A semiconductor processing method comprising: providing a first silicon-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is disposed within the processing region of the semiconductor processing chamber, and wherein the substrate defines one or more features along the substrate; forming a plasma of the first silicon-containing precursor; depositing a first silicon-containing material on the substrate, wherein the first silicon-containing material extends within the one or more features along the substrate; providing a second silicon-containing precursor; depositing a second silicon-containing material over the first silicon-containing material, wherein the second silicon-containing material extends within the one or more features along the substrate; providing an oxygen-containing precursor; as well as The second silicon-containing material is annealed with the oxygen-containing precursor, wherein the annealing causes the second silicon-containing material to expand within the one or more features.

9. The semiconductor processing method of claim 8, wherein: The first silicon-containing precursor includes tetraethoxysilane, and wherein the second silicon-containing precursor includes disilane.

10. The semiconductor processing method according to claim 8, wherein: The depositing of the second silicon-containing material is performed in a semiconductor processing chamber separate from the semiconductor processing chamber in which the first silicon-containing material is deposited.

11. The semiconductor processing method of claim 8, wherein: Annealing the second silicon-containing material increases the thickness of the second silicon-containing material by greater than or about 50%.

12. The semiconductor processing method of claim 8, wherein: The temperature is maintained at greater than or about 300° C. while depositing the second silicon-containing material on the substrate.

13. The semiconductor processing method of claim 12, wherein: Depositing the second silicon-containing material on the first silicon-containing material is performed as a plasma-free operation.

14. The semiconductor processing method of claim 12, wherein: The oxygen-containing precursor comprises steam; and Annealing the second silicon-containing material is performed at a temperature greater than or about 600°C.

15. A semiconductor processing method comprising: forming a plasma of a first silicon-containing precursor; depositing a first silicon-containing material on a substrate defining one or more features along the substrate, wherein the first silicon-containing material extends within the one or more features along the substrate; providing a second silicon-containing precursor; depositing a second silicon-containing material over the first silicon-containing material, wherein the second silicon-containing material extends within the one or more features along the substrate; providing an oxygen-containing precursor; forming a plasma of the oxygen-containing precursor; as well as The second silicon-containing material is treated with the plasma effluents of the oxygen-containing precursor, wherein the plasma effluents of the oxygen-containing precursor expand the second silicon-containing material on the substrate.

16. The semiconductor processing method of claim 15, wherein: The plasma forming the oxygen-containing precursor is performed at a temperature greater than or about 450°C.

17. The semiconductor processing method of claim 15, wherein: The plasma of the oxygen-containing precursor is generated at a plasma power of greater than or about 800W.

18. The semiconductor processing method of claim 15, wherein: The oxygen-containing precursor includes nitrous oxide, diatomic oxygen, or a combination thereof.

19. The semiconductor processing method of claim 15, wherein: The first silicon-containing precursor includes tetraethoxysilane; and The second silicon-containing precursor includes disilane.

20. The semiconductor processing method of claim 15, wherein: Treating the second silicon-containing material with the plasma effluent of the oxygen-containing precursor reduces gaps or voids defined in the second silicon-containing material.

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