Chip clock frequency control system based on lookup table

Abstract

The invention relates to the technical field of chips, in particular to a chip clock frequency control system based on a lookup table, which comprises a dynamic power consumption management module, an exception management module, a clock gear determination module, a lookup table module and a phase-locked loop module, the phase-locked loop module comprises a plurality of phase-locked loops, the lookup table comprises M clock gears and further comprises a phase-locked loop selection signal and a phase-locked loop adjustment parameter value corresponding to each clock gear, the size of the clock gears is inversely proportional to the chip clock frequency, and the difference value of the clock frequencies corresponding to two adjacent clock gears is smaller than a preset clock adjustment threshold value; wherein the dynamic power consumption management module and the abnormity management module are respectively connected with the clock gear determination module, the clock gear determination module is connected with the lookup table module, and the lookup table module is connected with the phase-locked loop module. According to the invention, a plurality of influence factors can be considered, and the chip clock frequency can be adjusted smoothly and effectively.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a chip clock frequency control system based on a lookup table. Background Art

[0002] During the normal operation of the chip, the clock frequency of the chip is usually dynamically adjusted according to the load size of the chip based on the dynamic power management (Dynamic Power Management, DPM) module. In the prior art, the clock frequency of the chip is usually adjusted by a phase-locked loop (Phase-Locked Loop, PLL), but it may cause the instantaneous adjustment of the clock frequency to be too large and the adjustment is not smooth enough. In addition, during the operation of the chip, abnormal conditions such as peak current or voltage drop may also occur, and when these abnormal conditions occur, the clock frequency of the chip needs to be reduced. At this time, if the dynamic power management module also needs to adjust the clock frequency, there are multiple factors affecting the adjustment of the clock frequency at the same time, and there is an adjustment conflict. In the prior art, only a chip clock frequency adjustment strategy is provided for a single factor, and no chip clock frequency adjustment strategy is proposed for multiple influencing factors. It can be seen from this that how to take into account multiple influencing factors and achieve smooth and effective adjustment of the chip clock frequency has become a technical problem that needs to be solved urgently. Summary of the invention

[0003] The object of the present invention is to provide a chip clock frequency control system based on a lookup table, which can take into account multiple influencing factors and achieve smooth and effective adjustment of the chip clock frequency.

[0004] According to one aspect of the present invention, a chip clock frequency control system based on a lookup table is provided, comprising a dynamic power management module, an abnormal management module, a clock gear determination module, a lookup table module and a phase-locked loop module; the phase-locked loop module comprises a plurality of phase-locked loops, the lookup table comprises M clock gears, and also comprises a phase-locked loop selection signal and a phase-locked loop adjustment parameter value corresponding to each clock gear, the clock gear size is inversely proportional to the chip clock frequency, and the difference in clock frequencies corresponding to two adjacent clock gears is less than a preset clock adjustment threshold;

[0005] The dynamic power management module and the abnormal management module are respectively connected to the clock gear determination module, the clock gear determination module is connected to the lookup table module, and the lookup table module is connected to the phase-locked loop module;

[0006] The dynamic power management module is used to obtain a first clock gear adjustment parameter based on a mapping relationship between the chip load size and the clock gear, and send the first clock gear adjustment parameter to the clock gear determination module;

[0007] The abnormality management module is used for generating a second clock gear adjustment parameter when the abnormality signal changes from a low level to a high level, and sending the second clock gear adjustment parameter to the clock gear determination module;

[0008] The clock gear determination module is used to determine the target clock gear based on the first clock gear adjustment parameter and the second clock gear adjustment parameter, and send the target clock gear to the lookup table module;

[0009] The lookup table module is used to query the lookup table according to the target clock gear, determine the corresponding target phase-locked loop selection signal and target phase-locked loop adjustment parameter value, and send them to the phase-locked loop module;

[0010] The phase-locked loop module is used to determine a target phase-locked loop based on a phase-locked loop selection signal, and set an adjustment parameter corresponding to the target phase-locked loop according to an adjustment parameter value of the target phase-locked loop, so that the target phase-locked loop outputs a target chip frequency.

[0011] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solution, the chip clock frequency control system based on the lookup table provided by the present invention can achieve considerable technical advancement and practicality, and has wide industrial utilization value, and has at least the following beneficial effects:

[0012] The present invention sets a plurality of smoothly changing clock gears by setting a plurality of phase-locked loops and a lookup table, and takes into account a plurality of influencing factors such as chip load and chip abnormality by setting a clock gear determination module, thereby achieving smooth and effective adjustment of the chip clock frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 A schematic diagram of a chip clock frequency control system based on a lookup table provided in an embodiment of the present invention;

[0015] Figure 2 A schematic diagram of the first clock gear adjustment parameter, the second clock gear adjustment parameter and the target gear adjustment effect provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0016] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0017] The embodiment of the present invention provides a chip clock frequency control system based on a lookup table, such as Figure 1 As shown, it includes a dynamic power management (Dynamic Power Management, referred to as DPM) module, an abnormal management module, a clock gear determination module, a lookup table module and a phase-locked loop module. The dynamic power management module is implemented by software, and the abnormal management module, the clock gear determination module, the lookup table module and the phase-locked loop module are implemented by hardware. The phase-locked loop module includes multiple phase-locked loops, and the lookup table includes M clock gears, M is the total number of clock gears, and the lookup table also includes a phase-locked loop selection signal and a phase-locked loop adjustment parameter value corresponding to each clock gear. The clock gear size is inversely proportional to the chip clock frequency, and the difference in clock frequencies corresponding to two adjacent clock gears is less than a preset clock adjustment threshold. It should be noted that a phase-locked loop can be selected from multiple phase-locked loops of the phase-locked loop module as a target phase-locked loop through the phase-locked switching selection signal. If there is only one phase-locked loop, assuming that the frequency after the phase-locked loop multiplies the reference frequency to 10G, after dividing by 2 through integer division, it is directly adjusted to 5G, and after dividing by 3 through integer division, it changes from 5G to 3.3G. The adjustment range is too large, making the clock frequency adjustment not smooth. In the present invention, by setting multiple phase-locked loops and multiple gears, the clock frequency difference of adjacent gears can be maintained within a smaller range, so that the clock frequency adjustment is smooth.

[0018] The dynamic power consumption management module and the abnormality management module are respectively connected to the clock gear determination module, the clock gear determination module is connected to the lookup table module, and the lookup table module is connected to the phase-locked loop module.

[0019] The dynamic power management module is used to obtain the first clock gear adjustment parameter determined based on the mapping relationship between the chip load size and the clock gear, and send the first clock gear adjustment parameter to the clock gear determination module. It should be noted that the determination of the first clock gear adjustment parameter based on the mapping relationship between the chip load size and the clock gear is specifically implemented by software, and the lookup table is also pre-configured by the software. In addition, the software can also configure the mapping relationship between the chip load size and the clock gear. It can be understood that the chip load size is inversely proportional to the clock gear size. The first clock gear adjustment parameter is the clock gear expected by the system when only considering the single factor of dynamic power management.

[0020] The abnormal management module is used to generate a second clock gear adjustment parameter when the abnormal signal changes from a low level to a high level, and send the second clock gear adjustment parameter to the clock gear determination module. The second clock gear adjustment parameter is the gear adjustment quantity contributed to the target gear under the dual influence factors of the dynamic power management module and the abnormal management module on the chip clock frequency. As an example, the abnormal management module can be a peak current control (PeakCurrent Control, referred to as PCC) module or a delay digital converter (Delay To Digital Converter, referred to as DDC), etc. The chip value current control module is used to monitor the chip current. When the chip has a peak current, the abnormal signal changes from a low level to a high level, and when the peak current disappears, the abnormal signal changes from a high level to a low level. The delay digital converter is used to monitor the chip voltage. When the voltage drop of the chip voltage exceeds the preset voltage drop threshold, the abnormal signal changes from a low level to a high level, and when the chip voltage recovers to the normal range, the abnormal signal changes from a high level to a low level. The abnormal management module can also be a Powerbreak module. When the system power supply is suddenly reduced, the abnormal signal of the Powerbreak module changes from a low level to a high level, notifying the PCIE system. The PCIE system will notify the chip to reduce power consumption to match the power supply capacity of the system. When the power supply returns to normal levels, the abnormal signal changes from a high level to a low level.

[0021] The clock gear determination module is used to determine the target clock gear based on the first clock gear adjustment parameter and the second clock gear adjustment parameter, and send the target clock gear to the lookup table module. It can be understood that the target clock gear is obtained by comprehensively considering the first clock gear adjustment parameter and the second clock gear adjustment parameter, and the priority of the first clock gear adjustment parameter is higher than the priority of the second clock gear adjustment parameter, that is, when the clock frequency is adjusted based on the load and the abnormal signal at the same time, when an adjustment conflict occurs, priority is given to ensuring the clock frequency requirement of the load.

[0022] The lookup table module is used to query the lookup table according to the target clock gear, determine the corresponding target phase-locked loop selection signal and the target phase-locked loop adjustment parameter value, and send them to the phase-locked loop module. The phase-locked loop module is used to determine the target phase-locked loop based on the phase-locked loop selection signal, and set the adjustment parameters corresponding to the target phase-locked loop according to the target phase-locked loop adjustment parameter value, so that the target phase-locked loop outputs the target chip frequency.

[0023] As an example, the abnormality management module is specifically used to adjust the second clock gear adjustment parameter from the starting clock gear when the abnormal signal changes from a low level to a high level, increase the preset step length λ at each preset time interval t, and transmit it to the clock gear determination module. It should be noted that the starting clock gear is 0, and when the abnormal signal changes from a low level to a high level, the system smoothly adjusts the contribution gear of the abnormality management module to the target gear according to the preset step length λ. Assuming that the gear in the lookup table is set to 10 gears, the preset step λ can be set to parameters such as 1 or 2, which are specifically set according to the adjustment requirements.

[0024] As an example, the clock gear determination module is used to obtain the third clock gear adjustment parameter c based on the first clock gear adjustment parameter and the second clock gear adjustment parameter, c=a+b, wherein a is the first clock gear adjustment parameter and b is the second clock gear adjustment parameter. The clock gear determination module is also used to determine whether the current third clock gear adjustment parameter is less than the maximum clock gear. If so, the current third clock gear adjustment parameter is determined as the target clock gear and output to the lookup table module; if the current third clock gear adjustment parameter is greater than the maximum clock gear, the maximum clock gear is determined as the target clock gear and output to the lookup table module.

[0025] Furthermore, if the current third clock gear adjustment parameter is greater than the maximum clock gear, the clock gear determination module is also used to set the feedback clock gear adjustment parameter e=da,d as the maximum clock gear, and send the feedback clock gear adjustment parameter to the exception management module; when the exception management module receives the feedback clock gear adjustment parameter, the value of the second clock gear adjustment parameter is set to e, and the operation of increasing the preset step size λ at each preset time interval t is suspended.

[0026] When the abnormal signal is still maintained at a high level, the chip load becomes smaller, resulting in a decrease in the first clock gear adjustment parameter, which may make it possible for the second clock gear adjustment parameter to continue to increase. At this time, the increase operation of the second clock gear adjustment parameter can be restored. As an example, the clock gear determination module is also used to determine that when the current third clock gear adjustment parameter changes from the maximum clock gear to less than the maximum clock gear, it sends a start adjustment signal to the abnormal management module; the abnormal management module is used to adjust the second clock gear adjustment parameter from the current value when the start adjustment signal is received and the abnormal signal is still at a high level, and increase the preset step size λ every preset time interval t, and transmit it to the clock gear determination module, and the current value refers to the current value corresponding to the second clock gear adjustment parameter.

[0027] When the abnormal situation disappears, the second clock gear adjustment parameter needs to be smoothly restored to 0, and it no longer contributes to the chip clock frequency adjustment. As an example, the second clock gear adjustment parameter abnormal management module is also used to adjust the second clock gear adjustment parameter from the current value when the abnormal signal changes from a high level to a low level, and reduce the preset step size λ at every preset time t until it is reduced to the starting clock gear.

[0028] It should be noted that the clock gear determination module makes the target clock gear always maintain within the maximum gear range, and timely adjusts the second clock gear adjustment parameter by feedback clock gear adjustment parameter, which reduces the invalid time consumed when the abnormal signal exits, so that the system frequency recovers faster. If the above adjustment logic is not set, assuming that the first clock gear adjustment parameter is equal to 5, the second clock gear adjustment parameter is equal to 7, the third clock gear adjustment parameter is equal to 12, and the maximum gear is 10, the preset step size λ is set to 1, when the abnormal signal changes from high level to low level, that is, when the abnormal situation disappears, the second clock gear adjustment parameter needs to be gradually reduced from 7 to 0, but in fact, in the process of the second clock gear parameter changing from 7 to 6 and 6 to 5, the target gear is always 10, which is an invalid exit process, and by setting the above logic, the second clock gear parameter has been directly set to 5, and when exiting, it is adjusted directly from 5, which reduces the invalid time consumed when the abnormal signal exits, so that the system frequency recovers faster.

[0029] In order to explain the present invention more clearly, Figure 2 It shows a schematic diagram of the first clock gear adjustment parameter, the second clock gear adjustment parameter and the target gear adjustment effect. Figure 2 In the corresponding example, the abnormal management module is the PCC module, the preset step size λ is set to 1, the maximum gear is set to 10, PCC_ALERT represents the corresponding abnormal signal, PCC_INDEX represents the corresponding second clock gear parameter, DPM_INDEX represents the corresponding first clock gear parameter, and FINAL_INDEX represents the corresponding target gear. Figure 2It can be seen that when the abnormal signal changes from low level to high level, PCC_INDEX starts to change from 0, and increases by 1 at every preset time interval. During this process, DPM_INDEX remains unchanged at 5. When PCC_INDEX rises to 5, it remains unchanged. When DPM_INDEX rises from 5 to 7, since DPM_INDEX has a higher priority, PCC_INDEX is changed to 3 at this time. When DPM_INDEX changes from 7 to 6, PCC_INDEX changes to 4, and then DPM_INDEX remains unchanged at 6, and PCC_INDEX remains unchanged at 4. When PCC_ALERT changes from high level to low level, PCC_INDEX starts from 4 and gradually decreases to 0 according to the preset step size λ.

[0030] As an example, each phase-locked loop includes a first frequency divider and a second frequency divider arranged in cascade, the phase-locked loop adjustment parameter includes a first frequency division value A corresponding to the first frequency divider and a second frequency division value B corresponding to the second frequency divider, and each phase-locked loop outputs a target clock frequency Fout based on the following formula:

[0031] Fout=(Fref*FBDIV) / [(A+1)*(B+1)]

[0032] Among them, Fref is the fixed reference clock of the phase-locked loop, FBDIV is the multiplication coefficient, and the value obtained by Fref*FBDIV is the fixed multiplication clock obtained by the phase-locked loop. It can be understood that the values ​​of Fref*FBDIV corresponding to different phase-locked loops in the phase-locked loop module are different, and (A+1)*(B+1) obtains the target division value. Therefore, through multiple phase-locked loops, multiple clock gears can be set to make the clock frequency change smoothly.

[0033] As an example, the phase-locked loop module includes two phase-locked loops, namely a first phase-locked loop and a second phase-locked loop. The Fref*FBDIV value corresponding to the first phase-locked loop is 10G, and the Fref*FBDIV value corresponding to the second phase-locked loop is 9G. When the selection signal is 0, the first phase-locked loop is enabled, and when the selection signal is 1, the second phase-locked loop is enabled. Table 1 shows an example of a search table:

[0034] Table 1

[0035]

[0036]

[0037] As can be seen from Table 1, the clock frequency difference between two adjacent gears is maintained within a small range, not exceeding 1.2G, and the clock frequency can be smoothly adjusted. It can be understood that Table 1 is only an example. In actual application, parameters such as the number of gears, the first frequency division value A, and the second frequency division value B can be adjusted accordingly.

[0038] In the process of hardware implementation of Fout=(Fref*FBDIV) / [(A+1)*(B+1)], (Fref*FBDIV) is first divided by (A+1), and then divided by (B+1). When the lookup table sends the target first frequency division value A and the target second frequency division value B to the corresponding target phase-locked loop, the target first frequency division value A and the target second frequency division value B may not reach the target phase-locked loop at the same time due to the different lengths of the lines after layout and routing. If the value of the first frequency division value A needs to be increased, at this time, if the target second frequency division value B arrives first, it will cause the clock frequency to rise for a short time, but it is expected that the frequency needs to be reduced. For example, assuming that the current A=4 , B=3, target A=7, target B=2. If the target B value arrives and is updated first, the clock frequency will rise for a short time. For such a scenario, as an example, the system also includes a frequency division value setting module arranged between the lookup table module and the phase-locked loop module. The frequency division value setting module is used to determine whether the current value of the first frequency division value corresponding to the target phase-locked loop is less than the target first frequency division value. If it is less than, the target first frequency division value is first sent to the target first frequency divider, and then the target second frequency division value is sent to the target second frequency divider. Otherwise, the target second frequency division value is first sent to the target second frequency divider, and then the target first frequency division value is sent to the target first frequency divider.

[0039] The embodiment of the present invention sets multiple smoothly changing clock gears by setting multiple phase-locked loops and lookup tables, and takes into account multiple influencing factors such as chip load and chip abnormality by setting a clock gear determination module, thereby achieving smooth and effective adjustment of the chip clock frequency.

[0040] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of the technical solution of the present invention.

Claims

1. A chip clock frequency control system based on a lookup table, characterized in that: It includes a dynamic power management module, an abnormal management module, a clock gear determination module, a lookup table module and a phase-locked loop module; the phase-locked loop module includes multiple phase-locked loops, the lookup table includes M clock gears, and also includes a phase-locked loop selection signal and a phase-locked loop adjustment parameter value corresponding to each clock gear. The size of the clock gear is inversely proportional to the chip clock frequency, and the difference in clock frequencies corresponding to two adjacent clock gears is less than a preset clock adjustment threshold; The dynamic power management module and the abnormal management module are respectively connected to the clock gear determination module, the clock gear determination module is connected to the lookup table module, and the lookup table module is connected to the phase-locked loop module; The dynamic power management module is used to obtain a first clock gear adjustment parameter based on a mapping relationship between the chip load size and the clock gear, and send the first clock gear adjustment parameter to the clock gear determination module; The abnormality management module is used for generating a second clock gear adjustment parameter when the abnormality signal changes from a low level to a high level, and sending the second clock gear adjustment parameter to the clock gear determination module; The clock gear determination module is used to determine the target clock gear based on the first clock gear adjustment parameter and the second clock gear adjustment parameter, and send the target clock gear to the lookup table module; The lookup table module is used to query the lookup table according to the target clock gear, determine the corresponding target phase-locked loop selection signal and target phase-locked loop adjustment parameter value, and send them to the phase-locked loop module; The phase-locked loop module is used to determine a target phase-locked loop based on a phase-locked loop selection signal, and set an adjustment parameter corresponding to the target phase-locked loop according to an adjustment parameter value of the target phase-locked loop, so that the target phase-locked loop outputs a target chip frequency.

2. The system according to claim 1, characterized in that The abnormality management module is specifically used to adjust the second clock gear adjustment parameter from the starting clock gear when the abnormal signal changes from a low level to a high level, increase the preset step length λ at each preset time interval t, and transmit it to the clock gear determination module.

3. The system according to claim 2, characterized in that The clock gear determination module is used to obtain the third clock gear adjustment parameter c based on the first clock gear adjustment parameter and the second clock gear adjustment parameter, c=a+b, wherein a is the first clock gear adjustment parameter and b is the second clock gear adjustment parameter. The clock gear determination module is also used to determine whether the current third clock gear adjustment parameter is less than the maximum clock gear. If so, the current third clock gear adjustment parameter is determined as the target clock gear and output to the lookup table module; if the current third clock gear adjustment parameter is greater than the maximum clock gear, the maximum clock gear is determined as the target clock gear and output to the lookup table module.

4. The system according to claim 3, characterized in that If the current third clock gear adjustment parameter is greater than the maximum clock gear, the clock gear determination module is further used to set the feedback clock gear adjustment parameter e=da,d as the maximum clock gear, and send the feedback clock gear adjustment parameter to the abnormality management module; When the abnormal management module receives the feedback clock gear adjustment parameter, the value of the second clock gear adjustment parameter is set to e, and the operation of increasing the preset step length λ at every preset time interval t is suspended.

5. The system according to claim 4, characterized in that The clock gear determination module is further used to send a start adjustment signal to the abnormal management module when it is determined that the current third clock gear adjustment parameter changes from the maximum clock gear to less than the maximum clock gear; The abnormal management module is used to adjust the second clock gear adjustment parameter from the current value when the start adjustment signal is received and the abnormal signal is still at a high level, increase the preset step size λ at each preset time interval t, and transmit it to the clock gear determination module.

6. The system according to claim 5, characterized in that The abnormality management module is also used to adjust the second clock gear adjustment parameter from the current value when the abnormal signal changes from a high level to a low level, and reduce the preset step size λ at each preset time interval t until it is reduced to the starting clock gear.

7. The system according to claim 1, characterized in that Each phase-locked loop includes a first frequency divider and a second frequency divider arranged in cascade, and the phase-locked loop adjustment parameters include a first frequency division value A corresponding to the first frequency divider and a second frequency division value B corresponding to the second frequency divider. Each phase-locked loop outputs a target clock frequency Fout based on the following formula: Fout=(Fref*FBDIV) / [(A+1)*(B+1)] Among them, Fref is the fixed reference clock of the phase-locked loop, and FBDIV is the frequency multiplication factor; The system also includes a frequency division value setting module arranged between the lookup table module and the phase-locked loop module, and the frequency division value setting module is used to determine whether the current value of the first frequency division value corresponding to the target phase-locked loop is less than the target first frequency division value. If it is less than, the target first frequency division value is first sent to the target first frequency divider, and then the target second frequency division value is sent to the target second frequency divider; otherwise, the target second frequency division value is first sent to the target second frequency divider, and then the target first frequency division value is sent to the target first frequency divider.

8. The system according to claim 1, characterized in that The abnormal management module is a peak current control module or a delay digital converter; The chip value current control module is used to monitor the chip current. When the chip has a peak current, the abnormal signal changes from a low level to a high level. When the peak current disappears, the abnormal signal changes from a high level to a low level. The delay digital converter is used to monitor the chip voltage. When the voltage drop of the chip voltage exceeds a preset voltage drop threshold, the abnormal signal changes from a low level to a high level. When the chip voltage returns to a normal range, the abnormal signal changes from a high level to a low level.

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