A low-power wake-up circuit integrated in an MCU

Abstract

The present invention belongs to the technical field of microprocessors, and particularly relates to a low-power wake-up circuit integrated in an MCU. It includes: flip-flops DQ1 to DQ6, NOT gates NOT1 to NOT5, AND gates AND1 to AND3, tri-state gate TS1, exclusive-OR gate XOR1, comparator CMP1, and selector MUX1; among them, the D terminals of flip-flops DQ1 to DQ4 and the output terminals of NOT gates NOT1 to NOT4 are all connected to the data bus, the CLK terminal of flip-flop DQ1 is connected to the write enable signal of the P0 register, the Q terminal of flip-flop DQ1 is connected to the input terminal of tri-state gate TS1, the output terminal of tri-state gate TS1 is connected to the port, the CLK terminal of flip-flop DQ2 is connected to the write enable signal of the P0IO register, the QN terminal of flip-flop DQ2 and the input terminal of NOT gate NOT1 are connected to the control terminal of tri-state gate TS1, and the control terminal of NOT gate NOT1 is connected to the read enable signal of the P0IO register. The present invention makes the port level change from high to low through the charge and discharge of the capacitor, thereby generating a wake-up signal. There is no need for external devices or internal programs to generate periodic wake-up signals, reducing the power consumption of the entire machine system.

Description

Technical Field

[0001] The present invention belongs to the technical field of microprocessors, and particularly relates to a low-power wake-up circuit integrated in an MCU. Background Art

[0002] In fields such as high-precision measurement and automation control, high requirements are imposed on clock accuracy and power consumption. More accurate clocks need to be used and power consumption needs to be controlled. Therefore, an external crystal oscillator needs to be used as the system main clock, and the system enters the sleep mode when it is not working to reduce power consumption. As the system main clock, the external crystal oscillator can only be set as the system main clock when the oscillation is stable. Generally, the external crystal oscillator is a low-speed clock with a frequency of 32.768 kHz, so the waiting time for the oscillation to stabilize is relatively long. In some fields of data acquisition and transmission or real-time monitoring, the MCU needs to be periodically awakened. Usually, an internal timer or RTC is used to time and wake up the system. In a circuit powered by a battery, extremely high requirements are imposed on power consumption, and the system power consumption needs to be reduced as much as possible.

[0003] In the existing periodic timing wake-up circuit, after the system main clock switches from the internal oscillation to the external crystal oscillator, the program starts to execute, the timer is configured, the internal low-speed oscillation is used as the timer counting clock, and the system enters the sleep mode. At this time, the external crystal oscillator stops oscillating. Wait for the timer to count to the set value to generate a wake-up signal. After the wake-up signal is generated, the external crystal oscillator starts to oscillate. After waiting for a certain time and the oscillation is stable, the circuit can use the external crystal oscillator as the system main clock. During the waiting period for the oscillation to stabilize, the entire system does not work.

[0004] However, during the sleep period of the microprocessor, the internal timer counts with the internal low-speed oscillation as the clock, generating a certain amount of power consumption. Using the external crystal oscillator as the system main clock, waiting for the oscillation to stabilize, from the arrival of the wake-up signal to the start of system operation, this period of time is relatively long, generating a certain amount of power consumption and reducing the code execution efficiency. Summary of the Invention

[0005] The purpose of the present invention is to overcome the above-mentioned deficiencies of the prior art. The present invention provides a low-power wake-up circuit integrated in an MCU. By means of port capacitance discharge, the circuit generates a periodic wake-up signal to wake up the circuit from the sleep mode. After the wake-up signal arrives, an internal and external dual-clock start circuit is used to achieve an extremely low-power circuit wake-up design.

[0006] To solve the above technical problems, the present invention provides a low-power wake-up circuit integrated in an MCU, including: flip-flops DQ1 to DQ6, NOT gates NOT1 to NOT5, AND gates AND1 to AND3, tri-state gate TS1, exclusive-OR gate XOR1, comparator CMP1, and selector MUX1;

[0007] Among them, the D terminals of flip-flops DQ1 to DQ4 and the output terminals of NOT gates NOT1 to NOT4 are all connected to the data bus. The CLK terminal of flip-flop DQ1 is connected to the write enable signal of the P0 register. The Q terminal of flip-flop DQ1 is connected to the input terminal of tri-state gate TS1. The output terminal of tri-state gate TS1 is connected to the IO port of the MCU. The CLK terminal of flip-flop DQ2 is connected to the write enable signal of the P0IO register. The QN terminal of flip-flop DQ2 and the input terminal of NOT gate NOT1 are connected to the control terminal of tri-state gate TS1. The control terminal of NOT gate NOT1 is connected to the read enable signal of the P0IO register. The control terminal of NOT gate NOT2 is connected to the read enable signal of the P0 register. The CLK terminal of flip-flop DQ3 is connected to the write enable signal of the IE0 register. The QN terminal of flip-flop DQ3 is connected to the input terminal of NOT gate NOT3. The control terminal of NOT gate NOT3 is connected to the read enable signal of the IE0 register. The CLK terminal of flip-flop DQ4 is connected to the write enable signal of the P0AN register. The Q terminal of flip-flop DQ4 is connected to the input terminal of NOT gate NOT5. The QN terminal of flip-flop DQ4 is connected to the input terminal of NOT gate NOT4. The control terminal of NOT gate NOT4 is connected to the read enable signal of the P0AN register. The three input terminals of AND gate AND1 are respectively connected to the Q terminals of flip-flops DQ1 and DQ3 and the output terminal of XOR gate XOR1. The output terminal of AND gate AND1 outputs a level change interrupt wake-up signal. The two input terminals of XOR gate XOR1 are respectively connected to the Q terminals of flip-flops DQ5 and DQ6. The Q terminal of flip-flop DQ5 is connected to the input terminal of NOT gate NOT2. The EN terminal of flip-flop DQ5 is connected to CLK3. The EN terminal of flip-flop DQ6 is connected to the read enable signal of the P0 register. The output terminals of NOT gate NOT5 and selector MUX1 are respectively connected to the two input terminals of AND gate AND2. The output terminal of AND gate AND2 is connected to the D terminals of flip-flops DQ5 and DQ6. The two input terminals of selector MUX1 are respectively connected to the inverting input terminal and the output terminal of comparator CMP1. The control terminal of selector MUX1 is connected to the ultra-low power wake-up enable signal ULPWKE and the first terminal of ultra-low power current IULP. The non-inverting input terminal of comparator CMP1 is connected to the output voltage VIL of the DAC module. The inverting input terminal of comparator CMP1 is connected to the output terminal of tri-state gate TS1 and the second terminal of ultra-low power current IULP. The ground terminal of ultra-low power current IULP is grounded.

[0008] Preferably, the ultra-low power consumption current IULP is generated by a capacitor module, and the capacitor module includes: PMOS transistor P1, NMOS transistor N1, capacitor C1, resistor R1, and AND gate AND3; three input terminals of the AND gate AND3 are respectively connected to the ultra-low power consumption wake-up enable signal ULPWKE, the sleep enable signal SLEEP, and the inverting input terminal of the comparator CMP1, the output terminal of the AND gate AND3 is connected to the gate terminal of the PMOS transistor P1, the source terminal of the PMOS transistor P1 is connected to the power supply voltage VDD, the drain terminal of the PMOS transistor P1 is connected to the ultra-low power consumption wake-up enable signal ULPWKE, one end of the capacitor C1, and the drain terminal of the NMOS transistor N1, the gate terminal of the NMOS transistor N1 is connected to the sleep enable signal SLEEP, the source terminal of the NMOS transistor N1 is grounded, the other end of the capacitor C1 is connected to one end of the resistor R1, and the other end of the resistor R1 is grounded.

[0009] Preferably, a diode module is further included, and the diode module includes diodes D1 to D2; the positive terminal of diode D1 and the negative terminal of diode D2 are connected to a port, the negative terminal of diode D1 is connected to the power supply voltage VDD, and the positive terminal of diode D2 is grounded.

[0010] Preferably, the P0 register is a data register with ports P00 to P07. Writing 1 to bit0 of the P0 register makes P00 port output 1, and writing 0 to bit0 of the P0 register makes P00 port output 0;

[0011] The IE0 register is an external port level change interrupt enable register, and the P00 port is the corresponding port of external interrupt 0, which is controlled by bit0 of the IE0 register;

[0012] The P0IO register is an input / output direction control register for a group of ports in the P0 register. When bit0 of the P0IO register is 1, the P00 port is in the input state, and when bit0 is 0, the P00 port is in the output state;

[0013] The P0AN register is a register for controlling the P00 port to perform analog input function or digital IO function. When bit0 of the P0AN register is 1, the P00 port performs analog input function, and when bit0 is 0, the P00 port performs digital IO function.

[0014] Preferably, by the DAC module integrated inside the MCU, different DAC module output voltage VIL values are set to achieve dynamic adjustment of the timing wake-up time; that is, through the formula VIL = VDDexp(-t / RC);

[0015] Wherein, VDD is the power supply voltage, R and C are the resistance and capacitance values integrated inside the MCU respectively, and t is the set timing wake-up time.

[0016] Preferably, after the wake-up signal arrives and before the external crystal oscillator oscillation stabilizes, the internal clock is used as the system main clock; after the external crystal oscillator oscillation stabilizes, the internal oscillation is switched to the external crystal oscillator as the system main clock.

[0017] Preferably, it also includes the working process of dual-speed clock startup: before entering the sleep mode, turn on the dual-speed clock startup enable; the system wakes up from the sleep mode; the internal oscillation starts to work at the frequency set before sleep, and the system starts to execute instructions at this frequency; at the same time as waking up, the external oscillation starts to work, the external oscillation counter starts to count, and when it counts to 1023, the FLAG is set; after the FLAG is set, the system clock remains low, waiting for the falling edge of the external oscillation to appear; switch the external oscillation to the system clock source.

[0018] Preferably, it also includes the working process of ultra-low-power port wake-up: set the P0 register to enable the P00 port to output 1; set the P0AN register to turn off the analog function of the P00 port; set the P0IO register to turn on the digital output function of the P00 port; wait for the capacitor C1 to be fully charged; enable the ultra-low-power wake-up enable signal ULPWKE; set the IE0 register to turn on the external interrupt 0 enable bit of the P00 port; set the P0IO register to set the P00 port to the input mode; enter the sleep mode and wait for the system to wake up automatically.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] The present invention integrates a capacitor inside the port. Through the charging and discharging of the capacitor, the port level changes from high to low, thereby generating a wake-up signal. There is no need for external devices or internal programs to generate periodic wake-up signals, reducing the power consumption of the entire machine system. Moreover, before the external crystal oscillator oscillation stabilizes, the internal oscillation is used as the system main clock to start executing the program, and after the external crystal oscillator oscillation stabilizes, the external crystal oscillator is switched as the system main clock, reducing the delay between the external oscillator starting up and the code execution. Description of the Drawings

[0021] Figure 1 It is a circuit diagram of a low-power wake-up circuit integrated in an MCU according to the present invention.

[0022] Figure 2 It is a non-overlapping timing diagram of four internal generations CLK1~CLK4 according to the present invention.

[0023] Figure 3 It is a waveform diagram of the dual-speed clock according to the present invention. Detailed Embodiments

[0024] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the embodiments of the present invention.

[0025] As Figure 1 shown, an embodiment of the present invention provides a low-power wake-up circuit integrated in an MCU, including: flip-flops DQ1 to DQ6, NOT gates NOT1 to NOT5, AND gates AND1 to AND3, tri-state gate TS1, exclusive-OR gate XOR1, comparator CMP1, and selector MUX1;

[0026] Among them, the D terminals of flip-flops DQ1 to DQ4 and the output terminals of NOT gates NOT1 to NOT4 are all connected to the data bus. The CLK terminal of flip-flop DQ1 is connected to the write enable signal of the P0 register. The Q terminal of flip-flop DQ1 is connected to the input terminal of tri-state gate TS1. The output terminal of tri-state gate TS1 is connected to the IO port of the MCU, serving as the data output path of a general-purpose IO port for communication with external devices. The CLK terminal of flip-flop DQ2 is connected to the write enable signal of the P0IO register. The QN terminal of flip-flop DQ2 and the input terminal of NOT gate NOT1 are connected to the control terminal of tri-state gate TS1. The control terminal of NOT gate NOT1 is connected to the read enable signal of the P0IO register. The control terminal of NOT gate NOT2 is connected to the read enable signal of the P0 register. The CLK terminal of flip-flop DQ3 is connected to the write enable signal of the IE0 register. The QN terminal of flip-flop DQ3 is connected to the input terminal of NOT gate NOT3. The control terminal of NOT gate NOT3 is connected to the read enable signal of the IE0 register. The CLK terminal of flip-flop DQ4 is connected to the write enable signal of the P0AN register. The Q terminal of flip-flop DQ4 is connected to the input terminal of NOT gate NOT5. The QN terminal of flip-flop DQ4 is connected to the input terminal of NOT gate NOT4. The control terminal of NOT gate NOT4 is connected to the read enable signal of the P0AN register. The three input terminals of AND gate AND1 are respectively connected to the Q terminals of flip-flops DQ1 and DQ3 and the output terminal of XOR gate XOR1. The output terminal of AND gate AND1 outputs a level change interrupt wake-up signal. The two input terminals of XOR gate XOR1 are respectively connected to the Q terminals of flip-flops DQ5 and DQ6. The Q terminal of flip-flop DQ5 is connected to the input terminal of NOT gate NOT2. The EN terminal of flip-flop DQ5 is connected to CLK3. The EN terminal of flip-flop DQ6 is connected to the read enable signal of the P0 register. The output terminals of NOT gate NOT5 and selector MUX1 are respectively connected to the two input terminals of AND gate AND2. The output terminal of AND gate AND2 is connected to the D terminals of flip-flops DQ5 and DQ6. The two input terminals of selector MUX1 are respectively connected to the inverting input terminal and the output terminal of comparator CMP1. The control terminal of selector MUX1 is connected to the ultra-low power wake-up enable signal ULPWKE and the first terminal of ultra-low power current IULP. The non-inverting input terminal of comparator CMP1 is connected to the output voltage VIL of the DAC module. The inverting input terminal of comparator CMP1 is connected to the output terminal of tri-state gate TS1 and the second terminal of ultra-low power current IULP. The ground terminal of ultra-low power current IULP is grounded.

[0027] The ultra-low power consumption current IULP is generated by a capacitor module. The capacitor module includes: PMOS transistor P1, NMOS transistor N1, capacitor C1, resistor R1, and AND gate AND3. The three input terminals of the AND gate AND3 are respectively connected to the ultra-low power consumption wake-up enable signal ULPWKE, the sleep enable signal SLEEP, and the inverting input terminal of comparator CMP1. The output terminal of the AND gate AND3 is connected to the gate terminal of the PMOS transistor P1. The source terminal of the PMOS transistor P1 is connected to the power supply voltage VDD. The drain terminal of the PMOS transistor P1 is connected to the ultra-low power consumption wake-up enable signal ULPWKE, one end of the capacitor C1, and the drain terminal of the NMOS transistor N1. The gate terminal of the NMOS transistor N1 is connected to the sleep enable signal SLEEP. The source terminal of the NMOS transistor N1 is grounded. The other end of the capacitor C1 is connected to one end of the resistor R1. The other end of the resistor R1 is grounded.

[0028] It further includes a diode module. The diode module includes diodes D1 to D2. The positive terminal of diode D1 and the negative terminal of diode D2 are connected to a port. The negative terminal of diode D1 is connected to the power supply voltage VDD. The positive terminal of diode D2 is grounded.

[0029] ULPWUE is the ultra-low power consumption wake-up enable bit, which is valid at high level. The IE0 register is the external port level change interrupt enable register. The P00 port is the external interrupt 0, which is controlled by bit0 of the IE0 register. The P0 register is the data register of ports P00 to P07. Writing 1 to bit0 makes the P00 port output 1. Writing 0 to bit0 makes the P00 port output 0. The P0IO register is the input / output direction control register of a group of ports of the P0 register. When bit0 of P0IO is 1, the P00 port is in the input state. When bit0 is 0, the P00 port is in the output state. Bit0 of the P0AN register controls whether the P00 port functions as an analog input or a digital IO. When bit0 is 1, the P00 port functions as an analog input. When bit0 is 0, the P00 port functions as a digital IO. V IL is the output voltage of the DAC module.

[0030] It further includes the following working principle:

[0031] ① When using the ultra-low power consumption wake-up function, in the normal working mode (SLEEP = 0), turn on the ultra-low power consumption wake-up enable (ULPWKE = 1).

[0032] ② Write 0 to bit0 of P0AN to set the P00 port to the digital IO function, that is, the non-analog input function (DQ4 outputs 0, NOT1 outputs 1).

[0033] ③ Write 0 to bit0 of P0IO to set the P00 port to the output state (the Q terminal of DQ2 outputs 0, QN outputs 1) and turn on the tri-state gate TS1.

[0034] ④ Write 1 to bit0 of the P0 register to configure the P00 port to output 1 (the Q end of DQ1 outputs 1, and TS1 outputs 1).

[0035] ⑤ At this time, AND3 outputs 0, turning on the PMOS transistor P1 to charge the capacitor C1 in the capacitor module. Wait for the capacitor C1 to finish charging.

[0036] ⑥ Write 1 to bit0 of the IE0 register to enable the P00 port level change interrupt (the Q end of DQ3 outputs 1, and the QN end outputs 0), and configure the P00 port as the input mode (the Q end of DQ2 outputs 1, and QN outputs 0).

[0037] ⑦ Execute the SLEEP command to enter the sleep mode, and the capacitor C1 starts to discharge.

[0038] ⑧ When the voltage on the P00 port drops to V IL And below, it is determined that there is a falling-edge level change on the P00 port, and the comparator CMP1 outputs 1. At this time, the multiplexer MUX1 outputs 1. At this time, it is in the digital input mode, and NOT1 outputs 1. The AND gate AND2 outputs 1, sampled with the CLK3 clock, and the Q end of DQ5 outputs 1. The enable of reading the P0 register is the in-phase clock of CLK1. The three devices DQ5, DQ1, and XOR1 form a handshake protocol. The Q end output of DQ5 and the Q end output of DQ6 will differ by two system clock times to be set to 1, and the exclusive-OR gate XOR1 will output 1 for two clocks, which is the level change interrupt wake-up signal, and an interrupt will be generated to wake up the device.

[0039] Read the status of the P00 port, set the enable of reading the P0IO register, turn on NOT1, and the data at the QN end of DQ2 passes through the inverter NOT1 and is written to the data bus. Read the value of the P0 register, set the enable signal of reading the P0 register, turn on NOT2, and write the data at the Q end of DQ4 to the data bus through NOT2. Read the IE0 register, set the enable of reading the IE0 register, turn on NOT3, and write the data at the QN end of DQ3 to the data bus through the inverter NOT3. Read the P0AN register, set the enable signal of reading P0AN, turn on NOT4, and write the data at the QN end of DQ4 to the data bus through the inverter NOT4.

[0040] Use the port output 1 to charge the capacitor. The discharge of the capacitor in the sleep mode causes a level signal change at the port, and this level change signal can be used as a wake-up signal. The ultra-low-power wake-up function on the P00 port allows the slowly decreasing voltage to generate a level change interrupt on the P00, while not consuming a large amount of current. Enabling the function control bit of the MCU register will generate a very small sink current, which can be used to discharge the capacitor on the P00 port.

[0041] The capacitor discharge time can be calculated by the formula:

[0042] Vt = V0exp(-t / RC); where V0 is the voltage before capacitor discharge, Vt is the voltage at any time after discharge, R is the discharge resistance, and C is the capacitance value.

[0043] The charging time of the capacitor can be calculated by the following formula:

[0044] Vt = Vu(1 - exp(-t / RC)); where Vu is the voltage after the capacitor is fully charged, and Vt is the voltage at any time after charging.

[0045] As Figure 2 shown, the system clock FSYS is provided by an external crystal oscillator or an internal oscillator. It is divided into four non - overlapping internal generated timings CLK1~CLK4, which constitute a complete instruction cycle. During the CLK1 time, the program counter is automatically incremented and a new instruction is fetched. CLK2~CLK4 complete the decoding and execution functions.

[0046] After the wake - up signal arrives and before the external crystal oscillator oscillation stabilizes, the internal clock is used as the system main clock. After the external crystal oscillator oscillation stabilizes, the internal oscillator is switched to the external crystal oscillator as the system main clock. This can minimize the delay between the external oscillator and code execution and further save power consumption.

[0047] Different V IL voltage values can be set through the DAC module integrated inside the MCU to dynamically adjust the timed wake - up time. Through the formula V IL = VDDexp(-t / RC), given the power supply voltage VDD, the internally integrated RC value, and the timed wake - up time t to be set, the actual value of V IL can be calculated and set through the DAC.

[0048] As Figure 3 shown, LIRC is the internal oscillation of the system, LXT is the low - speed oscillation external to the chip, LXT_CNT is a 10 - bit counter, FLAG is the overflow flag of LXT_CNT, PC is the microcontroller program register, and FSYS is the microcontroller system clock. The comparison of the LXT period and the LIRC period shown in the above Figure 3 waveform is not a comparison of the real periodic frequencies, but only for facilitating the understanding of the dual - speed clock wake - up process. The real frequencies differ greatly, and the greater the frequency difference, the more power consumption is saved.

[0049] The working sequence of the above - mentioned dual - speed clock startup: Before entering the sleep mode, turn on the dual - speed clock startup enable;

[0050] ① The system wakes up from the sleep mode;

[0051] ② The internal oscillation starts working at the frequency set before sleep, and the system starts executing instructions at this frequency;

[0052] ③ At the same time of waking up, the external oscillation starts working, the external oscillation counter starts counting, and when it counts to 1023, the FLAG is set;

[0053] ④ After the FLAG is set, the system clock remains low and waits for the falling edge of the external oscillation to appear;

[0054] ⑤ Switch the external oscillation to the system clock source.

[0055] The above working sequence of ultra-low-power port wake-up:

[0056] ① Set the P0 register to enable the P00 port to output 1;

[0057] ② Set the P0AN register to turn off the analog function of the P00 port; set POIO to turn on the digital output function of the P00 port;

[0058] ③ Wait for the capacitor to be fully charged;

[0059] ④ Enable the ultra-low-power wake-up enable bit ULPWUE;

[0060] ⑤ Set the IE0 register to turn on the external interrupt 0 enable bit of the P00 port;

[0061] ⑥ Set the P0IO register to set the P00 port to input mode;

[0062] ⑦ Enter the sleep mode and wait for the system to wake up automatically;

[0063] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the technical field of the present invention based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A low-power wake-up circuit integrated in an MCU, characterized in that, Including: Flip-flops DQ1 to DQ6, NOT gates NOT1 to NOT5, AND gates AND1 to AND3, tri-state gate TS1, exclusive-OR gate XOR1, comparator CMP1, and selector MUX1; Among them, the D terminals of flip-flops DQ1 to DQ4 and the output terminals of NOT gates NOT1 to NOT4 are all connected to the data bus. The CLK terminal of flip-flop DQ1 is connected to the write enable signal of the P0 register. The Q terminal of flip-flop DQ1 is connected to the input terminal of tri-state gate TS1. The output terminal of tri-state gate TS1 is connected to the IO port of the MCU. The CLK terminal of flip-flop DQ2 is connected to the write enable signal of the P0IO register. The QN terminal of flip-flop DQ2 and the input terminal of NOT gate NOT1 are connected to the control terminal of tri-state gate TS1. The control terminal of NOT gate NOT1 is connected to the read enable signal of the P0IO register. The control terminal of NOT gate NOT2 is connected to the read enable signal of the P0 register. The CLK terminal of flip-flop DQ3 is connected to the write enable signal of the IE0 register. The QN terminal of flip-flop DQ3 is connected to the input terminal of NOT gate NOT3. The control terminal of NOT gate NOT3 is connected to the read enable signal of the IE0 register. The CLK terminal of flip-flop DQ4 is connected to the write enable signal of the P0AN register. The Q terminal of flip-flop DQ4 is connected to the input terminal of NOT gate NOT5. The QN terminal of flip-flop DQ4 is connected to the input terminal of NOT gate NOT4. The control terminal of NOT gate NOT4 is connected to the read enable signal of the P0AN register. The three input terminals of AND gate AND1 are respectively connected to the Q terminals of flip-flops DQ1 and DQ3 and the output terminal of XOR gate XOR1. The output terminal of AND gate AND1 outputs a level change interrupt wake-up signal. The two input terminals of XOR gate XOR1 are respectively connected to the Q terminals of flip-flops DQ5 and DQ6. The Q terminal of flip-flop DQ5 is connected to the input terminal of NOT gate NOT2. The EN terminal of flip-flop DQ5 is connected to CLK3. The EN terminal of flip-flop DQ6 is connected to the read enable signal of the P0 register. The output terminals of NOT gate NOT5 and selector MUX1 are respectively connected to the two input terminals of AND gate AND2. The output terminal of AND gate AND2 is connected to the D terminals of flip-flops DQ5 and DQ6. The two input terminals of selector MUX1 are respectively connected to the inverting input terminal and the output terminal of comparator CMP1. The control terminal of selector MUX1 is connected to the ultra-low power wake-up enable signal ULPWKE and the ultra-low power current I ULP of the first terminal. The non-inverting input terminal of comparator CMP1 is connected to the output voltage V of the DAC module IL . The inverting input terminal of comparator CMP1 is connected to the output terminal of tri-state gate TS1 and the ultra-low power current I ULP of the second terminal. The ground terminal of the ultra-low power current I ULP is grounded; After the wake-up signal arrives and before the external crystal oscillator oscillation stabilizes, the internal clock is used as the system main clock; after the external crystal oscillator oscillation stabilizes, the internal oscillation is switched to the external crystal oscillator as the system main clock; It also includes the working process of dual-speed clock startup: before entering the sleep mode, enable the dual-speed clock startup; the system wakes up from the sleep mode; the internal oscillator starts working at the frequency set before sleep, and the system starts executing instructions at this frequency; at the same time as waking up, the external oscillator starts working, the external oscillator counter starts counting, and when it counts to 1023, FLAG is set; after FLAG is set, the system clock remains low, waiting for the falling edge of the external oscillator to appear; switch the external oscillator to be the system clock source.

2. The low-power wake-up circuit integrated in the MCU according to claim 1, characterized in that, The ultra-low power consumption current I ULP is generated by a capacitor module, the capacitor module includes: a PMOS transistor P1, an NMOS transistor N1, a capacitor C1, a resistor R1, and an AND gate AND3; three input terminals of the AND gate AND3 are respectively connected to an ultra-low power consumption wake-up enable signal ULPWKE, a sleep enable signal SLEEP, and an inverting input terminal of a comparator CMP1, an output terminal of the AND gate AND3 is connected to a gate terminal of the PMOS transistor P1, a source terminal of the PMOS transistor P1 is connected to a power supply voltage VDD, a drain terminal of the PMOS transistor P1 is connected to the ultra-low power consumption wake-up enable signal ULPWKE, one end of the capacitor C1, and a drain terminal of the NMOS transistor N1, a gate terminal of the NMOS transistor N1 is connected to the sleep enable signal SLEEP, a source terminal of the NMOS transistor N1 is grounded, the other end of the capacitor C1 is connected to one end of the resistor R1, and the other end of the resistor R1 is grounded.

3. The low-power wake-up circuit integrated in the MCU according to claim 1, characterized in that, It also includes a diode module, and the diode module includes diodes D1 to D2; the positive terminal of diode D1 and the negative terminal of diode D2 are connected to the port, the negative terminal of diode D1 is connected to the power supply voltage VDD, and the positive terminal of diode D2 is grounded.

4. The low-power wake-up circuit integrated in the MCU according to claim 1, characterized in that, The P0 register is a data register with ports P00 to P07. Writing 1 to bit0 of the P0 register makes P00 port output 1, and writing 0 to bit0 of the P0 register makes P00 port output 0; The IE0 register is an external port level change interrupt enable register, and the P00 port is the port corresponding to external interrupt 0, which is controlled by bit0 of the IE0 register; The P0IO register is an input / output direction control register for a group of ports in the P0 register. When bit0 of the P0IO register is 1, the P00 port is in the input state, and when bit0 is 0, the P00 port is in the output state; The P0AN register is a register that controls whether the P00 port functions as an analog input or a digital I / O. When bit0 of the P0AN register is 1, the P00 port functions as an analog input, and when bit0 is 0, the P00 port functions as a digital I / O.

5. The low-power wake-up circuit integrated in the MCU according to claim 1, characterized in that, By means of the DAC module integrated inside the MCU, different output voltages V of the DAC module are set IL values to achieve dynamic adjustment of the timed wake-up time; that is, through the formula V IL = VDDexp(-t / RC); Wherein, VDD is the power supply voltage, R and C are the resistance and capacitance values integrated inside the MCU respectively, and t is the set timing wake-up time.

6. The low-power wake-up circuit integrated in the MCU according to claim 2, characterized in that, It also includes the working process of ultra-low power port wake-up: set the P0 register to enable P00 port to output 1; set the P0AN register to turn off the analog function of P00 port; set the P0IO register to turn on the digital output function of P00 port; wait for the capacitor C1 to be fully charged; enable the ultra-low power wake-up enable signal ULPWKE; set the IE0 register to turn on the external interrupt 0 enable bit of P00 port; set the P0IO register to set the P00 port to the input mode; enter the sleep mode and wait for the system to wake up automatically.

Images