SPI communication module and SPI communication system

Abstract

The application discloses an SPI communication module and an SPI communication system, and belongs to the technical field of integrated circuits.The SPI communication module comprises an SPI function module and a test module, and the test logic of the test module and the function logic of the SPI function module are independent of each other.The test module comprises a plurality of test registers; the plurality of test registers are configured based on a CPU, and control the SPI communication module to work in a normal mode or a test mode; when the SPI communication module works in the normal mode, the test module does not work, and the SPI function module normally performs a communication function; when the SPI communication module works in the test mode, input signals and output signals of the SPI function module can be monitored through read-write access to the plurality of test registers, so that the test of the SPI communication module is realized.The design can help users to quickly locate an error source, reduces the test difficulty, improves the test efficiency, and simultaneously improves the test coverage.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to an SPI communication module and an SPI communication system. Background Technology

[0002] SPI (Serial Peripheral Interface) is a high-speed, full-duplex, synchronous communication bus that uses only four pins on a chip, saving pins and simplifying PCB (Printed Circuit Board) layout. Due to its ease of use, more and more chips integrate SPI communication modules, often simply referred to as SPI modules. For SPI communication modules, good design testability helps chip designers test whether the SPI communication module functions correctly within the overall chip system and quickly locate problems when faults occur.

[0003] Current design for testability (DPT) is divided into boundary scan testing, memory-in-memory self-test (WITS), and scan testing. Boundary scan testing aims to facilitate testing by interconnecting input / output pads (IO-PADs) using the JTAG (Joint Test Action Group) interface. Memory-in-memory self-test primarily targets internal SRAM (Static Random-Access Memory) and other storage modules. Scan testing replaces all flip-flops in the chip with scan flip-flops, which are then connected together to form a scan chain. In test mode, this scan chain allows for the movement of test data in and out, enabling control and observation of the circuit.

[0004] However, the boundary scan test described above targets the I / O pad, not the internal communication module. Memory-built-in self-test primarily targets SRAM and other memory types, while the scan test mainly tests whether the flip-flops in all modules function correctly. It is evident that existing chip design for testability cannot test internal modules or monitor their ports. When system problems occur, it is difficult to quickly locate the source of the error, impacting chip testing efficiency and reducing chip reliability. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides an SPI communication module and an SPI communication system. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] In a first aspect, the present invention proposes an SPI communication module, which includes an SPI functional module and a test module, wherein the test logic of the test module is independent of the functional logic of the SPI functional module; wherein the test module includes several test registers, and the several test registers are connected to the SPI functional module.

[0007] Several test registers, based on the CPU (Central Processing Unit) configuration, control the SPI communication module to operate in normal mode or test mode. When the SPI communication module operates in normal mode, the test module does not work, and the SPI functional module performs its communication function normally. When the SPI communication module operates in test mode, by reading and writing to several test registers, the input and output signals of the SPI functional module can be monitored, thereby enabling the testing of the SPI communication module.

[0008] Secondly, this invention proposes an SPI communication system, including a CPU chip, in which an SPI communication module is integrated. The SPI communication module includes an SPI functional module and a test module, and the test logic of the test module is independent of the functional logic of the SPI functional module. The test module includes several test registers, which are connected to the SPI functional module and are also connected to the CPU core through an AMBA (Advanced Microcontroller Bus Architecture) bus.

[0009] The CPU core, based on instructions issued by the host computer, configures several test registers via the AMBA bus, thereby controlling the SPI communication module to operate in normal mode or test mode. When the SPI communication module operates in normal mode, the test module does not work, and the SPI functional module performs its communication function normally. When the SPI communication module operates in test mode, by reading and writing to several test registers, the input and output signals of the SPI communication module can be monitored, thereby enabling the testing of the SPI communication module.

[0010] The beneficial effects of this invention are:

[0011] The SPI communication module provided by this invention embeds a test module within the SPI communication module from the initial chip design stage, separating the test logic of the test module from the functional logic of the SPI functional module. The test module is mainly implemented by several test registers. Through CPU configuration, the SPI communication module is controlled to operate in normal mode or test mode. In test mode, by reading and writing to these test registers, the input and output signals of the SPI functional module are monitored, realizing internal testing of the SPI communication module. This design helps users quickly locate the source of errors, reduces testing difficulty, improves testing efficiency, saves manpower and resources, and also increases test coverage.

[0012] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0013] Figure 1 This is an architecture diagram of an SPI communication module provided in an embodiment of the present invention;

[0014] Figure 2 This is a schematic diagram of the design scheme for the test input port of the SPI communication module provided in an embodiment of the present invention;

[0015] Figure 3 This is a schematic diagram of the design scheme for the test output port of the SPI communication module provided in an embodiment of the present invention;

[0016] Figure 4 This is an overall architecture diagram of the test module provided in an embodiment of the present invention;

[0017] Figure 5 This is a schematic diagram of the port design scheme for the loopback test mode of the SPI communication module provided in an embodiment of the present invention;

[0018] Figure 6 This is a CPU chip framework diagram including a test module in an SPI communication system provided by an embodiment of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] A first aspect of the present invention provides an SPI communication module. See also... Figure 1 , Figure 1This is an architecture diagram of an SPI communication module provided in an embodiment of the present invention. The SPI communication module includes an SPI functional module and a test module (also called an SPI test module), and the test logic of the test module is independent of the functional logic of the SPI functional module. The test module includes several test registers, which are connected to the SPI functional module.

[0021] Several test registers, based on the CPU configuration, control the SPI communication module to operate in normal mode or test mode. When the SPI communication module operates in normal mode, the test module does not work, and the SPI functional module performs its communication function normally. When the SPI communication module operates in test mode, the input and output signals of the SPI functional module can be monitored by reading and writing to the several test registers, thereby realizing the testing of the SPI communication module.

[0022] Generally, the SPI communication module is a sub-module of a chip, connected to the CPU via the AMBA bus, and performs normal functions based on the CPU's configuration. This invention embeds a test module within the SPI communication module, using C programming to issue instructions to the CPU, enabling normal and test access between the CPU and the SPI communication module.

[0023] Optionally, as one implementation method, the test module designed in this embodiment specifically includes four test registers, namely a test control register, a test input register, a test output register, and a test data register, and all four registers are readable and writable registers; at the same time, four test modes are also designed, namely input test mode, output test mode, data test mode, and loopback test mode.

[0024] The relevant information for the four test registers is shown in Table 1 below.

[0025] Table 1 Test Register List

[0026]

[0027]

[0028] The test control register is used to control the opening and closing of the test mode;

[0029] The test input register is used to read and write the input ports of the SPI function module in input test mode to test the input path of the signal from outside the chip to inside the chip;

[0030] The test output register is used to read and write the output port of the SPI function module in output test mode to realize the output path test of the signal from inside the chip to outside the chip;

[0031] The test data register is used to read and write the SPI function module's transmit and receive FIFO in data test mode to test the FIFO function.

[0032] The internal design and function of each test register are described in detail below.

[0033] For the test control register SPITCR, this embodiment configures it as a read / write register with a bit width of 2; wherein,

[0034] The first bit is the test mode enable pin, which is configured by the CPU and connected to the test input register and the test output register;

[0035] The second bit is the test FIFO enable pin, which is configured by the CPU and connected to the test data register and the FIFO.

[0036] The specific functional design of the test control register SPITCR is detailed in Table 2 below.

[0037] Table 2 Test Control Register Functions

[0038]

[0039] For the test input register SPITIR, this embodiment configures it as a 4-bit read / write register; wherein,

[0040] The first connection is to the SPIRXD port, which is the data input signal of the SPI function module, and is used to monitor the value of the SPIRXD port.

[0041] The second bit connects to the chip select input signal SPISIN port of the SPI function module and is used to monitor the value of the SPISIN port.

[0042] The third bit connects to the SPICLKIN port, which is the clock synchronization input signal of the SPI function module, and is used to monitor the value of the SPICLKIN port.

[0043] The fourth bit is configured by the CPU and is used to terminate the DMA transfer function.

[0044] The specific functional design of the test input register SPITIR is detailed in Table 3 below.

[0045] Table 3 Test Input Register Functionality

[0046]

[0047] For the test output register SPITOR, this embodiment configures it as a read / write register with a bit width of 7; wherein,

[0048] The first bit is configured by the CPU module and is used to send data output signals;

[0049] The second bit is configured by the CPU module and is used to issue the chip select output signal;

[0050] The third bit is configured by the CPU module and is used to output the clock signal;

[0051] The fourth bit is configured by the CPU module and is used to issue a clock output enable signal;

[0052] The fifth bit is configured by the CPU module and is used to issue an output enable signal;

[0053] The sixth bit is configured by the CPU and connected to the SPINTR port of the SPI function module. It is used to issue an interrupt service request signal and monitor the value of the SPINTR port.

[0054] The seventh bit is configured by the CPU and connected to the SPIDMAREQ port of the SPI function module. It is used to output a DMA request signal and monitor the value of the SPIDMAREQ port.

[0055] The specific functional design of the test output register SPITOR is detailed in Table 4 below.

[0056] Table 4 Test Output Register Function

[0057]

[0058] For the test data register SPITDR, the test data register is configured as a 16-bit readable and writable register; when the second bit of the test control register, the test FIFO enable pin, is configured to 1, the SPI communication module works in data test mode, and the FIFO function is tested by writing data to the receive FIFO or reading data from the transmit FIFO.

[0059] The specific functional design of the test data register SPITDR is shown in Table 5 below.

[0060] Table 5. Test Data Register

[0061]

[0062] This invention provides a testing function for the SPI communication module in a chip. It embeds a testing module, mainly composed of test registers, into the SPI communication module. By reading and writing to these test registers, the input and output signals of the SPI communication module can be monitored.

[0063] Understandably, after configuring a dedicated test register for access, the input / output terminals also need to be designed to ensure that testing is independent of normal function. The following section details the port design of the SPI communication module under different test modes.

[0064] Specifically, the data input terminal of the test control register SPITCR is connected to the CPU via the AMBA bus, allowing the CPU to configure its ITEN and TESTFIFO bits to control the SPI communication module's operation in normal or test mode. When ITEN is 1, the SPI communication module operates in test mode; when ITEN is 0, it operates in normal mode. The ITEN bit of the test control register acts as the control terminal, controlling the test input register SPITIR and the test output register SPITOR. When TESTFIFO is 1, data testing of the SPI communication module can be performed by reading and writing to the FIFO through the test register; when TESTFIFO is 0, data testing of the SPI communication module is not possible. The TESTFIFO bit of the test control register acts as the control terminal, controlling the test data register.

[0065] For the design of the SPI communication module's test input port, the input signal generated by the test input register SPITIR is independent and separate from the input signal in normal mode. When ITEN is 1, the SPI function module operates in test mode, and the input signal is generated by the test input register; if ITEN is 0, the SPI function module operates in normal mode, and the input signal is generated by an external module.

[0066] When test mode is enabled, and the SPITIR test input register is active, the SPI communication module operates in input test mode. Please refer to [link to relevant documentation]. Figure 2 , Figure 2 This is a schematic diagram of the design scheme of the test input port of the SPI communication module provided in this embodiment of the invention. The data input terminal of the test input register is connected to the CPU via the AMBA bus; the fourth bit of the test input register (i.e., SPITIR[3]) is configured by the CPU and then connected to the first multiplexer (i.e., ...). Figure 2 The first input terminal of the multiplexer 1) in the test module is connected to the second input terminal of the first multiplexer; the control terminal of the first multiplexer is connected to the test mode enable terminal.

[0067] When the SPI communication module is working in normal mode, the first multiplexer selects the DMA clear signal of the Ex_DMACLR port of the output test module to the input port of the SPI function module.

[0068] When the SPI communication module is working in input test mode, the CPU sends a DMACLR (clear interrupt) signal to the SPI function module by writing the fourth bit of the test input register. At the same time, it monitors the value of the input port of the SPI function module by reading the first to third bits of the test input register (i.e., SPITIR[2:0]) to determine whether the input path of the signal from outside the chip to inside the chip is normal.

[0069] Specifically, when 1 is written to ITEN in the test control register, the port input signal is determined by the corresponding bit of the SPITIR register. Writing 1 to SPITIR[3] and then writing 0 can simulate the transmission clear signal sent by the external DMA controller, and reading this bit can tell you what the clear value sent by the DMA controller to the SPI function module is.

[0070] In input test mode, the SPITIR[3] bit is written to send the DMACLR signal to the SPI function module instead of the DMA module inside the chip. The value of the SPI input port monitored by SPITIR[2:0] is read to determine whether the data path from outside the chip to inside the chip is normal.

[0071] Furthermore, for the design of the test output port of the SPI function module, the output signal generated by the test is independently separated from the signal generated by the normal function. If ITEN is 1, the output signal is generated by the test register; if ITEN is 0, the output signal is generated by the internal function module.

[0072] When test mode is enabled, and the test output register SPITOR is active, the SPI communication module operates in output test mode. Please refer to [link to relevant documentation]. Figure 3 , Figure 3 This is a schematic diagram of the design scheme for the test output port of the SPI communication module provided in this embodiment of the invention. The data input terminal of the test output register is connected to the CPU via an AMBA bus; the sixth and seventh bits (i.e., SPITOR[6:5]) of the test output register are configured by the CPU and then connected to the second multiplexer (i.e.,... Figure 3 The first input terminal of the multiplexer 2) in the SPI module; the second input terminal of the second multiplexer is connected to the SPIDMAREQ port and the SPIINTR port of the SPI function module; the control terminal of the second multiplexer is connected to the test mode enable terminal;

[0073] The first to fifth bits of the test output register (i.e., SPITOR[4:0]) are configured by the CPU module and then connected to the third multiplexer (i.e., Figure 3The first input terminal of the multiplexer 3) in the SPI module; the second input terminal of the third multiplexer is connected to the normal function register of the SPI module, and the control terminal of the third multiplexer is connected to the test mode enable terminal;

[0074] When the SPI communication module is working in normal mode, the second multiplexer selects the data from the SPIDMAREQ port and SPIINTR port of the output SPI function module to the DMA controller and the interrupt controller; the third multiplexer selects the data from the normal function register of the output SPI function module to the output port of the SPI function module.

[0075] When the SPI communication module is operating in output test mode, the second multiplexer selects the sixth and seventh bits of the output test output register to the DMA controller and the interrupt controller; the third multiplexer selects the first to fifth bits of the output test output register to the output port of the SPI function module.

[0076] Specifically, writing 1 to ITEN in the test control register first enters the test mode. Then, writing 1 to SPITOR[6:5] followed by 0 can issue DMA request signals and interrupt request signals. When ITEN is written to 0, reading this register can reveal the signal values ​​generated by the internal functional modules, thus determining whether there are any internal errors.

[0077] In output test mode, by writing SPITOR[6:5] bits to send signals to DMA and interrupt controller instead of the normal function module inside SPI, and by writing SPITOR[4:0] bits to send data to SPI output port, it can be determined whether the data path from inside the chip to outside the chip is normal.

[0078] Furthermore, when the test mode is enabled, the SPI communication module operates in data test mode when the test data register SPIDR is active.

[0079] In data test mode, the data reading and writing of the test FIFO within the SPI function module is controlled by reading and writing the SPITDR register to determine whether the normal FIFO is functioning properly.

[0080] This embodiment rationally designs the functions of the four test registers in the test module and the port design between each test register and the SPI communication module, realizing the testing of different ports of the SPI functional module. The overall architecture of the test module is as follows: Figure 4 As shown in the figure, each test register is mainly implemented by a D flip-flop, and the signal descriptions of each port in the figure are shown in Table 6 below.

[0081] Table 6. Explanation of Test Module Port Signals

[0082]

[0083]

[0084] The port signals are divided into AMBA bus signals, SPI internal signals, and SPI communication signals. Among them, SPICR mainly generates the enable signal for the multiplexer inside the test module.

[0085] In test mode, the SPITIR test input register can mainly read clock and data signals received on the SPI channel for monitoring, and can also generate a DMA clear signal to be sent to the SPI control core.

[0086] In test mode, the SPITOR test output register can primarily read and monitor signals such as clock and data sent by the SPI controller. It can also generate DMA request signals to the DMA controller within the chip and interrupt request signals to the interrupt controller within the chip.

[0087] To read the value of a test register, the CPU can access the address of the corresponding test register to read the data, which is then sent to the APB bus via PRDATA.

[0088] Depend on Figure 4 It can be seen that when ITEN is 0, SPI is working in normal mode, all test registers are closed, and the input signals of the test module will bypass all test registers and be output directly without affecting normal function.

[0089] It should be noted that, with test mode enabled, the input and output ports of the SPI module can be connected to allow the SPI communication module to operate in loopback test mode. The port design scheme for the SPI communication module's loopback test mode is as follows: Figure 5 As shown.

[0090] In loopback test mode, the SPI function module can be used to send and receive data to check whether the entire data path is normal.

[0091] The SPI communication module provided by this invention embeds a test module within the SPI communication module from the initial chip design stage, separating the test logic of the test module from the functional logic of the SPI functional module. The test module is mainly implemented by several test registers. Through CPU configuration, the SPI communication module is controlled to operate in normal mode or test mode. In test mode, these test registers are accessed by reading and writing to monitor the input and output signals of the SPI functional module, realizing internal testing of the SPI communication module. Specifically, in the SPI communication module designed in this invention, the signals are mainly divided into two parts: one part is the data for communication between SPI modules, and the other part is the bus signal for communication between the internal module and the CPU core. The test module embedded in the SPI communication module is mainly used to monitor the communication data of the SPI functional module and a portion of the bus signals. When the test function is not enabled, all data bypasses the test module and directly enters the SPI functional module. This design helps users quickly locate the source of errors, reduces testing difficulty, improves testing efficiency, saves manpower and resources, and also increases test coverage.

[0092] A second aspect of the present invention also provides an SPI communication system, which includes a CPU chip. The CPU chip integrates an SPI communication module, which includes an SPI functional module and a test module. The test logic of the test module is independent of the functional logic of the SPI functional module. Please refer to [link to relevant documentation]. Figure 6 , Figure 6 This is a CPU chip framework diagram including a test module in an SPI communication system provided by an embodiment of the present invention. The test module includes several test registers, which are connected to the SPI functional module and also connected to the CPU core via an AMBA bus.

[0093] Based on instructions issued by the host computer, the CPU core configures several test registers via the AMBA bus, thereby controlling the SPI communication module to operate in normal mode or test mode. When the SPI communication module operates in normal mode, the test module does not work, and the SPI functional module performs its communication function normally. When the SPI communication module operates in test mode, by reading and writing to several test registers, the input and output signals of the SPI functional module can be monitored, thereby enabling the testing of the SPI communication module.

[0094] For details regarding the specific structural design and testing principles of the SPI communication module, please refer to the relevant description in the first aspect above. It can be seen that the SPI communication module provided by this invention mainly achieves the following functions:

[0095] 1. The input signals of the SPI function module are captured and entered into the internal register for monitoring;

[0096] 2. Simulate the output signal of the SPI function module;

[0097] 3. Connect the input and output signals of the SPI function module to test whether the SPI communication module is correctly connected to the system.

[0098] The generation, transmission, and reception of test signals are all performed via the AMBA bus.

[0099] Therefore, the SPI communication system provided by this invention can also be used to test SPI functional modules, thereby determining whether the chip is working properly in the system, improving chip reliability, reducing testing difficulty, and improving testing efficiency.

[0100] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0101] Although this application has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the accompanying drawings, the disclosure, and the appended claims, will understand and implement other variations of the disclosed embodiments in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple instances. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0102] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. An SPI communication circuit, characterized in that, The SPI communication circuit includes an SPI functional module and a test module, and the test logic of the test module is independent of the functional logic of the SPI functional module. The test module includes four test registers: a test control register, a test input register, a test output register, and a test data register. These four test registers are connected to the SPI functional module. The four test registers, based on the CPU configuration, control the SPI communication circuit to operate in normal mode or test mode. The test modes include input test mode, output test mode, data test mode, and loopback test mode. When the SPI communication circuit operates in normal mode, the test module is inactive, and the SPI functional module performs its communication function normally. When the SPI communication circuit operates in test mode, by reading and writing to the four test registers, the input and output signals of the SPI functional module can be monitored, thereby enabling the testing of the SPI communication circuit. The test control register is used to control the opening and closing of the test mode; the test input register is used to read and write the input port of the SPI function module in the input test mode to realize the input path test of the signal from outside the chip to inside the chip; the test output register is used to read and write the output port of the SPI function module in the output test mode to realize the output path test of the signal from inside the chip to outside the chip; the test data register is used to read and write the transmit and receive FIFO of the SPI function module in the data test mode to realize the test of the FIFO function. The test control register is configured as a 2-bit register; wherein, the first bit is the test mode enable bit, configured by the CPU and connected to the test input register and the test output register; the second bit is the test FIFO enable bit, configured by the CPU and connected to the test data register and the FIFO; The test input register is configured as a 4-bit register; wherein, the first bit is connected to the data input signal SPIRXD port of the SPI function module and is used to monitor the value of the SPIRXD port; the second bit is connected to the chip select input signal SPISIN port of the SPI function module and is used to monitor the value of the SPISIN port; the third bit is connected to the clock synchronization input signal SPICLKIN port of the SPI function module and is used to monitor the value of the SPISIN port; the fourth bit is configured by the CPU and is used to terminate the DMA transfer function. The test output register is configured as a 7-bit register; wherein, the first bit is configured by the CPU to issue a data output signal; the second bit is configured by the CPU to issue a chip select output signal; the third bit is configured by the CPU to issue a clock output signal; the fourth bit is configured by the CPU to issue a clock output enable signal; the fifth bit is configured by the CPU to issue an output enable signal; the sixth bit is configured by the CPU and connected to the SPINTR port of the SPI functional module to issue an interrupt service request signal and monitor the value of the SPINTR port; the seventh bit is configured by the CPU and connected to the SPIDMAREQ port of the SPI functional module to issue a DMA request signal and monitor the value of the SPIDMAREQ port. The test data register is configured as a 16-bit register; when the second bit of the test control register, the test FIFO enable pin, is configured to 1, the SPI communication circuit operates in data test mode, and the FIFO function is tested by writing data into the receive FIFO or reading data from the transmit FIFO.

2. The SPI communication circuit according to claim 1, characterized in that, The data input terminal of the test input register is connected to the CPU via the AMBA bus; the fourth bit of the test input register is configured by the CPU and connected to the first input terminal of the first multiplexer; the second input terminal of the first multiplexer is connected to the Ex_DMACLR port of the test module; the control terminal of the first multiplexer is connected to the test mode enable terminal. When the SPI communication circuit is operating in normal mode, the first multiplexer selects and outputs the DMA clear signal of the Ex_DMACLR port of the test module to the input port of the SPI function module. When the SPI communication circuit is operating in input test mode, the CPU sends a DMACLR signal to the SPI function module by writing the fourth bit of the test input register. At the same time, it monitors the value of the input port of the SPI function module by reading the first to third bits of the test input register to determine whether the input path of the signal from outside the chip to inside the chip is normal.

3. The SPI communication circuit according to claim 1, characterized in that, The data input terminal of the test output register is connected to the CPU via the AMBA bus; the sixth and seventh bits of the test output register are configured by the CPU and connected to the first input terminal of the second multiplexer; the second input terminal of the second multiplexer is connected to the SPIDMAREQ port and SPIINTR port of the SPI function module; the control terminal of the second multiplexer is connected to the test mode enable terminal. The first to fifth bits of the test output register are configured by the CPU and then connected to the first input of the third multiplexer; the second input of the third multiplexer is connected to the normal function register of the SPI module, and the control terminal of the third multiplexer is connected to the test mode enable terminal. When the SPI communication circuit is operating in normal mode, the second multiplexer selects to output data from the SPIDMAREQ port and SPIINTR port of the SPI function module to the DMA controller and the interrupt controller; the third multiplexer selects to output data from the normal function register of the SPI function module to the output port of the SPI function module. When the SPI communication circuit is operating in output test mode, the second multiplexer selects to output the sixth and seventh bits of the test output register to the DMA controller and the interrupt controller; the third multiplexer selects to output the first to fifth bits of the test output register to the output port of the SPI functional module.

4. The SPI communication circuit according to claim 3, characterized in that, When the SPI communication circuit operates in loopback test mode, the output port and input port of the SPI functional module are connected to test the connection relationship between the SPI communication circuit and the external system.

5. An SPI communication system, comprising a CPU chip, characterized in that, The CPU chip integrates an SPI communication circuit, which includes an SPI functional module and a test module. The test logic of the test module is independent of the functional logic of the SPI functional module. The test module includes four test registers: a test control register, a test input register, a test output register, and a test data register. The four test registers are connected to the SPI functional module and also connected to the CPU core via an AMBA bus. The CPU core, based on instructions from the host computer, configures the four test registers via the AMBA bus, thereby controlling the SPI communication circuit to operate in normal mode or test mode. The test modes include input test mode, output test mode, data test mode, and loopback test mode. When the SPI communication circuit operates in normal mode, the test module is inactive, and the SPI functional module performs its communication function normally. When the SPI communication circuit operates in test mode, by reading and writing to the four test registers, the input and output signals of the SPI functional module can be monitored, thereby enabling testing of the SPI communication circuit. The test control register is used to control the opening and closing of the test mode; the test input register is used to read and write the input port of the SPI function module in the input test mode to realize the input path test of the signal from outside the chip to inside the chip; the test output register is used to read and write the output port of the SPI function module in the output test mode to realize the output path test of the signal from inside the chip to outside the chip; the test data register is used to read and write the transmit and receive FIFO of the SPI function module in the data test mode to realize the test of the FIFO function. The test control register is configured as a 2-bit register; wherein, the first bit is the test mode enable bit, configured by the CPU and connected to the test input register and the test output register; the second bit is the test FIFO enable bit, configured by the CPU and connected to the test data register and the FIFO; The test input register is configured as a 4-bit register; wherein, the first bit is connected to the data input signal SPIRXD port of the SPI function module and is used to monitor the value of the SPIRXD port; the second bit is connected to the chip select input signal SPISIN port of the SPI function module and is used to monitor the value of the SPISIN port; the third bit is connected to the clock synchronization input signal SPICLKIN port of the SPI function module and is used to monitor the value of the SPISIN port; the fourth bit is configured by the CPU and is used to terminate the DMA transfer function. The test output register is configured as a 7-bit register; wherein, the first bit is configured by the CPU to issue a data output signal; the second bit is configured by the CPU to issue a chip select output signal; the third bit is configured by the CPU to issue a clock output signal; the fourth bit is configured by the CPU to issue a clock output enable signal; the fifth bit is configured by the CPU to issue an output enable signal; the sixth bit is configured by the CPU and connected to the SPINTR port of the SPI functional module to issue an interrupt service request signal and monitor the value of the SPINTR port; the seventh bit is configured by the CPU and connected to the SPIDMAREQ port of the SPI functional module to issue a DMA request signal and monitor the value of the SPIDMAREQ port. The test data register is configured as a 16-bit register; when the second bit of the test control register, the test FIFO enable pin, is configured to 1, the SPI communication circuit operates in data test mode, and the FIFO function is tested by writing data into the receive FIFO or reading data from the transmit FIFO.

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