An interface circuit for a universal robot controller

Abstract

The present invention relates to the technical field of interface electronic signal processing, in particular to the technical field of controller interface circuits, and specifically discloses an interface circuit of a universal robot controller, including an IO expansion unit, an input-output unit and an external interface unit, wherein the IO expansion unit includes an expansion chip, the input-output unit includes a single-pole double-throw switch chip, a PMOS tube, an NMOS tube, a diode and a resistor, and the external interface unit includes an external connector. The structural circuit can be independently configured into any one of source output, drain output, NPN signal input and PNP signal input through software, which can improve the versatility of the controller, improve the robot's limited internal space, meet the peripheral interface requirements of different types of robots, and solve the problems existing in the prior art.

Description

Technical Field

[0001] The present invention relates to the technical field of interface electronic signal processing, in particular to the technical field of controller interface circuit. Background Art

[0002] There are many types of robots, such as handling robots, unmanned forklifts, patrol robots, etc. Different types of controllers require different numbers of external input and output interfaces, and the signal types are not all the same. If each robot needs to be designed with a dedicated controller according to the use needs, it will not only be costly but also not conducive to hardware maintenance. In addition, when the existing robot peripherals are connected to the controller, the sensor signal is often connected to the controller, and the sensor power supply is then connected to the terminal block, and the overall assembly line wiring process is complicated.

[0003] For example, the existing robot peripherals include emergency stop switches, anti-collision strips, status indicator strips and fill lights, relays, photoelectric sensors, motors, etc. The number and types of IO interface peripherals are large, requiring a large number of CPU input and output interface resources, which not only increases the BOM cost, but also increases the development, manufacturing and testing costs. In addition, robots are different from other traditional products. They are mainly customized, and different customer needs are different, resulting in different robots having different requirements for the input interface and output interface circuits of the controller. Therefore, in order to reduce costs and improve the versatility of controllers, the compatibility and adaptability of peripheral interfaces are very necessary (that is, the external interface can be either input or output). The traditional peripheral interface design of traditional controllers is to separate the output port and the input port, but for controllers with general needs, there are more compatible peripherals, which requires more input and output interfaces, which leads to more external interfaces, large circuit board size, and large controller size, which is a serious problem for the internal space of compact robots. In addition, the traditional input port is generally only applicable to one of the PNP type or NPN type sensors, which cannot be well compatible. Different interface circuits often need to be designed for different types of sensors.

[0004] For example, the Chinese patent application authorization announcement number CN115967394B discloses a multi-channel isolation multiplexing port circuit based on a robot arm controller. When the port is used as an input, it only supports sensors with NPN type signals, but not sensors with PNP type signals, so the compatibility is poor. Another example is the IO interface circuit of a robot controller disclosed in the patent application authorization announcement number CN118093492B. When the circuit structure is used as an external output, it can only be used as a sink output (output ground), and cannot be used as a source output (output positive power supply).

[0005] In summary, there is an urgent need for an interface circuit of a controller that can meet the needs of different types of robots. Summary of the invention

[0006] The object of the present invention is to provide an interface circuit for a universal robot controller. The structural circuit can improve the versatility of the controller and meet the peripheral interface requirements of different types of robots within the limited internal space of the robot, so as to solve the problems existing in the above-mentioned prior art.

[0007] To achieve the above-mentioned purpose, the technical solution of the present invention is: an interface circuit of a universal controller of a robot, comprising an IO expansion unit, an input-output unit and an external interface unit, the IO expansion unit comprising an expansion chip, the input-output unit comprising a single-pole double-throw switch chip, a PMOS tube, an NMOS tube, a fuse, a diode and a resistor, and the external interface unit comprising an external connector.

[0008] The PMOS tube includes a PMOS tube customized as Q1 and Q2, the NMOS tube includes an NMOS tube customized as Q5, Q7 and Q9, the diode includes a diode customized as D1, D3, D5 and D7, and the resistor includes a resistor customized as R1, R3, R5, R7, R8, R11, R12, R15, R16, R17 and R19; the external connector CN1 has multiple IO interfaces, each of which can be used independently as an output port or an input port, wherein the connection of one IO1 signal pin is as follows, and the remaining IO interfaces can be connected in the same way as the IO1 signal pin for extended application.

[0009] The CS# signal pin of the expansion chip is connected to the SPI-CS signal pin of the controller CPU chip, the SCK signal pin is connected to the SPI-SCK signal pin of the controller CPU chip, the SI signal pin is connected to the SPI-SI signal pin of the controller CPU chip, the SO signal pin is connected to the SPI-SO signal pin of the controller CPU chip, the INTB signal pin is connected to the INTB signal pin of the controller CPU chip, the INTA signal pin is connected to the INTA signal pin of the controller CPU chip, the VDD signal pin is connected to the power supply and connected to the power ground GND through capacitor C5, the VSS signal pin is connected to the power ground GND, the A0 signal pin is connected to the power ground GND, the A1 signal pin is connected to the power ground GND, and the A2 signal pin is connected to the power ground GND.

[0010] The Y1 signal pin of the single-pole double-throw switch chip is connected to the gate of the NMOS tube Q5, the Y2 signal pin is connected to the gate of the NMOS tube Q7 through the resistor R12, the COM signal pin and the VCC signal pin are both connected to the power supply and connected to the power ground GND through the capacitor C1; the GND signal pins are both connected to the power ground GND, the INH signal pin is connected to the GPA0 signal pin of the expansion chip U5, the A signal pin is connected to the GPA1 signal pin of the expansion chip U5, the INH signal pin and the A signal pin are output ends, and the Y1 signal pin and the Y2 signal pin are connected to the power supply. The pin is the input terminal, and the truth table of its control input terminal and output terminal is as follows: when the INH signal pin and the A signal pin are low level, the Y1 signal pin = the COM signal pin, and the Y2 signal pin is suspended; when the INH signal pin is low level and the A signal pin is high level, the Y1 signal pin is suspended, and the Y2 signal pin = the COM signal pin; when the INH signal pin is high level and the A signal pin is low level, the Y1 signal pin is suspended, and the Y2 signal pin is suspended; when the INH signal pin is high level and the A signal pin is high level, the Y1 signal pin is suspended, and the Y2 signal pin is suspended.

[0011] The source of the NMOS transistor Q7 is connected to the power ground GND, the gate is connected to the power ground GND through a resistor R15, and the drain is connected to the IO1 signal pin of the external connector CN1. The source of the NMOS transistor Q5 is connected to the power ground GND, and the drain is connected to the gate of the PMOS transistor Q1 through a resistor R7. The gate of the NMOS transistor Q9 is connected to the power ground GND through a resistor R19, the source is connected to the power ground GND, and the drain is connected to the power supply through a resistor R11 and connected to the GPA3 signal pin of the expansion chip U5.

[0012] The S signal pin of the PMOS tube Q1 is connected to the power supply through the fuse F1 and connected to the gate of the PMOS tube Q1 through the resistor R5, and the drain is connected to the IO1 signal pin of the external connector CN1. The source of the PMOS tube Q2 is connected to the power supply, the gate is connected to the power supply through the resistor R1, and the drain is connected to the power ground GND through the resistor R8 and connected to the GPA2 signal pin of the expansion chip U5.

[0013] The IO1 signal pin of the external connector CN1 is respectively connected to the anode of the diode D1, the cathode of the diode D7, the cathode of the diode D3 and the anode of the diode D5, the cathode of the diode D1 is connected to the power supply, the anode of the diode D7 is connected to the power ground GND, the anode of the diode D3 is connected to the gate of the PMOS tube Q2 through the resistor R3, and the cathode of the diode D5 is connected to the gate of the NMOS tube Q9 through the resistor R17.

[0014] When applied, when the external interface is configured as a source output, the controller CPU chip sets the GPA0 signal pin of the expansion chip U5 to output a low level and the GPA1 signal pin to output a low level through the SPI bus, controls the Y1 signal pin of the single-pole double-throw switch chip U1 to output a high level, and the NMOS tube Q5 is turned on, thereby controlling the PMOS tube Q1 to turn on, and each of its external output S signal pins is connected to the power supply through the fuse F1. When the external interface is configured as a drain output, the controller CPU chip sets the GPA0 signal pin of the expansion chip U5 to output a low level and the GPA1 signal pin to output a high level through the SPI bus, controls the Y2 signal pin of the single-pole double-throw switch chip U1 to output a high level, and the NMOS tube Q7 is turned on, and each of its external output S signal pins is connected to the power ground GND. When the external interface is configured as input and an NPN signal is input, the controller CPU chip reads the state of the GPA2 signal pin of the expansion chip U5 through the SPI bus to read the signal. When the NPN signal is triggered, the external connector CN1 is connected to the power ground, the diode D3 is turned on, the gate voltage of the PMOS tube Q1 is less than the threshold value, the PMOS tube Q1 is turned on, and the GPA2 signal pin of the expansion chip U5 jumps from a low level to a high level, triggering the terminal of the INTA signal pin of the expansion chip U5. The controller CPU chip reads the data of the GPA2 signal pin of the expansion chip U5 through the SPI bus. When the external interface is configured as input and a PNP signal is input, the controller CPU chip reads the state of the GPA3 signal pin of the expansion chip U5 through the SPI bus to read the signal. When the PNP signal is triggered, the external connector CN1 is turned on to the power supply, the diode D5 is turned on, the gate voltage of the NMOS tube Q9 is greater than the threshold value, the NMOS tube Q9 is turned on, and the GPA3 signal pin of the expansion chip U5 jumps from a high level to a low level, triggering the INTA signal pin terminal of the expansion chip U5. The controller CPU chip reads the data of the GPA3 signal pin of the expansion chip U5 through the SPI bus.

[0015] The model of the expansion chip U5 is MCP23S17T-E / SS, the model of the single-pole double-throw switch chip U1 is SN74LVC2G53DCUR, the model of the fuse F1 is BSMD1206-100-30V, the model of the PMOS tube Q1 is AONR21357, the model of the PMOS tube Q2 is BSS84LT1G, the model of the NMOS tube Q7 is AON7264E, the model of the NMOS tubes Q5 and Q9 is 2N7002, the model of the diodes D1 and D7 is S310, the model of the diodes D3 and D5 is 1N4148W, the model of the external connector CN1 is DB128V-5.08-4P, the resistance of the resistor R12 is 1 KΩ, the resistance of the resistor R3 is 3 The resistance values ​​of the resistors R7, R8 and R11 are 4.7 KΩ, the resistance values ​​of the resistors R17 and R19 are 6.8 KΩ and / or the resistance values ​​of the resistors R1, R5, R15 and R16 are 10 KΩ.

[0016] The expansion chip U5 and / or the external connector CN1 can be multiple settings, and the IO interfaces of the multiple external connectors CN1 can be connected to the IO1 signal pin in the same way to expand the application.

[0017] By adopting the above technical solution, the beneficial effects of the present invention are: to solve the problems existing in the above prior art and meet the peripheral interface requirements of different types of robots in a limited internal space, reduce costs, improve hardware development efficiency, and improve the versatility of the controller, the interface circuit of a robot universal controller with the above structure of the present invention can be independently configured into any one of source output, sink output, NPN signal input and PNP signal input through software, and also has the following advantages:

[0018] (1) Good scalability: As shown in the following embodiment, up to 7 groups of identical circuits can be added. The controller CPU uses a group of SPI buses and 2 INT interrupt signals, and the signal expansion can expand 32 software-configurable input and output general interfaces.

[0019] (2) Versatility: When the interface circuit is used as an input, it is compatible with PNP type or NPN type sensors. When the interface circuit is used as an output, the source type or sink type output can be configured through software. Therefore, the interface circuit of a robot universal controller of the present invention helps to improve the versatility of the controller and meet the interface requirements of various controllers, such as forklift AGV, rail-mounted robot and inspection robot.

[0020] (3) Output self-check function: Regardless of whether the configured output is a sink or source type, the controller CPU can read the expansion chip IO status through SPI to verify whether the output is normal.

[0021] (4) The program software is highly efficient. When the controller controls the output, it only needs to write data to the expansion chip. When there is a change in the input interface, an interrupt is triggered, and the controller then reads the expansion circuit chip register.

[0022] (5) When the controller CPU initializes the default level, the IO interface will not have any output. Since the single-pole double-throw module has an intermediate state, there will be no output. The output port will not cause simultaneous output short circuit due to program problems. When the source output is used, the output power passes through a fuse to provide overcurrent protection. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 The invention relates to a circuit schematic diagram of an input / output unit and an external interface unit in an interface circuit of a universal robot controller.

[0024] Figure 2 The invention relates to a circuit schematic diagram of an IO expansion unit in an interface circuit of a universal robot controller.

[0025] Figure 3 It is a schematic diagram of an input-output single circuit in which an external connector CN1 is connected to an IO2 signal pin in an interface circuit of a robot universal controller according to the present invention;

[0026] Figure 4 The present invention relates to a single circuit schematic diagram of an input and output circuit in which an external connector CN1 is connected to an IO3 signal pin in an interface circuit of a robot universal controller.

[0027] Figure 5 The present invention relates to a single circuit schematic diagram of an input and output circuit in which an external connector CN1 is connected to an IO4 signal pin in an interface circuit of a robot universal controller.

[0028] In the figure:

[0029] IO expansion unit 1, input and output unit 2, external interface unit 3. DETAILED DESCRIPTION

[0030] In order to further explain the technical solution of the present invention, the present invention is described in detail below through specific embodiments.

[0031] The interface circuit of a robot universal controller disclosed in this embodiment is as follows: Figure 1 and Figure 2As shown, it includes an IO expansion unit 1, an input-output unit 2 and an external interface unit 3; the IO expansion unit 1 includes an expansion chip U5 and a capacitor C1; the input-output unit 2 includes a single-pole double-throw switch chip U1, PMOS tubes Q1 and Q2, NMOS tubes Q5, Q7 and Q9, diodes D1, D3, D5 and D7, resistors R1, R3, R5, R7, R8, R11, R12, R15, R16, R17 and R19 and a fuse F1, and the external interface unit 3 includes an external connector CN1. In this embodiment, the single-pole double-throw switch chip U1 is used to switch the output, which can effectively avoid the simultaneous output of the power supply 24V+ and the power supply ground due to program abnormalities, and avoid short circuits. The external connector CN1 described in this embodiment is a multi-IO interface, that is, a multi-channel IO signal pin. As shown in the figure, there are 4 channels IO1-IO4. Each channel interface can be used as an output port or an input port independently without interfering with each other. The following is combined with the accompanying drawings to connect the 1-channel IO signal pin of the external connector CN1 as an example to describe the circuit connection structure setting of each unit.

[0032] The 11th signal pin (CS# signal pin) of the expansion chip U5 is connected to the SPI-CS signal pin of the controller CPU chip;

[0033] The 12th signal pin (SCK signal pin) of the expansion chip U5 is connected to the SPI-SCK signal pin of the controller CPU chip;

[0034] The 13th signal (SI signal pin) of the expansion chip U5 is connected to the SPI-SI signal pin of the controller CPU chip;

[0035] The 14th signal pin (SO signal pin) of the expansion chip U5 is connected to the SPI-SO signal pin of the controller CPU chip;

[0036] The 19th signal pin (INTB signal pin) of the expansion chip U5 is connected to the INTB signal pin of the controller CPU chip;

[0037] The 20th signal pin (INTA signal pin) of the expansion chip U5 is connected to the INTA signal pin of the controller CPU chip;

[0038] The 9th signal (pin VDD signal pin) of the expansion chip U5 is connected to the power supply +3.3V inside the controller, and is connected to the power ground GND through the capacitor C5;

[0039] The 10th signal pin (VSS signal pin) of the expansion chip U5 is connected to the power ground GND of the controller;

[0040] The 15th signal pin (A0 signal pin) of the expansion chip U5 is connected to the power ground GND of the controller;

[0041] The 16th signal pin (A1 signal pin) of the expansion chip U5 is connected to the power ground GND of the controller;

[0042] The 17th signal pin (A2 signal pin) of the expansion chip U5 is connected to the power ground GND of the controller;

[0043] The 7th signal pin (Y1 signal pin) of the single-pole double-throw switch chip U1 is connected to the gate of the NMOS tube Q5 and is connected to the power ground GND through the resistor R16;

[0044] The sixth signal pin (Y2 signal pin) of the single-pole double-throw switch chip U1 is connected to the gate (fourth signal pin) of the NMOS tube Q7 through the resistor R12;

[0045] The 1st signal pin (COM signal pin) and the 8th signal pin (VCC signal pin) of the single-pole double-throw switch chip U1 are both connected to the power supply +3.3V inside the controller, and connected to the power ground GND through the capacitor C1;

[0046] The third signal pin and the fourth signal pin (GND signal pin) of the single-pole double-throw switch chip U1 are both connected to the power ground GND of the controller;

[0047] The second signal pin (INH signal pin) of the single-pole double-throw switch chip U1 is connected to the 21st signal pin (GPA0 signal pin) of the expansion chip U5;

[0048] The 5th signal pin (A signal pin) of the single-pole double-throw switch chip U1 is connected to the 22nd signal pin (GPA1 signal pin) of the expansion chip U5;

[0049] The control input and output truth tables of the single-pole double-throw switch chip U1 are as follows:

[0050] The first signal pin, the second signal pin and the third signal pin (S signal pin, source) of the NMOS tube Q7 are all connected to the power ground GND;

[0051] The gate (G signal pin) of the NMOS tube Q7 is connected to the power ground GND through the resistor R15;

[0052] The 5th signal pin, the 6th signal pin, the 7th signal pin, the 8th signal pin and the 9th signal pin (D signal pin) of the NMOS transistor Q7 are all connected to the first signal pin (IO1 signal pin) of the external connector CN1;

[0053] The source (S signal pin) of the NMOS tube Q5 is connected to the power ground GND;

[0054] The drain (D signal pin) of the NMOS tube Q5 is connected to the gate (G signal pin) of the PMOS tube Q1 through the resistor R7;

[0055] The gate of the NMOS tube Q9 is connected to the power ground GND of the controller through a resistor R19;

[0056] The source of the NMOS tube Q9 is connected to the power ground GND of the controller;

[0057] The drain of the NMOS tube Q9 is connected to the power supply +3.3.V of the controller through the resistor R11;

[0058] The drain of the NMOS tube Q9 is connected to the 24th signal pin (GPA3 signal pin) of the expansion chip U5;

[0059] The 1st signal pin, the 2nd signal pin and the 3rd signal pin (S signal pin) of the PMOS tube Q1 are all connected to the power supply +24V of the controller through the fuse F1, and are connected to the 4th signal pin (G signal pin) of the PMOS tube Q1 through the resistor R5;

[0060] The 5th signal pin, the 6th signal pin, the 7th signal pin, the 8th signal pin and the 9th signal pin (D signal pin) of the PMOS tube Q1 are all connected to the first signal pin (IO1 signal pin) of the external connector CN1;

[0061] The source of the PMOS tube Q2 is connected to the power supply +3.3.V of the controller;

[0062] The gate of the PMOS tube Q2 is connected to the power supply +3.3.V of the controller through the resistor R1;

[0063] The drain of the PMOS tube Q2 is connected to the power ground GND of the controller through a resistor R8;

[0064] The drain of the PMOS tube Q2 is connected to the 23rd signal pin (GPA2 signal pin) of the expansion chip U5;

[0065] The first signal pin (IO1 signal pin) of the external connector CN1 is connected to the anode of the diode D1, and the cathode of the diode D1 is connected to the power supply +24V of the controller;

[0066] The first signal pin (IO1 signal pin) of the external connector CN1 is connected to the cathode of the diode D7, and the anode of the diode D7 is connected to the power ground GND of the controller;

[0067] The first signal pin IO1 of the external connector CN1 is connected to the cathode of the diode D3, and the anode of the diode D3 is connected to the gate of the PMOS tube Q2 through the resistor R3;

[0068] The first signal pin IO1 of the external connector CN1 is connected to the anode of the diode D5, and the cathode of the diode D5 is connected to the gate of the NMOS transistor Q9 through the resistor R17.

[0069] The connection structure of the above components constitutes an interface circuit of a universal robot controller of the present invention. In application, when the external interface is configured as a source output, the controller CPU chip sets the 21st signal pin (GPA0 signal pin) of the expansion chip U5 to output a low level and the 22nd signal pin (GPA1 signal pin) to output a low level through the SPI bus, controls the 7th signal pin (Y1 signal pin) of the single-pole double-throw switch chip U1 to output a high level, the NMOS tube Q5 is turned on, and then controls the PMOS tube Q1 to turn on, and the external output IO1 signal pin is connected to the power supply +24V through the fuse F1.

[0070] In application, when the external interface is configured as a leakage output, the controller CPU chip sets the 21st signal pin (GPA0 signal pin) of the expansion chip U5 to output a low level and the 22nd signal pin (GPA1 signal pin) to output a high level through the SPI bus, controls the 6th signal pin (Y2 signal pin) of the single-pole double-throw switch chip U1 to output a high level, the NMOS tube Q7 is turned on, and the external output IO1 signal pin is connected to the power ground GND.

[0071] In application, when the external interface is configured as input and the NPN signal is input, the controller CPU chip reads the state of the 23rd signal pin GPA2 of the expansion chip U5 through the SPI bus to read the signal; its working principle is: when the NPN signal is triggered, the external connector CN1 is connected to the power ground, the diode D3 is turned on, the voltage difference between the gate and the source (S signal pin) of the PMOS tube Q2 is less than the threshold value, the PMOS tube Q2 is turned on, and the 23rd signal pin (GPA2 signal pin) of the expansion chip U5 jumps from a low level to a high level, triggering the interrupt of the 20th signal pin (INTA signal pin) of the expansion chip U5, and the controller CPU chip reads the data of the 23rd signal pin (GPA2 signal pin) of the expansion chip U5 through the SPI bus.

[0072] In application, when the external interface is configured as input and a PNP signal is input, the controller CPU chip reads the state of the 24th signal pin (GPA3 signal pin) of the expansion chip U5 through the SPI bus to read the signal; its working principle is: when the PNP signal is triggered, the external connector CN1 is connected to the power supply +24V, the diode D5 is turned on, the voltage difference between the gate and the source of the NMOS tube Q9 is greater than the threshold value, the NMOS tube Q9 is turned on, and the 24th signal pin (GPA3 signal pin) of the expansion chip U5 jumps from a high level to a low level, triggering the interruption of the 20th signal pin (INTA signal pin) of the expansion chip U5, and the controller CPU chip reads the data of the 24th signal pin (GPA3 signal pin) of the expansion chip U5 through the SPI bus.

[0073] In the experimental embodiment of the present invention, the expansion chip U5 adopts a chip of model MCP23S17T-E / SS, and its hardware address is set to 000; the single-pole double-throw switch chip U1 adopts a model SN74LVC2G53DCUR; the fuse F1 adopts a model BSMD1206-100-30V, whose trip current is 1.8A, the holding current is 1A, and the maximum voltage is 30V; the PMOS tube Q1 adopts a model AONR21357; the PMOS tube Q2 adopts a model BSS84LT1G; the NMOS tube Q7 adopts a model AON7264E; the NMOS tubes Q5 and Q9 adopt a model 2N7002; the diodes D1 and D7 adopt a model S310; the diodes D3 and D5 adopt a model 1N4148W; the resistance of the resistor R12 is 1 KΩ; the resistance of the resistor R3 is 3 The resistance of the resistors R7, R8 and R11 is 4.7KΩ; the resistance of the resistors R17 and R19 is 6.8KΩ; the resistance of the resistors R1, R5, R15 and R16 is 10KΩ; the model of the external connector CN1 is DB128V-5.08-4P. The above components are existing technology products and can be directly purchased on the market.

[0074] The above circuit structure and the same structural principle can be extended to connect the other three IO signals of the external connector CN1. The specific circuit structure can be obtained by those skilled in the art by connecting the above external connector CN1 to the IO1 signal pin. Figure 3 , Figure 4 and Figure 5 The schematic diagrams of the input-output unit circuits are shown in which the external connector CN1 is connected to the IO2 signal pin, the IO3 signal pin, and the IO4 signal pin, which will not be described in detail here.

[0075] The interface circuit of the present invention has a self-checking function. When the output is set to source type, a PNP type input signal triggers, and when the output is set to sink type, an NPN type input signal triggers. The controller reads the extended input circuit through the SPI bus, obtains the interface level at this time, and self-checks whether the output is normal.

[0076] The interface circuit of the present invention has good expansibility, and can expand more external interfaces by adding expansion chips, external connectors, etc., and can expand up to 32 input and output interfaces by using 2 interrupt IO ports and an SPI bus. The principle is that 8 IO expansion chips are set with 8 different addresses, and the 8 IO expansion chips share 2 interrupt signals. When the interrupt is triggered, the CPU polls the IO expansion chip through the SPI bus to obtain the input signal status.

[0077] The above embodiments and drawings do not limit the product form and style of the present invention. Any appropriate changes or modifications made by ordinary technicians in the relevant technical field should be deemed to be within the patent scope of the present invention.

Claims

1. An interface circuit for a universal robot controller, characterized in that: It includes an IO expansion unit, an input-output unit and an external interface unit, wherein the IO expansion unit includes an expansion chip, the input-output unit includes a single-pole double-throw switch chip U1, a PMOS tube, an NMOS tube, a fuse, a diode and a resistor, and the external interface unit includes an external connector CN1; The PMOS tube includes a PMOS tube customized as Q1 and Q2, the NMOS tube includes an NMOS tube customized as Q5, Q7 and Q9, the diode includes a diode customized as D1, D3, D5 and D7, and the resistor includes a resistor customized as R1, R3, R5, R7, R8, R11, R12, R15, R16, R17 and R19; the external connector CN1 has multiple IO interfaces, each of which can be used as an output port or an input port independently, wherein the connection of one IO1 signal pin is as follows, and the other IO interfaces can be connected to the IO1 signal pin in the same way for extended application; The CS# signal pin of the expansion chip is connected to the SPI-CS signal pin of the controller CPU chip, the SCK signal pin is connected to the SPI-SCK signal pin of the controller CPU chip, the SI signal pin is connected to the SPI-SI signal pin of the controller CPU chip, the SO signal pin is connected to the SPI-SO signal pin of the controller CPU chip, the INTB signal pin is connected to the INTB signal pin of the controller CPU chip, the INTA signal pin is connected to the INTA signal pin of the controller CPU chip, the VDD signal pin is connected to the power supply and connected to the power ground GND through the capacitor C5, the VSS signal pin is connected to the power ground GND, the A0 signal pin is connected to the power ground GND, the A1 signal pin is connected to the power ground GND, and the A2 signal pin is connected to the power ground GND; The Y1 signal pin of the single-pole double-throw switch chip U1 is connected to the gate of the NMOS tube Q5, the Y2 signal pin is connected to the gate of the NMOS tube Q7 through the resistor R12, the COM signal pin and the VCC signal pin are both connected to the power supply and connected to the power ground GND through the capacitor C1; the GND signal pins are both connected to the power ground GND, the INH signal pin is connected to the GPA0 signal pin of the extension chip U5, the A signal pin is connected to the GPA1 signal pin of the extension chip U5, the INH signal pin and the A signal pin are output ends, the Y1 signal pin and the Y2 signal pin are connected to the power supply and connected to the power ground GND through the capacitor C1; the GND signal pins are both connected to the power ground GND, the INH signal pin is connected to the GPA0 signal pin of the extension chip U5, the A signal pin is connected to the GPA1 signal pin of the extension chip U5, the INH signal pin and the A signal pin are output ends, and ... connected to the power ground GND, and the INH signal pin and the A signal pin are output ends. The INH signal pin is the input terminal, and its control input terminal and output terminal truth table are as follows: when the INH signal pin and the A signal pin are low level, the Y1 signal pin = the COM signal pin, and the Y2 signal pin is suspended; when the INH signal pin is low level and the A signal pin is high level, the Y1 signal pin is suspended, and the Y2 signal pin = the COM signal pin; when the INH signal pin is high level and the A signal pin is low level, the Y1 signal pin is suspended, and the Y2 signal pin is suspended; when the INH signal pin is high level and the A signal pin is high level, the Y1 signal pin is suspended, and the Y2 signal pin is suspended; The source of the NMOS transistor Q7 is connected to the power ground GND, the gate is connected to the power ground GND through the resistor R15, and the drain is connected to the IO1 signal pin of the external connector CN1; The source of the NMOS transistor Q5 is connected to the power ground GND, and the drain is connected to the gate of the PMOS transistor Q1 through a resistor R7; The gate of the NMOS tube Q9 is connected to the power ground GND through a resistor R19, the source is connected to the power ground GND, and the drain is connected to the power supply through a resistor R11 and connected to the GPA3 signal pin of the expansion chip U5; The source of the PMOS tube Q1 is connected to the power supply through the fuse F1 and connected to the gate of the PMOS tube Q1 through the resistor R5, and the drain is connected to the IO1 signal pin of the external connector CN1; The source of the PMOS tube Q2 is connected to the power supply, the gate is connected to the power supply through the resistor R1, and the drain is connected to the power ground GND through the resistor R8 and connected to the GPA2 signal pin of the expansion chip U5; The IO1 signal pin of the external connector CN1 is respectively connected to the anode of the diode D1, the cathode of the diode D7, the cathode of the diode D3 and the anode of the diode D5, the cathode of the diode D1 is connected to the power supply, the anode of the diode D7 is connected to the power ground GND, the anode of the diode D3 is connected to the gate of the PMOS tube Q2 through the resistor R3, and the cathode of the diode D5 is connected to the gate of the NMOS tube Q9 through the resistor R17.

2. The interface circuit of a robot universal controller as claimed in claim 1, characterized in that: When it is used, when the external interface is configured as a source output, the controller CPU chip sets the GPA0 signal pin of the expansion chip U5 to output a low level and the GPA1 signal pin to output a low level through the SPI bus, controls the Y1 signal pin of the single-pole double-throw switch chip U1 to output a high level, and turns on the NMOS tube Q5, thereby controlling the PMOS tube Q1 to turn on, and each external output S signal pin is connected to the power supply through the fuse F1; When the external interface is configured as a leakage output, the controller CPU chip sets the GPA0 signal pin of the expansion chip U5 to output a low level and the GPA1 signal pin to output a high level through the SPI bus, controls the Y2 signal pin of the single-pole double-throw switch chip U1 to output a high level, and the NMOS tube Q7 is turned on, and its external output S signal pins are connected to the power ground GND; When the external interface is configured as input, an NPN signal is input, and the controller CPU chip reads the state of the GPA2 signal pin of the expansion chip U5 through the SPI bus to read the signal. When the NPN signal is triggered, the external connector CN1 is connected to the power ground, the diode D3 is turned on, the gate voltage of the PMOS tube Q1 is less than the threshold value, the PMOS tube Q1 is turned on, and the GPA2 signal pin of the expansion chip U5 jumps from a low level to a high level, triggering the terminal of the INTA signal pin of the expansion chip U5. The controller CPU chip reads the data of the GPA2 signal pin of the expansion chip U5 through the SPI bus; When the external interface is configured as input, a PNP signal is input, and the controller CPU chip reads the state of the GPA3 signal pin of the expansion chip U5 through the SPI bus to read the signal. When the PNP signal is triggered, the external connector CN1 is turned on to the power supply, the diode D5 is turned on, the gate voltage of the NMOS tube Q9 is greater than the threshold value, the NMOS tube Q9 is turned on, and the GPA3 signal pin of the expansion chip U5 jumps from a high level to a low level, triggering the INTA signal pin terminal of the expansion chip U5. The controller CPU chip reads the data of the GPA3 signal pin of the expansion chip U5 through the SPI bus.

3. An interface circuit of a robot universal controller as claimed in claim 1 or 2, characterized in that: The model of the expansion chip U5 is MCP23S17T-E / SS, the model of the single-pole double-throw switch chip U1 is SN74LVC2G53DCUR, the model of the fuse F1 is BSMD1206-100-30V, the model of the PMOS tube Q1 is AONR21357, the model of the PMOS tube Q2 is BSS84LT1G, the model of the NMOS tube Q7 is AON7264E, the model of the NMOS tubes Q5 and Q9 is 2N7002, the model of the diodes D1 and D7 is S310, the model of the diodes D3 and D5 is 1N4148W, the model of the external connector CN1 is DB128V-5.08-4P, the resistance of the resistor R12 is 1 KΩ, the resistance of the resistor R3 is 3 The resistance values ​​of the resistors R7, R8 and R11 are 4.7 KΩ, the resistance values ​​of the resistors R17 and R19 are 6.8 KΩ and / or the resistance values ​​of the resistors R1, R5, R15 and R16 are 10 KΩ.

4. An interface circuit of a robot universal controller as claimed in claim 1 or 2, characterized in that: The expansion chip U5 and / or the external connector CN1 can be configured in multiple ways, and the IO interfaces of the multiple external connectors CN1 can be connected to the IO1 signal pin in the same way for expansion application.

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