Virtualization test and system-process collaborative optimization method for influence of residual stress of post-process of core particle integration on performance of transistor device

Abstract

The invention discloses a virtualization test and system-process collaborative optimization method for influence of residual stress of a post-process of core particle integration on performance of a transistor device. Starting from core particle integration back-end process simulation and a quantum transport equation, the influence of the residual stress of the core particle integration back-end process on the performance of the transistor device is studied, and the performance indexes such as a current-voltage curve, carrier distribution and state density of the device are evaluated. The method mainly comprises the following steps: (1) modeling and simulating a core particle integration subsequent process to determine residual stress caused by the core particle integration subsequent process; (2) combining the residual stress of the core particle integration post-process with a deformation potential theory, and substituting into quantum transport simulation to consider the influence of the stress on the energy band structure of the device; and (3) analyzing a simulation result, and realizing virtualization test and system-technology collaborative optimization of the influence of the residual stress of the post-process of core particle integration on the performance of the transistor device. The method has important application value in the fields of technological process system-technology collaborative optimization and semiconductor device simulation and design.

Description

Technical Field

[0001] The present invention relates to the field of chip integration back-end process optimization and design, and relates to a virtualization test and system-process collaborative optimization method for the impact of residual stress in a chip integration back-end process on transistor device performance. Background Art

[0002] Hybrid bonding has attracted great attention in 2.5D / 3D integrated circuits / chips in recent years due to its unique advantages such as higher interconnection density, lower power consumption and better signal integrity. In 2022, AMD and Intel respectively used hybrid bonding technology to integrate memory into computing chips in a vertical stacking manner or through a multi-die interconnect bridge (EMIB), significantly improving memory bandwidth and reducing latency. The products were named Ryzen 75800X3D and Ponte Vecchio respectively.

[0003] Currently, most research focuses on improving the effectiveness and reliability of hybrid bonding, including increasing Cu pillar density, lowering bonding temperature, and reducing stress migration [K.Lee et al., "Novel Hybrid Bonding Technology Using Ultra-High Density Cu Nano-Pillar for Exascale 2.5D / 3D Integration," IEEE Electron Device Letter, 2016].

[0004] However, although visible damage such as voids in Cu can be significantly reduced through process optimization, stress will still be introduced into the chip during the final annealing and cooling steps of hybrid bonding, which will cause changes in transistor device characteristics such as current density, Y parameter and gate capacitance by changing the band structure of the semiconductor, further affecting the performance of the processor.

[0005] On the other hand, FinFET is widely used in logic computing in commercial high-performance processors because its three-dimensional channel structure can better suppress short channel effects than planar MOSFET. Due to the extremely small size of FinFET, quantum effects are very significant and cannot be ignored, such as quantum confinement and source-drain tunneling. The non-equilibrium Green's function method [S. Datta, Quantum transport: atom to transistor. Cambridge university press, 2005.] can provide a general and rigorous framework to capture these quantum effects in FinFET and accurately evaluate FinFET performance.

[0006] However, there are currently few studies investigating the impact of stress induced by the hybrid bonding process on FinFET quantum transport in chips, which is necessary for the performance evaluation of 3D integrated circuits and further system-technology co-optimization.

[0007] The present invention is based on the core-grain integration back-end process modeling and calculation method and the quantum transport non-equilibrium Green's function method. By calculating the residual stress of the core-grain integration back-end process and combining it with the non-equilibrium Green's function, a virtual testing and system-process collaborative optimization method for the impact of residual stress of the core-grain integration back-end process on the performance of transistor devices is provided. Summary of the invention

[0008] In view of the deficiencies in the prior art, the present invention provides a virtual testing and system-process collaborative optimization method for the impact of residual stress in a chip integration back-end process on transistor device performance.

[0009] The technical solution adopted by the present invention is as follows:

[0010] A virtual testing and system-process collaborative optimization method for the influence of residual stress of chip integration back-end process on transistor device performance, mainly including:

[0011] Modeling and simulation of die integration back-end processes to determine the residual stresses caused;

[0012] Combine the residual stress of the back-end process of core particle integration with the deformation potential theory and substitute it into quantum transport simulation to consider the influence of stress on the device band structure;

[0013] Analyze simulation results to realize virtual testing of the impact of residual stress in the back-end process of chip integration on transistor device performance, thereby guiding optimization.

[0014] In the above technical scheme, further, the back-end process of core particle integration is modeled to obtain the residual strain of the copper pillar process, which is used as the strain source, and the solid mechanics numerical simulation of the entire core particle integration structure is performed to obtain the distribution of the residual stress of the back-end process of core particle integration in the transistor device, and the process residual stress is introduced into the deformation potential Hamiltonian of the device quantum transport simulation to consider the influence of stress on the device band structure, and then the non-equilibrium Green's function and Poisson's equation considering the stress deformation potential Hamiltonian are self-consistently solved to a steady state, and post-processing is performed to obtain the performance indicators of the device, and finally a comprehensive evaluation of the influence of the residual stress of the back-end process of core particle integration on the device performance is obtained.

[0015] Furthermore, the back-end process of core particle integration is modeled and simulated to obtain the process residual stress distribution, including:

[0016] (1) Modeling the back-end process of core particle integration, which includes core particle surface smoothing, interconnected copper pillar fabrication, room temperature oxide-oxide bonding, temperature rise annealing, and cooling; wherein the interconnected copper pillar fabrication introduces initial stress to the core particles, and when the temperature rises, the copper pillars at the upper and lower core particles expand and contact to form bonds, and the stress of the copper pillars relaxes during the annealing process. During the cooling step, stress is generated due to the thermal mismatch between the copper pillars and the core particles, which ultimately forms residual stress in the back-end process of core particle integration;

[0017] (2) According to the above modeling, solid mechanics numerical simulation is performed on the residual stress of the back-end process of core particle integration. The stress source is the thermal mismatch stress between the copper pillar and the oxide. The numerical equation to be solved is the stress equilibrium equation, thereby obtaining the distribution of the residual stress of the back-end process of core particle integration in the transistor device.

[0018] Furthermore, the process residual stress is introduced into the deformation potential Hamiltonian of the device quantum transport simulation to consider the influence of stress on the device band structure, including the following:

[0019] The residual stress of the post-process of core particle integration is transferred from the device coordinate system to the crystal coordinate system, and the deformation Hamiltonian is calculated according to the deformation potential theory; the system Hamiltonian is:

[0020] H=H k·p +H SO +H strain

[0021] Among them, H k·p is the six-band k·p Hamiltonian, H SO is the orbital-self-selection coupling Hamiltonian, H strain is the stress-deformation potential Hamiltonian.

[0022] Furthermore, the non-equilibrium Green's function and Poisson's equation are self-consistently solved to obtain steady-state simulation results of the device, and the device performance characteristics are further extracted. The device performance includes gate capacitance, current-voltage relationship curve, carrier distribution, or potential distribution, to evaluate the impact of post-process stress of core particle integration on device performance.

[0023] Furthermore, the process parameters are adjusted according to the evaluation results of the impact of residual stress in the back-end process of chip integration on device performance, or process parameters that optimize the performance of chiplets, integrated circuits and transistor devices are further selected from multiple sets of process parameters to achieve system-technology coordinated optimization of chiplets.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] 1. The present invention provides a virtual testing and system-process collaborative optimization method for the effect of residual stress in the back-end process of core particle integration on the performance of transistor devices. Compared with the traditional TCAD drift-diffusion transport simulation, this method can characterize the effect of residual stress in core particle integration on device performance from the perspective of stress affecting the band structure, evaluate the device current-voltage curve, gate capacitance, etc., and has guiding significance for further improving device performance. It has important application value in the fields of back-end process optimization, device design, and reliability evaluation of core particle integration.

[0026] 2. The present invention uses deformation potential theory to characterize the effect of stress on the device band structure, and then combines it with the six-band k·p Hamiltonian, and further self-consistently solves the non-equilibrium Green's function and Poisson's equation. Compared with traditional drift-diffusion transport simulation, this method can characterize the effect of stress on the band structure and depict quantum effects in advanced transistor devices, such as source-drain tunneling effect, quantum confinement effect, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Other features, objectives and advantages of the present invention will become more apparent from a reading of the detailed description of non-limiting embodiments made with reference to the following accompanying drawings.

[0028] Figure 1 A typical core particle integration structure is provided for the present invention, which is composed of a bonding copper pillar, a back-end process dielectric layer, and a silicon substrate, wherein Figure (a) is a 3D structure, and Figure (b) is a schematic diagram of its XZ cross section;

[0029] Figure 2 The present invention provides a typical transistor device structure, namely a fin field effect transistor, wherein Figure (a) is a 3D structure, and Figure (b) is a YZ cross-sectional schematic diagram thereof;

[0030] Figure 3 A virtualized test flow chart of the impact of the chip integration back-end process provided by the present invention on the performance of semiconductor devices;

[0031] Figure 4 Schematic diagram of stress evolution during the back-end process of core particle integration;

[0032] Figure 5 Schematic diagram of the key steps in the back-end process of chip integration;

[0033] Figure 6 The stress distribution of residual stress in the back-end process of core particle integration at the interface of silicon substrate / silicon dioxide medium according to an embodiment of the present invention;

[0034] Figure 7 Figure 1 is the residual stress distribution of the back-end process of the core particle integration of the embodiment of the present invention, wherein Figure (a) is the stress distribution at the core particle scale, and Figure (b) is the stress distribution at the device scale;

[0035] Figure 8 Schematic diagram of the distribution of the fin field effect transistor in the core particle according to an embodiment of the present invention, the position of the transistor is determined by a polar coordinate system, the center of the copper column is the origin, and the direction of the transistor and the distance between the transistor and the center of the copper column are used as the representation of the position;

[0036] Fig. 9 The effect of residual stress of the back-end process of core particle integration on the turn-on current of devices at different positions with different crystal orientations in the embodiment of the present invention. The crystal orientation of the device in Figure (a) is (110) / [-110], the crystal orientation of the device in Figure (b) is (001) /

[100] , and the crystal orientation of the device in Figure (c) is (111) / [-110].

[0037] Fig.10 Figure 1 is the effect of the key parameters of the back-end process of core particle integration on the transistor turn-on current and channel stress distribution in the embodiment of the present invention. Figure (a) shows the effect of different copper pillar spacings on the transistor turn-on current and channel stress distribution, Figure (b) shows the effect of different copper pillar diameters on the transistor turn-on current and channel stress distribution, and Figure (c) shows the effect of different annealing temperatures on the transistor turn-on current and channel stress distribution; DETAILED DESCRIPTION

[0038] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several changes and improvements can also be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0039] like Figure 1 As shown in the figure, it is a typical core-grain integrated structure, including bonding copper pillars, back-end process dielectric layers, and silicon substrates. Figure 1 (a) is the 3D structure. Figure 1 (b) is a schematic diagram of its XZ cross section; a typical nano-semiconductor electronic device is selected, taking the fin field effect transistor (FinFET) as an example, Figure 2 As shown, a comprehensive and detailed description is given of the virtual test of the device performance under the residual stress of the chip integration post-process. The virtual test method for the influence of residual stress of the chip integration post-process on device performance proposed in the present invention is not only applicable to fin field effect transistors, but also to most nanoscale semiconductor electronic devices.

[0040] According to a specific example of the present invention, a virtual testing and system-process collaborative optimization method for the influence of residual stress of a chip integration back-end process on transistor device performance includes the following steps:

[0041] like Figure 3As shown in the figure, a virtual test and system-process collaborative optimization method for the influence of residual stress in the back-end process of core particle integration on the performance of transistor devices is provided. First, a model is built for the back-end process of core particle integration. The back-end process of core particle integration generally includes core particle surface smoothing, interconnect copper pillar production, room temperature oxide-oxide bonding, temperature annealing, and cooling. The key steps are as follows Figure 5 As shown, the corresponding stress change process in the copper column is as follows Figure 4 As shown. When the temperature is increased before annealing, the copper pillar will try to expand, but compressive stress will form in the copper due to the limitation of the surrounding dielectric. Subsequently, during the longer annealing process, it can be observed that the stress in the copper pillar is relieved, and relatively low compressive stress is obtained at high temperature. When cooled from the annealed state to room temperature, the stress in the copper pillar increases rapidly to a high tensile value. Subsequently, the process residual strain of the copper pillar obtained by modeling (Equation 1) is used as the strain source, and the solid mechanics numerical simulation of the entire core particle integration structure is performed to obtain the distribution of the residual stress of the core particle integration post-process in the transistor. This step can be completed by solving the equilibrium equation (Equation 2). Subsequently, the process residual stress is introduced into the Hamiltonian in the device quantum transport simulation (Equation 3), and further quantum transport simulation of the self-consistent solution of the non-equilibrium Green's function (Equation 5) and the Poisson equation (Equation 4) is performed, and the current (Equation 6) and other results are further calculated to accurately evaluate the transistor device performance affected by the residual stress of the core particle integration post-process. By changing different process parameters and performing multiple rounds of virtual testing, we can obtain the process parameters that optimize the performance of transistor devices and chiplets, and achieve system-technology coordinated optimization of chiplet integration back-end processes and transistor device performance.

[0042] The back-end process of core particle integration is modeled, in which the interconnected copper pillars introduce initial stress to the core particles. When the temperature rises, the copper pillars at the upper and lower core particles expand and contact to form bonds. The stress of the copper pillars relaxes during the annealing process. During the cooling step, stress is generated due to the thermal mismatch between the copper pillars and the core particles, which eventually forms the residual stress of the back-end process of core particle integration. The process residual strain in the copper pillars is expressed as

[0043] ε=α(T room -T anneal ) (1)

[0044] Where α is the thermal expansion coefficient of the material, T room is room temperature, T anneal is the annealing temperature.

[0045] According to the above modeling, the residual stress of the back-end process of core particle integration is simulated by solid mechanics numerical simulation. The numerical method can be selected from finite element or finite difference methods. The stress source is the thermal mismatch stress between the copper pillar and the oxide. The numerical equation to be solved is the stress balance equation, which can obtain the distribution of the residual stress of the back-end process of core particle integration in the transistor device. The stress balance equation is as follows:

[0046]

[0047] Among them, F x，y，z is the stress load, σ x，y，z is the normal stress, τ xy(yz)(zx) is the shear stress.

[0048] The core residual stress is transferred from the device coordinate system to the crystal coordinate system and substituted into the deformation potential Hamiltonian. The deformation potential Hamiltonian is added to the six-band k·p Hamiltonian to obtain the total Hamiltonian, which is then substituted into the non-equilibrium Green's function to consider the effect of stress on the energy band in the simulation. The system Hamiltonian is in the form of:

[0049] H=H k·p +H SO +H strain (3)

[0050] Among them, H k·p is the six-band k·p Hamiltonian, H SO is the orbital-self-selection coupling Hamiltonian, H strain is the stress-deformation potential Hamiltonian.

[0051] The non-equilibrium Green's function and Poisson's equation are solved by self-consistent iteration. The Poisson's equation is as follows:

[0052]

[0053] Among them, ε r is the relative dielectric constant of the material, ε0 is the vacuum dielectric constant, V is the electric potential, q is the elementary charge, N D(A) is the donor (acceptor) doping concentration, and n(p) is the electron (hole concentration).

[0054] The non-equilibrium Green's function has the following form:

[0055] G r =[EI-HU-∑ s -∑ D ] -1 (5)

[0056] Where E is the energy level, I is the unit matrix, H is the Hamiltonian, U is the electric potential, ∑ s(D) is the source (drain) self-energy; and the convergence of the solution is judged, the error is relative error, and the physical quantity is judged by potential or current density. If the error of the current step is less than the error tolerance, it is judged as non-convergence, and the iterative operation is continued until convergence, otherwise the iteration is terminated and post-processing is performed to extract device performance such as gate capacitance, current-voltage relationship curve, carrier distribution, potential distribution, etc., to evaluate the impact of post-process stress of core particle integration on device performance.

[0057] The current calculation formula is as follows:

[0058]

[0059] in, is the reduced Planck constant, Trace is the trace of the matrix, G ＞ is greater than the Green's function, e is the elementary charge, q is the layer number, E is the energy level, and R is the coupling matrix between the q layer and the q+1 layer.

[0060] The evaluation results of the impact of residual stress in the back-end process of chip integration on device performance can be used to guide the optimization and adjustment of process parameters, or further select process parameters from multiple sets of process parameters that optimize the performance of chiplets, integrated circuits and transistor devices, thereby achieving system-technology coordinated optimization of chiplets.

[0061] The method of the present invention is used for Figure 1 and Figure 2 The relevant parameters used in the simulation are listed in Table 1.

[0062] Table 1 Device related parameters

[0063]

[0064] Figure 6 To model and simulate the stress distribution of residual stress at the interface of silicon substrate / silicon dioxide medium in the back-end process of core-grain integration; Figure 7 (a) shows the distribution of residual stress at the core particle scale in the back-end process of core particle integration. It can be observed that there is a sudden stress change at the interface between the transistor device and the dielectric. This is because the material of the transistor channel is silicon, and its Young's modulus is different from that of the oxide dielectric. Figure 7 (b) shows the distribution of residual stress in the back-end process of core integration at the transistor device scale, where the zz stress component is much larger than other stress components. Figure 8 The schematic diagram of the distribution of the fin field effect transistor in the core particle is shown in FIG. 1 , where the position of the transistor is determined by a polar coordinate system, the center of the copper column is the origin, and the direction of the transistor and the distance between the transistor and the center of the copper column are used as the representation of the position; Fig. 9 This is the effect of residual stress in the back-end process of core particle integration on the turn-on current of transistors at different positions in different crystal phases. The device in Figure (a) corresponds to a device with a crystal orientation of (110) / [-110], the device in Figure (b) corresponds to a device with a crystal orientation of (001) /

[100] , and the device in Figure (c) corresponds to a device with a crystal orientation of (111) / [-110]. Fig.10Figure 3 shows the influence of key parameters of the back-end process of core particle integration on the turn-on current and channel stress distribution of the transistor in this example. Figure (a) shows the influence of different copper pillar spacings on the turn-on current and channel stress distribution of the transistor. Figure (b) shows the influence of different copper pillar diameters on the turn-on current and channel stress distribution of the transistor. Figure (c) shows the influence of different annealing temperatures on the turn-on current and channel stress distribution of the transistor.

[0065] Combined with the simulation results, it can be seen that the back-end process of core particle integration will introduce stress of tens of megapascals to hundreds of megapascals in the transistor, and the zz stress component is significantly larger than other stress components. Process residual stress will cause the transistor turn-on current to increase, and the transistor turn-on current directly below the copper pillar changes the most. As the transistor is located away from the copper pillar, the impact on it gradually decreases. Increasing the copper pillar spacing, reducing the copper pillar diameter or annealing temperature can reduce the process residual stress in the transistor, thereby reducing the impact of the process on the transistor performance. A virtual test and system-process collaborative optimization method for the impact of core particle integration back-end process residual stress on transistor device performance provided by the present invention has important application value in the fields of 3D integrated circuit design, semiconductor process optimization, and transistor device design.

[0066] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essence of the present invention. In the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily.

Claims

1. A virtual test and system-process collaborative optimization method for the impact of residual stress in the back-end process of chip integration on transistor device performance, characterized in that: include: Modeling and simulation of die integration back-end processes to determine the residual stresses caused; Combine the residual stress of the back-end process of core integration with the deformation potential theory and substitute it into the quantum transport simulation to consider the influence of stress on the device band structure; Analyze simulation results to realize virtual testing of the impact of residual stress in the back-end process of chip integration on transistor device performance, thereby guiding optimization.

2. The virtual testing and system-process collaborative optimization method for the influence of residual stress of chip integration back-end process on transistor device performance according to claim 1, characterized in that: The core particle integration back-end process is modeled to obtain the residual strain of the copper pillar process. It is used as a strain source to perform solid mechanics numerical simulation of the entire core particle integration structure to obtain the distribution of residual stress in the core particle integration back-end process in the transistor device, and the process residual stress is introduced into the deformation potential Hamiltonian of the device quantum transport simulation to consider the influence of stress on the device band structure. Subsequently, the non-equilibrium Green's function and Poisson's equation considering the stress-deformation potential Hamiltonian are self-consistently solved to a steady state, and post-processing is performed to obtain the performance indicators of the device. Finally, a comprehensive evaluation of the influence of residual stress in the core particle integration back-end process on the device performance is obtained.

3. The virtual testing and system-process collaborative optimization method for the influence of residual stress of chip integration back-end process on transistor device performance according to claim 1, characterized in that: The chip integration back-end process is modeled and simulated to obtain the process residual stress distribution, including: (1) Modeling the back-end process of core particle integration, which includes core particle surface smoothing, interconnected copper pillar fabrication, room temperature oxide-oxide bonding, temperature rise annealing, and cooling; wherein the interconnected copper pillar fabrication introduces initial stress to the core particles, and when the temperature rises, the copper pillars at the upper and lower core particles expand and contact to form bonds, and the stress of the copper pillars relaxes during the annealing process. During the cooling step, stress is generated due to the thermal mismatch between the copper pillars and the core particles, which ultimately forms residual stress in the back-end process of core particle integration; (2) According to the above modeling, solid mechanics numerical simulation is performed on the residual stress of the back-end process of core particle integration. The stress source is the thermal mismatch stress between the copper pillar and the oxide. The numerical equation to be solved is the stress equilibrium equation, thereby obtaining the distribution of the residual stress of the back-end process of core particle integration in the transistor device.

4. The virtual testing and system-process collaborative optimization method for the influence of residual stress of chip integration back-end process on transistor device performance according to claim 1, characterized in that: The process residual stress is introduced into the deformation potential Hamiltonian of the device quantum transport simulation to consider the influence of stress on the device band structure, including the following: The residual stress of the post-process of core particle integration is transferred from the device coordinate system to the crystal coordinate system, and the deformation potential Hamiltonian is calculated according to the deformation potential theory; the system Hamiltonian is: H=H k·P +H SO +H strain Among them, H k·p is the six-band k·p Hamiltonian, H SO is the orbital-self-selection coupling Hamiltonian, H strain is the stress-deformation potential Hamiltonian.

5. The virtual testing and system-process collaborative optimization method for the influence of residual stress of chip integration back-end process on transistor device performance according to claim 1, characterized in that: The non-equilibrium Green's function and Poisson's equation are self-consistently solved to obtain the steady-state simulation results of the device, and the device performance characteristics are further extracted. The device performance includes gate capacitance, current-voltage relationship curve, carrier distribution, or potential distribution, and the impact of residual stress in the post-process of core particle integration on device performance is evaluated.

6. The virtual testing and system-process collaborative optimization method for the influence of residual stress of chip integration back-end process on transistor device performance according to claim 1, characterized in that: Adjust the process parameters based on the evaluation results of the impact of residual stress in the back-end process of chip integration on device performance, or further select process parameters that optimize the performance of chiplets, integrated circuits and transistor devices from multiple groups of process parameters to achieve system-technology coordinated optimization of chiplets.

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