Hardware-in-the-loop simulation model design method for high-voltage cascade energy storage system

Abstract

The invention discloses a high-voltage cascade energy storage system hardware-in-the-loop simulation model design method and simulation system, and the method comprises the steps: constructing a plurality of component simulation models needed in the hardware-in-the-loop simulation test process according to the hardware-in-the-loop simulation test content, and obtaining the time change characteristics of the parameters of the component simulation models; embedding the component simulation model into a large-step simulation model or a small-step simulation model based on the hardware-in-the-loop simulation test instruction and the time change characteristics of the parameters of the component simulation model; acquiring to-be-exchanged data between the large-step simulation model and the small-step simulation model; dividing the to-be-exchanged data into a plurality of groups according to time change characteristics of the to-be-exchanged data, and establishing a communication mechanism between the large-step simulation model and the small-step simulation model according to a grouping result; and performing hardware-in-the-loop simulation test, running the large-step simulation model and the small-step simulation model, and updating the step length of the large-step simulation model.

Description

Technical Field

[0001] The present invention belongs to the technical field of hardware-in-the-loop simulation of energy storage systems, and in particular relates to a hardware-in-the-loop simulation model design method and a simulation system for a high-voltage cascade energy storage system. Background Art

[0002] High-voltage direct-mounted cascade energy storage system is a new energy storage system technology developed in recent years. It can be directly connected to the medium-voltage power grid (6kV, 10kV, 35kV) without a transformer. High-voltage direct-mounted cascade energy storage system has significant advantages in energy storage converter conversion efficiency, large-capacity system cost, response time, single-machine power capacity, battery capacity utilization, and energy balance between battery clusters.

[0003] The high-voltage direct-mounted cascade energy storage system adopts the gentle idea of ​​energy storage converters and battery clusters, and rationally decomposes hundreds of thousands of battery cells and tens of megawatts of high-power converters of 100-megawatt energy storage power stations into energy storage modules composed of small-capacity battery clusters and energy storage converters that match their power. These energy storage modules (including battery clusters and energy storage converters) are connected in a cascade form, and the voltage reaches 6~35kV, so as to be directly connected to the medium-voltage power grid. The technology of one cluster one management, fault intelligent bypass, AC side series multi-level connection is adopted to realize the organization and management of massive battery cells in 100-megawatt energy storage power stations, realize the imbalance between battery clusters at the energy storage converter level, greatly reduce the circulation phenomenon of battery clusters, and effectively improve the safety of energy storage power stations, battery capacity utilization and access power quality.

[0004] In a high-voltage direct-mounted cascade energy storage system, each phase has several to hundreds of energy storage modules (the number is related to the voltage level) cascaded and directly connected to the grid through inductance. The number of energy storage modules in a three-phase high-voltage direct-mounted cascade energy storage system can reach hundreds, and the number of power devices can reach thousands. The opening time and time interval of these power devices are from a few microseconds to tens of microseconds. Currently, cascade energy storage modules are widely used. Figure 1 In the full-bridge topology shown, the system includes inductors (LA, LB, LC, etc.), switches (QF1, QL1), resistors (RA, RB, RC, etc.), and each energy storage module includes: power devices (Q1, Q2, Q3, Q4), inductors (L1), capacitors (C1), battery clusters (BAT), switches (K1, K2, K3, etc.). The power of high-voltage direct-mounted cascade energy storage systems is generally above the MW level, and the cost of the energy storage system is high (in millions of yuan). In addition, some operating performance requires special cooperation from the power grid. These factors make the actual testing cost and trial-and-error cost of cascade energy storage systems very high. The hardware-in-the-loop simulation technology that has emerged in recent years has become an important technical means to test the functions of cascade energy storage systems, verify the functions of the entire energy storage system, verify the control algorithm, and evaluate the impact of energy storage system access.

[0005] The hardware-in-the-loop simulation system mainly includes hardware-in-the-loop simulation equipment, signal collection circuit board and cascade energy storage control system. The three are connected by high-speed optical fiber and other communication connections. Typical applications include Figure 2 . Hardware-in-the-loop simulation equipment can use high-speed boards (FPGA boards), design the simulation algorithm logic required for the cascade energy storage system test into a model and run it on the FPGA board, and use hardware logic gates to implement the logic algorithm of the simulation model. The disadvantage is that the cost of FPGA equipment is relatively high. Hardware-in-the-loop simulation equipment can also use high-speed boards and combine them with slow boards (such as CPU boards). In the simulation algorithm logic required for the cascade energy storage system test, the slow-running part (such as the battery cluster and inductor in the energy storage module) establishes a simulation logic model (longer step simulation model) in the slow board; the fast-running part (such as the power device in the energy storage module, the network of the cascade energy storage system, etc.) establishes a simulation algorithm logic model (shorter step simulation model) in the high-speed board. The running time step of the simulation model with a longer step is generally in the range of 25~500us, and the time step of the simulation model with a shorter step is generally in the range of 0.1~5us. The two parts of the model need to coordinate and run synchronously, and exchange data with the time step of the simulation model with a longer step. During each step time of the simulation model with a longer step length, the simulation model with a shorter step length receives the data requiring interaction sent by the simulation model with a longer step length, and the simulation model with a longer step length receives the data requiring interaction sent by the simulation model with a shorter step length.

[0006] A large high-voltage direct-mounted cascade energy storage system includes hundreds of energy storage modules, each of which has hundreds of cells, several power devices, several capacitors, inductors, resistors and other electrical components. If the system of these components is designed into a model, the model will be very large and complex. If all these models are run on high-speed boards, the requirements for high-speed boards are very high, and multiple high-speed boards are often required to implement them, which greatly increases the cost; and for FPGA boards, the model design and development cycle is long. If a method combining a high-speed board with a slow board is used, the amount of data required to be exchanged between the model running on the high-speed board and the model running on the slow board is very large, and the data interaction time will be very long, affecting the operation of the simulation model. The commonly used solution in the prior art is to increase the communication bandwidth for data interaction or increase the running step size of the simulation model. However, both methods have certain disadvantages. The former will greatly increase the purchase cost and hardware design difficulty of the simulation equipment, while the latter will increase the time granularity of the simulation, affecting the simulation accuracy and reliability of the simulation model.

[0007] Aiming at the shortcomings of the existing FPGA board simulation test equipment being expensive and the long-step simulation model and short-step simulation model data interaction requiring a large amount of simulation step time during the operation of the FPGA board and CPU board combined simulation test equipment. According to the operation characteristics of the high-voltage direct-mounted cascade energy storage system, the present invention proposes a simulation model design method that reduces data interaction time, reduces simulation step length, and improves simulation effect. Summary of the invention

[0008] In order to overcome one or more of the above-mentioned technical defects, the present invention provides a method for designing a hardware-in-the-loop simulation model for a high-voltage cascade energy storage system, which reduces data interaction time, reduces simulation step size, and improves simulation effect.

[0009] In order to solve the above problems, the first aspect of the present invention provides a method for designing a hardware-in-the-loop simulation model of a high-voltage cascade energy storage system, comprising the steps of: Construct large-step-size simulation models and small-step-size simulation models; According to the hardware-in-the-loop simulation test content, build several component simulation models required in the hardware-in-the-loop simulation test process, and obtain the time variation characteristics of the component simulation model parameters; Based on the time-varying characteristics of hardware-in-the-loop simulation test instructions and component simulation model parameters, the component simulation model is embedded into a large-step simulation model or a small-step simulation model; Acquire the data to be exchanged between the large-step simulation model and the small-step simulation model, and analyze the time variation characteristics of the data to be exchanged; According to the time variation characteristics of the data to be exchanged, the data to be exchanged are divided into several groups, and a communication mechanism between the large-step simulation model and the small-step simulation model is established according to the grouping results; Perform hardware-in-the-loop simulation tests, run large-step simulation models and small-step simulation models, and update the step size of the large-step simulation model.

[0010] Furthermore, the acquisition of the time variation characteristics of the component simulation model parameters includes: Get the parameters of the component simulation model; Identify the data type of the parameter, obtain the time variation characteristic formula corresponding to the parameter data type, and analyze the data size of the parameter. The data type of the parameter includes analog quantity and switch state quantity. The time variation characteristic of the analog quantity is , , the time variation characteristic of the switch state quantity is , It is the shortest time for the switch state quantity to change.

[0011] Furthermore, the method further comprises the steps of: Based on the hardware performance of the hardware-in-the-loop simulation equipment and the time-varying characteristics of the parameters of the component simulation model, the first step size and the second step size are set, wherein the first step size is the simulation time step of the large-step simulation model, and the second step size is the simulation time step of the small-step simulation model. The first step size is smaller than the time-varying characteristics of the parameters of the component simulation model embedded in the large-step simulation model, and the second step size is smaller than the time-varying characteristics of the parameters of the component simulation model embedded in the small-step simulation model.

[0012] Furthermore, the analyzing the time variation characteristics of the data to be exchanged includes: Identify the data type of the data to be exchanged, where the data type includes analog quantity and switch state quantity. The time variation characteristics of the analog quantity are: , , the time variation characteristic of the switch state quantity is , It is the shortest time for the switch state quantity to change.

[0013] Further, the hardware-in-the-loop simulation test is performed, a large-step simulation model and a small-step simulation model are run, and the step size of the large-step simulation model is updated, including: Perform hardware-in-the-loop simulation tests, run large-step simulation models and small-step simulation models, and obtain the actual running time within each step in the large-step simulation model and the actual running time within each step in the small-step simulation model; Update the first step length according to the actual running time in each step length in the large-step simulation model and the actual running time in each step length in the small-step simulation model.

[0014] A second aspect of the present invention provides a high-voltage cascade energy storage system hardware-in-the-loop simulation system for implementing the above method, wherein the high-voltage cascade energy storage system hardware-in-the-loop simulation system comprises a hardware-in-the-loop simulation device, a signal receiving circuit board, and a cascade energy storage conversion control system, wherein the hardware-in-the-loop simulation device, the signal receiving circuit board, and the cascade energy storage conversion control system are connected by high-speed optical fiber communication, and the hardware-in-the-loop simulation device comprises a high-speed board and a slow board. The high-speed board is used to run the small-step simulation model, and the slow board is used to run the large-step simulation model. When performing hardware-in-the-loop simulation testing, the large-step simulation model and the small-step simulation model are run simultaneously, and data is exchanged between the high-speed board and the slow board.

[0015] Compared with the prior art, the present invention has the following beneficial effects: According to the operation characteristics of a high-voltage direct-mounted cascade energy storage system, the present invention discloses a method for designing a hardware-in-the-loop simulation model for a high-voltage cascade energy storage system, the steps of which include constructing a large-step simulation model and a small-step simulation model; constructing a number of component simulation models required in the hardware-in-the-loop simulation test process according to the hardware-in-the-loop simulation test content, and obtaining the time-varying characteristics of the component simulation model parameters; embedding the component simulation model into the large-step simulation model or the small-step simulation model based on the hardware-in-the-loop simulation test instructions and the time-varying characteristics of the component simulation model parameters; obtaining the data to be exchanged between the large-step simulation model and the small-step simulation model, and analyzing the time-varying characteristics of the data to be exchanged; dividing the data to be exchanged into a number of groups according to the time-varying characteristics of the data to be exchanged, and establishing a communication mechanism between the large-step simulation model and the small-step simulation model according to the grouping results; performing a hardware-in-the-loop simulation test, running the large-step simulation model and the small-step simulation model, and updating the step size of the large-step simulation model. By analyzing the time variation characteristics of the parameters of the component simulation model corresponding to the components of the high-voltage cascade energy storage system, the simulation models of each component are reasonably embedded in the large-step simulation model or the small-step simulation model, and the data to be exchanged are grouped according to the time requirements. Different communication mechanisms are used for different grouping situations. Data is exchanged according to the time required for time simulation, which reduces the number of data exchanges and the data exchange time, thereby reducing the communication bandwidth and equipment costs, and reducing the model running time, so as to reduce the time step of the large-step simulation model running in the slow board and improve the model accuracy and effectiveness. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The specific embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings, wherein: Figure 1 The cascade energy storage module of the full-bridge topology described in the background technology; Figure 2 The existing hardware-in-the-loop simulation system described in the background technology; Figure 3 This is a flow chart of the method for designing a hardware-in-the-loop simulation model for a high-voltage cascade energy storage system as described in Example 1. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0018] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0020] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0021] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0022] Example 1 This embodiment discloses a method for designing a hardware-in-the-loop simulation model for a high-voltage cascade energy storage system. Figure 3 , including the steps of: S1. Construct a large-step simulation model and a small-step simulation model, wherein the large-step simulation model is a simulation model with a longer simulation time step, and the small-step simulation model is a simulation model with a shorter simulation time step.

[0023] S2. According to the hardware-in-the-loop simulation test content, construct several component simulation models required in the hardware-in-the-loop simulation test process, and obtain the time variation characteristics of the component simulation model parameters.

[0024] According to the common components and hardware-in-the-loop simulation test instructions in the high-voltage cascade energy storage system, the components required in the hardware-in-the-loop simulation test process are obtained, and the corresponding component simulation model is constructed based on the characteristics of each component. At the same time, the power grid system is equivalent to a power grid source model and a disturbance source model.

[0025] In this embodiment, the step of obtaining the time variation characteristics of the component simulation model parameters includes: Get the parameters of the component simulation model. The parameters of the component simulation model include capacitor current, capacitor voltage, inductor current, inductor voltage, resistor current, resistor voltage, battery current, battery voltage, battery SOC, battery temperature, power electronic switch device conduction state, mechanical switch open and close state, grid source current, grid source voltage, grid source amplitude, grid source frequency, disturbance source current, disturbance source voltage, disturbance source amplitude and disturbance source frequency, etc.

[0026] Identify the data type of the parameter, obtain the time variation characteristic formula corresponding to the parameter data type, and analyze the data size of the parameter. The data type of the parameter includes analog quantity and switch state quantity. For the analog quantity, perform frequency domain analysis on it, and the time variation characteristic of the analog quantity is: , , if an analog quantity is composed of frequency domain quantities such as 1Hz, 50Hz, 100Hz, and 1000Hz, and the simulation test of this analog quantity focuses on frequencies below 1000Hz, then its maximum frequency in the frequency domain is 1000Hz. For the switch state quantity, analyze how long it will take for it to change, and the time change characteristic of the switch state quantity is , The shortest time for a switch state quantity to change. If a switch state quantity can remain unchanged for one minute or one hour, but the shortest change time is not less than 1 second, then the shortest change time is The data size of analog quantity is 16 bits, 32 bits or 64 bits. The specific size is determined by the data accuracy requirement. The higher the data accuracy requirement, the more bits are required. The data size of switch state quantity is 1 bit.

[0027] In this embodiment, the steps are also included: Based on the hardware performance of the hardware-in-the-loop simulation equipment and the time-varying characteristics of the parameters of the component simulation model, the first step length and the second step length are set, wherein the first step length is the simulation time step length of the large-step simulation model, and the second step length is the simulation time step length of the small-step simulation model. The first step length is smaller than the time-varying characteristics of the parameters of the component simulation model embedded in the large-step simulation model, and the second step length is smaller than the time-varying characteristics of the parameters of the component simulation model embedded in the small-step simulation model. Step length of the simulation model Time Variation Characteristics of Component Simulation Model Parameters At least one order of magnitude smaller, .

[0028] S3. Based on the time-varying characteristics of the hardware-in-the-loop simulation test instructions and the component simulation model parameters, each component simulation model is embedded into a large-step simulation model or a small-step simulation model.

[0029] S4. Obtain the data to be exchanged between the large-step simulation model and the small-step simulation model, and analyze the time variation characteristics of the data to be exchanged.

[0030] In this embodiment, analyzing the time variation characteristics of the data to be exchanged includes: Identify the data type of the data to be exchanged, where the data type includes analog quantity and switch state quantity. The time variation characteristics of the analog quantity are: , the time variation characteristic of the switch state quantity is , It is the shortest time for the switch state quantity to change.

[0031] S5. Divide the data to be exchanged into several groups according to the time variation characteristics of the data to be exchanged, and establish a communication mechanism between the large-step simulation model and the small-step simulation model according to the grouping results. For example, the data to be exchanged within each simulation time step is a group, the data to be exchanged within every two simulation time steps is a group, ..., the data to be exchanged within every n simulation time steps is a group, and specifically, n is determined according to actual needs.

[0032] According to the grouping results of the data to be exchanged, a communication mechanism is established between the large-step simulation model and the small-step simulation model. The grouping data of the data to be exchanged are one, two, ... n, and in each simulation time step, one of the above grouping numbers is exchanged, that is, corresponding to the grouping data: all grouping data, 1 / 2 grouping data, ..., 1 / n grouping data.

[0033] S6. Perform a hardware-in-the-loop simulation test, run a large-step simulation model and a small-step simulation model, and update the step size of the large-step simulation model.

[0034] In this embodiment, step S6 includes: Perform a hardware-in-the-loop simulation test, run the large-step simulation model and the small-step simulation model, repeat step S5, and obtain the actual running time within each step in the large-step simulation model and the actual running time within each step in the small-step simulation model.

[0035] According to the actual running time in each step of the large-step simulation model and the actual running time in each step of the small-step simulation model, the first step is updated so that the first and second step are as small as possible, while there is enough time to run the simulation and exchange data.

[0036] In the actual operation of the high-voltage direct-mounted cascade energy storage system, the relationship between the parameter changes of various components and time is not consistent. Some parameters change significantly within sub-microseconds, some parameters change significantly within microseconds, some parameters change significantly within tens or hundreds of microseconds, and some parameters are only observed to change within seconds, minutes, or even hours or days.

[0037] The present invention proposes a model design method for improving data exchange efficiency, reducing data exchange time, and thereby reducing the simulation time step of the model of the hardware-in-the-loop simulation test, thereby improving the model operation performance. According to the simulation requirements of the cascade energy storage system, the components required for the model design are statistically obtained and the corresponding component simulation models are constructed, and attention is paid to the parameters of the component simulation models in the hardware-in-the-loop simulation test. The time characteristics of the parameters and the hardware-in-the-loop simulation test requirements are analyzed, and the component simulation models are respectively assigned to simulation models with different time steps, and simulation models with different simulation time steps, namely, large-step simulation models and small-step simulation models, are constructed.

[0038] Analyze the parameter data that need to be exchanged for the simulation model operation with different simulation time steps and the time characteristics of the data to be exchanged, and determine the time requirements for data exchange. According to the data exchange time requirements, group the data that need to be exchanged: data that needs to be exchanged every 1 time step, data that needs to be exchanged every 2 time steps, …, data that needs to be exchanged every n time steps. Exchange data according to the exchange time requirements of each group: exchange all grouped data every 1 time step, exchange all data every 2 time steps (i.e., exchange 1 / 2 of all grouped data every time step), …, exchange all data every n time steps (i.e., exchange 1 / 2 of all grouped data every time step).

[0039] Test-run the simulation model to detect the actual running time of the large-step simulation model and the small-step simulation model within the time step, so as to adjust the simulation time step, data grouping results and communication mechanism of the two models, so that the simulation time step is as small as possible while having enough margin to ensure the reliable operation of the model.

[0040] Example 2 The present embodiment discloses a hardware-in-the-loop simulation system for a high-voltage cascade energy storage system, which is used to implement the method described in Example 1. The hardware-in-the-loop simulation system for the high-voltage cascade energy storage system includes a hardware-in-the-loop simulation device, a signal receiving circuit board, and a cascade energy storage current conversion control system. The hardware-in-the-loop simulation device, the signal receiving circuit board, and the cascade energy storage current conversion control system are connected by high-speed optical fiber communication. The hardware-in-the-loop simulation device includes a high-speed board and a slow board. The high-speed board is used to run a small-step simulation model, and the slow board is used to run a large-step simulation model. When performing a hardware-in-the-loop simulation test, the large-step simulation model and the small-step simulation model are run simultaneously, and data is exchanged between the high-speed board and the slow board.

[0041] The following takes the hardware-in-the-loop simulation model design of a 35kV-25MW-50MWh star-connected (three-phase total 192 energy storage modules, 64 energy storage modules per phase) cascade energy storage system as an example to illustrate: The high-speed board uses an FPGA board with a main frequency of 125MHz; the slow board uses an industrial computer (6-core 4.0GHz main frequency CPU. PCIe is used for communication between the high-speed board and the slow board. Each energy storage module includes 4 IGBT bridges, a capacitor group C, an inductor L, a cluster of batteries (240 cells), an input switch, a pre-charge circuit, a cooling water circuit, etc.

[0042] According to the common components and hardware-in-the-loop simulation test instructions in the high-voltage cascade energy storage system, the grid model, the switches connected to the grid model, the pre-charging circuit, the energy storage access inductor, the IGBTs in all energy storage modules and other component simulation models are designed, and embedded in the high-speed board for operation; the battery cluster Bat (240 cells), capacitor group C, inductor L, input switch, pre-charging circuit, cooling water circuit and other component simulation models in all energy storage modules are designed, and embedded in the slow board for operation.

[0043] Generally speaking, the simulation time step of the small-step simulation model in the FPGA board is set to no more than 0.5us, which can meet the hardware-in-the-loop simulation requirements of the high-voltage cascade energy storage system. The simulation time step of the large-step simulation model in the CPU board is generally 25~100us. For the CPU board, the smaller the simulation time step, the better the simulation effect; in this embodiment, the simulation time step of the large-step simulation model in the CPU board is initially set to 100us. And according to the actual running time of the simulation model, adjust the data grouping and communication mechanism to adjust the simulation time step of the simulation model in the CPU board to as small as possible.

[0044] Obtain the data to be exchanged between the large-step simulation model and the small-step simulation model: IGBT trigger pulse, capacitor bank voltage, current flowing to the IGBT bridge, battery cluster voltage, battery cluster SOC, battery cluster voltage SOC temperature extremes, switch control / feedback signals within the module, grid parameter signals, small disturbance parameter signals, and DA proportional bias parameters.

[0045] When using existing technology, the amount of data that needs to be exchanged for: ,in, The data exchanged within each simulation time step is: The data exchanged within every 2 simulation time steps is as follows... The data exchanged within every n simulation time steps.

[0046] Group the data to be exchanged and establish a communication mechanism (according to the simulation time step of the large-step simulation model in the CPU board): The small-step simulation model in the FPGA board needs to complete the exchange of data within each simulation time step: IGBT trigger pulse, switch control / feedback signal in the module.

[0047] The large-step simulation model in the CPU board requires the data to be exchanged within each simulation time step: capacitor bank voltage, current flowing to the IGBT bridge, and battery cluster current.

[0048] The data that needs to be exchanged within every 2 simulation time steps: power grid parameter signal, small disturbance parameter signal, and DA proportional bias parameter.

[0049] … The data that needs to be exchanged every 20 simulation time steps include: battery cluster voltage, battery cluster SOC, and the maximum and minimum values ​​of the voltage, SOC and temperature of the cells in the battery cluster.

[0050] When the method provided by the present invention is used, the amount of data to be exchanged is for: ,in, The data exchanged within each simulation time step is: The data exchanged within every 2 simulation time steps is as follows... The data exchanged within every n simulation time steps is now completed, and n is the data divided into n parts. At this time, the amount of data to be exchanged is reduced by about half compared to the amount of data to be exchanged when using the existing technology.

[0051] According to the above grouping results, a communication mechanism is established between the small-step simulation model in the FPGA board and the large-step simulation model in the CPU board, and a hardware-in-the-loop simulation test is performed. At this time, the running time of the small-step simulation model in the FPGA board is less than 0.3us, and the running time of the large-step simulation model in the CPU board is about 48.5us. The running time of the small-step simulation model on the FPGA board meets the simulation requirements, and the running time of the large-step simulation model on the CPU board is close to 50us, which meets the simulation requirements of running under 100us, and the time margin is sufficient. When the simulation time step is directly adjusted to 50us without adjusting the data grouping to be exchanged and the corresponding communication mechanism, since the simulation running time of the CPU board is very close to the simulation time step, the simulation model has a stability risk, so the simulation time step is adjusted to 50us, and the grouping results and communication mechanism are adjusted accordingly.

[0052] After adjusting the simulation time step to 50us: The data that needs to be exchanged within each simulation time step: IGBT trigger pulse, switch control / feedback signal within the module.

[0053] The data that needs to be exchanged every 2 simulation time steps: capacitor bank voltage, current flowing to the IGBT bridge, and battery cluster current.

[0054] The data that needs to be exchanged within every 4 simulation time steps: power grid parameter signal, small disturbance parameter signal, and DA proportional bias parameter.

[0055] … The data that needs to be exchanged every 40 simulation time steps include: battery cluster voltage, battery cluster SOC, and the maximum and minimum values ​​of the voltage, SOC and temperature of the cells in the battery cluster.

[0056] After the simulation time step is adjusted, the amount of data that needs to be exchanged for: ,in, The data exchanged within each simulation time step is: The data exchanged within every 2 simulation time steps is as follows... The data exchanged within every n simulation time steps is now completed, and n is the data divided into n parts. Compared with the last time, the amount of exchanged data required is reduced by about half.

[0057] A hardware-in-the-loop simulation test was performed by running a large-step simulation model and a small-step simulation model. The simulation running time of the FPGA board was less than 0.3us, and the simulation running time of the CPU board was less than 35us. At this time, the simulation model had enough time margin to keep the simulation time step at 50us.

[0058] For other specific implementation details, please refer to Example 1 and will not be repeated here.

[0059] The design of existing high-voltage cascade energy storage system hardware-in-the-loop simulation models usually adopts the following two common methods: 1. Design simulation models based on high-speed boards (such as FPGA boards). Models of all components in the high-voltage cascade energy storage system are designed on high-speed boards.

[0060] 2. Based on the combination of a high-speed board (such as an FPGA board) and a slow board (such as a CPU board), the simulation model in the high-speed board and the simulation model in the slow board reduce the data exchange time by increasing the communication bandwidth.

[0061] Compared with the above two methods, the simulation model design method proposed in the present invention analyzes the simulation requirements, analyzes the various components involved in the hardware-in-the-loop simulation test of the high-voltage cascade energy storage system, constructs the corresponding component simulation model, analyzes the time characteristics of the component simulation model (equivalent to analyzing the time characteristics of the component), and reasonably embeds each component simulation model into the simulation model with different simulation time steps on the high-speed board and the slow board. The data to be exchanged of the two models are grouped according to different exchange time requirements, different communication mechanisms are established for different groups, and data is exchanged according to the time required for time simulation, thereby reducing the number of data exchanges and reducing the data exchange time.

[0062] The high-speed board used for the hardware-in-the-loop simulation model of the high-voltage cascade energy storage system has good speed (short running time step), high cost, and long model development cycle of the board; the slow board used for the hardware-in-the-loop simulation model of the high-voltage cascade energy storage system has low cost but poor speed (long running time step, which becomes the shortcoming of simulation test performance). Compared with the existing hardware-in-the-loop simulation model design method, the hardware-in-the-loop simulation model design method proposed in the present invention allocates part of the component simulation model to the high-speed board (small step simulation model), which can greatly reduce the cost of the hardware-in-the-loop simulation equipment (board). And according to the time characteristics and requirements, the simulation models of various components are reasonably allocated to high-speed boards and slow boards. For component models that need to pay attention to microseconds / sub-microseconds during operation, such as power electronic switching devices and peripheral circuits (including power switching devices, cascade inductors, etc.), power grid models, power grid disturbance models, etc., they are arranged on high-speed boards (small step simulation models), and for component models that need to pay attention to tens of microseconds and longer during operation, such as batteries and their surrounding capacitors / inductors / resistance circuits, mechanical switches, etc., they are arranged on slow boards (large step simulation models). Grouping the data to be exchanged and establishing different communication mechanisms based on different grouped data greatly reduces data exchange time, communication bandwidth, and equipment costs, thereby reducing the model running time, reducing the time step of the running model in the slow board, and improving the accuracy and effectiveness of the model.

[0063] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Therefore, any modification, equivalent change and modification made to the above embodiment based on the technical essence of the present invention without departing from the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A method for designing a hardware-in-the-loop simulation model for a high-voltage cascade energy storage system, characterized in that: Includes steps: Construct large-step-size simulation models and small-step-size simulation models; According to the hardware-in-the-loop simulation test content, build several component simulation models required in the hardware-in-the-loop simulation test process, and obtain the time variation characteristics of the component simulation model parameters; Based on the time-varying characteristics of hardware-in-the-loop simulation test instructions and component simulation model parameters, the component simulation model is embedded into a large-step simulation model or a small-step simulation model; Acquire the data to be exchanged between the large-step simulation model and the small-step simulation model, and analyze the time variation characteristics of the data to be exchanged; According to the time variation characteristics of the data to be exchanged, the data to be exchanged are divided into several groups, and a communication mechanism between the large-step simulation model and the small-step simulation model is established according to the grouping results; Perform hardware-in-the-loop simulation tests, run large-step simulation models and small-step simulation models, and update the step size of the large-step simulation model.

2. The method for designing a hardware-in-the-loop simulation model for a high-voltage cascade energy storage system according to claim 1, characterized in that: The step of obtaining the time variation characteristics of the component simulation model parameters includes: Get the parameters of the component simulation model; Identify the data type of the parameter, obtain the time variation characteristic formula corresponding to the parameter data type, and analyze the data size of the parameter. The data type of the parameter includes analog quantity and switch state quantity. The time variation characteristic of the analog quantity is , the time variation characteristic of the switch state quantity is , It is the shortest time for the switch state quantity to change.

3. The method for designing a hardware-in-the-loop simulation model for a high-voltage cascade energy storage system according to claim 1, characterized in that: Also includes the steps: Based on the hardware performance of the hardware-in-the-loop simulation equipment and the time-varying characteristics of the parameters of the component simulation model, the first step size and the second step size are set, wherein the first step size is the simulation time step of the large-step simulation model, and the second step size is the simulation time step of the small-step simulation model. The first step size is smaller than the time-varying characteristics of the parameters of the component simulation model embedded in the large-step simulation model, and the second step size is smaller than the time-varying characteristics of the parameters of the component simulation model embedded in the small-step simulation model.

4. The method for designing a hardware-in-the-loop simulation model for a high-voltage cascade energy storage system according to claim 1, characterized in that: The analyzing the time variation characteristics of the data to be exchanged includes: Identify the data type of the data to be exchanged, where the data type includes analog quantity and switch state quantity. The time variation characteristics of the analog quantity are: , the time variation characteristic of the switch state quantity is , It is the shortest time for the switch state quantity to change.

5. The method for designing a hardware-in-the-loop simulation model for a high-voltage cascade energy storage system according to claim 3, characterized in that: The hardware-in-the-loop simulation test is performed, a large-step simulation model and a small-step simulation model are run, and the step size of the large-step simulation model is updated, including: Perform hardware-in-the-loop simulation tests, run large-step simulation models and small-step simulation models, and obtain the actual running time within each step in the large-step simulation model and the actual running time within each step in the small-step simulation model; Update the first step length according to the actual running time in each step length in the large-step simulation model and the actual running time in each step length in the small-step simulation model.

6. A high-voltage cascade energy storage system hardware-in-the-loop simulation system, used to implement the method described in any one of claims 1-5, wherein the high-voltage cascade energy storage system hardware-in-the-loop simulation system comprises a hardware-in-the-loop simulation device, a signal receiving circuit board, and a cascade energy storage conversion control system, wherein the hardware-in-the-loop simulation device, the signal receiving circuit board, and the cascade energy storage conversion control system are connected by high-speed optical fiber communication, and characterized in that: Hardware-in-the-loop simulation equipment includes high-speed boards and slow boards. The high-speed board is used to run the small-step simulation model, and the slow board is used to run the large-step simulation model. When performing hardware-in-the-loop simulation testing, the large-step simulation model and the small-step simulation model are run simultaneously, and data is exchanged between the high-speed board and the slow board.

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