Packaging substrate, warping optimization method thereof and related equipment

Abstract

The invention discloses a packaging substrate and a warping optimization method and related equipment thereof, a model of the packaging substrate comprises a plurality of wiring layers and a plurality of dielectric layers which are stacked, one dielectric layer is arranged between any two wiring layers, and the method comprises the following steps: responding to a warping optimization instruction; obtaining a first distance of a bare chip mounting area of the model of the packaging substrate, wherein the first distance is the maximum distance between the center of the bare chip mounting area and the boundary of the bare chip mounting area; determining a second distance based on the first distance and a preset size relationship between the first distance and the second distance, wherein the second distance is the maximum distance between the center of the first area of the model of the packaging substrate and the boundary of the first area; determining the boundary of the first area based on the second distance and the preset shape of the first area; and setting a region, located at the boundary of the first region, in the at least one wiring layer as an open region so as to break a stress conduction path of the wiring layer between the first region and other regions, and optimizing warping of the package substrate.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design, and in particular to a packaging substrate and a warpage optimization method and related equipment. Background Art

[0002] The package substrate is usually formed by laminating a wiring layer and a dielectric layer. However, because the thermal expansion coefficients of the wiring layer and the dielectric layer are different, the package substrate after lamination will be warped. Excessive warping will cause problems such as cold solder joints, bridges or short circuits on the package substrate, seriously affecting the reliability of the package substrate. Therefore, how to optimize the warping of the package substrate is one of the problems that technicians in this field need to solve urgently. Summary of the invention

[0003] The present application discloses a packaging substrate and a warpage optimization method and related equipment thereof to reduce the warpage of the packaging substrate.

[0004] In a first aspect, the present application discloses a method for optimizing the warpage of a packaging substrate, comprising: in response to a warpage optimization instruction, obtaining a first distance of a die mounting area of ​​a model of the packaging substrate, the first distance being the maximum distance between the center of the die mounting area and its boundary; the die mounting area is used to mount a die; the model of the packaging substrate is a model constructed by simulating the structure of the packaging substrate to be manufactured; the model of the packaging substrate comprises a plurality of wiring layers and a plurality of dielectric layers arranged in a stacked manner, and a dielectric layer is arranged between any two wiring layers; based on the first distance and a preset relationship between the first distance and the second distance, determining a second distance, the second distance being the maximum distance between the center of a first area of ​​the model of the packaging substrate and its boundary; the first area comprises the die mounting area; the center of the first area is the same as the center of the die mounting area; based on the second distance and a preset shape of the first area, determining the boundary of the first area; setting an area at the boundary of the first area in at least one of the wiring layers as an opening area to disconnect the stress conduction path of the wiring layer between the first area and other areas, optimizing the warpage of the model of the packaging substrate, and optimizing the warpage of the packaging substrate manufactured according to the model.

[0005] In this way, by setting the area located at the boundary of the first area in at least one wiring layer as an opening area, the stress conduction path of the wiring layer between the first area and other areas can be disconnected, the warping of the model of the packaging substrate can be optimized, and the warping of the packaging substrate made according to the model of the packaging substrate can be optimized.

[0006] In some embodiments of the present application, the shape of the first area includes circle, ellipse or square.

[0007] In some embodiments of the present application, it also includes: obtaining a preset boundary spacing; the boundary spacing is the spacing of the boundaries between any two adjacent areas; based on the boundary of the first area and the boundary spacing, determining the boundary from the second area to the Nth area of ​​the model of the packaging substrate; N is an integer greater than or equal to 2; from the first area to the Nth area, the latter area surrounds the former area; setting an area of ​​at least one of the wiring layers located at the boundary of any area from the second area to the Nth area as an open area to disconnect the stress conduction path of the wiring layer between the second area and the Nth area, thereby optimizing the warping of the model of the packaging substrate.

[0008] In this way, the stress conduction path between the third area and the second area can be disconnected, thereby preventing the warping at the corners and sides of the packaging substrate from being transmitted through the wire layer at the third area to the wire layer at the second area, and further preventing the warping from being transmitted through the wire layer at the second area to the wire layer at the bare chip mounting area, thereby preventing the warping from affecting the connection between the bare chip and the packaging substrate at the bare chip mounting area, and thereby preventing problems such as cold solder joints, bridging or short circuits on the packaging substrate.

[0009] In some embodiments of the present application, the further step includes: setting the sharp corner of the boundary of any region from the first region to the Nth region to be a rounded corner or a chamfered corner.

[0010] In this way, warping or spikes of the wiring layer caused by sharp corners can be reduced.

[0011] In some embodiments of the present application, the method further includes: setting at least one wiring layer in any area from the first area to the Nth area to be a grid-shaped wiring layer or a planar wiring layer.

[0012] In this way, the warpage of the package substrate can be optimized by adjusting the filling method of the wiring layer in any area.

[0013] In some embodiments of the present application, it also includes: setting the thickness of at least one wiring layer on the first side of the model close to the packaging substrate to a first thickness, and setting the thickness of at least one wiring layer away from the first side to a second thickness, and the second thickness is greater than the first thickness; the first side is a side of the model of the packaging substrate on which a bare chip can be installed; and / or, setting the thickness of at least one dielectric layer close to the first side to a third thickness, and setting the thickness of at least one dielectric layer away from the first side to a fourth thickness, and the fourth thickness is greater than the third thickness.

[0014] In this way, the warpage of the package substrate can be optimized by adjusting the thickness of the wiring layer and / or the dielectric layer.

[0015] In a second aspect, the present application discloses a computer device, comprising a memory and a processor; the memory is used to store instructions; the processor is used to execute the warpage optimization method of the packaging substrate as described in any of the above items according to the instructions stored in the memory.

[0016] In a third aspect, the present application discloses a computer-readable storage medium having stored thereon instructions for executing the warpage optimization method for a packaging substrate as described in any one of the above items.

[0017] In a fourth aspect, the present application discloses a packaging substrate, which includes a plurality of wiring layers and a plurality of dielectric layers arranged in a stacked manner, with a dielectric layer between any two wiring layers; at least one of the wiring layers has a first opening at the boundary of a first area; the first area includes a bare die mounting area; the center of the first area is the same as the center of the bare die mounting area; the bare die mounting area is used to mount a bare die; the first opening is used to disconnect the stress conduction path of the wiring layer between the first area and other areas, thereby optimizing the warping of the packaging substrate.

[0018] In this way, by providing a first opening at the boundary of the first area in at least one wiring layer, the stress conduction path between the wiring layer in the first area and other areas can be disconnected, thereby optimizing the warping of the model of the packaging substrate, and further optimizing the warping of the packaging substrate manufactured according to the model of the packaging substrate.

[0019] In some embodiments of the present application, the shape of the first area includes a circle, an ellipse or a square; and / or, at least one of the wiring layers has a second opening at the boundary of any area from the second area to the Nth area, and the second opening is used to disconnect the stress conduction path of the wiring layer between the second area and the Nth area, thereby optimizing the warping of the packaging substrate; and / or, the corner of the boundary of any area from the first area to the Nth area is a rounded corner or a chamfered corner; and / or, the wiring layer of any area from the first area to the Nth area is a grid-shaped wiring layer or a planar wiring layer; and / or, the thickness of at least one wiring layer close to the first side of the packaging substrate is a first thickness, and the thickness of at least one wiring layer away from the first side is a second thickness, and the second thickness is greater than the first thickness; the first side is a side of the packaging substrate on which a bare chip can be mounted; and / or, the thickness of at least one dielectric layer close to the first side is a third thickness, and the thickness of at least one dielectric layer away from the first side is a fourth thickness, and the fourth thickness is greater than the third thickness.

[0020] In this way, the warpage of the package substrate can be optimized by adjusting the shape of the first region, the number of regions, the pattern of the regions, the thickness of the wiring layer and / or the dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background technology, the drawings required for use in the embodiments of the present application or the background technology will be described below.

[0022] Figure 1 A schematic cross-sectional view of a chip packaging structure disclosed in an embodiment of the present application.

[0023] Figure 2 A schematic diagram of the cross-sectional structure of a packaging substrate disclosed in an embodiment of the present application.

[0024] Figure 3 This is a flow chart of a warpage optimization method for a packaging substrate model disclosed in an embodiment of the present application.

[0025] Figure 4 A schematic diagram of the planar structure of a model of a packaging substrate disclosed in an embodiment of the present application.

[0026] Figure 5 A schematic planar structural diagram of a model of another packaging substrate disclosed in an embodiment of the present application.

[0027] Figure 6 A schematic planar structural diagram of a model of another packaging substrate disclosed in an embodiment of the present application.

[0028] Figure 7 A schematic planar structural diagram of a model of another packaging substrate disclosed in an embodiment of the present application.

[0029] Figure 8 A schematic planar structural diagram of a model of another packaging substrate disclosed in an embodiment of the present application.

[0030] Fig. 9 A schematic planar structural diagram of a model of another packaging substrate disclosed in an embodiment of the present application.

[0031] Fig.10 It is a schematic diagram of the cross-sectional structure of a model of another packaging substrate disclosed in an embodiment of the present application. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0033] like Figure 1 As shown, Figure 1FIG. 1 is a schematic cross-sectional view of a chip packaging structure disclosed in an embodiment of the present application. The chip packaging structure includes a packaging substrate 11, a bare chip 12 and a packaging cover 13 located on one side of the packaging substrate 11, etc. Figure 2 As shown, Figure 2 The cross-sectional structure diagram of a package substrate disclosed in an embodiment of the present application, the package substrate 11 includes a plurality of wiring layers 111 and a plurality of dielectric layers 112 arranged in a stacked manner, and a dielectric layer 112 is arranged between any two wiring layers 111. Among them, the wiring layer 111 is usually a copper layer, and the core layer is a dielectric layer located at the core of the package substrate 11.

[0034] Each wiring layer 111 includes a wiring 1110, and the wirings 1110 of any two wiring layers 111 are electrically connected through a via 1111 that penetrates the dielectric layer 112 therebetween. In addition, the wiring 1110, the via 1111, and the first solder balls 113 and the second solder balls 114 located on both sides of the package substrate 11 respectively constitute a channel for electrically connecting the bare chip 12 and the printed circuit board.

[0035] Currently, most methods optimize the warpage of the package substrate 11 during processing by controlling the copper plating rate of the wiring layer 111, and optimize the warpage of the package substrate 11 during chip packaging by using jigs, etc., wherein the copper plating rate refers to the ratio of the copper plating area to the area of ​​the entire package substrate 11. However, since the warpage of the package substrate 11 is random, the above method cannot effectively optimize the warpage.

[0036] Based on this, the present application discloses a warping optimization scheme, which optimizes the warping of the model of the packaging substrate by disconnecting the stress conduction path of the wiring layer of the model of the packaging substrate, and manufactures the packaging substrate according to the optimization effect of the model of the packaging substrate to effectively optimize the warping of the packaging substrate.

[0037] As an optional implementation of the content disclosed in this application, the embodiment of this application discloses a method for optimizing the warpage of a packaging substrate, such as Figure 3 As shown, Figure 3 This is a flow chart of a warpage optimization method for a packaging substrate disclosed in an embodiment of the present application, the method comprising:

[0038] S101: In response to a warpage optimization instruction, obtaining a first distance of a die mounting area of ​​a model of a package substrate, the first distance being a maximum distance between a center of the die mounting area and a boundary thereof, the die mounting area being used to mount a die.

[0039] The model of the package substrate is a model constructed by simulating the structure of the package substrate to be manufactured. The structure of the model of the package substrate can be Figure 2The packaging substrates shown have the same structure, including a plurality of wiring layers and a plurality of dielectric layers stacked in layers, and a dielectric layer is disposed between any two wiring layers.

[0040] like Figure 4 As shown, Figure 4 The schematic diagram of the planar structure of a model of a packaging substrate disclosed in an embodiment of the present application, wherein the model of the packaging substrate includes a die mounting area A, which is an area in the packaging substrate for mounting a die. The first distance D1 is the maximum distance between the center of the die mounting area A and its boundary. Taking the die mounting area A as a square area as an example, the first distance D1 is half the length of the diagonal of the square area. Of course, in the embodiment of the present application, only the die mounting area A is a square area as an example for explanation, and it is not limited to this. In other embodiments, the die mounting area A can also be a rectangular area, etc.

[0041] It is understandable that after the model of the package substrate is designed using an integrated circuit design tool (such as EDA, etc.), various data of the model of the package substrate, such as the location and size of the bare die mounting area, will be stored in the design tool. After receiving the warpage optimization instruction sent by the user, the warpage optimization device of the model of the package substrate in the embodiment of the present application will respond to the warpage optimization instruction, obtain the data of the model of the package substrate from the design tool, and obtain the first distance of the bare die mounting area based on the data. Among them, the warpage optimization device of the model of the package substrate in the embodiment of the present application can be integrated in the design tool.

[0042] S102: Determine a second distance based on the first distance and a preset relationship between the first distance and the second distance, where the second distance is a maximum distance between a center of a first region of a model of a packaging substrate and a boundary thereof.

[0043] In the embodiment of the present application, the magnitude relationship between the first distance and the second distance is pre-set in the warpage optimization device of the package substrate model, for example, the second distance is preset to be 1.2 times the first distance. Based on this, the second distance can be calculated according to the acquired first distance and the preset magnitude relationship between the first distance and the second distance.

[0044] like Figure 5 As shown, Figure 5 It is a schematic diagram of the planar structure of another model of a package substrate disclosed in an embodiment of the present application, and the second distance D2 is the maximum distance between the center of the first area B1 of the model of the package substrate and its boundary, wherein the first area B1 includes the bare die mounting area A, or in other words, the bare die mounting area A is located in the first area B1, and the center of the first area B1 is the same as the center of the bare die mounting area A, such as point O. It should be noted that the first area B1 can be the same as the bare die mounting area A, or can be slightly larger than the bare die mounting area A.

[0045] S103: Determine a boundary of the first area based on the second distance and a preset shape of the first area.

[0046] In the embodiment of the present application, the shape of the first area is also set in advance in the warpage optimization device of the package substrate model, for example, the shape of the first area is set to be a square. Figure 5 As shown, taking the shape of the preset first area B1 as a square as an example, after calculating the second distance D2, the side length of the square can be calculated according to the second distance D2 and the square diagonal and area calculation formula, and then the boundary of the first area B1 can be determined. Of course, the present application is not limited to this. In other embodiments, the shape of the first area B1 can also be circular or elliptical, etc., which will not be repeated here.

[0047] S104: setting an area at the boundary of the first area in at least one wiring layer as an open area to disconnect the stress conduction path of the wiring layer between the first area and other areas, and optimizing the warping of the model of the packaging substrate to optimize the warping of the packaging substrate manufactured according to the model.

[0048] like Figure 6 As shown, Figure 6 This is a schematic diagram of the planar structure of another packaging substrate model disclosed in an embodiment of the present application. After determining the boundary of the first area B1, the area at the boundary of the first area B1 in at least one wiring layer is set as an opening area K, or in other words, the wiring layer in the first area B1 in at least one wiring layer is disconnected from the wiring layer outside the first area B1, so as to disconnect the stress conduction path between the first area B1 and other areas of the wiring layer, optimize the warpage of the packaging substrate model, and then optimize the warpage of the packaging substrate made according to the packaging substrate model. Among them, the opening area K is not a blank area, which will be filled with the dielectric layer.

[0049] Typically, the die mounting area is located in the central area of ​​the package substrate, and the warping at the corners and sides of the package substrate will affect the connection between the die and the package substrate. Therefore, in the embodiment of the present application, by disconnecting the stress conduction path between the first area and other areas of at least one wiring layer, it is possible to prevent the warping at the corners and sides of the package substrate from being transmitted to the wire layer at the die mounting area through the wire layer at other areas, thereby preventing the warping generated during the processing and packaging process from affecting the connection between the die at the die mounting area and the package substrate, thereby preventing problems such as cold solder joints, bridges or short circuits on the package substrate.

[0050] In some embodiments of the present application, only the area at the boundary of the first area in one wiring layer can be set as an opening area. This wiring layer is the wiring layer closest to the bare die among all the wiring layers. This is because the warping of this wiring layer has the greatest impact on the connection between the bare die and the packaging substrate. Of course, the present application is not limited to this. In other embodiments, the area at the boundary of the first area in multiple wiring layers can also be set as an opening area. These multiple wiring layers can be arranged in sequence in the direction from close to far from the bare die.

[0051] It can be understood that the area at the boundary of the first area in the wiring layer closest to the bare chip can be set as an opening area first, and then the model of the packaging substrate can be simulated to analyze whether its warping is within an acceptable range. If it is not within the acceptable range, another wiring layer will be selected in the direction from close to away from the bare chip, and the area at the boundary of the first area in the other wiring layer will be set as an opening area, and then the simulation and selection will continue until the warping of the packaging substrate is within an acceptable range, or there are no wiring layers to be selected.

[0052] It should be noted that when presetting the size relationship between the first distance and the second distance, presetting the shape of the first area, and selecting the wiring layer, it is necessary to ensure that the boundary of the first area has no intersection with the routing and vias in the wiring layer, or in other words, it is necessary to ensure that the opening at the boundary of the first area does not affect the channel between the bare chip and the printed circuit board in the packaging substrate.

[0053] In some embodiments of the present application, at least one wiring layer can be divided into multiple regions, and the connection between the wiring layers of the multiple regions can be disconnected to further optimize the effect of warping. Specifically, a preset boundary spacing can be obtained, which is the spacing between the boundaries of any two adjacent regions. Based on the boundary of the first region and the boundary spacing, the boundary from the second region to the Nth region of the model of the packaging substrate is determined, and the region located at the boundary of any region from the second region to the Nth region in at least one wiring layer is set as an open region to disconnect the stress conduction path of the wiring layer between the second region and the Nth region, thereby optimizing the warping of the model of the packaging substrate. Wherein, N is an integer greater than or equal to 2, and the latter region from the first region to the Nth region surrounds the former region, and the centers of the first region to the Nth region are the same, for example, they are all point O.

[0054] like Figure 7 As shown, Figure 7The present invention is a schematic diagram of the planar structure of a model of another packaging substrate disclosed in an embodiment of the present application. At least one wiring layer can be divided into three areas. The second area B2 surrounds the first area B1, and the third area B3 surrounds the second area B2. The spacing between the boundaries of the second area B2 and the first area B1 is equal to the preset boundary spacing S, and the spacing between the boundaries of the third area B3 and the second area B2 is equal to the preset boundary spacing S. The area at the boundary between the second area B2 and the first area B1 is an opening area K, and the area at the boundary between the third area B3 and the second area B2 is also an opening area K, so that the stress conduction path between the third area B3 and the second area B2 can be disconnected, and the warping at the corners and sides of the packaging substrate is prevented from being transmitted to the wire layer at the second area B2 through the wire layer at the third area B3, and further, the warping is prevented from being transmitted to the wire layer at the bare chip mounting area through the wire layer at the second area B2, so that the warping can be prevented from affecting the connection between the bare chip and the packaging substrate at the bare chip mounting area, and further, the packaging substrate can be prevented from having problems such as cold solder joints, bridges or short circuits. The second area B2 and the first area B1 can reduce stress around the die, and the third area B3 can reduce stress of the package cover on the package substrate.

[0055] Of course, the present application is not limited to this, and in other embodiments, different wiring layers may be set to have different numbers of opening areas according to requirements. For example, one wiring layer is set to have an opening area only at the boundary of the first area, and another wiring layer is set to have an opening area at the boundary of both the first area and the second area.

[0056] In other embodiments, the boundary distances between different regions can be set as required. For example, the preset boundary distance between the third region and the second region can be set to S1, the preset boundary distance between the second region and the first region can be set to S1, and S1 is greater than S2.

[0057] In other embodiments, the area sizes may be preset to determine the area boundaries. For example, the preset size of the first area is 18 mm×18 mm, the size of the second area is 27 mm×27 mm, and the size of the third area is 40 mm×40 mm, then the boundaries of the first area, the second area, and the third area may be determined according to these sizes.

[0058] Similarly, the area at the boundary of the first area in at least one wiring layer can be set as an opening area first, and then the model of the packaging substrate can be simulated to analyze whether its warping is within an acceptable range. If it is not within the acceptable range, the area at the boundary of the second area in at least one wiring layer can be set as an opening area, and then the simulation and setting are continued until the warping of the packaging substrate is within an acceptable range, or there are no wiring layers that can be set.

[0059] On this basis, in some embodiments of the present application, the sharp corners of the boundaries of any region from the first region to the Nth region may be rounded or chamfered. Because the stress at the sharp corners is more concentrated, the wiring layer at the sharp corners is prone to warping or spikes, etc. Therefore, in order to reduce the warping or spikes of the wiring layer, the sharp corners of the boundaries of any region from the first region to the Nth region may be rounded or chamfered. Figure 8 As shown, Figure 8 This is a schematic diagram of the planar structure of a model of another packaging substrate disclosed in an embodiment of the present application, in which the sharp corners of the boundaries of any area from the first area B1 to the third area B3 can be set to be rounded or chamfered.

[0060] In some embodiments of the present application, at least one wiring layer in any area from the first area to the Nth area can also be set as a grid-shaped wiring layer or a planar wiring layer. Because the copper plating rate of the grid-shaped wiring layer is small, the warping caused by thermal expansion is small. However, considering factors such as packaging technology and design convenience, it can also be set as a planar wiring layer.

[0061] like Fig. 9 As shown, Fig. 9 This is a schematic diagram of the planar structure of a model of another packaging substrate disclosed in an embodiment of the present application, in which at least one wiring layer of the second area B2 can be set as a grid-shaped wiring layer, and at least one wiring layer of the first area B1 and the third area B3 can be set as a planar wiring layer.

[0062] Likewise, it is possible to determine which wiring layers are to be set as grid-shaped wiring layers and which wiring layers are to be set as planar wiring layers based on the simulation results of the model of the package substrate.

[0063] Because the thickness of the wiring layer and the dielectric layer will affect the warping of the package substrate, the warping of the package substrate can be optimized by adjusting the thickness of the wiring layer and / or the dielectric layer. In some embodiments of the present application, the thickness of at least one wiring layer on the first side of the model close to the package substrate can be set to a first thickness, and the thickness of at least one wiring layer away from the first side can be set to a second thickness, and the second thickness is greater than the first thickness; the first side is the side of the model of the package substrate where the bare die can be mounted; and / or, the thickness of at least one dielectric layer close to the first side is set to a third thickness, and the thickness of at least one dielectric layer away from the first side is set to a fourth thickness, and the fourth thickness is greater than the third thickness.

[0064] like Fig.10 As shown, Fig.10This is a schematic cross-sectional structure diagram of another model of a package substrate disclosed in an embodiment of the present application, wherein the thickness of the first wiring layer 101 close to the first side C1 is the first thickness d1, the thickness of the m-th wiring layer 102 away from the first side C1 is the second thickness d2, d2 is greater than d1, the thickness of the first dielectric layer 201 close to the first side C1 is the third thickness d3, the thickness of the m-th dielectric layer 202 away from the first side C1 is the fourth thickness d4, d4 is greater than d3. In other words, the warpage of the package substrate can be optimized by reducing the thickness of the wiring layer and / or dielectric layer between the core layer and the first side C1.

[0065] Of course, the present application is not limited to this. In other embodiments, the thickness of the wiring layer and / or the dielectric layer on the other side of the core layer may be adjusted to optimize the warping of the package substrate. In other embodiments, the thickness of the wiring layer and / or the dielectric layer on both sides of the core layer may be adjusted to optimize the warping of the package substrate.

[0066] As another optional implementation of the content disclosed in this application, the embodiment of this application also discloses a packaging substrate, referring to Figure 2 The package substrate includes a plurality of wiring layers 111 and a plurality of dielectric layers 112 stacked in layers, and there is a dielectric layer 112 between any two wiring layers 111. Figure 6 At least one wiring layer 111 has a first opening such as an opening area K at the boundary of the first area B1, the first area B1 includes a bare die mounting area A, the center of the first area B1 is the same as the center of the bare die mounting area A, the bare die mounting area A is used to mount the bare die, and the first opening such as the opening area K is used to disconnect the stress conduction path of the wiring layer 11 between the first area B1 and other areas, thereby optimizing the warping of the packaging substrate.

[0067] In some embodiments of this application, reference Figure 6 The shape of the first area B1 is a square. Of course, the present application is not limited to this. In other embodiments, the shape of the first area B1 can also be a circle, an ellipse or a square.

[0068] In some embodiments of the present application, at least one wiring layer has a second opening at the boundary of any region from the second region to the Nth region, and the second opening is used to disconnect the stress conduction path between the second region and the Nth region of the wiring layer to optimize the warpage of the package substrate. Figure 7At least one wiring layer has a second opening such as an opening area K at the boundary of the second area B2 or the third area B3 to disconnect the stress conduction path between the third area B3 and the second area B2, thereby preventing the warping at the corners and sides of the packaging substrate from being transmitted to the wire layer at the second area B2 through the wire layer at the third area B3, and further preventing the warping from being transmitted to the wire layer at the die mounting area through the wire layer at the second area B2, thereby preventing the warping from affecting the connection between the die and the packaging substrate at the die mounting area, and thereby preventing problems such as cold solder joints, bridges or short circuits on the packaging substrate.

[0069] In some embodiments of the present application, the corners of the boundaries of any region from the first region to the Nth region are rounded or chamfered. Figure 8 The sharp corners of the boundaries of any area from the first area B1 to the third area B3 are set to be rounded or chamfered to reduce warping or spikes of the wiring layer caused by the sharp corners.

[0070] In some embodiments of the present application, in the first region to the Nth region, the wiring layer of any region is a grid-shaped wiring layer or a plane-shaped wiring layer. Fig. 9 At least one wiring layer of the second area B2 is set as a grid-shaped wiring layer, and at least one wiring layer of the first area B1 and the third area B3 is set as a plane-shaped wiring layer.

[0071] In some embodiments of the present application, the thickness of at least one wiring layer close to the first side of the packaging substrate is a first thickness, the thickness of at least one wiring layer away from the first side is a second thickness, the second thickness is greater than the first thickness, the first side is a side of the packaging substrate on which the bare chip can be mounted, and / or, the thickness of at least one dielectric layer close to the first side is a third thickness, the thickness of at least one dielectric layer away from the first side is a fourth thickness, and the fourth thickness is greater than the third thickness, so as to optimize the warping of the packaging substrate by adjusting the thickness of the wiring layer and / or the dielectric layer.

[0072] refer to Fig.10 , the thickness of the first wiring layer 101 close to the first side C1 is the first thickness d1, the thickness of the m-th wiring layer 102 away from the first side C1 is the second thickness d2, d2 is greater than d1, the thickness of the first dielectric layer 201 close to the first side C1 is the third thickness d3, the thickness of the m-th dielectric layer 202 away from the first side C1 is the fourth thickness d4, d4 is greater than d3. In other words, the warpage of the package substrate can be optimized by reducing the thickness of the wiring layer and / or dielectric layer between the core layer and the first side C1.

[0073] As another optional implementation of the contents disclosed in the present application, an embodiment of the present application further discloses a computer device, including a memory and a processor; the memory is used to store instructions; the processor is used to execute the warpage optimization method of the model of the packaging substrate disclosed in any of the above embodiments according to the instructions stored in the memory.

[0074] As another optional implementation of the contents disclosed in the present application, an embodiment of the present application further discloses a computer-readable storage medium on which instructions for executing the warpage optimization method of the model of the packaging substrate disclosed in any of the above embodiments are stored.

[0075] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this specification can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0076] As another optional implementation of the contents disclosed in the present application, an embodiment of the present application further discloses a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the warpage optimization method of the model of the packaging substrate disclosed in any of the above embodiments.

[0077] The computer program product may be written in any combination of one or more programming languages ​​to write program codes for performing the operations of the embodiments of the present application, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" language or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0078] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0079] The above embodiments only express several implementation methods of this specification, and the descriptions are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of this specification, which all belong to the protection scope of this specification. Therefore, the protection scope of the patent of this specification shall be based on the attached claims.

Claims

1. A method for optimizing the warpage of a packaging substrate, characterized in that: include: In response to the warpage optimization instruction, a first distance of a die mounting area of ​​a model of a package substrate is obtained, wherein the first distance is a maximum distance between a center of the die mounting area and a boundary thereof; the die mounting area is used to mount a die; the model of the package substrate is a model constructed by simulating the structure of a package substrate to be manufactured; the model of the package substrate includes a plurality of wiring layers and a plurality of dielectric layers stacked in layers, and a dielectric layer is disposed between any two wiring layers; Based on the first distance and a preset relationship between the first distance and the second distance, a second distance is determined, where the second distance is a maximum distance between a center of a first area of ​​the model of the package substrate and a boundary thereof; the first area includes the die mounting area; and the center of the first area is the same as the center of the die mounting area; Determine a boundary of the first area based on the second distance and a preset shape of the first area; An area at the boundary of the first area in at least one of the wiring layers is set as an open area to disconnect the stress conduction path of the wiring layer between the first area and other areas, thereby optimizing the warping of the model of the packaging substrate and optimizing the warping of the packaging substrate made according to the model.

2. The method according to claim 1, characterized in that The shape of the first area includes circle, ellipse or square.

3. The method according to claim 1 or 2, characterized in that: Also includes: Obtaining a preset boundary spacing; the boundary spacing is the spacing between the boundaries of any two adjacent regions; Based on the boundary of the first region and the boundary spacing, determine the boundary from the second region to the Nth region of the model of the packaging substrate; N is an integer greater than or equal to 2; among the first region to the Nth region, the latter region surrounds the former region; An area of ​​at least one of the wiring layers located at a boundary of any area from the second area to the Nth area is set as an open area to disconnect the stress conduction path of the wiring layer between the second area and the Nth area, thereby optimizing the warping of the model of the packaging substrate.

4. The method according to claim 3, characterized in that: Also includes: The sharp corner of the boundary of any region from the first region to the Nth region is set to be rounded or chamfered.

5. The method according to claim 3, characterized in that: Also includes: At least one wiring layer in any one of the first region to the Nth region is set as a grid-shaped wiring layer or a plane-shaped wiring layer.

6. The method according to claim 1, characterized in that Also includes: The thickness of at least one wiring layer on a first side of the model close to the package substrate is set to a first thickness, and the thickness of at least one wiring layer away from the first side is set to a second thickness, wherein the second thickness is greater than the first thickness; the first side is a side of the model of the package substrate on which a bare die can be mounted; and / or, The thickness of at least one dielectric layer close to the first side is set to a third thickness, and the thickness of at least one dielectric layer far from the first side is set to a fourth thickness, wherein the fourth thickness is greater than the third thickness.

7. A computer device, characterized in that: including memory and processor; The memory is used to store instructions; The processor is used to execute the warpage optimization method for the packaging substrate according to any one of claims 1 to 6 according to the instructions stored in the memory.

8. A computer-readable storage medium, characterized in that: Instructions for executing the warpage optimization method for a packaging substrate as claimed in any one of claims 1 to 6 are stored thereon.

9. A packaging substrate, characterized in that: The packaging substrate comprises a plurality of wiring layers and a plurality of dielectric layers stacked in layers, and there is a dielectric layer between any two wiring layers; At least one of the wiring layers has a first opening at the boundary of the first area; the first area includes a bare die mounting area; the center of the first area is the same as the center of the bare die mounting area; the bare die mounting area is used to mount a bare die; the first opening is used to disconnect the stress conduction path of the wiring layer between the first area and other areas, thereby optimizing the warping of the packaging substrate.

10. The packaging substrate according to claim 9, characterized in that: The shape of the first region includes a circle, an ellipse or a square; and / or at least one of the wiring layers has a second opening at a boundary of any region from the second region to the Nth region, and the second opening is used to disconnect the stress conduction path of the wiring layer between the second region and the Nth region, thereby optimizing the warping of the package substrate; And / or, the corners of the boundaries of any region from the first region to the Nth region are rounded or chamfered; and / or, the wiring layer of any region from the first region to the Nth region is a grid-shaped wiring layer or a planar wiring layer; and / or, the thickness of at least one wiring layer close to the first side of the packaging substrate is a first thickness, and the thickness of at least one wiring layer away from the first side is a second thickness, and the second thickness is greater than the first thickness; the first side is a side of the packaging substrate on which a bare chip can be mounted; and / or, the thickness of at least one dielectric layer close to the first side is a third thickness, and the thickness of at least one dielectric layer away from the first side is a fourth thickness, and the fourth thickness is greater than the third thickness.

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