Artificial intelligence chip realized by adopting analog circuit and calculation and control method thereof

Abstract

According to the artificial intelligence chip realized by adopting the analog circuit and the calculation and control method thereof provided by the invention, an analog circuit such as an operational amplifier is utilized to realize a neuron function, a neural network calculation input parameter signal is converted into an analog signal, and a weighted value corresponding to the convolution operation of a neuron is converted into an impedance value for operation; the internal impedance value is adjusted by controlling the on-off state of an MOS tube connected with the impedance in parallel in the impedance matching module, so that the weighted value corresponding to each neuron is adjusted, and finally, the convolution operation function of the neuron is realized through the multiplication and addition operation module. The artificial intelligence chip can realize multiplication and addition operation between a plurality of analog signals and weighted values in one time node, and one-by-one calculation is not needed, so that the calculation efficiency is improved.

Description

Technical Field

[0001] The present invention belongs to the field of artificial intelligence, and specifically relates to an artificial intelligence chip implemented by an analog circuit and a calculation and control method thereof. Background Art

[0002] Currently, almost all artificial intelligence computing uses models based on neural networks: for example, GPT (artificial intelligence model) is a neural network based on the Transformer model, while LSTM (Long Short-Term Memory Network) and RNN (Recurrent Neural Network) are based on recurrent structures. The simplest neural network can be described by the perceptron model, see Figure 1 , the output o1 = x1*u1+x2*u2+x3*u3, is the sum of multiple binomial products, similar to matrix calculations and convolution operations. In practical neural networks, especially large models such as GPT, the number of neuron nodes and connections is very large, and they are divided into multiple layers, with connections of different weights between multiple neurons. For large models that need to process hundreds of billions or even trillions of parameters, the number of multiplication and addition operations required to perform each task may reach more than a trillion times.

[0003] The NPU (neural network processor) / GPU (graphics processor) based on digital circuits are all limited by the von Neumann architecture, and the basic components include an operator, a controller, a memory, and input and output devices. Every time a neural network is calculated, data needs to be read from the memory and input into the calculation module. After the calculation is completed, the calculation result is stored in the memory. Take the convolution operation of two 3*3 matrices as an example: 18 data need to be read, 27 multiplications and 27 additions are performed, and 9 data are stored. The reading and storage of data consumes a lot of time. When the number of neural nodes is very large, a lot of multiplication and addition operations need to be performed, which indirectly causes data access to take up more computing time. Summary of the invention

[0004] The present invention provides an artificial intelligence chip implemented by an analog circuit and a calculation and control method thereof, which realizes convolution operation through the analog circuit and improves the speed of convolution operation.

[0005] The present invention discloses an artificial intelligence chip implemented by an analog circuit, comprising:

[0006] An input holding and selection module outputs a preselected analog signal to an input channel selection module and an impedance output channel selection module;

[0007] An input channel selection module inputs the plurality of pre-selected analog signals into a plurality of impedance matching modules, wherein any of the pre-selected analog signals is correspondingly output to at least one impedance matching module;

[0008] An impedance matching module receives the preselected analog signal, adjusts the internal impedance value according to the weighted value corresponding to the preselected analog signal, and outputs the impedance value to the impedance output channel selection module;

[0009] An impedance output channel selection module, outputting the plurality of impedance values ​​to a plurality of multiplication-addition operation modules, wherein at least one impedance value and a preselected analog signal corresponding to the impedance value are output together to any multiplication-addition operation module;

[0010] The multiplication and addition operation module is used to perform multiplication and addition operations on the preselected analog signal and the impedance value corresponding to the preselected analog signal.

[0011] Furthermore, it also includes: an output channel selection module, which is used to use the multiplication and addition operation results as the input signal of the next round of convolution operation, or output the multiplication and addition operation results.

[0012] Furthermore, the impedance matching module, the impedance output channel selection module and the output channel selection module are all array switch matrices.

[0013] Further, it also includes: a control module for controlling each input holding and selection module to store a plurality of analog signals and output a preselected analog signal;

[0014] The control module is also used to control the input channel selection module to simultaneously output a plurality of the analog signals to a corresponding plurality of impedance matching modules;

[0015] The control module is also used to control each of the impedance matching modules to adjust the internal impedance value according to the weighted value corresponding to the preselected analog signal;

[0016] The control module is also used to control the matching connection between each impedance value and each preselected analog signal, and simultaneously input multiple impedance values ​​and the preselected analog signals corresponding to the impedance values ​​into corresponding multiplication and addition operation modules.

[0017] Further, the input holding and selection module includes:

[0018] a first operational amplifier;

[0019] a plurality of analog signal input paths connected to the first input terminal of the first operational amplifier;

[0020] Any of the analog signal input paths includes a first MOS transistor, a second MOS transistor and a signal holding capacitor;

[0021] The input end of the analog signal input path is connected to the source end of the first MOS tube, the drain end of the first MOS tube is connected to one end of a signal holding capacitor, and the gate end of the first MOS tube is connected to the control module; one end of the signal holding capacitor is also connected to the source end of the second MOS tube, the drain end of the second MOS tube is connected to the input end of the first operational amplifier, and the gate end of the second MOS tube is connected to the control module; the other end of the signal holding capacitor is connected to the other end of the signal holding capacitor in the remaining analog signal input paths and then grounded.

[0022] Furthermore, the impedance matching module includes:

[0023] n resistors connected in series in sequence; and a third MOS tube connected in parallel to the resistors; wherein n is an integer greater than 1.

[0024] Further, the multiplication-addition operation module includes: a second operational amplifier and a feedback resistor;

[0025] The positive input terminal of the second operational amplifier is connected to the plurality of input paths;

[0026] The analog signal and the impedance value corresponding to the analog signal are input into the second operational amplifier through the input path, a feedback resistor is connected between the positive input terminal and the output terminal of the second operational amplifier; the negative input terminal of the second operational amplifier is grounded; and the output terminal of the second operational amplifier outputs the multiplication and addition calculation result.

[0027] The present invention also discloses an artificial intelligence calculation and control method implemented by analog circuits, the method comprising:

[0028] Output multiple pre-selected analog signals within preset time nodes;

[0029] According to the number and size of the weighted values ​​corresponding to the preselected analog signal, a corresponding number of impedance values ​​of different sizes are obtained;

[0030] After the preselected analog signal is matched with the impedance value, the preselected analog signal and the impedance value corresponding to the preselected analog signal are multiplied and added respectively to obtain a plurality of weighted values, and the plurality of weighted values ​​are summed.

[0031] Furthermore, the method also includes: before outputting a plurality of preselected analog signals within a preset time node, storing a plurality of analog signals simultaneously.

[0032] Furthermore, after performing multiplication and addition operations on the analog signal and the impedance value corresponding to the analog signal, the multiplication and addition operation result is used as the preselected analog signal to perform multiplication and addition operation again, or the multiplication and addition operation result is output.

[0033] Compared with the prior art, the present invention has at least the following technical effects:

[0034] In the present invention, analog circuits such as operational amplifiers are used to realize neuron functions, neuron parameter signals are converted into analog signals, and the weighted values ​​corresponding to the convolution operation of neurons are converted into impedance values ​​for operation. The internal impedance value is adjusted according to the weighted value of each signal by controlling the impedance matching module, thereby adjusting the weighted value corresponding to each neuron. Finally, the multiplication and addition operation module is used to realize the multiplication and addition operation between neurons, that is, the convolution operation of the neural network is realized. The above-mentioned artificial intelligence chip can realize the multiplication and addition operation between multiple analog signals and weighted values ​​within a time node without calculating them one by one, thereby improving the calculation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a schematic diagram of the structure of a neural network model in the prior art;

[0036] Figure 2 It is a schematic diagram of the structure of the input holding and selection module in the present invention;

[0037] Figure 3 is a schematic structural diagram of the input channel selection module in the present invention;

[0038] Figure 4 It is a schematic diagram showing the structure of the impedance matching module in the present invention;

[0039] Figure 5 This is a schematic structural diagram of the impedance output channel selection module in the present invention;

[0040] Figure 6 It is a schematic diagram of the structure of the multiplication and addition operation module in the present invention;

[0041] Figure 7 This is a schematic diagram of the structure of the output channel selection module in the present invention. DETAILED DESCRIPTION

[0042] The following is a description of an artificial intelligence chip implemented by analog circuits and its calculation and control method of the present invention in conjunction with a schematic diagram, which shows a preferred embodiment of the present invention. It should be understood that those skilled in the art can modify the present invention described herein and still achieve the beneficial effects of the present invention. Therefore, the following description should be understood as being widely known to those skilled in the art and not as a limitation of the present invention.

[0043] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in illustrating the purpose of the embodiments of the present invention.

[0044] Please refer to Figure 2-Figure 7 The artificial intelligence chip implemented by analog circuit includes at least: an input holding and selection module, an input channel selection module, an impedance matching module, an impedance output channel selection module and a multiplication and addition operation module.

[0045] Specifically, the input holding and selection module is used to output a preselected analog signal Vn to the input channel selection module and the impedance output channel selection module; the input channel selection module is used to receive multiple preselected analog signals V1-Vn output from multiple input holding and selection modules and then input the multiple preselected analog signals V1-Vn into multiple impedance matching modules, wherein any of the preselected analog signals Vn is correspondingly output to at least one impedance matching module; the impedance matching module is used to receive any of the preselected analog signals Vn, and adjust the internal impedance value according to the size of the weighted value corresponding to the preselected analog signal Vn; the impedance output channel selection module is used to input the multiple impedance values ​​R1-Rn into multiple multiplication and addition operation modules, wherein at least one of the impedance values ​​Rn and the preselected analog signal Vn corresponding to the impedance value Rn are output together to any multiplication and addition operation module; the multiplication and addition operation module is used to perform multiplication and addition operations on the preselected analog signal Vn and the impedance value Rn corresponding to the preselected analog signal Vn.

[0046] In this embodiment, the preselected analog signal Vn is selected according to the neuron model to be calculated, and no specific limitation is made here.

[0047] In this embodiment, analog circuits such as operational amplifiers are used to implement neuron functions, neuron parameter signals are converted into analog signals, and the weighted values ​​corresponding to the convolution operation of neurons are converted into impedance values ​​for operation. The internal impedance value is adjusted according to the weighted value of each signal by controlling the impedance matching module, and finally the multiplication and addition operation module is used to implement the multiplication and addition operation between neurons, that is, the convolution operation of the neural network is implemented. The above-mentioned artificial intelligence chip can implement the multiplication and addition operation between multiple analog signals and weighted values ​​within a time node without calculating them one by one, thereby improving the computing efficiency.

[0048] In this embodiment, a control module is also included, which is used to control the opening and closing of the input holding and selection module, the input channel selection module, the impedance matching module, the impedance output channel selection module and the multiplication and addition operation module within a preset time node.

[0049] In this embodiment, the number of input holding and selection modules is not specifically limited, for example, 1, 2, and 3. Each input holding and selection module has multiple analog signal input channels, which receive the original digital quantity Vin and perform digital-to-analog conversion through the input holding and selection module, or receive the calculation result Vin returned by the multiplication and addition operation module.

[0050] In a specific embodiment, please refer to Figure 2 , Figure 2 The figure shows a possible structure diagram of an input holding and selection module, which includes: a first operational amplifier U1; a plurality of analog signal input paths 1 connected to the first input end of the first operational amplifier U1; any of the analog signal input paths 1 includes a first MOS transistor M1, a second MOS transistor M2 and a signal holding capacitor C1; the input end of the analog signal input path 1 is connected to the source end of the first MOS transistor M1, the drain end of the first MOS transistor M1 is connected to one end of a signal holding capacitor C1, and the gate end of the first MOS transistor M1 is connected to a control module; one end of the signal holding capacitor C1 is also connected to the source end of the second MOS transistor M2, the drain end of the second MOS transistor M2 is connected to the input end of the first operational amplifier U1, and the gate end of the second MOS transistor M2 is connected to the control module; the other end of the signal holding capacitor C1 is connected to the other end of the signal holding capacitor C1 in the remaining analog signal input paths 1 and then grounded.

[0051] In the above specific embodiment, when the original digital quantity or the calculation result returned by the multiplication and addition operation module is input into the analog signal input path 1, the first MOS tube M1 in the analog signal input path 1 is closed to store energy, and the first MOS tube M1 is disconnected after the voltage stabilizes. When a preset analog signal needs to be output to participate in the calculation, the second MOS tube M2 in the corresponding analog signal input path 1 is controlled to be in a conducting state, and the analog signal is output to the input channel selection module after voltage following, wherein the magnitude of the analog signal Vn is the same as the magnitude of the voltage on the signal holding capacitor C1. In particular, multiple first MOS tubes M1 can be closed at the same time to input multiple analog signals at the same time and store energy, but an input holding and selection module can only control the output of one analog signal at a preset time node.

[0052] In this embodiment, the preset time node is not specifically limited and can be selected according to the specific calculation accuracy and the computing power of the circuit.

[0053] It can be understood that the number of the input holding and selection module, and the analog signal input paths 1 in the input holding and selection module are not specifically limited here, and can be selected according to the actual situation of the calculation amount and calculation accuracy. For example, when the calculation amount and calculation accuracy are large, multiple analog signal input paths are controlled to be connected.

[0054] In a specific embodiment, please refer to Figure 3 , the input channel selection module is an array switch matrix. The input line of the array switch matrix is ​​shown as I1-In, and the output of an input channel selection module can be connected to at least one input line; the output line is shown as Z1-Zn, and the input of an impedance matching module can be connected to at least one output line; a MOS switch is set at the intersection of the input line and the output line.

[0055] At any time point, by simultaneously turning on different MOS switches, multiple pre-selected analog signals V1-Vn can be controlled to be input into multiple impedance matching modules through multiple input lines.

[0056] In the above specific embodiment, the number of the array switch matrix is ​​not specifically limited, and is generally 1. If the amount of calculation or the calculation accuracy is large, multiple input channel selection modules can be set. The array switch matrix is ​​used to reduce the design cost on the basis of realizing that multiple pre-selected analog signals V1-Vn are input into multiple impedance matching modules at the same time.

[0057] Further, in a specific embodiment, the impedance matching module includes: n resistors Ry1-Ryn connected in series in sequence; and a third MOS tube M3 connected in parallel to the resistors; wherein n is an integer greater than or equal to 1; specifically, the source and drain of the third MOS tube M3 are connected in parallel at both ends of the resistor, and the gate of the third MOS tube is connected to the control module.

[0058] In this embodiment, by short-circuiting resistors of different resistance values ​​by the third MOS tube M3, multi-bit weight configuration can be achieved. It can be understood that the number of resistors Ry1-Ryn and the third MOS tube M3 can be determined according to the actual number of weight configuration bits required. For example, when the calculation accuracy is 16 bits, 16 impedances can be connected in series and 15 third MOS tubes M3 can be used for control.

[0059] In a specific embodiment, please refer to Figure 4 , the impedance matching module is composed of 8 resistors and 7 third MOS tubes M3, and each resistor satisfies the following relationship:

[0060] Ry8=2Ry7=4Ry6=8Ry5=16Ry4=32Ry3=64Ry2=128Ry1.

[0061] When a third MOS tube M3 is turned on, the impedance connected to it is short-circuited and is not included in the series resistance. For example, if the conduction relationship of the seven third MOS tubes M3 is 1010101 (where 1 represents conduction and 0 represents off), the total series impedance R=128R1+32R1+16R1+4R1+R1=181R1. All multiples of R1 except 0 can be obtained according to the working state combination of each third MOS tube M3. The weighted value of each signal participating in the multiplication and addition operation can be achieved by controlling the series impedance, and there are 256 possibilities, that is, one byte.

[0062] For further information, please refer to Figure 5 In a specific embodiment, the impedance output channel selection module is also a matrix switch. The input lines of the array switch matrix are shown as I1-In, and an input channel selection module can be connected to at least one input line; the output lines are shown as Z1-Zn, and a multiplication and addition operation module can be connected to one end of at least one output line, and the other end of the output line corresponds to a preset analog value Vn; a MOS switch is set at the intersection of the input line and the output line.

[0063] At a preset time node, different MOS switches are turned on according to the matching relationship between neurons and weights, and multiple pre-selected analog signals V1-Vn and corresponding weighted values ​​Vn are output.

[0064] Please refer to Figure 6 In a specific embodiment, the multiplication and addition operation module includes: a second operational amplifier U2 and a feedback resistor Rx.

[0065] Specifically, a plurality of preselected analog signals V1-Vn are respectively input to the positive input terminal of the second operational amplifier U2 through a plurality of input paths; a feedback resistor R is connected between the positive input terminal and the output terminal of the second operational amplifier U2. X ; The negative input terminal of the operational amplifier U2 is grounded.

[0066] In a specific embodiment, assuming that there are n analog signal inputs, and the corresponding impedance values ​​are R1 to Rn, the output signal voltage Von is: Von = V1*Rx / R1+V2*Rx / R2+…Vn*Rx / Rn. ​​Among them, Von is the total value of the multiplication and addition of multiple analog signals and the corresponding impedance values ​​(i.e., weights), V1 to Vn are the magnitudes of the 1st to nth analog signals, R1 to Rn are the impedance values ​​corresponding to the 1st to nth analog signals, and Rx is the resistance value of the feedback resistor.

[0067] It is understandable that the resistance of the feedback resistor can be adjusted according to calculation requirements, and no specific impedance value is limited here.

[0068] In this embodiment, the multiplication and addition operation unit can process multiple input signals at the same time, and multiply them with corresponding weighted values ​​and then add them up, thereby realizing parallel calculation and improving the calculation speed.

[0069] It is understandable that the number of the multiplication-addition operation unit and the number of input paths in the multiplication-addition operation unit are determined according to the amount of calculation and the calculation accuracy, and no specific limitation is made here.

[0070] Furthermore, in this embodiment, it also includes: an output channel selection module, which is used to return the multiplication and addition operation result output by the multiplication and addition operation module to the input holding and selection module, and the multiplication and addition operation result is used as the input signal of the next round of convolution operation; or output the multiplication and addition operation result, and after outputting the multiplication and addition operation result, execute an analog activation function or convert through ADC (analog-to-digital converter), digitize the result and hand it over to the digital processing module for further processing.

[0071] In a specific embodiment, please refer to Figure 7 , the output channel selection module is also an array switch matrix. The input lines of the array switch matrix are shown in the figure I1-In, and the output of a multiplication and addition operation module (that is, multiple output signal voltages Vo1-Von) can be connected to at least one input line; the output lines are shown in the figure Z1-Zn, and the output lines can be connected to other modules or the input end of the input holding and selection module; a MOS switch is set at the intersection of the input line and the output line.

[0072] Furthermore, in the present embodiment, the control module is specifically used to control the opening and closing of the first MOS tube and the second MOS tube in a plurality of input holding and selection modules, so as to realize the simultaneous storage of a plurality of analog signals and the output of a certain analog signal; it is also used to control the opening and closing of the third MOS tube M3 in the impedance matching module, so as to realize the configuration of weighted values ​​of different bits; it is also used to control the opening and closing of the MOS tubes in the three array switch matrices, so as to realize the connection between different analog signals and various impedances, as well as the connection selection of various impedance matching modules, various multiplication and addition operation modules, various input holding and selection modules or other modules.

[0073] In addition, the control module can also control the timing, for example, control any module to operate at any preset time node. In a specific embodiment, the control module sequentially controls the input holding and selection module, the input channel selection module, the impedance matching module, the impedance output channel selection module, the multiplication and addition operation unit and the output channel selection module to operate at different preset time nodes, thereby realizing a complete neuron calculation process. In this embodiment, different timing control methods and the time used to complete a complete neuron calculation process can be selected according to actual conditions.

[0074] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. An artificial intelligence chip implemented using analog circuits, characterized in that: include: An input holding and selection module outputs a preselected analog signal to an input channel selection module and an impedance output channel selection module; An input channel selection module inputs the plurality of pre-selected analog signals into a plurality of impedance matching modules, wherein any of the pre-selected analog signals is correspondingly output to at least one impedance matching module; An impedance matching module receives the preselected analog signal, adjusts the internal impedance value according to the weighted value corresponding to the preselected analog signal, and outputs the impedance value to the impedance output channel selection module; An impedance output channel selection module, outputting the plurality of impedance values ​​to a plurality of multiplication-addition operation modules, wherein at least one impedance value and a preselected analog signal corresponding to the impedance value are output together to any multiplication-addition operation module; The multiplication and addition operation module is used to perform multiplication and addition operations on the preselected analog signal and the impedance value corresponding to the preselected analog signal.

2. The artificial intelligence chip implemented by analog circuit according to claim 1, characterized in that: Also includes: The output channel selection module is used to use the multiplication and addition operation result as the input signal of the next round of convolution operation, or to output the multiplication and addition operation result.

3. The artificial intelligence chip implemented by analog circuit according to claim 2, characterized in that: The impedance matching module, the impedance output channel selection module and the output channel selection module are all array switch matrices.

4. The artificial intelligence chip implemented by analog circuit according to claim 2, characterized in that: Also includes: A control module, used for controlling each input holding and selection module to store a plurality of analog signals and output a preselected analog signal; The control module is also used to control the input channel selection module to simultaneously output a plurality of the analog signals to a corresponding plurality of impedance matching modules; The control module is also used to control each of the impedance matching modules to adjust the internal impedance value according to the weighted value corresponding to the preselected analog signal; The control module is also used to control the matching connection between each impedance value and each preselected analog signal, and simultaneously input multiple impedance values ​​and the preselected analog signals corresponding to the impedance values ​​into corresponding multiplication and addition operation modules.

5. The artificial intelligence chip implemented by analog circuit according to claim 4, characterized in that: The input holding and selection module comprises: An operational amplifier, a signal holding capacitor, a first MOS tube and a second MOS tube; a plurality of analog signal input paths connected to the first input terminal of the first operational amplifier; Any of the analog signal input paths includes a first MOS transistor, a second MOS transistor and a signal holding capacitor; The input end of the analog signal input path is connected to the source end of the first MOS tube, the drain end of the first MOS tube is connected to one end of a signal holding capacitor, and the gate end of the first MOS tube is connected to the control module; one end of the signal holding capacitor is also connected to the source end of the second MOS tube, the drain end of the second MOS tube is connected to the input end of the first operational amplifier, and the gate end of the second MOS tube is connected to the control module; the other end of the signal holding capacitor is connected to the other end of the signal holding capacitor in the remaining analog signal input paths and then grounded.

6. The artificial intelligence chip implemented by analog circuit according to claim 4, characterized in that: The impedance matching module comprises: n resistors connected in series in sequence; and n third MOS tubes connected in parallel to the n resistors; wherein n is an integer greater than 1; The source and drain of the third MOS tube are connected in parallel at two ends of the resistor, and the gate of the third MOS tube is connected to the control module.

7. The artificial intelligence chip implemented by analog circuit according to claim 1, characterized in that: The multiplication and addition operation module includes: a second operational amplifier and a feedback resistor; The positive input terminal of the second operational amplifier is connected to the plurality of input paths; The analog signal and the impedance value corresponding to the analog signal are input into the second operational amplifier through the input path, a feedback resistor is connected between the positive input terminal and the output terminal of the second operational amplifier; the negative input terminal of the second operational amplifier is grounded; and the output terminal of the second operational amplifier outputs the multiplication and addition operation result.

8. An artificial intelligence calculation and control method implemented by analog circuit, characterized in that: The method comprises: Output multiple pre-selected analog signals within preset time nodes; According to the number and size of the weighted values ​​corresponding to the preselected analog signal, a corresponding number of impedance values ​​of different sizes are obtained; After the preselected analog signal is matched with the impedance value, the preselected analog signal and any impedance value corresponding to the preselected analog signal are multiplied and added to obtain a weighted value, and a plurality of the weighted values ​​are summed.

9. The artificial intelligence calculation and control method using analog circuits as claimed in claim 8, characterized in that: The method further comprises: Before outputting a plurality of preselected analog signals within a preset time node, a plurality of analog signals are stored simultaneously.

10. The artificial intelligence calculation and control method using analog circuits as claimed in claim 9, characterized in that: The method further comprises: After performing multiplication and addition operations on the analog signal and the impedance value corresponding to the analog signal, the multiplication and addition operation result is used as the preselected analog signal to perform multiplication and addition operation again, or the multiplication and addition operation result is output.

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