Method for improving performance of high-voltage PMOS (P-channel Metal Oxide Semiconductor) based on photoresist stripping

Abstract

The invention discloses a method for improving the performance of a high-voltage PMOS (P-channel Metal Oxide Semiconductor) by photoresist stripping, which comprises the following steps of: providing a semiconductor substrate, forming an active region and an isolation region on the semiconductor substrate to form a substrate, and spin-coating photoresist on the surface of the substrate; performing exposure and development in the first region of the photoresist to form a first inlet; first ion implantation is carried out on the active region of the substrate through the first inlet; extending outwards along the radial direction of the first region to define a second region, and etching the photoresist in the second region to form a second inlet; respectively carrying out second ion implantation and third ion implantation on the active region of the substrate through the second inlet; and removing the residual photoresist on the surface of the substrate. According to the method, the photoresist is stripped for multiple times in the ion implantation process, so that the distribution of ion implantation is adjusted on the premise that the implantation concentration is not changed, the problem that the high-voltage PMOS cannot be completely exhausted is effectively solved, and the performance of the low-voltage PMOS and the performance of the high-voltage PMOS are compatible.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor process technology, and in particular to a method for improving high-voltage PMOS performance based on photoresist stripping. Background Art

[0002] BCD process is a monolithic integration process technology, which can produce Bipolar, CMOS and DMOS devices on the same chip, referred to as BCD process. BCD process can select different devices for different circuits to achieve the optimization of corresponding electronic circuit devices, and realize the requirements of low power consumption, high integration, high speed and high driving capability of the whole circuit.

[0003] RESURF (Reduced Surface Field) technology is the basis of high-voltage MOS design - by adjusting the design of device structure and injection concentration, the largest space charge region can be obtained as much as possible, so that the high-voltage electric field is evenly distributed on the space charge region and the breakdown voltage is increased. Due to the wide variety of operating voltages in the BCD process, the same set of ion implantation procedures are required during the development process to meet the requirements of high voltage and low voltage at the same time. The device needs to reduce the on-resistance as much as possible while meeting the breakdown voltage. However, the method of improving the breakdown voltage by reducing the surface ion implantation concentration in the prior art will greatly affect the on-resistance. For example, when the breakdown voltage of 24V high-voltage LDPMOS (lateral double diffused metal oxide semiconductor) is insufficient under the injection condition, a wider space charge region can be obtained by reducing the surface implantation concentration to obtain a higher breakdown voltage, but this operation will also cause the on-current of 12V low-voltage EDPMOS (drain extended metal oxide semiconductor) to decrease and the on-resistance to increase. However, such a result is not in line with our expectations. Therefore, a method is needed to increase the drain-source breakdown voltage of 24V high-voltage LDPMOS without reducing the ion implantation concentration.

[0004] Therefore, there is still a need in the prior art to improve the method of improving the performance of high-voltage PMOS. Summary of the invention

[0005] In view of this, the purpose of an embodiment of the present invention is to propose a method for improving the performance of high-voltage PMOS based on photoresist stripping. The method of the present invention strips the photoresist multiple times during the ion implantation process to adjust the distribution of ion implantation without changing the implantation concentration, thereby effectively improving the problem that the high-voltage PMOS cannot be completely depleted and achieving compatibility with the performance of low-voltage and high-voltage PMOS.

[0006] Based on the above purpose, an embodiment of the present invention provides a method for improving high-voltage PMOS performance based on photoresist stripping, comprising the following steps:

[0007] S1, providing a semiconductor substrate, forming an active area and an isolation area on the semiconductor substrate to form a base, and spin coating a photoresist on the surface of the base;

[0008] S2, performing exposure and development in the first area of ​​the photoresist to form a first inlet;

[0009] S3, performing a first ion implantation into the active area of ​​the substrate through the first inlet;

[0010] S4, extending radially outward from the first region to define a second region, and etching the photoresist in the second region to form a second inlet;

[0011] S5, performing a second ion implantation and a third ion implantation into the active area of ​​the substrate through the second inlet;

[0012] S6. Remove the remaining photoresist on the surface of the substrate.

[0013] In some embodiments, a depth of the second ion implantation is less than a thickness of the isolation region, and a depth of the third ion implantation is greater than the thickness of the isolation region.

[0014] In some embodiments, the first ion implantation depth is 0-0.03 μm, the second ion implantation depth is 0.3-0.7 μm, and the third ion implantation depth is 1-2 μm.

[0015] In some embodiments, the diameter of the first inlet is 0-0.3 μm, and the diameter of the second inlet is 0.6-0.9 μm.

[0016] In some embodiments, the substances of the first ion implantation, the second ion implantation, and the third ion implantation are boron ions.

[0017] In some embodiments, the active region is an N-well formed by implanting impurity ions into a semiconductor substrate, and the isolation regions are distributed on both sides of the active region.

[0018] In some embodiments, the semiconductor substrate is a P-type substrate.

[0019] The present invention has at least the following beneficial technical effects:

[0020] The present invention provides a method for improving the performance of high-voltage PMOS based on photoresist stripping. In view of the problem that the operating voltages required by BCD process customers are various and the platform development process often requires the same set of ion implantation procedures to simultaneously meet high / low voltage requirements, the photoresist is stripped multiple times in the ion implantation procedure to adjust the distribution area of ​​ion implantation without changing the implantation concentration, thereby effectively improving the problem that the high-voltage PMOS cannot be completely exhausted and making the performance of 12V and 24V PMOS compatible. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can be obtained based on these drawings without paying creative work.

[0022] Figure 1 A flow chart of an embodiment of the present invention for improving high-voltage PMOS performance based on photoresist stripping;

[0023] Figure 2 This is a diagram of the substrate structure of the PMOS provided by the present invention.

[0024] 1. Substrate; 2. N-well; 3. Shallow trench isolation area; 4. Photoresist. DETAILED DESCRIPTION

[0025] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field of the present invention; the terms used in this specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. For example, the directions or positions indicated by the terms "length", "width", "up", "down", "left", "right", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. are based on the directions or positions shown in the drawings, which are only for the convenience of description and should not be understood as limitations on the present technical solution.

[0027] The terms "including" and "having" and any variations thereof in the specification and claims of the present invention and the above-mentioned drawings are intended to cover non-exclusive inclusions; the terms "first", "second", etc. in the specification and claims of the present invention or the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order. "Multiple" means two or more, unless otherwise clearly and specifically defined.

[0028] In addition, reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0029] BCD is a process technology that integrates bipolar transistors (Bipolar), complementary metal oxide semiconductors (CMOS) and double diffused metal oxide semiconductors (DMOS) for high voltage processing on the same chip. It is widely used in the manufacture of power semiconductors. Compared with ordinary semiconductors, power semiconductors require higher rated voltages and higher reliability. With the expansion of power semiconductor applications, the demand for BCD is also increasing. RESURF (Reduced Surface Field) technology is the basis of HVLDMOS design - by adjusting the device structure and the design of the injection concentration, the largest space charge region is obtained as much as possible, so that the high voltage electric field is evenly distributed on the space charge region, and the breakdown voltage is increased. Due to the wide variety of operating voltages required by BCD process customers, the platform development process often requires the same set of ion implants to meet high / low voltage requirements at the same time. Therefore, the method for improving the performance of high-voltage PMOS based on photoresist stripping provided by the present invention, the PMOS process mainly includes forming a double deep N-well isolation structure (Deep N-Well, DNW), ion diffusion, ion implantation, P / N well formation, SAB, back-end processes, etc., and the present invention is designed for the ion implantation procedure.

[0030] like Figure 1 The flowchart of an embodiment of the method of the present invention is shown, and the order indicated by the arrows is S1-S6, which specifically includes the following steps:

[0031] S1, providing a semiconductor substrate, forming an active region and an isolation region on the semiconductor substrate to form a base, and spin coating a photoresist (PR) on the surface of the base;

[0032] S2, performing exposure and development in the first area of ​​the photoresist to form a first inlet;

[0033] S3, performing a first ion implantation into the active area of ​​the substrate through the first inlet;

[0034] S4, extending radially outward from the first region to define a second region, and etching the photoresist in the second region to form a second inlet;

[0035] S5, performing a second ion implantation and a third ion implantation into the active area of ​​the substrate through the second inlet;

[0036] S6. Remove the remaining photoresist on the surface of the substrate.

[0037] Furthermore, in S1, if Figure 2 The substrate structure shown in the figure provides a semiconductor substrate as a P-type substrate 1, impurity ions are injected into the substrate to form an N-well 2 to define an active area, shallow trench isolation regions (STI) 3 are made on both sides of the active area to form a substrate, and photoresist 4 is spin-coated on the surface of the substrate.

[0038] Further, in S2, exposure and development are performed in the first region of the photoresist to form a first inlet, and the diameter of the first inlet is 0-0.3 μm.

[0039] Furthermore, in S3, a first ion implantation is performed into the active region of the substrate through the first inlet, and the first ion implantation depth is 0 to 0.03 μm.

[0040] Further, in S4, a second region is defined by radially extending outward along the first region, and the photoresist is etched in the second region to form a second inlet, that is, the ion injection inlet is enlarged by trimming the photoresist, and the diameter of the second inlet is larger than that of the first inlet. In some embodiments, the diameter of the second inlet is 0.6 to 0.9 μm.

[0041] Further, in S5, a second ion implantation and a third ion implantation are respectively performed into the active area of ​​the substrate through the second entrance, the second ion implantation depth is 0.3-0.7 μm, the third ion implantation depth is 1-2 μm, and the second ion implantation depth is less than the thickness of the isolation region, and the third ion implantation depth is greater than the thickness of the isolation region.

[0042] Furthermore, the substances of the first ion implantation, the second ion implantation and the third ion implantation are boron ions.

[0043] Table 1 Experimental comparison based on different ion implantation procedures

[0044]

[0045] As shown in Table 1, the breakdown voltage (BVD) change of 24V PMOS after ion implantation using the method of the present invention is shown. A total of 4 experiments were conducted, using the same MOS device and implantation procedure, and adjusting the size of the photoresist entrance. The first experiment was a control group, that is, the photoresist was not trimmed, and multiple ion implantations were all performed in the same entrance. The test results showed that the breakdown voltage was 32.63V. The second, third, and fourth experiments were performed by trimming the ion implantation entrance of the photoresist with different differences. When the difference was 0.3μm, the breakdown voltage was 37.9V, and when the difference was 0.6μm, the breakdown voltage was 1.2V. The voltage further increases to 44.83V. When the difference is 0.9μm, the breakdown voltage is 48.73V. By differentiated design of the injection aperture during the ion implantation procedure, the concentrations and ranges of the three ion implantations are different, but the overall ion implantation concentration does not need to be changed, resulting in the HVPF being more depleted as the space charge region. Therefore, the breakdown voltage of the high-voltage device can be increased without changing the total ion implantation concentration, providing more possibilities for the compatibility of high-voltage and low-voltage devices in the BCD process.

[0046] The above are exemplary embodiments disclosed in the present invention, but it should be noted that various changes and modifications may be made without departing from the scope disclosed in the embodiments of the present invention as defined in the claims. The functions, steps and / or actions of the method claims according to the disclosed embodiments described herein do not need to be performed in any particular order. In addition, although the elements disclosed in the embodiments of the present invention may be described or required in individual form, they may also be understood as multiple unless explicitly limited to the singular.

[0047] It should be understood that, as used herein, the singular forms "a", "an" are intended to include the plural forms as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations including one or more of the associated listed items.

[0048] The serial numbers of the embodiments disclosed in the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0049] A person skilled in the art should understand that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the disclosure of the embodiments of the present invention (including the claims) is limited to these examples; under the concept of the embodiments of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and there are many other changes in different aspects of the embodiments of the present invention as above, which are not provided in detail for the sake of simplicity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present invention should be included in the protection scope of the embodiments of the present invention.

Claims

1. A method for improving high-voltage PMOS performance based on photoresist stripping, characterized in that: include: S1, providing a semiconductor substrate, forming an active region and an isolation region on the semiconductor substrate to form a base, and spin coating a photoresist on a surface of the base; S2, performing exposure and development in the first area of ​​the photoresist to form a first inlet; S3, performing a first ion implantation into the active area of ​​the substrate through the first inlet; S4, extending radially outward from the first region to define a second region, and etching the photoresist in the second region to form a second inlet; S5, performing a second ion implantation and a third ion implantation into the active area of ​​the substrate through the second inlet; S6. Removing the remaining photoresist on the surface of the substrate.

2. The method for improving high-voltage PMOS performance based on photoresist stripping according to claim 1, characterized in that: The depth of the second ion implantation is less than the thickness of the isolation region, and the depth of the third ion implantation is greater than the thickness of the isolation region.

3. The method for improving high-voltage PMOS performance based on photoresist stripping according to claim 2, characterized in that: The first ion implantation depth is 0 to 0.03 μm, the second ion implantation depth is 0.3 to 0.7 μm, and the third ion implantation depth is 1 to 2 μm.

4. The method for improving high-voltage PMOS performance based on photoresist stripping according to claim 1, characterized in that: The diameter of the first inlet is 0-0.3 μm, and the diameter of the second inlet is 0.6-0.9 μm.

5. The method for improving high-voltage PMOS performance based on photoresist stripping according to claim 1, characterized in that: The substances of the first ion implantation, the second ion implantation and the third ion implantation are boron ions.

6. The method for improving high-voltage PMOS performance based on photoresist stripping according to claim 1, characterized in that: The active region is an N-well formed by injecting impurity ions into the semiconductor substrate, and the isolation region is distributed on both sides of the active region.

7. The method for improving high-voltage PMOS performance based on photoresist stripping according to claim 1, characterized in that: The semiconductor substrate is a P-type substrate.

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