Method of packaging a chip assembly

Abstract

The application relates to a packaging method of a chip assembly. The packaging method of the chip assembly comprises the following steps: cutting a first wafer to form a first chip; bonding the front surface of the first chip with the front surface of a second wafer to form a first semi-finished product; cutting the first semi-finished product, so that the second wafer is cut to form a second chip, and the first chip and the second chip bonded with each other form a chip assembly; arranging the chip assembly on a carrier; and arranging a first packaging layer on the carrier, and the first packaging layer covers the chip assembly. The first chip and the second chip are stacked and bonded to form the chip assembly, and then the chip assembly is arranged on the carrier, and then the first packaging layer is used to cover the chip assembly, so that more chips can be packaged without affecting the thickness of the first packaging layer, the density of the packaging structure is improved, and the miniaturization function of the packaging structure is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a packaging method of a chip assembly. BACKGROUND

[0002] In recent years, terminal consumer electronics products are designed to be light, thin, short and small, which leads to the development of chip packaging towards thinness and high density. The packaging structure of multi-chip module (MCM) is widely used in electronic devices. The packaging structure of multi-chip module mainly includes two or more chips to improve the electrical properties and performance of the packaging structure of multi-chip module. However, the multiple chips in the packaging structure of multi-chip module are currently arranged in the form of single-layer chips in the packaging structure of multi-chip module, and the miniaturization space of the packaging structure of multi-chip module is less. SUMMARY

[0003] The purpose of the present application is to provide a packaging method of a chip assembly, which can solve the technical problem that the multiple chips in the packaging structure of multi-chip module are arranged in the form of single-layer chips in the packaging structure of multi-chip module, and the miniaturization space of the packaging structure of multi-chip module is less.

[0004] To solve the above problems, the present application provides a packaging method of a chip assembly, which includes: cutting a first wafer to form a first chip; bonding the front surface of the first chip with the front surface of a second wafer to form a first semi-finished product; cutting the first semi-finished product so that the second wafer is cut to form a second chip, and the first chip and the second chip bonded with each other form a chip assembly; arranging the chip assembly on a carrier, the carrier having a first direction; arranging a first packaging layer on the carrier, the first packaging layer covering the chip assembly; arranging a first substrate on the side of the first packaging layer away from the carrier; performing a patterning process on the first substrate and the first packaging layer to form a first conductive hole, the first conductive hole penetrating through the first substrate and the first packaging layer along the first direction; preparing a first redistribution layer on the side of the first conductive hole away from the first substrate; and preparing a solder ball on the side of the first redistribution layer away from the first substrate, the solder ball being electrically connected to the first redistribution layer.

[0005] In some embodiments, the step of cutting a first wafer to form a first chip includes: arranging a first protective film on the front surface of the first wafer; performing a thinning process on the back surface of the first wafer; removing the first protective film; arranging a second protective film on the back surface of the first wafer; and cutting the first wafer to form the first chip.

[0006] In some embodiments, the step of bonding the front surface of the first chip with a front surface of a second wafer to form a first semi-product comprises: disposing a third protective film on the front surface of the second wafer; thinning the back surface of the second wafer; removing the third protective film; and bonding the front surface of the first chip with the front surface of the second wafer to form the first semi-product.

[0007] In some embodiments, the first wafer comprises a first main body and a first conductive part disposed on one side of the first main body, and the second wafer comprises a second main body and a second conductive part disposed on one side of the second main body; the step of bonding the front surface of the first chip with a front surface of a second wafer to form a first semi-product comprises: bonding the first conductive part of the first chip with the second conductive part of the second wafer to form the first semi-product.

[0008] In some embodiments, the step of bonding the front surface of the first chip with the front surface of the second wafer to form the first semi-product is performed by at least one of thermal compression bonding, ultrasonic bonding, laser bonding, conductive adhesive bonding, and micro bonding.

[0009] In some embodiments, the step of cutting the first semi-product such that the second wafer is cut to form second chips, and the first chips and the second chips bonded with each other form a chip assembly comprises: disposing a fourth protective film on the back surface of the second wafer; and cutting the second wafer of the first semi-product such that the second wafer is cut to form the second chips, and the first chips and the second chips bonded with each other form the chip assembly.

[0010] In some embodiments, the step of disposing the chip assembly on a carrier comprises: disposing an adhesive layer on the carrier, and adhering the chip assembly to the adhesive layer; and the step of preparing the solder balls on the side of the first redistribution layer away from the first substrate further comprises: removing the carrier and the adhesive layer.

[0011] In some embodiments, the step of patterning the first substrate and the first packaging layer to form the first conductive hole comprises: patterning the first substrate and the first packaging layer to form the first conductive hole by a laser process.

[0012] In some embodiments, the step of preparing the soldering balls on the side of the first redistribution layer away from the first substrate further comprises: preparing at least one sub-encapsulation structure on the side of the first substrate away from the first encapsulation layer, the sub-encapsulation structure covering the first redistribution layer; the step of preparing the at least one sub-encapsulation structure on the side of the first substrate away from the first encapsulation layer comprises: preparing a sub-encapsulation layer on the side of the first substrate away from the first encapsulation layer, the sub-encapsulation layer covering the first redistribution layer; preparing a sub-substrate on the side of the sub-encapsulation layer away from the first substrate; patterning the sub-substrate and the sub-encapsulation layer to form a sub-conductive hole, the sub-conductive hole penetrating through the sub-substrate and the sub-encapsulation layer along a first direction; preparing a sub-redistribution layer in the sub-conductive hole and on the side of the sub-substrate away from the sub-encapsulation layer, the sub-redistribution layer closest to the first substrate being electrically connected to the first redistribution layer; and preparing the soldering balls on the side of the sub-redistribution layer away from the sub-substrate, the soldering balls being electrically connected to the sub-redistribution layer farthest from the first substrate.

[0013] In some embodiments, the step of preparing the at least one sub-encapsulation structure on the side of the first substrate away from the first encapsulation layer further comprises: disposing a chip assembly on the side of the first substrate away from the first encapsulation layer and / or on the side of the sub-substrate away from the sub-encapsulation layer, the sub-encapsulation layer covering the chip assembly.

[0014] The present application adopts bonding of a first chip and a second wafer, then cutting the first semi-finished product to form a second chip from the second wafer, so that the first chip and the second chip bonded with each other form a chip assembly, then disposing the chip assembly on a carrier, disposing a first encapsulation layer on the carrier, and the first encapsulation layer covering the chip assembly. By disposing the chip assembly formed by stacking and bonding of the first chip and the second chip on the carrier, and then covering the chip assembly with the first encapsulation layer, more chips can be encapsulated without affecting the thickness of the first encapsulation layer, the density of the encapsulation structure is improved, and the miniaturization of the encapsulation structure is realized. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0016] Figure 1 is a flowchart of an encapsulation method of a chip assembly according to an embodiment of the present application;

[0017] Figures 2a-2f is a structural schematic diagram of cutting a first wafer to form a first chip according to an embodiment of the present application;

[0018] Figures 3a-3dThis is a structural diagram of bonding the front side of a first chip to the front side of a second wafer to form a first semi-finished product in an embodiment of the present application;

[0019] Figures 4a-4c This is a schematic structural diagram of cutting the first semi-finished product in an embodiment of the present application;

[0020] Figure 5 This is a schematic structural diagram of an embodiment of the present application in which a chip component is disposed on a carrier;

[0021] Figure 6 Schematic diagram of the structure of the first packaging layer provided on the carrier according to an embodiment of the present application;

[0022] Figure 7 This is a structural diagram of an embodiment of the present application in which a first substrate is provided on a first packaging layer;

[0023] Figure 8 This is a structural schematic diagram of an embodiment of the present application in which a first substrate and a first packaging layer are patterned to form a first conductive hole;

[0024] Figure 9 This is a schematic structural diagram of an embodiment of the present application in which a first redistribution layer is prepared in the first conductive hole and on the side of the first substrate away from the first packaging layer;

[0025] Figure 10 This is a schematic diagram of the structure of the embodiment of the present application without the carrier and the adhesive layer;

[0026] Figure 11 This is a schematic structural diagram of preparing solder balls on a side of the first redistribution layer away from the first substrate in an embodiment of the present application;

[0027] Figures 12a-12e This is a structural schematic diagram of an embodiment of the present application in which a sub-encapsulation structure is prepared on a side of the first substrate away from the first encapsulation layer;

[0028] Figure 13 This embodiment of the present application is Figure 12e Schematic diagram of the structure with the carrier and glue layer removed from the foundation;

[0029] Figure 14 This embodiment of the present application is Figure 13 A schematic diagram of a structure in which solder balls are prepared on a side of the sub-redistribution layer away from the sub-substrate;

[0030] Figure 15 This is a structural schematic diagram of a three-layer sub-encapsulation structure prepared on a side of the first substrate away from the first encapsulation layer in an embodiment of the present application;

[0031] Figure 16 This embodiment of the present application is Figure 15 Schematic diagram of the structure with the carrier and glue layer removed from the foundation;

[0032] Figure 17 is a structural schematic diagram of the application embodiment in which the solder balls are prepared on the side of the sub-redistribution layer far from the substrate. Figure 16

[0033] BRIEF DESCRIPTION OF DRAWINGS

[0034] 1, first wafer; 2, first protective film; 3, second protective film; 4, first chip; 5, second wafer; 6, third protective film; 7, first semi-finished product; 8, fourth protective film; 9, chip assembly; 10, second chip; 11, first packaging layer; 12, carrier; 13, adhesive layer; 14, first substrate; 15, first conductive hole; 16, first redistribution layer; 17, solder ball; 18, sub-packaging structure; 110, first main body; 120, first conductive part; 510, second main body; 520, second conductive part; 1810, sub-packaging layer; 1820, sub-substrate; 1830, sub-conductive hole; 1840, sub-redistribution layer. DETAILED DESCRIPTION

[0035] The preferred embodiments of the present application will be described in detail below with reference to the accompanying drawings, to give a full understanding of the technical content of the present application to those skilled in the art, to prove that the present application can be implemented by way of examples, to make the technical content disclosed by the present application more clear, and to make those skilled in the art more easily understand how to implement the present application. However, the present application can be embodied in many different forms of embodiments, and the protection scope of the present application is not limited to the embodiments mentioned herein, and the description of the embodiments below is not used to limit the scope of the present application.

[0036] The direction terms mentioned in the present application, such as "up", "down", "front", "back", "left", "right", "inner", "outer", "side", etc., are only the directions in the drawings, and the direction terms used herein are used to explain and describe the present application, and are not used to limit the protection scope of the present application.

[0037] In the drawings, the same numbers are used to represent the same components throughout the drawings, and the components with similar structures or functions are represented by similar numbers. In addition, in order to facilitate understanding and description, the size and thickness of each component shown in the drawings are arbitrarily shown, and the present application does not limit the size and thickness of each component.

[0038] Please refer to Figure 1 , Figure 1 ​is a flow chart of a packaging method of a chip assembly according to an embodiment of the present application. The packaging method of the chip assembly comprises: step 101, cutting a first wafer 1 to form a first chip 4; step 102, bonding a front surface of the first chip 4 with a front surface of a second wafer 5 to form a first semi-finished product 7; step 103, cutting the first semi-finished product 7 so that the second wafer 5 is cut to form a second chip 10, and so that the first chip 4 and the second chip 10 bonded with each other form a chip assembly 9; step 104, disposing the chip assembly 9 on a carrier 12, the carrier 12 having a first direction M; step 105, disposing a first encapsulation layer 11 on the carrier 12, the first encapsulation layer 11 encapsulating the chip assembly 9; step 106, disposing a first substrate on a side of the first encapsulation layer away from the carrier; step 107, performing a patterning process on the first substrate and the first encapsulation layer to form a first conductive hole, the first conductive hole penetrating through the first substrate and the first encapsulation layer along the first direction; step 108, preparing a first redistribution layer on a side of the first conductive hole and a side of the first substrate away from the first encapsulation layer; and step 109, preparing a solder ball on a side of the first redistribution layer away from the first substrate, the solder ball being electrically connected to the first redistribution layer.

[0039] Referring to Figure 2a In some embodiments, step 101 comprises disposing a first protective film 2 on the front surface of the first wafer 1. Specifically, the first wafer 1 comprises a first main body part 110 and a first conductive part 120 disposed on a side of the first main body part 110. The first protective film 2 covers a side of the first conductive part 120 away from the first main body part 110. That is, the front surface of the first wafer 1 refers to the surface of the side of the first conductive part 120 away from the first main body part 110, and the back surface of the first wafer 1 refers to the surface of the side of the first main body part 110 away from the first conductive part 120.

[0040] Referring to Figure 2b In some embodiments, step 101 comprises performing a thinning process on the back surface of the first wafer 1. Specifically, the surface of the side of the first main body part 110 away from the first conductive part 120 can be ground to thin the thickness of the first main body part 110, and thus to reduce the overall thickness of the first wafer 1.

[0041] Referring to Figure 2c In some embodiments, step 101 comprises removing the first protective film 2.

[0042] Referring to Figure 2d In some embodiments, step 101 comprises disposing a second protective film 3 on the back surface of the first wafer 1. That is, the second protective film 3 covers the surface of the side of the first main body part 110 away from the first conductive part 120.

[0043] Referring to Figure 2eIn some embodiments, step 101 comprises cutting the first wafer 1 to form the first chips 4. Specifically, the first wafer 1 can be cut by a cutting process such as laser cutting to form a plurality of first chips 4, as shown in Figure 2f

[0044] Referring to Figure 2f , the first chip 4 comprises a first main body 110 and at least two first conductive parts 120 arranged on one side of the first main body 110.

[0045] Referring to Figure 3a In some embodiments, step 102 comprises arranging a third protective film 6 on the front surface of the second wafer 5. Specifically, the second wafer 5 comprises a second main body 510 and a second conductive part 520 arranged on one side of the second main body 510. The third protective film 6 covers the side of the second conductive part 520 away from the second main body 510. That is, the front surface of the second wafer 5 refers to the surface of the side of the second conductive part 520 away from the second main body 510, and the back surface of the second wafer 5 refers to the surface of the side of the second main body 510 away from the second conductive part 520.

[0046] Referring to Figure 3b In some embodiments, step 102 comprises thinning the back surface of the second wafer 5. Specifically, the surface of the side of the second main body 510 away from the second conductive part 520 can be ground to thin the second main body 510, thereby reducing the overall thickness of the second wafer 5.

[0047] Referring to Figure 3c In some embodiments, step 102 comprises removing the third protective film 6;

[0048] Referring to Figure 3d In some embodiments, step 102 comprises bonding the front surface of the first chip 4 to the front surface of the second wafer 5 to form a first semi-finished product 7. Specifically, the first conductive part 120 of the first chip 4 is bonded to the second conductive part 520 of the second wafer 5 to form the first semi-finished product 7.

[0049] In some embodiments, at least one of heat pressing, ultrasonic welding, laser welding, conductive adhesive welding, and micro welding is used to bond the front surface of the first chip 4 to the front surface of the second wafer 5 to form the first semi-finished product 7.

[0050] Referring to Figure 4a In some embodiments, step 103 comprises arranging a fourth protective film 8 on the back surface of the second wafer 5. That is, the fourth protective film 8 covers the surface of the side of the second main body 510 away from the second conductive part 520.

[0051] Referring to Figure 4b ​In some embodiments, step 103 comprises: cutting the second wafer 5 of the first semi-finished product 7, the second wafer 5 is cut to form the second chip 10, and the first chip 4 and the second chip 10 bonded to each other form the chip assembly 9. Specifically, the second wafer 5 can be cut to form a plurality of second chips 10 by using a cutting process such as laser cutting, and the second chip 10 and the first chip 4 are combined to form the chip assembly 9.

[0052] Referring to Figure 4c In some embodiments, the chip assembly 9 comprises the first chip 4 and the second chip 10 stacked along the first direction M. The first chip 4 and the second chip 10 are bonded to each other, and the second chip 10 and the first chip 4 are combined to form the chip assembly 9.

[0053] Referring to Figure 5 In some embodiments, step 104 comprises: disposing the adhesive layer 13 on the carrier 12, and bonding the chip assembly 9 on the adhesive layer 13. In some embodiments, the adhesive layer 13 can be double-sided adhesive tape. Specifically, the adhesive layer 13 is bonded to the surface of one side of the carrier 12.

[0054] Referring to Figure 6 In some embodiments, step 105 comprises: preparing the first encapsulation layer 11 on the side of the adhesive layer 13 away from the carrier 12, and the first encapsulation layer 11 encapsulates the chip assembly 9.

[0055] Through the above scheme, the first chip 4 and the second chip 10 are stacked and bonded to form the chip assembly 9, which is then disposed on the carrier 12, and then the first encapsulation layer 11 is used to encapsulate the chip assembly 9. Without affecting the thickness of the first encapsulation layer 11, more chips are encapsulated, the density of the encapsulation structure is improved, and the miniaturization function of the encapsulation structure is realized.

[0056] Referring to Figure 7 In some embodiments, step 106 comprises: disposing the first substrate 14 on the side of the first encapsulation layer 11 away from the carrier 12. In this embodiment, the material of the first substrate 14 is polyimide (PI).

[0057] Referring to Figure 8 In some embodiments, step 107 comprises: patterning the first substrate 14 and the first encapsulation layer 11 to form the first conductive hole 15, and the first conductive hole 15 penetrates the first substrate 14 and the first encapsulation layer 11 along the first direction M. In some embodiments, the first conductive hole 15 is formed by patterning the first substrate 14 and the first encapsulation layer 11 by using a laser process, and one end of the first conductive hole 15 on the side close to the carrier 12 abuts against the surface of the side of the second conductive part 520 away from the second main body part 510.

[0058] Referring toFigure 9 In some embodiments, step 108 comprises: preparing the first redistribution layer 16 on the first conductive hole 15 and the side of the first substrate 14 away from the first package layer 11. In some embodiments, the first redistribution layer 16 is prepared by a sputtering process, and the material of the first redistribution layer 16 is copper. In other embodiments, other processes and other conductive materials can be used to prepare the first redistribution layer 16 according to actual conditions and requirements.

[0059] Referring to Figure 10 In some embodiments, the method for packaging the chip assembly further comprises: removing the carrier 12 and the adhesive layer 13.

[0060] Referring to Figure 11 In some embodiments, step 109 comprises: preparing the solder ball 17 on the side of the first redistribution layer 16 away from the first substrate 14, and the solder ball 17 is electrically connected to the first redistribution layer 16.

[0061] Referring to Figures 12a-12e In some embodiments, step 109 further comprises: preparing a sub-package structure 18 on the side of the first substrate 14 away from the first package layer 11, and the sub-package structure 18 covers the first redistribution layer 16. Specifically, between step 108 and the step of removing the carrier 12 and the adhesive layer 13, a sub-package structure 18 is prepared on the side of the first substrate 14 away from the first package layer 11, and the sub-package structure 18 covers the first redistribution layer 16.

[0062] Referring to Figure 12a In some embodiments, the step of preparing at least one sub-package structure 18 on the side of the first substrate 14 away from the first package layer 11 comprises: arranging the chip assembly 9 on the side of the first substrate 14 away from the first package layer 11. In this embodiment, the chip assembly 9 is arranged on the side of the first substrate 14 away from the first package layer 11, and in other embodiments, the chip assembly 9 can not be arranged on the side of the first substrate 14 away from the first package layer 11 according to actual requirements.

[0063] Referring to Figure 12b In some embodiments, the step of preparing at least one sub-package structure 18 on the side of the first substrate 14 away from the first package layer 11 further comprises: preparing a sub-package layer 1810 on the side of the first substrate 14 away from the first package layer 11, and the sub-package layer 1810 covers the first redistribution layer 16 and the chip assembly 9. In this embodiment, after the first chip 4 and the second chip 10 are stacked and bonded to form the chip assembly 9, the chip assembly 9 is arranged on the first substrate 14, and then the chip assembly 9 is covered by the sub-package layer 1810. On the basis of not affecting the thickness of the sub-package layer 1810, more chips are packaged, the density of the packaging structure is improved, and the miniaturization function of the packaging structure is realized.

[0064] Referring toFigure 12c In some embodiments, the step of preparing at least one sub-encapsulation structure 18 on the side of the first substrate 14 away from the first encapsulation layer 11 further comprises: preparing a sub-substrate 1820 on the side of the sub-encapsulation layer 1810 away from the first substrate 14. In this embodiment, the material of the sub-substrate 1820 is polyimide (PI).

[0065] Referring to Figure 12d In some embodiments, the step of preparing at least one sub-encapsulation structure 18 on the side of the first substrate 14 away from the first encapsulation layer 11 further comprises: performing a patterning process on the sub-substrate 1820 and the sub-encapsulation layer 1810 to form sub-conductive holes 1830, the sub-conductive holes 1830 penetrating through the sub-substrate 1820 and the sub-encapsulation layer 1810 along the first direction M. In some embodiments, the patterning process on the sub-substrate 1820 and the sub-encapsulation layer 1810 is performed by a laser process, and one end of some of the sub-conductive holes 1830 near the side of the first substrate 14 abuts against the surface of the side of the second conductive part 520 on the first substrate 14 away from the second main part 510, and one end of some of the sub-conductive holes 1830 near the side of the first substrate 14 abuts against the surface of the side of the first redistribution layer 16 away from the first substrate 14.

[0066] Referring to Figure 12e In some embodiments, the step of preparing at least one sub-encapsulation structure 18 on the side of the first substrate 14 away from the first encapsulation layer 11 further comprises: preparing a sub-redistribution layer 1840 in the sub-conductive holes 1830 and on the side of the sub-substrate 1820 away from the sub-encapsulation layer 1810, the sub-redistribution layer 1840 being electrically connected to the first redistribution layer 16.

[0067] Referring to Figure 13 In some embodiments, the step of preparing at least one sub-encapsulation structure 18 on the side of the first substrate 14 away from the first encapsulation layer 11 further comprises: Figure 12e removing the carrier and the adhesive layer 13.

[0068] Referring to Figure 14 In some embodiments, the step of preparing at least one sub-encapsulation structure 18 on the side of the first substrate 14 away from the first encapsulation layer 11 further comprises: Figure 13 on the basis of the sub-redistribution layer 1840 away from the sub-substrate 1820, preparing solder balls 17 electrically connected to the sub-redistribution layer 1840.

[0069] Referring to Figure 15In some embodiments, the step of preparing the solder balls 17 on the side of the first redistribution layer 16 distal to the first substrate 14 is preceded by the step of preparing a three-layer sub-package structure 18 on the side of the first substrate 14 distal to the first package layer 11, the sub-package structure 18 covering the first redistribution layer 16. Specifically, the step of preparing the first redistribution layer 16 on the side of the first substrate 14 distal to the first package layer 11 and the step of removing the carrier 12 and the adhesive layer 13 are preceded by the step of preparing a three-layer sub-package structure 18 on the side of the first substrate 14 distal to the first package layer 11, the sub-package structure 18 covering the first redistribution layer 16. The sub- redistribution layer 1840 closest to the first substrate 14 is electrically connected to the first redistribution layer 16. In this embodiment, the lowermost sub-redistribution layer 1840 is electrically connected to the first redistribution layer 16.

[0070] Referring to Figure 15 In this embodiment, the chip assembly 9 is disposed on the side of the first substrate 14 distal to the first package layer 11 and on the side of the sub-substrate 1820 distal to the sub-package layer 1810. Specifically, the side of the first substrate 14 distal to the first package layer 11 and the side of each sub-substrate 1820 distal to the sub-package layer 1810 are each provided with a chip assembly 9. In other embodiments, the chip assembly 9 can be disposed on the first substrate 14 or on some of the sub-substrates 1820, or none of the first substrate 14 and any of the sub-substrates 1820 can be provided with a chip assembly 9.

[0071] Referring to Figure 16 In some embodiments, the step of removing the carrier and the adhesive layer 13 is preceded by the step of preparing a three-layer sub-package structure 18 on the side of the first substrate 14 distal to the first package layer 11, the sub-package structure 18 covering the first redistribution layer 16. Figure 15

[0072] Referring to Figure 17 In some embodiments, the step of preparing the solder balls 17 on the side of the sub-redistribution layer 1840 distal to the sub-substrate 1820 is preceded by the step of removing the carrier and the adhesive layer 13. Figure 16

[0073] ​​In some embodiments, the packaging method of the chip assembly comprises: disposing a first protective film 2 on the front surface of a first wafer 1, thinning the back surface of the first wafer 1, removing the first protective film 2, disposing a second protective film 3 on the back surface of the first wafer 1, and cutting the first wafer 1 to form a first chip 4; disposing a third protective film 6 on the front surface of a second wafer 5, thinning the back surface of the second wafer 5, removing the third protective film 6, bonding the front surface of the first chip 4 with the front surface of the second wafer 5 to form a first semi-finished product 7, disposing a fourth protective film 8 on the back surface of the second wafer 5, cutting the second wafer 5 of the first semi-finished product 7, and cutting the second wafer 5 to form a second chip 10, and the first chip 4 and the second chip 10 bonded with each other form a chip assembly 9; disposing a glue layer 13 on a carrier 12, and bonding the chip assembly 9 on the glue layer 13; preparing a first packaging layer 11 on the side of the glue layer 13 away from the carrier 12, and the first packaging layer 11 covers the chip assembly 9; disposing a first substrate 14 on the side of the first packaging layer 11 away from the carrier 12; performing a patterning process on the first substrate 14 and the first packaging layer 11 to form a first conductive hole 15; preparing a first redistribution layer 16 in the first conductive hole 15 and on the side of the first substrate 14 away from the first packaging layer 11; disposing the chip assembly 9 on the side of the first substrate 14 away from the first packaging layer 11; preparing a sub-packaging layer 1810 on the side of the first substrate 14 away from the first packaging layer 11, and the sub-packaging layer 1810 covers the first redistribution layer 16 and the chip assembly 9; preparing a sub-substrate 1820 on the side of the sub-packaging layer 1810 away from the first substrate 14; performing a patterning process on the sub-substrate 1820 and the sub-packaging layer 1810 to form a sub-conductive hole 1830; preparing a sub-redistribution layer 1840 in the sub-conductive hole 1830 and on the side of the sub-substrate 1820 away from the sub-packaging layer 1810, and a sub-packaging structure 18 is formed by the combination of the sub-packaging layer 1810, the sub-substrate 1820, the sub-conductive hole 1830, and the sub-redistribution layer 1840; removing the carrier 12 and the glue layer 13; and preparing a solder ball 17 on the side of the sub-redistribution layer 1840 farthest from the first substrate 14 away from the sub-substrate 1820.

[0074] The packaging method of the chip assembly provided in the present application is described in detail above, and specific examples are applied in the description of the principles and implementation modes of the present application. The above examples are only used to help understand the core idea of the present application; meanwhile, for those skilled in the art, the specific implementation modes and application ranges can be changed according to the idea of the present application, and the above description should not be understood as a limitation of the present application.

Claims

1. A chip assembly (9) packaging method, characterized in that: The packaging method of the chip component (9) comprises: Cutting a first wafer (1) to form a first chip (4); Bonding the front surface of the first chip (4) to the front surface of a second wafer (5) to form a first semi-finished product (7); cutting the first semi-finished product (7) so that the second wafer (5) is cut to form a second chip (10), and the first chip (4) and the second chip (10) bonded to each other form a chip assembly (9); The chip assembly (9) is arranged on a carrier (12), wherein the carrier (12) has a first direction (M); A first packaging layer (11) is provided on the carrier (12), wherein the first packaging layer (11) covers the chip component (9); A first substrate (14) is provided on a side of the first packaging layer (11) away from the carrier (12); The first substrate (14) and the first packaging layer (11) are patterned to form a first conductive hole (15), wherein the first conductive hole (15) penetrates the first substrate (14) and the first packaging layer (11) along the first direction (M); preparing a first redistribution layer (16) in the first conductive hole (15) and on a side of the first substrate (14) away from the first packaging layer (11); A solder ball (17) is prepared on a side of the first redistribution layer (16) away from the first substrate (14), and the solder ball (17) is electrically connected to the first redistribution layer (16).

2. The packaging method of the chip assembly (9) according to claim 1, characterized in that: The step of cutting a first wafer (1) to form a first chip (4) comprises: Providing a first protective film (2) on the front surface of the first wafer (1); Performing a thinning process on the back side of the first wafer (1); removing the first protective film (2); Providing a second protective film (3) on the back side of the first wafer (1); The first wafer (1) is cut to form the first chip (4).

3. The packaging method of the chip assembly (9) according to claim 1, characterized in that: The step of bonding the front surface of the first chip (4) to the front surface of a second wafer (5) to form a first semi-finished product (7) comprises: Providing a third protective film (6) on the front surface of the second wafer (5); Performing a thinning process on the back side of the second wafer (5); removing the third protective film (6); The front side of the first chip (4) is bonded to the front side of the second wafer (5) to form the first semi-finished product (7).

4. The packaging method of the chip assembly (9) according to claim 1, characterized in that: The first wafer (1) comprises a first main body (110) and a first conductive portion (120) arranged on one side of the first main body (110); the second wafer (5) comprises a second main body (510) and a second conductive portion (520) arranged on one side of the second main body (510); The step of bonding the front surface of the first chip (4) to the front surface of a second wafer (5) to form a first semi-finished product (7) comprises: The first conductive portion (120) of the first chip (4) and the second conductive portion (520) of the second wafer (5) are bonded to form a first semi-finished product (7).

5. The packaging method of the chip assembly (9) according to claim 1, characterized in that: The front side of the first chip (4) and the front side of the second wafer (5) are bonded to form a first semi-finished product (7) by using at least one of hot pressing welding, ultrasonic welding, laser welding, conductive adhesive welding and micro welding.

6. The chip assembly (9) packaging method according to claim 1, characterized in that: The step of cutting the first semi-finished product (7) so that the second wafer (5) is cut to form a second chip (10), and the first chip (4) and the second chip (10) bonded to each other form a chip assembly (9) comprises: Providing a fourth protective film (8) on the back side of the second wafer (5); The second wafer (5) of the first semi-finished product (7) is cut to form the second chip (10). The first chip (4) and the second chip (10) bonded to each other form the chip assembly (9).

7. The packaging method of the chip assembly (9) according to claim 1, characterized in that: The step of placing the chip component (9) on a carrier (12) includes: placing an adhesive layer (13) on the carrier (12), and attaching the chip component (9) to the adhesive layer (13); Before the step of preparing solder balls (17) on the side of the first redistribution layer (16) away from the first substrate (14), the step further includes: removing the carrier (12) and the glue layer (13).

8. The packaging method of the chip assembly (9) according to claim 1, characterized in that: The step of patterning the first substrate (14) and the first packaging layer (11) to form a first conductive hole (15) comprises: The first substrate (14) and the first packaging layer (11) are patterned by a laser process to form a first conductive hole (15).

9. The chip assembly (9) packaging method according to claim 1, characterized in that: Before the step of preparing solder balls (17) on the side of the first redistribution layer (16) away from the first substrate (14), the method further includes: preparing at least one sub-encapsulation structure (18) on the side of the first substrate (14) away from the first encapsulation layer (11), wherein the sub-encapsulation structure (18) covers the first redistribution layer (16); The step of preparing at least one sub-encapsulation structure (18) on a side of the first substrate (14) away from the first encapsulation layer (11) comprises: A sub-encapsulation layer (1810) is prepared on a side of the first substrate (14) away from the first encapsulation layer (11), wherein the sub-encapsulation layer (1810) covers the first redistribution layer (16); preparing a sub-substrate (1820) on a side of the sub-encapsulation layer (1810) away from the first substrate (14); The sub-substrate (1820) and the sub-encapsulation layer (1810) are patterned to form a sub-conductive hole (1830), wherein the sub-conductive hole (1830) penetrates the sub-substrate (1820) and the sub-encapsulation layer (1810) along the first direction (M); A sub-redistribution layer (1840) is prepared in the sub-conductive hole (1830) and on a side of the sub-substrate (1820) away from the sub-packaging layer (1810), and the sub-redistribution layer (1840) closest to the first substrate (14) is electrically connected to the first redistribution layer (16); The solder ball (17) is prepared on the side of the sub-redistribution layer (1840) away from the sub-substrate (1820), and the solder ball (17) is electrically connected to the sub-redistribution layer (1840) farthest from the first substrate (14).

10. The chip assembly (9) packaging method according to claim 9, characterized in that: The step of preparing at least one sub-encapsulation structure (18) on a side of the first substrate (14) away from the first encapsulation layer (11) further comprises: The chip component (9) is arranged on a side of the first substrate (14) away from the first packaging layer (11) and / or on a side of the sub-substrate (1820) away from the sub-packaging layer (1810), and the sub-packaging layer (1810) covers the chip component (9).

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